Managing operations in memory system

Abstract

Methods, systems, and apparatus for managing operations in a memory system are described. An example system includes a memory device and a memory controller. The memory device includes: a first buffer; a second buffer; and a third buffer including a plurality of data buffers. The memory device receives a first portion of the first data of the first request from the memory controller and stores the first portion of the first data in a first data buffer of the first buffer or the third buffer. The memory controller sends a second request to the memory device. In response to the second request, the storage device moves a first portion of the first data from the first buffer or the first data buffer to the second buffer. The memory device performs an operation in response to the second request without using the second buffer.

Description

Technical Field

[0001] The present disclosure relates generally to memory systems, and more particularly to management of operations of memory systems. Background Art

[0002] The memory system may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. Typically, the host system may utilize the memory system to store data in the memory components and retrieve data from the memory components. Summary of the invention

[0003] This disclosure describes management of operations in a memory system.

[0004] In one aspect, the present disclosure describes a method performed by a memory device. The memory device includes: a first buffer, a second buffer, and a third buffer. The third buffer includes a plurality of data buffers. The method includes: the memory device receives a first portion of a first data of a first request from a memory controller, wherein the first request includes at least the first portion of the first data and the second portion of the first data; the memory device stores the first portion of the first data in a first data buffer of the first buffer or the third buffer; the memory device receives a second request from the memory controller; in response to the second request, the memory device moves the first portion of the first data from the first buffer or the first data buffer of the third buffer to the second buffer; the memory device performs an operation without using the second buffer in response to the second request; the memory device sends an execution result of the second request to the memory controller; the memory device receives the second portion of the first data from the memory controller; and the memory device stores the second portion of the first data in a second data buffer of the third buffer.

[0005] On the other hand, the present disclosure describes a memory device. The memory device includes: a first buffer, a second buffer, a third buffer, an array of memory cells, and control logic. The third buffer includes a plurality of data buffers. The control logic is coupled to at least one memory storing programming instructions, and the programming instructions, when executed by the control logic, cause the memory device to perform operations including: receiving a first portion of first data of a first request from a memory controller, wherein the first request includes at least the first portion of the first data and the second portion of the first data; storing the first portion of the first data in a first data buffer of the first buffer or the third buffer; receiving a second request from the memory controller; moving the first portion of the first data from the first data buffer of the first buffer or the third buffer to the second buffer in response to the second request; performing an operation without using the second buffer in response to the second request; sending the execution result of the second request to the memory controller; receiving the second portion of the first data from the memory controller; and storing the second portion of the first data in a second data buffer of the third buffer.

[0006] In another aspect, the present disclosure describes a system including a memory device and a memory controller. The memory device includes: a first buffer, a second buffer, a third buffer, an array of storage cells, and control logic. The third buffer includes a plurality of data buffers. The control logic is coupled to at least one memory storing programming instructions, and the programming instructions, when executed by the control logic, cause the memory device to perform operations including: receiving a first portion of a first data of a first request from the memory controller, wherein the first request includes at least the first portion of the first data and the second portion of the first data; storing the first portion of the first data in a first data buffer of the first buffer or the third buffer; receiving a second request from the memory controller; moving the first portion of the first data from the first data buffer of the first buffer or the third buffer to the second buffer in response to the second request; performing an operation without using the second buffer in response to the second request; sending the execution result of the second request to the memory controller; receiving the second portion of the first data from the memory controller; and storing the second portion of the first data in a second data buffer of the third buffer.

[0007] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram of an example system is shown in accordance with one or more implementations of the present disclosure.

[0009] Figure 2A A diagram of an example memory card is shown in accordance with one or more implementations of the present disclosure.

[0010] Figure 2B A diagram of an example solid-state drive (SSD) is shown in accordance with one or more implementations of the present disclosure.

[0011] Figure 3 A block diagram of an example memory system is shown in accordance with one or more implementations of the present disclosure.

[0012] Figure 4 A block diagram of an example memory system is shown in accordance with one or more implementations of the present disclosure.

[0013] Figure 5 A block diagram of an example memory device is shown in accordance with one or more implementations of the present disclosure.

[0014] Figure 6 A schematic diagram of an example memory cell array in a memory device according to one or more implementations of the present disclosure is shown.

[0015] Figure 7 A block diagram of an example page buffer of a memory device according to one or more implementations of the present disclosure is shown.

[0016] Figure 8 A block diagram of an example memory device is shown in accordance with one or more implementations of the present disclosure.

[0017] Fig. 9 A flow chart illustrating an example process of management operations performed by a memory system in accordance with one or more implementations of the present disclosure.

[0018] Fig.10 Example data structures for use in a memory system in accordance with one or more implementations of the present disclosure are shown.

[0019] Fig.11 A swim lane diagram illustrating an example process performed by a memory system including a memory controller and a memory device according to one or more implementations of the present disclosure.

[0020] Fig.12 A flow chart illustrating an example process performed by a memory controller in accordance with one or more implementations of the present disclosure is shown.

[0021] Fig.13 A flowchart illustrating an example process performed by a storage device according to one or more implementations of the present disclosure is shown.

[0022] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0023] The memory system may be a storage device, a storage module, or a combination of a storage device and a storage module. Figure 1 and Figure 2A and Figure 2B Examples of storage devices and storage modules are described. In general, a host system may utilize a memory system that includes one or more memory components (e.g., a storage device that stores data). The host system may provide data to be stored in the storage device and may request data to be retrieved from the storage device.

[0024] The memory device may include a plurality of memory cells. Each memory cell may be configured to have a different storage mode or state, for example, a single-level cell (SLC) or a multi-level cell (MLC). SLC may store only one bit per storage element, while MLC may store more than one bit of information. For example, a triple level cell (TLC) may store three bits of data, a quadruple level cell (QLC) may store four bits of data, and a penta level cell (PLC) may store five bits of data. In this specification, TLC, QLC, PLC, and other cells capable of storing more than one bit of information are collectively referred to as MLC. The state of a memory cell may be programmed, and the state of a memory cell may be determined by comparing a read voltage of the memory cell with one or more read level thresholds.

[0025] QoS (quality of service) is a key evaluation factor for memory systems. QoS metrics may include, for example, latency / response time, system throughput, and other measurements. Different QoS latency metrics or numbers may be established for various applications. For example, a mixed write and read (or mixed input and output (I / O)) workload environment may include, for example, a random write / read workload and a sequential write / read workload. In one example, for a mixed workload with a drive capacity of 70% write / 30% write / read ratio, 4K page size, and queue depth = 1, a memory system may have a QoS target of 99.9%. In another example, for a mixed workload with a drive capacity of 70% write / 30% write / read ratio, 4K page size, and queue depth = 32, a memory system may have a QoS target of 99.999%.

[0026] Each programming pass performed on the memory system takes a period of time to complete (eg, programming time). Long programming times associated with memory systems, and particularly MLC memory systems storing more than 2 bits of information per storage element, can negatively impact achievement of associated QoS goals.

[0027] In a memory system operating with a mixed workload, if a read operation request is received while a previous program operation is in progress, the read operation is forced to wait until the program operation has completed. Due to the longer program times associated with MLC memory systems storing more than 2 bits of information per storage element, read operations are delayed during the longer program times, negatively impacting QoS latency and throughput targets.

[0028] Specific implementations of the subject matter described in the present disclosure can be implemented and help achieve one or more of the following advantages. In some implementations, the QoS of the memory system and the user experience of read operations (or other operations with higher execution priority) (e.g., in terms of system response time) can be improved because ongoing lower execution priority operations (e.g., programming or write operations) can be preempted by higher execution priority operations. For example, a data transfer interrupt mechanism can be introduced on the memory controller and storage device of the memory system so that lower execution priority operations (e.g., programming operations) can be paused earlier to perform higher execution priority operations (e.g., read operations) than other memory systems that do not implement the disclosed features. In addition, in some cases, unlike a write pause command that can only pause an ongoing programming operation after the data transfer from the controller to the storage device is completed (e.g., but before the data is actually stored in the storage device), the technology described in the present disclosure can pause an ongoing programming operation while the data is still being transferred from the memory controller, without having to wait until the storage device completes receiving the complete data from the controller.

[0029] In some implementations, the described techniques allow for a pre-check method to be implemented on the memory controller side to ensure that processing of a read operation will preempt the program data transfer process of a program operation. In some implementations, on the memory controller side, the firmware does not need to involve any additional control actions, and the hardware can handle the pre-check or determination. The read handle can automatically pause data transfer to reduce latency.

[0030] On the storage device, a page-buffer dynamic switching method can be implemented to ensure that read operations and write operations can be mixed and properly processed. In some implementations, in the described technology, the command-based preemption interaction mechanism is designed to avoid confusion in the internal processing logic on the storage device side. For example, using this feature, the storage device can automatically identify the type of operation and switch the read / program context without disrupting the internal state machine of the storage device.

[0031] In some implementations, the described techniques can reduce stalls of other memory operations, improve efficiency in processing read commands, and / or increase throughput of a memory system because waiting until data transfer for an ongoing programming operation is completed can be avoided.

[0032] Figure 11 shows a block diagram of an example system 100 according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102. Memory system 102 includes one or more memory devices 104 and a memory controller 106. Host 108 may be, for example, a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). Host 108 may be configured to send data to or receive data from memory device 104. In order to send data to or receive data from memory device 104, host 108 may also send instructions to memory system 102 in addition to data.

[0033] The memory device 104 may be any memory device disclosed in the present disclosure. As disclosed in detail below, the memory device 104 (eg, a NAND flash memory device) may support a program operation suspension triggered by an interrupt.

[0034] In some implementations, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller 106 is designed for operation in a high duty cycle environment SSD or embedded multi-media-cards (eMMC), which are used as data storage libraries and enterprise storage arrays for mobile devices (e.g., smart phones, tablet computers, laptop computers, etc.).

[0035] The memory controller 106 may be configured to control the operation of the memory device 104 (e.g., read, erase, and program (or write) operations). For example, based on instructions received from the host 108, the memory controller 106 may send various commands (e.g., program (or write) commands, read commands, erase commands, etc.) to the memory device 104 to control the operation of the memory device 104. Consistent with the scope of the present disclosure, in some implementations, the memory controller 106 sends a program command to the memory device 104 to initiate a programming operation to be performed by the memory device 104. During an ongoing programming operation, an interruption (e.g., a read operation to another page) may occur, for example, from the host 108. The memory controller 106 may be configured to send an interrupt command to the memory device 104 to suspend the programming operation. In some implementations, upon completion of other operations triggered by the interruption, the memory controller 106 may also be configured to send a resume command to the memory device 104 to resume and complete the suspended programming operation.

[0036] The memory controller 106 may also be configured to manage various functions regarding data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some implementations, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions (e.g., formatting the memory device 104). The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices via at least one of various interface protocols (for example, USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer system small interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.).

[0037] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices and may, for example, be included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of final electronic products. Figure 2A In one example shown, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor configured to connect the memory card 202 to a host (e.g., Figure 1 The host 108 in the memory card connector 204 is coupled. Figure 2B In another example shown in FIG. 1 , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor configured to connect the SSD 206 to a host (eg, Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the corresponding storage capacity and / or operating speed of the memory card 202.

[0038] Figure 3 304. The memory system 302 includes a memory controller 306 and a memory device 304. The memory controller 306 and the memory device 304 may be respectively combined with Figure 1 and Figure 2A and Figure 2B Example implementations of the memory controller 106 and the memory device 104 are discussed.

[0039] The memory controller 306 may, for example, respond to a request from a host (eg, Figure 1 The memory controller 306 may exchange data with the memory device 304 in response to a request from the host 108. As an example, the memory controller 306 may read data from the memory device 304 in response to a request from the host, and may provide the read data to the host. As another example, the memory controller 306 may write or program data into the memory device 304 in response to a program request from the host.

[0040] In some implementations, to perform the above operations, the memory controller 306 may provide signals such as an address (ADDR), a command (CMD), and a control signal (CTRL) to the memory device 304, and may exchange data (DATA) with the memory device 304. In response to the signal received from the memory controller 306, the memory device 304 may output the data or may program the received data.

[0041] The memory controller 306 may provide a read command, a program command, an erase command, etc. as a command to the memory device 304. For example, the memory controller 306 may request a programming operation of a word line unit of the memory device 304 through a program command. The memory controller 306 may send one or more addresses indicating one or more word lines for which a programming operation is performed, so that programming is performed on the memory cells on one or more word lines of the memory block of the memory device 304 indicated by the one or more addresses ADDR. As another example, the memory controller 306 may request a read operation to read data stored in the memory cells on one or more word lines of the memory device 304 through a read command. As another example, the memory controller 306 may request an erase operation to erase data programmed in the memory cells of one or more memory blocks or sub-block units of the memory device 304 through an erase command.

[0042] Figure 4 A block diagram of an example memory system 400 according to some aspects of the present disclosure is shown. The memory system 400 includes a host 408, a memory controller 406, a storage device 404, and a DRAM 426. The memory controller 406 includes one or more processors 422 and one or more memories including one or more of a cache 424 and / or another type of data storage repository. Figure 4 A dynamic random access memory (DRAM) 426 is shown as being separate from the memory controller 406, however, in some other implementations, the DRAM 426 may be included as part of the memory included in the memory controller 406. In some implementations, the memory controller 406 may include a DRAM controller 425 for the DRAM 426. The memory controller 406 may also include an interface (I / F) 428 (also referred to as a "front-end interface") to the host 408 and an interface (I / F) 430 (also referred to as a "back-end interface") to the memory device 404. In some implementations, the interface 428 may receive instructions and data from the host 408 and forward the instructions and data to the processor 422 and the DRAM 426, respectively. In some implementations, the interface 430 may transmit control signals and data from the processor 422 and the DRAM 426 to the memory device 404, respectively.

[0043] In some implementations, the processor 422 may include an arithmetic logic unit (ALU) configured to perform arithmetic and / or logic operations. The memory device 404, one or more memories (e.g., cache 424) of the memory controller 406, or a combination of these components may store programming instructions that, when loaded into the processor 422, may be executed by the processor 422 to run various functions of the memory controller 406, such as the functions described in the present disclosure. As an example, the memory controller 406 is configured to perform such functions as, for example, repeatedly checking whether a second command is received from the host 408 while performing a data transfer to the memory device 404 for a first operation corresponding to a first command, and sending a pause command to the memory device 404 whenever the second command is received as long as the data transfer in the current allocation unit is completed.

[0044] Figure 5 1 shows a block diagram of an example memory device 500 according to some aspects of the present disclosure. The memory device 500 may be a memory device that combines Figure 1 , Figure 2A and Figure 2B as well as Figure 3 Example embodiments of the memory device 104 or 304 discussed. As shown, the memory device 500 includes a memory cell array 502, a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It is understood that in some examples, the memory device 500 may also include a memory cell array 502, a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. Figure 5 Additional circuitry not shown.

[0045] The memory cell array 502 may be a NAND flash memory cell array, wherein the memory cells are provided in the form of an array of NAND memory strings, each NAND memory string extending vertically above a substrate (not shown). Figure 6 In some implementations, each NAND memory string 608 includes a plurality of memory cells 606 coupled in series and stacked vertically. Each memory cell 606 can hold a continuous analog value (e.g., voltage or charge) that depends on the number of electrons trapped in the region of the memory cell 606. Each memory cell 606 can be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

[0046] In some implementations, each memory cell 606 is a single-layer cell (SLC) with two possible memory states (levels), and thus can store one bit of data. For example, a first memory state "0" can correspond to a first range of threshold voltages, and a second memory state "1" can correspond to a second range of threshold voltages. In some implementations, each memory cell 606 is an xLC capable of storing more than a single bit of data in more than four memory states (levels). For example, an xLC can store two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC). Each xLC can be programmed to have a range of possible nominal storage values ​​(i.e., 2N segments of N-bit data, e.g., Gray code). In one example, an MLC can be programmed by writing one of three possible nominal storage values ​​to a cell to have one of three possible programming levels from an erased state. A fourth nominal storage value can be used for an erased state.

[0047] Each NAND string 608 may also include a source select gate (SSG) transistor 610 at its source end and a drain select gate (DSG) transistor 612 at its drain end. The SSG transistor 610 and the DSG transistor 612 may be configured to activate a select NAND string 608 (column of the array) during read and program operations. In some implementations, the sources of the NAND strings 608 in the same block 604 are coupled by the same source line (SL) 614 (e.g., a common SL). In other words, according to some implementations, all NAND strings 608 in the same block 604 have an array common source (ACS). According to some implementations, the drain of each NAND string 608 is coupled to a corresponding bit line 616, from which data may be read or written via an output bus (not shown). In some implementations, each NAND storage string 608 is configured to be selected or deselected by applying a selection voltage or a deselection voltage to the gate of the corresponding DSG transistor 612 through one or more DSG lines 613 and / or applying a selection voltage or a deselection voltage to the gate of the corresponding SSG transistor 610 through one or more SSG lines 615.

[0048] The NAND memory strings 608 may be organized into a plurality of blocks 604, each of which may have a common source line 614 (e.g., coupled to an ACS). In some implementations, each block 604 is a basic data unit for an erase operation, i.e., all memory cells 606 on the same block 604 are erased simultaneously. To erase the memory cells 606 in a selected block 604, the source lines 614 coupled to the selected block 604 and the unselected blocks 604 in the same plane as the selected block 604 may be biased with an erase voltage (Vers), e.g., a high positive bias voltage (e.g., 20V or higher). The memory cells 606 of adjacent NAND memory strings 608 may be coupled by word lines 618, which select which row of memory cells 606 is affected by read and program operations. In some implementations, each word line 618 is coupled to one or more pages of memory cells 606, which are the basic data unit for read and program operations. The size (in bits) of one or more pages may be related to the number of NAND memory strings 608 coupled by word lines 618 in a block 604. Each word line 618 may include a plurality of control gates (gate electrodes) at each memory cell 606 and gate lines coupled to the control gates.

[0049] The memory cell array 502 may include an array of memory cells 606 in multiple rows and multiple columns in each block 604. According to some implementations, a row of memory cells 606 corresponds to one or more pages, and a column of memory cells corresponds to one NAND memory string 608. Multiple rows of memory cells 606 may be coupled to word lines 618, respectively, and multiple columns of memory cells 606 may be coupled to bit lines 616, respectively.

[0050] Back to Figure 5, the page buffer / sense amplifier 504 can be configured to read data from the memory cell array 502 and program (write) data to the memory cell array 502 according to the control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store one or more pages of programming data to be programmed into the memory cell array 502. In another example, the page buffer / sense amplifier 504 can verify the programmed selected memory cell 606 in each programming / verification cycle (cycle) in the programming operation to ensure that the data has been properly programmed into the memory cell 606 coupled to the selection word line 618. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal representing a data bit stored in the memory cell 606 from the bit line 616, and amplify the small voltage swing to a recognizable logic level in a read operation. As described in detail below and consistent with the scope of the present disclosure, in a programming operation, the page buffer / sense amplifier 504 may include multiple page buffer circuits respectively coupled to the bit lines 616, and each page buffer circuit includes a set of storage units (e.g., latches) that are used to temporarily store a segment of N-bit data (e.g., in the form of Gray code) received from the data bus 518 and provide the segment of N-bit data to the corresponding selected storage cell 606 through the corresponding bit line 616 in a programming operation using a multi-cache loading scheme.

[0051] The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512, and select one or more NAND memory strings 608 by applying a bit line voltage generated from the voltage generator 510. The row decoder / word line driver 508 may be configured to be controlled by the control logic 512, and select / deselect a block of the memory cell array 502 and select / deselect a word line 618 of the block 604. The row decoder / word line driver 508 may also be configured to drive the word line 618 using a word line voltage generated from the voltage generator 510. The voltage generator 510 may be configured to be controlled by the control logic 512, and generate a word line voltage (e.g., a read voltage, a program voltage, a channel pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 502.

[0052] The control logic 512 may be coupled to each circuit described above and configured to control the operation of each circuit. The register 514 may be coupled to the control logic 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address to control the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512 and used as a control buffer to transfer data from a memory controller (e.g., Figure 1106) and / or a host (e.g., Figure 1 The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518 and used as a data input / output (I / O) interface and data buffer to buffer and relay data to and from the memory cell array 502.

[0053] Figure 7 is a block diagram of an example page buffer / sense amplifier 504 according to some aspects of the present disclosure. In some implementations, the page buffer / sense amplifier 504 includes a plurality of page buffer circuits 702, each of which is coupled to a respective one of the bit lines 616. In other words, each page buffer circuit 702 can be coupled to a respective column of memory cells 606 (e.g., NAND memory string 608) via a corresponding bit line 616.

[0054] In some implementations, to implement a multi-cache data loading scheme for sequential programming operations, each page buffer circuit 702 may include a set of data storage units 706 and cache storage units 708. In some implementations, the page buffer circuit 702 may include additional storage units in addition to the data storage units 706 and the cache storage units 708. The additional storage units, the data storage units 706, and the cache storage units 708 may be used together to store current data.

[0055] Each page buffer circuit 702 may include a plurality of storage cells that are used to store non-data page information, that is, any information other than data bits in the data to be programmed into the memory cell array. Figure 7 As shown, in some implementations, the page buffer circuit 702 includes: a sense / program storage unit 712, which is configured to store information indicating whether the current operation performed by the page buffer / sense amplifier 504 is a read operation or a program operation; and a 3BL storage unit (DL) 710, which is configured to store bias information of the corresponding bit line 616 coupled to the page buffer circuit 702. Figure 7As shown, each page buffer circuit 702 may also include a bias circuit 704 coupled to a corresponding bit line 616, the bias circuit 704 being configured to apply a bit line voltage to a corresponding selected memory cell 606 coupled to the corresponding bit line 616 in a programming operation. Depending on whether the corresponding selected memory cell 606 has passed the verification at the corresponding level according to the N-bit data for programming the selected memory cell 606, for example, a high voltage level and a low voltage level may be used as the bit line voltage to bias the corresponding bit line 616. In some implementations, in order to optimize the threshold voltage distribution, for example, to expand the read margin between adjacent levels and reduce the width of each level, a medium voltage level is also used to bias the bit line voltage. That is, three voltage levels (e.g., high, medium, and low) may be applied to the corresponding bit line 616 (referred to herein as 3BL). In some implementations, the voltage level (e.g., 3BL bias) applied to the corresponding bit line 616 is non-data page information stored in the 3BL storage unit 710.

[0056] Figure 8 800 according to some aspects of the present disclosure. The memory device 800 may be an example of the memory device 104, the memory device 304, or the memory device 500. As shown, the memory device 800 includes a cache buffer 802, an internal buffer 804, a data buffer 806, and a memory cell array 808. It is understood that in some examples, the memory device 800 may also include a cache buffer 802, an internal buffer 804, a data buffer 806, and a memory cell array 808. Figure 8 In some implementations, cache buffer 802, internal buffer 804, data buffer 806 may be examples of cache storage unit 708, storage unit 710, and data storage unit 706, respectively.

[0057] In some implementations, the cache buffer 802 operates as a cache memory of the memory device 800 for fast data access. For example, the cache buffer 802 may temporarily store data received from a memory controller or a host, or may temporarily store metadata (e.g., a mapping table) of the memory cell array 808.

[0058] In some implementations, the internal buffer 804 operates as additional storage space for the memory device 800. For example, the internal buffer 804 can temporarily store data received from the cache buffer 802 and forward the data to the data buffer 806 during a program operation. In some examples, the internal buffer 804 can temporarily store data received from the data buffer 806 and forward the data to the cache buffer 802 during a read operation. In some examples, the memory device 800 can move data from the cache buffer 802 to the data buffer 806, or vice versa, without using the internal buffer 804.

[0059] In some implementations, the data buffer 806 includes a plurality of buffer units (or page registers). In some implementations, the data buffer 806 is connected to the memory cell array 808 via a bit line. In some implementations, the data buffer 806 is connected to the cache buffer 802 via a plurality of data lines. The data buffer 806 may store data to be programmed in a memory cell of the memory cell array 808 or data read from a memory cell. During an example programming operation, the data buffer 806 may receive data to be programmed in a memory cell from the cache buffer 802 and store the received data. During an example read operation, the data buffer 808 may temporarily store data read from the memory cell array 808 and output the data to the cache buffer 802. In some implementations, in addition to the page buffer, the data buffer 806 may include a column selection circuit, etc.

[0060] Fig. 9 A flow chart of an example process 900 for managing operations associated with a memory system according to some aspects of the present disclosure is shown. The example process 900 can be performed by any suitable device disclosed herein (e.g., memory system 100, 202, 206, 302, or 400, etc.). The example process 900 will be described as being performed by a memory system having a memory controller and a memory device appropriately programmed according to the present disclosure. The memory controller can be any suitable device disclosed herein, for example, memory controller 106, 306, or 406, etc. The memory device can be any suitable device disclosed herein, for example, memory device 104, 304, 404, 500, 800, etc. In some implementations, some or all of the operations in the example process 900 can be based on a combination of Figure 1-Figure 8 The operations shown in process 900 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Fig. 9 Execute in the order shown.

[0061] In the example shown, the memory device receives a first command from a memory controller. In some implementations, the first command instructs the memory device to perform a first operation to program first data into a memory cell array of the memory device. For example, the first command may be a TLC programming command or a QLC programming command. The first operation indicated by the first command includes the memory controller sending or transferring the first data to the memory device. In some implementations, the memory controller performs data transfer to the memory device in terms of allocation units (AUs). That is, in order to transfer the first data to the memory device, the memory controller divides the first data into a sequence of multiple AUs and sends the AUs one by one in sequence according to the sequence of AUs. AU is a basic unit or minimum amount of data that can be retrieved from or written to a memory system individually. In some implementations, AUs have the same size in the memory system. In some other implementations, the size of the AU may vary within the memory system or vary from one memory system to another. Reference Fig.10 , example data 1000 as first data that may be transmitted by a memory controller includes three AUs, where the three AUs are represented by a lower page (LP) 1002 , a middle page (MP) 1004 , and an upper page (UP) 1006 .

[0062] Back to Fig. 9 After receiving the first command, the memory controller transmits a first AU of first data (e.g., LP1002) to the memory device (902). In some implementations, upon receiving the first AU, the memory device may store the first AU in a cache buffer (e.g., cache buffer 802) of the memory device.

[0063] Programming operations (including data transfer from a memory controller to a memory device) take a period of time to complete. In general, different operations may have different characteristics (e.g., execution priorities) and may take or be associated with different time periods to complete. In order to improve the overall execution efficiency or response time of the memory system, one programming operation with a higher execution priority than another programming operation may preempt or interrupt the execution of the other programming operation, even though the other programming operation may already be executing or a command for the programming operation with a higher execution priority is received after a command for another programming operation with a lower execution priority.

[0064] During execution of a program operation, the memory system checks in a repetitive manner whether another command related to the memory system is received, for example, while performing data transfer to a memory device for an operation of a program command.

[0065] In some cases, if no other commands are received, the memory controller continues to transfer the current AU, or proceeds to transfer the next AU in the sequence to the memory device.

[0066] Before sending the second AU of the first data (e.g., MP 1004) to the memory device, the memory controller receives a second command for programming the second data into the memory device (904). In the example shown, the second command has a higher execution priority than the first command. Fig. 9 The second command is shown as a programming command, but more generally, the second command can be any command requesting an operation with a higher execution priority than the programming operation of the first command. In some implementations, the execution priority of different operations can be determined based on the time period for completing different operations. For example, an operation that requires a shorter time period to complete can have a higher execution priority. In some implementations, the second command may involve an operation that takes a shorter time period to complete than the programming operation of the first command. In one example, the second command may involve a programming operation that writes a smaller amount of data to a storage device, which will take a shorter time period to complete than the first command that writes a larger amount of data to the storage device. In another example, the second command may involve a read operation that will take a shorter time period to complete than the first command. In some other implementations, the execution priority of different operations can be determined, or otherwise based on the importance of the operation or other factors or preferences.

[0067] exist Fig. 9 In the example shown, in response to receiving or detecting a second command having a higher execution priority than the first command, a data transfer pause command may be issued to pause the ongoing data transfer process for the programming operation of the first command. In some cases, the data transfer pause command is issued upon detection of the second command to limit the delay in servicing the second command. In some implementations, the memory controller may send the data transfer pause immediately after completing the transfer of the current AU and before the transfer of the subsequent AU begins. In some implementations, if the transfer of the current AU has not yet completed, the memory controller may wait for the transfer of the current AU to end and then continue processing the switch to perform operations related to the second command.

[0068] In response to receiving the data transfer pause command, the storage device can suspend the operation of the first command and start processing the second command. In some examples, the storage device moves the first AU of the first data from the cache buffer to the internal buffer of the storage device (e.g., internal buffer 804), and stores the second data of the second command in the cache buffer of the storage device. Then, the storage device moves the second data from the cache buffer to the data buffer of the storage device (e.g., data buffer 806), and confirms that all data of the second command are ready to be programmed into the storage cell array (906). After confirming that all data of the second command are stored in the data buffer, the storage device programs the data of the second command into the storage cell array (908).

[0069] In some examples, before receiving the second command, the storage device may have moved the first AU of the first data from the cache buffer to a data buffer of the storage device. In these examples, after receiving the second command, the storage device moves the first AU of the first data from the data buffer to an internal buffer of the storage device.

[0070] In some implementations, after the operation of the second command is completed, a resume last operation command is issued. The resume last operation command resumes the previously suspended operation of the storage device, and more specifically, resumes the data transfer process to enable the data transfer of the previously suspended programming operation to continue. In some implementations, the data transfer process can be resumed from the next AU (e.g., MP 1004) in the sequence of AUs in which the data transfer process has been suspended, so that the data to be programmed from the memory controller to the storage device can be completed. In some implementations, upon receiving the resume last operation command, the storage device moves the first AU of the first data of the first command from the internal buffer to the data buffer of the storage device.

[0071] After the operation of the second command is completed, the memory device resumes the programming operation of the first command and stores the second AU of the first data (e.g., MP 1004) in a cache buffer of the memory device (910). In some implementations, the memory device moves the second AU of the first data from the cache buffer to a data buffer of the memory without using an internal buffer without receiving another command having a higher execution priority than the first command.

[0072] The storage device continues to receive a third AU of the first data (e.g., UP 1006) and stores the third AU in a cache buffer of the storage device (912). In some implementations, the storage device moves the third AU of the first data from the cache buffer to a data buffer of the storage device without using an internal buffer without receiving another command having a higher execution priority than the first command.

[0073] After receiving all AUs of the first data, the memory device confirms that the first data is ready to be programmed into the memory device (914), and programs the first data into a memory cell array of the memory device (916).

[0074] Fig.11 A swim lane diagram of an example process 1100 for managing operations in a memory system according to some aspects of the present disclosure is shown. The example process 1100 can be performed by any suitable device disclosed herein (e.g., memory system 100, 202, 206, 302, or 400, etc.). The example process 1100 will be described as being performed by a memory system having a memory controller and a memory device that are appropriately programmed according to the present disclosure. The memory controller can be any suitable device disclosed herein, for example, memory controller 106, 306, or 406, etc. The memory device can be any suitable device disclosed herein, for example, memory device 104, 304, 404, 500, 800, etc. In some implementations, some or all of the operations in the example process 1100 can be based on a combination of Figure 1-Figure 10 The operations shown in process 1100 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Fig.11 Execute in the order shown.

[0075] like Fig.11 As shown, the memory controller receives a first request (1102). In some implementations, the memory controller receives the first request from a host. The first request can be a request for the memory device to perform a first operation. The first operation can be, for example, a programming operation, an erase operation, or another operation to be performed by the memory device. In the example shown, the first request is a request to perform a programming operation to program first data into the memory device.

[0076] In some implementations, the memory controller includes a cache having a size less than a size of the first data. After receiving a first request to program the first data, the memory controller may store a portion of the first data in the cache and send a portion of the first data to the memory device until all portions of the first data are sent. In the example shown, the first request includes at least a first portion and a second portion. The size of each of the first portion and the second portion is equal to or less than the size of the cache of the memory controller. The memory controller may store the first portion of the first data in the cache and send the first portion of the first data to the memory device (1104).

[0077] After receiving the first portion of the first data from the memory controller, the memory device may store the first portion of the first data in a buffer of the memory device. In some implementations, the memory device includes a first buffer, a second buffer, and a third buffer. In some implementations, the third buffer includes a plurality of data buffers. In some examples, the first buffer may be implemented as a cache storage device 708 or a cache buffer 804, the second buffer may be implemented as a storage unit 710 or an internal buffer 804, and the third buffer may be implemented as a data storage unit 706 or a data buffer 806.

[0078] In the example shown, the storage device receives a first portion of the first data and stores the first portion in a first buffer or a third buffer of the storage device (1106). In some examples, before storing the first portion of the first data in the third buffer, the storage device stores the first portion of the first data in the first buffer and moves the first portion of the first data from the first buffer to the third buffer. In some examples, when the third buffer includes a plurality of data buffers, the storage device may store the first portion of the first data in one of the data buffers of the third buffer.

[0079] When the first portion of the first data is transferred to the storage device, the memory controller can monitor and determine whether the second request is received and whether the data transfer of the first portion of the first data is completed. In the example shown, the memory controller receives a second request from the host (1108). The storage device determines that the second request is associated with a second operation having a higher execution priority than the first operation (1110), so that the first operation can be suspended and preempted by the second operation. As an example, the second request can be a request to read data from the storage device. As another example, the second request can be a request to program data other than the first data into the storage device before completing a programming operation to program the first data.

[0080] In some implementations, the memory controller may perform a check whether the second request is received once, periodically, or from time to time. As an example, the memory controller may repeatedly perform the check at a predetermined frequency (e.g., every 1us, 10us, or 50us). As another example, the memory controller may perform the check before or during the transmission of each portion of the first data.

[0081] In some implementations, in response to determining that no second request (or no request including an operation having a higher execution priority than the current first operation) has been received, the data transfer will continue and the next portion of the first data will be transferred from the memory controller to the memory device.

[0082] In some implementations, in response to determining that the second request is received and the data transfer of the first portion of the first data is not complete, the memory controller may wait for the data transfer of the first portion of the first data to be complete.

[0083] In response to determining that the second request is received and the data transfer of the first portion of the first data is complete, the memory controller sends the second request to the memory device (1112). In some implementations, the memory controller may send a pause command to the memory device together with the second request. The pause command may request the memory device to temporarily pause the current operation(s) and perform another operation(s) indicated by the second request.

[0084] In some implementations, the second command sent by the memory controller to the memory device may have a different format than the second request received by the memory controller from the host. For example, the second request sent by the memory controller to the memory device may be generated by the memory controller based on information included in the second request received by the memory controller from the host, for example, to indicate a read operation to read data from the memory device. The second request sent by the memory controller to the memory device may include, for example, additional or different data fields, control information, or have a different format than the second request received by the memory controller from the host.

[0085] By stopping or interrupting the ongoing first operation even before the data transfer of the first operation from the memory controller to the memory device is completed, the memory system can react more quickly to a second request (e.g., a read command) with a higher execution priority. Advantageously, in some implementations, the first operation can be suspended substantially simultaneously with the recognition of the second command to reduce or limit the operation latency of the second operation, for example, in view of an applicable QoS metric in a mixed write and read workload environment.

[0086] After receiving the second request from the memory controller, the memory device may interrupt or stop the current operation. The memory device may also store the received data for the first operation and the context of the execution state of the first operation in the internal memory of the memory device. In the example shown, in response to receiving the second request, the memory device moves the first part of the first data from the first buffer to the second buffer of the memory device, or moves the first part of the first data from the third buffer to the second buffer of the memory device when the first part of the first data has been moved from the first buffer to the third buffer (1114). By moving the first part of the first data to the second buffer, the memory device can free up space in the first buffer and the third buffer for the operation indicated by the second request.

[0087] After moving the first portion of the first data to the second buffer, the memory device continues to perform the second operation after the first operation (e.g., programming operation) is suspended, resulting in little or no delay in servicing the second request. In a memory system operating with a mixed workload, pausing the data transfer of the first operation enables the second operation to be serviced without having to wait for the transfer of the remaining data to complete the ongoing first operation. Therefore, the latency of the memory system can be significantly reduced in some instances.

[0088] In the example shown, the memory device performs a second operation (1116) without using the second buffer in response to the second request. In some examples, when the second request includes an SLC program command for programming the second data into the memory device, the memory device may store the second data in the first buffer, move the second data from the first buffer to the third buffer, and program the second data into a memory cell array of the memory device. In some examples, when the second request includes a read command to read data from the memory device, the memory device may read the data from the memory cell array of the memory device, store the data in the third buffer, move the data from the third buffer to the first buffer, and send the data from the first buffer to the memory controller.

[0089] After performing the second operation in response to the second request, the memory device sends the result of the execution of the second request to the memory controller (1118). For example, as a result of the execution of the read operation indicated by the second request, the memory device can send data obtained from the memory cell array of the memory device. As another example, when the second request indicates an operation to program data into the memory device, the memory device can send an indication to the memory controller, thereby indicating that the data has been programmed into the memory cell array of the memory device.

[0090] In addition to sending the execution result of the second request to the memory controller, the memory device also moves the first portion of the first data from the second buffer to the third buffer 1120. In some examples where the memory device moves the first portion of the first data from a data buffer of the third buffer to the second buffer before satisfying the second request, the memory device may move the first portion of the first data from the second buffer back to the same data buffer of the third buffer.

[0091] The memory controller sends the second portion of the first data to the memory device after receiving the execution result of the second request from the memory device (1122). In some implementations, the memory controller may send a resume command together with the second portion of the first data to the memory device to resume the first operation and continue to transmit the second portion of the first data. In some implementations, the memory controller may obtain the second portion of the first data from the host after receiving the execution result of the second request from the memory device.

[0092] In response to receiving the second portion of the first data from the memory controller, the memory device stores the second portion of the first data in the first buffer (1124). In some examples, the memory device receives a resume command from the memory controller that resumes the context for the first operation and continues to perform the first operation by storing the second portion of the first data.

[0093] The storage device then moves the second portion of the first data from the first buffer to the third buffer (1126). In some implementations, when the storage device stores the first portion of the first data in a data buffer of the third buffer, the storage device may store the second portion of the first data in another data buffer of the third buffer.

[0094] After all portions of the first data have been received by the memory device and stored in the third buffer, the memory device performs a first operation in response to the first request (1130). For example, the memory device may perform a programming operation to program the first data including the first portion and the second portion into a memory cell array of the memory device.

[0095] In some implementations, before performing the first operation in response to the first request, the memory device may receive an indication from the memory controller indicating that all data for the first request has been sent. In the example shown, the memory controller sends an indication of data transfer completion of the first data to the memory device before the memory device performs the first operation (1128).

[0096] Fig.12A flow chart of an example process 1200 for managing operations performed by a memory controller in a memory system according to some aspects of the present disclosure is shown. The example process 1200 can be performed by any suitable device disclosed herein (e.g., the memory controller 106, 306, or 406). The example process 1200 will be described as being performed by a memory controller of a memory system having a memory controller and a memory device that are appropriately programmed according to the present disclosure. In some implementations, some or all of the operations in the example process 1200 can be based on a combination of Figure 1-Figure 11 The operations shown in process 1200 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Fig.12 Execute in the order shown.

[0097] In the example shown, process 1200 begins with a memory controller receiving a first request (1202). The memory controller may receive the first request from a host device. The first request may be a request to perform a first operation on a memory device. The first operation may be, for example, a programming operation to program first data into a memory cell array of the memory device. The first data includes at least a first portion and a second portion. The size of each of the first portion and the second portion may be equal to or less than the size of a cache of the memory controller. The memory controller then stores a first portion of the first data in the cache (1204) and sends the first portion of the first data to the memory device (1206).

[0098] When the first portion of the first data is transferred to the memory device, the memory controller can monitor and determine whether the second request is received and whether the data transfer is completed. In the example shown, the memory controller receives the second request (1208). As an example, the second request can be a request to read data from the memory device. As another example, the second request can be a request to program data other than the first data into the memory device before completing the first operation of programming the first data. The memory device determines that the second request is associated with a second operation having a higher execution priority than the first operation (1210), so that the first operation can be suspended and preempted by the second operation.

[0099] In response to determining that the second request is associated with a second operation having a higher execution priority than the first operation indicated by the first request, the memory controller sends the second request to the memory device (1212). In some implementations, the memory controller can send a pause command to the memory device along with the second request. The pause command can request the memory device to temporarily pause the current operation(s) and perform another operation(s) indicated by the second request.

[0100] After the memory device performs the second operation in response to the second request, the memory controller receives the execution result of the second request from the memory device (1214). For example, as a result of performing the read operation indicated by the second request, the memory device may send data obtained from the memory cell array of the memory device. As another example, when the second request indicates an operation of programming data into the memory device, the memory device may send an indication to the memory controller, thereby indicating that the data has been programmed into the memory cell array of the memory device.

[0101] After sending the first portion of the first data to the memory device, the memory controller may release cache space previously used to store the first portion of the first data, store the second portion of the first data in the cache (1216), and send the second portion of the first data to the memory device (1218).

[0102] In some implementations, if the first data includes more than the first portion and the second portion, the memory controller may continue to transmit the remaining portions of the first data until all portions of the first data have been transmitted to the memory device.

[0103] Fig.13 A flow chart of an example process 1300 for managing operations performed by a memory device in a memory system according to some aspects of the present disclosure is shown. The example process 1300 can be performed by any suitable memory device disclosed herein (e.g., memory device 104, 304, 404, or 502). The example process 1300 will be described as being performed by a memory device of a memory system having a memory controller and memory device appropriately programmed according to the present disclosure. In some implementations, some or all of the operations in the example process 1300 can be based on a combination of Figure 1-Figure 11 The operations shown in method 1300 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Fig.13 Execute in the order shown.

[0104] The memory device receives a first portion of first data of a first request from a memory controller (1302). In some implementations, the first request is a request to perform a first operation on the memory device. The first operation can be, for example, a programming operation, an erase operation, or another operation to be performed by the memory device. In the example shown, the first request is a request to program the first data into the memory device.

[0105] In some implementations, the storage device includes a first buffer, a second buffer, and a third buffer. In some implementations, the third buffer includes a plurality of data buffers. In some examples, the first buffer may be implemented as a cache storage device 708 or a cache buffer 804, the second buffer may be implemented as a storage unit 710 or an internal buffer 804, and the third buffer may be implemented as a data storage unit 706 or a data buffer 806.

[0106] After receiving the first portion of the first data from the memory controller, the memory device stores the first portion of the first data in a first data buffer of a first buffer or a third buffer of the memory device (1304).

[0107] The storage device may store the first portion of the first data in the first buffer and move the first portion of the first data from the first buffer to the first data buffer of the third buffer before storing the first portion of the first data in the first data buffer of the third buffer.

[0108] After receiving the first portion of the first data, the memory device receives a second request from the memory controller (1306). In some implementations, the second request is associated with a second operation having a higher execution priority than the first operation, so that the first operation can be suspended and preempted by the second operation. As an example, the second request can be a request to read data from a storage device. As another example, the second request can be a request to program data other than the first data into the memory device.

[0109] After receiving the second request from the memory controller, the memory device may interrupt or stop the current operation. The memory device may also store the received data for the first operation and the context of the execution state of the first operation in the internal memory of the memory device. In the example shown, in response to receiving the second request, the memory device moves the first portion of the first data from the first buffer to the second buffer of the memory device, or moves the first portion of the first data from the first data buffer of the third buffer to the second buffer of the memory device when the first portion of the first data has been moved from the first buffer to the first data buffer (1308). By moving the first portion of the first data to the second buffer, the memory device can free up space in the first buffer or the third buffer for the operation indicated by the second request.

[0110] After moving the first portion of the first data to the second buffer, the memory device continues to perform the second operation after the first operation (e.g., programming operation) is suspended, resulting in little or no delay in servicing the second request. In a memory system operating with a mixed workload, pausing the data transfer of the first operation enables the second operation to be serviced without having to wait for the transfer of the remaining data to complete the ongoing first operation. Therefore, the latency of the memory system can be significantly reduced in some instances.

[0111] In the example shown, the memory device performs a second operation (1310) without using a second buffer in response to the second request. In some examples, when the second request includes an SLC program command for programming second data into the memory device, the memory device may store the second data in the first buffer, move the second data from the first buffer to a third buffer, and program the second data into a memory cell array of the memory device. In some examples where the second request includes a read command for reading data from the memory device, the memory device may read data from the memory cell array, store the data in a third buffer, move the data from the third buffer to the first buffer, and send the data from the first buffer to the memory controller.

[0112] After performing the second operation in response to the second request, the memory device sends the result of the execution of the second request to the memory controller (1312). For example, as a result of performing the read operation indicated by the second request, the memory device may send data obtained from the memory cell array of the memory device. As another example, when the second request indicates an operation to program data into the memory device, the memory device may send an indication to the memory controller, thereby indicating that the data has been programmed into the memory cell array of the memory device.

[0113] In addition to sending the execution result of the second request to the memory controller, the memory device also moves the first portion of the first data from the second buffer to the third buffer. In some examples where the memory device moves the first portion of the first data from a data buffer of the third buffer to the second buffer before satisfying the second request, the memory device may move the first portion of the first data from the second buffer back to the same data buffer of the third buffer.

[0114] The memory device continues to receive the second portion of the first data from the memory controller (1314) and stores the second portion of the first data in the second data buffer of the third buffer (1316). In some examples, before storing the second portion of the first data in the second data buffer of the third buffer, the memory device stores the second portion of the first data in the first buffer of the memory device and moves the second portion of the first data from the first buffer to the second data buffer of the third buffer.

[0115] After all portions of the first data have been received by the memory device and stored in the third buffer, the memory device performs a first operation in response to the first request. For example, the memory device may perform a programming operation to program the first data including the first portion and the second portion into a memory cell array of the memory device.

[0116] In some implementations, before performing the first operation in response to the first request, the memory device may receive an indication from the memory controller indicating that all data of the first request has been sent. For example, the memory controller may send an indication of data transfer completion of the first data to the memory device.

[0117] According to one aspect of the present disclosure, a method performed by a memory device is disclosed. The method includes: a memory device including a first buffer, a second buffer, and a third buffer receives a first portion of first data of a first request from a memory controller, wherein the first request includes at least the first portion of the first data and the second portion of the first data, and wherein the third buffer includes a plurality of data buffers; the memory device stores the first portion of the first data in a first data buffer of the first buffer or the third buffer; the memory device receives a second request from the memory controller; in response to the second request, the memory device moves the first portion of the first data from the first buffer or the first data buffer of the third buffer to the second buffer; the memory device performs an operation without using the second buffer in response to the second request; the memory device sends an execution result of the second request to the memory controller; the memory device receives the second portion of the first data from the memory controller; and the memory device stores the second portion of the first data in a second data buffer of the third buffer.

[0118] In some implementations, the method further includes: the memory device moving the first portion of the first data from the second buffer to the first data buffer of the third buffer; the memory device performing an operation using the first portion and the second portion of the first data in the third buffer in response to the first request; and the memory device sending an execution result of the first request to the memory controller.

[0119] In some implementations, the first request includes a triple-level cell (TLC) program command or a quad-level cell (QLC) program command. The memory device performing the operation in response to the first request includes: the memory device programming the first portion and the second portion of the first data of the first request in the third buffer into an array of memory cells of the memory device.

[0120] In some implementations, the second request includes a single-level cell (SLC) program command for programming second data into the memory device. The memory device performs the operation without using the second buffer in response to the second request, including: the memory device stores the second data in the first buffer; the memory device moves the second data from the first buffer to the first data buffer of the third buffer; and the memory device programs the second data into an array of memory cells of the memory device.

[0121] In some implementations, the second request includes a read command.

[0122] In some implementations, the method further includes: the memory device receiving a pause request requesting the memory device to suspend a current operation and execute the second request; and after sending an execution result of the second request to the memory controller, the memory device resuming one or more operations of the first request.

[0123] In some implementations, storing, by the storage device, the second portion of the first data in the second data buffer of the third buffer includes: storing, by the storage device, the second portion of the first data in the first buffer; and moving, by the storage device, the second portion of the first data from the first buffer to the second data buffer of the third buffer.

[0124] According to another aspect of the present disclosure, a memory device is disclosed. The memory device includes: a first buffer; a second buffer; a third buffer, the third buffer including a plurality of data buffers; an array of memory cells; and control logic. The control logic is coupled to at least one memory storing programming instructions, and the programming instructions, when executed by the control logic, cause the memory device to perform operations including: receiving a first portion of first data of a first request from a memory controller, wherein the first request includes at least the first portion of the first data and the second portion of the first data; storing the first portion of the first data in a first data buffer of the first buffer or the third buffer; receiving a second request from the memory controller; moving the first portion of the first data from the first data buffer of the first buffer or the third buffer to the second buffer in response to the second request; performing an operation without using the second buffer in response to the second request; sending the execution result of the second request to the memory controller; receiving the second portion of the first data from the memory controller; and storing the second portion of the first data in a second data buffer of the third buffer.

[0125] In some implementations, the operation also includes: moving the first portion of the first data from the second buffer to the first data buffer of the third buffer; performing an operation using the first portion and the second portion of the first data in the third buffer in response to the first request; and sending an execution result of the first request to the memory controller.

[0126] In some implementations, the first request includes a triple-level cell (TLC) program command or a quad-level cell (QLC) program command. Performing the operation in response to the first request includes programming the first portion and the second portion of the first data in the third buffer into an array of memory cells of the memory device.

[0127] In some implementations, the second request includes a single-level cell (SLC) program command for programming second data into the memory device. Performing the operation without using the second buffer in response to the second request includes: storing the second data in the first buffer; moving the second data from the first buffer to the first data buffer of the third buffer; and programming the second data into an array of memory cells of the memory device.

[0128] In some implementations, the second request includes a read command.

[0129] In some implementations, the operation includes: receiving a suspend request requesting the memory device to suspend current operations and execute the second request; and resuming one or more operations of the first request after sending an execution result of the second request to the memory controller.

[0130] In some implementations, storing the second portion of the first data in the second data buffer of the third buffer includes: storing the second portion of the first data in the first buffer; and moving the second portion of the first data from the first buffer to the second data buffer of the third buffer.

[0131] According to another aspect of the present disclosure, a system including a memory device and a memory controller is disclosed. The memory device includes: a first buffer; a second buffer; a third buffer, the third buffer including a plurality of data buffers; an array of memory cells; and control logic. The control logic is coupled to at least one memory storing programming instructions, and the programming instructions, when executed by the control logic, cause the memory device to perform operations including: receiving a first portion of first data of a first request from the memory controller, wherein the first request includes at least the first portion of the first data and the second portion of the first data; storing the first portion of the first data in a first data buffer of the first buffer or the third buffer; receiving a second request from the memory controller; moving the first portion of the first data from the first data buffer of the first buffer or the third buffer to the second buffer in response to the second request; performing an operation without using the second buffer in response to the second request; sending the execution result of the second request to the memory controller; receiving the second portion of the first data from the memory controller; and storing the second portion of the first data in a second data buffer of the third buffer.

[0132] In some implementations, the first request includes a triple level cell (TLC) program command or a quad level cell (QLC) program command.

[0133] In some implementations, the second request includes a single-level cell (SLC) program command.

[0134] In some implementations, the second request includes a read command.

[0135] In some implementations, the memory controller includes a cache and a processor coupled to the cache, and the processor is configured to: store the second portion of the first data in the cache of the memory controller before sending the second portion of the first data to the memory device, wherein a size of the second portion of the first data does not exceed a size of the cache of the memory controller.

[0136] In some implementations, the size of the first data exceeds the size of the cache of the memory controller, and the processor is further configured to: store the first portion of the first data in the cache of the memory controller before sending the first portion of the first data to the memory device, wherein the size of the first portion of the first data does not exceed the size of the cache of the memory controller.

[0137] The foregoing description of specific implementations can be readily modified and / or adapted for various applications. Therefore, based on the teaching and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed implementations.

[0138] The breadth and scope of the present disclosure should not be limited by any of the above-described example implementations, but should be defined only in accordance with the following claims and their equivalents. Accordingly, other implementations are within the scope of the claims.

Claims

1. A method comprising: A memory device including a first buffer, a second buffer, and a third buffer receives a first portion of first data of a first request from a memory controller, wherein the first request includes at least the first portion of the first data and a second portion of the first data, and wherein the third buffer includes a plurality of data buffers; The storage device stores the first portion of the first data in a first data buffer of the first buffer or the third buffer; The memory device receives a second request from the memory controller; In response to the second request, the memory device moves the first portion of the first data from the first data buffer of the first buffer or the third buffer to the second buffer; the memory device performing an operation without using the second buffer in response to the second request; The memory device sends the execution result of the second request to the memory controller; The memory device receives the second portion of the first data from the memory controller; and The memory device stores the second portion of the first data in a second data buffer of the third buffer.

2. The method according to claim 1, further comprising: the storage device moving the first portion of the first data from the second buffer to the first data buffer of the third buffer; the memory device performing an operation using the first portion and the second portion of the first data in the third buffer in response to the first request; as well as The memory device transmits an execution result of the first request to the memory controller.

3. The method according to claim 2, wherein: The first request includes a triple-level cell (TLC) program command or a quad-level cell (QLC) program command; as well as The memory device performing the operation in response to the first request includes: The memory device programs the first portion and the second portion of the first data of the first request in the third buffer into an array of memory cells of the memory device.

4. The method according to claim 1, wherein: The second request includes a single level cell (SLC) program command for programming second data into the memory device; as well as The memory device performing the operation without using the second buffer in response to the second request includes: The storage device stores the second data in the first buffer; The memory device moves the second data from the first buffer to the first data buffer of the third buffer; and The memory device programs the second data into an array of memory cells of the memory device.

5. The method according to claim 1, wherein: The second request includes a read command.

6. The method according to claim 1, further comprising: receiving, by the storage device, a suspend request requesting the storage device to suspend a current operation and execute the second request; as well as After sending the execution result of the second request to the memory controller, the memory device resumes one or more operations of the first request.

7. The method according to claim 1, wherein: The storage device storing the second part of the first data in the second data buffer of the third buffer comprises: The storage device stores the second portion of the first data in the first buffer; and The memory device moves the second portion of the first data from the first buffer to the second data buffer of the third buffer.

8. A storage device, comprising: First buffer; Second buffer; a third buffer, the third buffer comprising a plurality of data buffers; an array of storage cells; as well as control logic coupled to at least one memory storing programming instructions that, when executed by the control logic, cause the memory device to perform operations comprising: receiving a first portion of first data of a first request from a memory controller, wherein the first request includes at least the first portion of the first data and a second portion of the first data; storing the first portion of the first data in a first data buffer of the first buffer or the third buffer; receiving a second request from the memory controller; In response to the second request, moving the first portion of the first data from the first data buffer of the first buffer or the third buffer to the second buffer; performing an operation without using the second buffer in response to the second request; sending the execution result of the second request to the memory controller; receiving the second portion of the first data from the memory controller; and The second portion of the first data is stored in a second data buffer of the third buffer.

9. The memory device according to claim 8, wherein: The operations also include: moving the first portion of the first data from the second buffer to the first data buffer of the third buffer; performing an operation using the first portion and the second portion of the first data in the third buffer in response to the first request; and The execution result of the first request is sent to the memory controller.

10. The memory device according to claim 9, wherein: The first request includes a triple-level cell (TLC) program command or a quad-level cell (QLC) program command; as well as Performing the operation in response to the first request includes: The first portion and the second portion of the first data in the third buffer are programmed into an array of memory cells of the memory device.

11. The memory device according to claim 8, wherein: The second request includes a single level cell (SLC) program command for programming second data into the memory device; as well as Performing the operation without using the second buffer in response to the second request includes: storing the second data in the first buffer; moving the second data from the first buffer to the first data buffer of the third buffer; and The second data is programmed into an array of memory cells of the memory device.

12. The memory device according to claim 8, wherein: The second request includes a read command.

13. The memory device according to claim 8, wherein: The operations include: receiving a suspend request requesting the storage device to suspend a current operation and execute the second request; and After sending the execution result of the second request to the memory controller, one or more operations of the first request are resumed.

14. The memory device according to claim 8, wherein: Storing the second portion of the first data in the second data buffer of the third buffer comprises: storing the second portion of the first data in the first buffer; and The second portion of the first data is moved from the first buffer to the second data buffer of the third buffer.

15. A system comprising a memory controller and a memory device, wherein: The storage device comprises: First buffer; Second buffer; a third buffer, the third buffer comprising a plurality of data buffers; an array of memory cells; and control logic coupled to at least one memory storing programming instructions that, when executed by the control logic, cause the memory device to perform operations comprising: receiving, from the memory controller, a first portion of first data of a first request, wherein the first request includes at least the first portion of the first data and a second portion of the first data; storing the first portion of the first data in a first data buffer of the first buffer or the third buffer; receiving a second request from the memory controller; In response to the second request, moving the first portion of the first data from the first data buffer of the first buffer or the third buffer to the second buffer; performing an operation without using the second buffer in response to the second request; sending the execution result of the second request to the memory controller; receiving the second portion of the first data from the memory controller; and The second portion of the first data is stored in a second data buffer of the third buffer.

16. The system of claim 15, wherein: The first request includes a triple level cell (TLC) program command or a quad level cell (QLC) program command.

17. The system of claim 15, wherein: The second request includes a single level cell (SLC) program command.

18. The system of claim 15, wherein: The second request includes a read command.

19. The system of claim 15, wherein: The memory controller includes a cache and a processor coupled to the cache, and wherein the processor is configured to: The second portion of the first data is stored in the cache of the memory controller before sending the second portion of the first data to the memory device, wherein a size of the second portion of the first data does not exceed a size of the cache of the memory controller.

20. The system of claim 19, wherein: The size of the first data exceeds the size of the cache of the memory controller, and the processor is further configured to: The first portion of the first data is stored in the cache of the memory controller before sending the first portion of the first data to the memory device, wherein a size of the first portion of the first data does not exceed the size of the cache of the memory controller.

Images