Double-CPU (central processing unit) synchronization system and method and method for CPU to execute interrupt service

Abstract

The invention relates to a double-CPU (Central Processing Unit) synchronization system and method and a method for executing interrupt service by CPUs. The system comprises the two CPUs which are the same and operate independently; the first logic module is used for sending trigger signals to the two first INTs when it is determined that the first IO ports of the two CPUs send pulse signals at the same time; the second logic module is used for sending trigger signals to the two second INTs when it is determined that the data signals transmitted by the n data IOs of the two CPUs at the same time are different; the two CPUs respectively execute the following interrupt services when respective internal timers overflow: a pulse signal is output through a first IO, and after a first INT receives a trigger signal, a SysTick timer is reset; wherein the set overflow time of the internal timer is the same as that of the SysTick timer; and outputting a data signal through the n data IOs, and executing CPU resetting after the second INT receives the trigger signal. Therefore, internal timer synchronization (namely heartbeat synchronization) and instruction level synchronization of the two CPUs are realized, namely, synchronous operation of the two CPUs is realized.

Description

Technical Field

[0001] The present application relates to the technical field of embedded systems, and in particular to a dual CPU synchronization system and method, and a method for CPU to execute interrupt services. Background Art

[0002] In the field of embedded systems, the "2x2 take 2" system is widely used as a highly redundant structure. The system achieves redundancy in task execution through two identical and independent subsystems (i.e., the "2×2" structure), and the "take 2" mechanism ensures that only when at least two subsystems give the same result or state, the system will determine that the result or state is valid and output it, thereby greatly improving the safety and reliability of the system.

[0003] Existing "2x2get2" systems usually rely on complex hardware and software collaboration to synchronize the execution of programs by dual CPUs. Common synchronization schemes include:

[0004] Clock synchronization technology: Ensure the consistency of operations between CPUs by accessing a unified high-precision clock signal. This method requires a high-precision clock source as a basis.

[0005] Communication protocol: Use specific communication protocols (such as TSN switches or customized FPGAs) to achieve data transmission and instruction synchronization between CPUs. This approach can ensure timely and accurate delivery of instructions.

[0006] Hardware synchronization mechanism: Use hardware components such as latches and triggers to achieve instruction-level synchronization. This type of solution usually requires dedicated hardware support.

[0007] Redundant checking and error correction: Redundant information is introduced during instruction transmission and processing for checking and error correction to ensure the integrity and consistency of instructions.

[0008] Although the above solution meets the synchronization requirements to a certain extent, it also has many shortcomings:

[0009] High hardware cost: Since most application areas are not sensitive to cost, existing synchronization solutions mostly rely on high-cost hardware assistance, such as switches, FPGAs and other customized hardware, which increases the overall cost of the system.

[0010] Poor versatility: Different CPU platforms and system architectures often require different synchronization solutions, which results in poor versatility of existing synchronization solutions and makes them difficult to be widely used in different systems.

[0011] Coarse synchronization granularity: Existing synchronization solutions mostly focus on system-level or module-level synchronization, but are unable to cope with instruction-level or heartbeat-level synchronization, and are unable to meet application scenarios that require higher synchronization accuracy. Summary of the invention

[0012] In view of the above problems in the prior art, the present application provides a dual CPU synchronization system and method, and a method for CPU to execute interrupt services, which realize the internal timer synchronization (heartbeat synchronization) and instruction-level synchronization of the two CPUs, that is, realize the synchronous operation of the two CPUs and improve the reliability of the system.

[0013] To achieve the above object, the first aspect of the present application provides a dual CPU synchronization system, including:

[0014] Two identical and independently running CPUs, each with an interface including a first IO, a first INT, n data IOs, and a second INT;

[0015] The first logic module is connected to the first IO ports and the first INT ports of the two CPUs, and is used to send a trigger signal to the two first INT ports when it is determined that the first IO ports of the two CPUs send pulse signals at the same time;

[0016] The second logic module is connected to the n data IOs and the second INTs of the two CPUs, and is used to send a trigger signal to the two second INTs when it is determined that the data signals simultaneously transmitted by the n data IOs of the two CPUs are different;

[0017] The two CPUs each perform the following interrupt service when their respective internal timers overflow: output a pulse signal through the first IO, and reset the SysTick timer after the first INT receives a trigger signal; wherein the set internal timer overflow time is the same as the SysTick timer; output data signals through n data IOs, and execute CPU reset after the second INT receives a trigger signal.

[0018] Thus, in the present application, when the first IO ports of the two CPUs send out pulse signals at the same time, the first logic module sends a trigger signal to the first INT of the two CPUs to reset the SysTick timer. This mechanism can detect any timer asynchrony, thereby synchronizing the heartbeats of the two CPUs. When the second logic module detects that the data signals transmitted by the two CPUs through n data IOs are inconsistent, a trigger signal is sent to the second INT of the two CPUs to immediately reset the CPU when the asynchrony is detected, thereby preventing the accumulation and propagation of errors, thereby achieving synchronization of instructions between the two CPUs.

[0019] As a possible implementation manner of the first aspect, the first logic module includes:

[0020] An AND gate logic device has two input terminals connected to the respective first IOs of the two CPUs, and an output terminal connected in series with a first monostable trigger and then connected to the respective first INTs of the two CPUs.

[0021] In this way, when the internal timers of the two CPUs overflow, they will output pulse signals through the first IO port, and detect whether the two pulse signals occur at the same time through the first logic module. If it is detected that they occur at the same time, the heartbeat synchronization is considered successful, and a trigger signal is sent to the first INT of the two CPUs, thereby resetting the SysTick timer. In addition, the synchronization control between CPUs is realized through simple logic gates and monostable triggers, without the need for complex hardware equipment or algorithm support, reducing the overall complexity and cost of the system.

[0022] As a possible implementation manner of the first aspect, the second logic module includes:

[0023] There are n XOR gate logic devices, wherein the two input ends of each XOR gate logic device are connected to one of the n data IOs of the two CPUs, the output ends of the n XOR gate logic devices are connected to the input end of an OR gate logic device, and the output end of the OR gate logic device is connected in series with a second monostable trigger and then connected to the second INT of the two CPUs respectively.

[0024] In this way, through the detailed design of the second logic module, combined with logic devices such as XOR gates, OR gates and monostable triggers, efficient synchronization verification and error processing of the two CPU data signals are achieved, further improving the synchronization accuracy, reliability and economy of the system.

[0025] As a possible implementation manner of the first aspect, the data signals transmitted by the n data IOs include at least one of the following data signals:

[0026] The return address before executing the interrupt service, the top pointer value of the register stack, the value of the CPU status register, and the count value of the SysTick timer.

[0027] In this way, by comparing the data signals transmitted by the two CPUs, any asynchronous situation caused by hardware failure or software error can be detected. When an asynchronous situation is detected, the normal working state of the system can be restored by performing a reset operation, which is conducive to the subsequent synchronization of instructions between the two CPUs.

[0028] To achieve the above-mentioned object, the second aspect of the present application provides a dual CPU synchronization method, which is applied to the dual CPU synchronization system described in any one of the first aspects, and the method includes:

[0029] When the internal timer of each CPU overflows, the two CPUs output a pulse signal through their first IOs;

[0030] When the first logic module determines that the first IO ports of the two CPUs send pulse signals at the same time, a trigger signal is sent to the first INT ports of the two CPUs;

[0031] After the first INT of the two CPUs receives the trigger signal, the SysTick timer is reset; wherein the internal timer overflow time is set to be the same as the SysTick timer; and the data signal is output through n data IOs;

[0032] When the second logic module determines that the data signals transmitted simultaneously by the n data IOs of the two CPUs are different, a trigger signal is sent to the two second INTs;

[0033] After the second INTs of the two CPUs receive the trigger signal, the CPUs are reset.

[0034] In this way, when the first IO ports of the two CPUs send out pulse signals at the same time, the first logic module sends a trigger signal to the first INT of the two CPUs to reset the SysTick timer. This mechanism can detect any timer asynchrony, thereby synchronizing the heartbeats of the two CPUs. When the second logic module detects that the data signals transmitted by the two CPUs through n data IOs are inconsistent, a trigger signal is sent to the second INT of the two CPUs to immediately reset the CPU when asynchrony is detected, thereby preventing the accumulation and propagation of errors and achieving synchronization of instructions between the two CPUs.

[0035] As a possible implementation manner of the second aspect, the first logic module includes:

[0036] An AND gate logic device has two input terminals connected to the respective first IOs of the two CPUs, and an output terminal connected in series with a first monostable trigger and then connected to the respective first INTs of the two CPUs.

[0037] In this way, when the internal timers of the two CPUs overflow, they will output pulse signals through the first IO port, and detect whether the two pulse signals occur at the same time through the first logic module. If it is detected that they occur at the same time, the heartbeat synchronization is considered successful, and a trigger signal is sent to the first INT of the two CPUs, thereby resetting the SysTick timer. In addition, the synchronization control between CPUs is realized through simple logic gates and monostable triggers, without the need for complex hardware equipment or algorithm support, reducing the overall complexity and cost of the system.

[0038] As a possible implementation manner of the second aspect, the second logic module includes:

[0039] There are n XOR gate logic devices, wherein the two input ends of each XOR gate logic device are connected to one of the n data IOs of the two CPUs, the output ends of the n XOR gate logic devices are connected to the input end of an OR gate logic device, and the output end of the OR gate logic device is connected in series with a second monostable trigger and then connected to the second INT of the two CPUs respectively.

[0040] In this way, through the detailed design of the second logic module, combined with logic devices such as XOR gates, OR gates and monostable triggers, efficient synchronization verification and error processing of the two CPU data signals are achieved, further improving the synchronization accuracy, reliability and economy of the system.

[0041] As a possible implementation manner of the second aspect, the data signals transmitted by the n data IOs include at least one of the following data signals:

[0042] The return address before executing the interrupt service, the top pointer value of the register stack, the value of the CPU status register, and the count value of the SysTick timer.

[0043] In this way, by comparing the data signals transmitted by the two CPUs, any asynchronous situation caused by hardware failure or software error can be detected. When an asynchronous situation is detected, the normal working state of the system can be restored by performing a reset operation, which is conducive to the subsequent synchronization of instructions between the two CPUs.

[0044] As a possible implementation manner of the second aspect, the method further includes: powering on the two CPUs simultaneously during startup of the devices where the two CPUs are located, and resetting the two CPUs.

[0045] In this way, powering on the two CPUs at the same time when the device starts can ensure that the two CPUs start running from the same initial state, avoiding the asynchronous problem caused by different power-on sequences, and ensuring that the system is in a synchronized state from the beginning. In addition, when the two CPUs are reset, they will be reinitialized under the same conditions, thus ensuring that the states of the two CPUs are consistent after the reset, which helps to quickly restore the synchronous operation of the system after a failure.

[0046] To achieve the above-mentioned object, the third aspect of the present application provides a method for a CPU to execute an interrupt service, which is applied to the dual CPU synchronization system described in any one of the first aspects, and the method comprises: in response to an overflow of a CPU internal timer, executing the following:

[0047] Output a pulse signal through the first IO;

[0048] When a trigger signal is received through the first INT, the SysTick timer is reset; wherein the internal timer overflow time is set to be the same as the SysTick timer;

[0049] Output data signals through n data IOs;

[0050] When a trigger signal is received through the second INT, a CPU reset is executed.

[0051] In this way, by ensuring that the two CPUs output pulse signals synchronously when the internal timer overflows and immediately performing a reset operation when an asynchronous situation is detected, not only the system reliability is improved, but also the fault detection and recovery process is simplified, ensuring data consistency and system stability.

[0052] To achieve the above-mentioned object, the fourth aspect of the present application provides a computing device, including:

[0053] processor, and

[0054] A memory having program instructions stored thereon, wherein when the program instructions are executed by the processor, the processor executes the synchronization method described in any one of the second aspect and the method for CPU to execute interrupt service described in the third aspect.

[0055] To achieve the above-mentioned objectives, the fifth aspect of the present application provides a computer-readable storage medium on which program instructions are stored. When the program instructions are executed by a computer, the computer implements the synchronization method described in any one of the second aspect and the method of CPU executing interrupt service described in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a circuit diagram of a dual CPU synchronization system provided by the present application;

[0057] Figure 2 It is a flow chart of the main steps of a dual CPU synchronization method provided by the present application;

[0058] Figure 3 It is a structural schematic diagram of a computing device provided by the present application.

[0059] It should be understood that the size and shape of each block diagram in the above structural diagram are for reference only and should not constitute an exclusive interpretation of the embodiment of the present invention. The relative position and inclusion relationship between the blocks presented in the structural diagram are only schematic representations of the structural association between the blocks, and do not limit the physical connection method of the embodiment of the present invention. DETAILED DESCRIPTION

[0060] The technical solution provided by the present application is further described below with reference to the accompanying drawings and examples. It should be understood that the system structure and business scenarios provided in the examples of the present application are mainly to illustrate the possible implementation methods of the technical solution of the present application and should not be interpreted as the only limitation on the technical solution of the present application. It is known to those of ordinary skill in the art that with the evolution of the system structure and the emergence of new business scenarios, the technical solution provided by the present application is also applicable to similar technical problems.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. In case of any inconsistency, the meaning described in this specification or the meaning derived from the contents recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0062] The present application embodiment provides a dual CPU synchronization system, such as Figure 1 As shown, including:

[0063] Two identical and independently running CPUs, each with an interface including a first IO, a first INT, n data IOs, and a second INT;

[0064] The first logic module is connected to the first IO ports and the first INT ports of the two CPUs, and is used to send a trigger signal to the two first INT ports when it is determined that the first IO ports of the two CPUs send pulse signals at the same time;

[0065] The second logic module is connected to the n data IOs and the second INTs of the two CPUs, and is used to send a trigger signal to the two second INTs when it is determined that the data signals simultaneously transmitted by the n data IOs of the two CPUs are different;

[0066] The two CPUs each perform the following interrupt service when their respective internal timers overflow: output a pulse signal through the first IO, and reset the SysTick timer after the first INT receives a trigger signal; wherein the set internal timer overflow time is the same as the SysTick timer; output data signals through n data IOs, and execute CPU reset after the second INT receives a trigger signal.

[0067] The value of n is related to the system bandwidth, n = system bit width / 2. The system bit width refers to the data width that the processor in the computer system can directly process, that is, the size of the CPU register or the width of the data bus.

[0068] For example, for an 8-bit system, n = 8 / 2 = 4, which means that 4 XOR gates are required;

[0069] For a 32-bit system, n=32 / 2=16, which means 16 XOR gates are required.

[0070] It is worth noting that the SysTick timer is usually used as the heartbeat clock of the operating system to generate periodic interrupts, thereby helping the operating system manage time, schedule tasks and other timed operations. The internal timer is a physical device that implements the SysTick function and is responsible for actual time measurement and interrupt triggering. The details are as follows:

[0071] The SysTick timer is set to 1 millisecond (ms), which means that the system will generate an interrupt every 1 millisecond and enter the SysTick interrupt service function. In this function, the system can perform time-related task scheduling, update system time variables, and other operations.

[0072] The internal timer is the physical device that actually performs the timing function. The internal timer is configured to generate an interrupt every 1 millisecond. This interrupt will be used to trigger SysTick.

[0073] In this way, when the first IO ports of the two CPUs send out pulse signals at the same time, the first logic module sends a trigger signal to the first INT of the two CPUs to reset the SysTick timer. This mechanism can detect any timer asynchrony, thereby synchronizing the heartbeats of the two CPUs. When the second logic module detects that the data signals transmitted by the two CPUs through n data IOs are inconsistent, a trigger signal is sent to the second INT of the two CPUs to immediately reset the CPU when asynchrony is detected, thereby preventing the accumulation and propagation of errors and achieving synchronization of instructions between the two CPUs.

[0074] In some embodiments, the first logic module includes:

[0075] An AND gate logic device has two input terminals connected to the respective first IOs of the two CPUs, and an output terminal connected in series with a first monostable trigger and then connected to the respective first INTs of the two CPUs.

[0076] Among them, the AND gate logic device ensures that only when the first IO ports of the two CPUs send out pulse signals at the same time, a high-level signal will be output. This mechanism strictly controls the triggering conditions of synchronization and avoids false triggering caused by the pulse signal of a single CPU.

[0077] The first monostable trigger can be used to generate a pulse signal of a fixed length. Specifically, when the SysTick interrupts of the two CPUs occur, they each output a short high-level pulse through the I / O port. After the two pulses pass through the AND gate logic device, if both are valid at the same time, the first monostable trigger will be triggered, causing it to output a low-level signal to the first INT of the two CPUs. This signal causes the two CPUs to reinitialize the SysTick timer, thereby ensuring the synchronization of the SysTick timer.

[0078] In this way, when the internal timers of the two CPUs overflow, they will output pulse signals through the first IO port, and detect whether the two pulse signals occur at the same time through the first logic module. If it is detected that they occur at the same time, the heartbeat synchronization is considered successful, and a trigger signal is sent to the first INT of the two CPUs, thereby resetting the SysTick timer. In addition, the synchronization control between CPUs is realized through simple logic gates and monostable triggers, without the need for complex hardware equipment or algorithm support, reducing the overall complexity and cost of the system.

[0079] In some embodiments, the second logic module includes:

[0080] There are n XOR gate logic devices, wherein the two input ends of each XOR gate logic device are connected to one of the n data IOs of the two CPUs, the output ends of the n XOR gate logic devices are connected to the input end of an OR gate logic device, and the output end of the OR gate logic device is connected in series with a second monostable trigger and then connected to the second INT of the two CPUs respectively.

[0081] Each device is described in detail below.

[0082] XOR gate logic device: used to compare two input signals. If the two input signals are the same, the output is low (0); if the two input signals are different, the output is high (1).

[0083] OR gate logic device: used to implement logical OR operation. As long as any input is high, the output is high.

[0084] The second monostable trigger: after receiving the trigger signal output by the OR gate logic device, it will output a pulse signal with a fixed width.

[0085] Specifically, each XOR gate logic device is connected to one of the n data IOs of the two CPUs, respectively, to compare whether the data signals output by the two CPUs through their respective data IOs at the same time are consistent. The output ends of the n XOR gate logic devices are connected to the input ends of the OR gate logic device, so that when any XOR gate outputs a high level (that is, when the corresponding data IOs of the two CPUs are inconsistent), the OR gate will output a high level. After the second monostable trigger receives the high level signal output by the OR gate logic device, it will output a pulse signal to the second INT pins of the two CPUs, which is used to trigger an interrupt and perform a corresponding reset or synchronization operation. This ensures that the two CPUs can keep in sync at the instruction level, improving the reliability and security of the system.

[0086] In this way, through the detailed design of the second logic module, combined with logic devices such as XOR gates, OR gates and monostable triggers, efficient synchronization verification and error processing of the two CPU data signals are achieved, further improving the synchronization accuracy, reliability and economy of the system.

[0087] In some embodiments, the data signals transmitted by the n data IOs include at least one of the following data signals:

[0088] The return address before executing the interrupt service, the top pointer value of the register stack, the value of the CPU status register, and the count value of the SysTick timer.

[0089] In this way, by comparing the data signals transmitted by the two CPUs, any asynchronous situation caused by hardware failure or software error can be detected. When an asynchronous situation is detected, the normal working state of the system can be restored by performing a reset operation, which is conducive to the subsequent synchronization of instructions between the two CPUs.

[0090] Among them, the above four data signals are outputted through their respective data IO ports. That is to say, in the output process, there are four independent data IO ports. For example, the data signal transmitted by the first data IO is the return address before executing the interrupt service, the data signal transmitted by the second data IO is the stack top pointer value of the register stack, the data signal transmitted by the third data IO is the value of the CPU status register, and the data signal transmitted by the fourth data IO is the count value of the SysTick timer.

[0091] However, in some embodiments, for example including 8 data IOs, see Figure 1 As shown, the data signals transmitted by the fifth to eighth data IOs may be, but are not limited to, the following program counter, instruction register, general register or conditional code register.

[0092] Expandable, in addition to the four data signals mentioned above (the return address before executing the interrupt service, the stack top pointer value of the register stack, the value of the CPU status register, and the count value of the SysTick timer), there are other data signals that can be used to determine whether two CPU instructions are synchronized.

[0093] For example: Program Counter (PC): The address of the instruction currently being executed. If the PCs of two CPUs are the same, it means that they are executing the same instruction.

[0094] Instruction Register (IR): The place in the CPU where the instruction currently being decoded is stored. If the IRs of two CPUs are the same, it means that they are decoding the same instruction.

[0095] General Purpose Registers (GPRs): Registers in the CPU that store data. Comparing certain general purpose registers (such as accumulators, index registers, etc.) can help confirm whether the data states of two CPUs are consistent.

[0096] Condition Code Register (CCR): The condition code register contains various flags, such as zero flag (Z), carry flag (C), borrow flag (V), etc. These flags reflect the results of the most recently executed instruction.

[0097] Interrupt Mask Register (IMR): If the system supports interrupts, the interrupt mask register can be used to determine which interrupts are enabled or disabled. If the IMRs of two CPUs are the same, then their response strategies for interrupts are consistent.

[0098] Floating Point Registers: For CPUs that support floating-point operations, the state of the floating-point registers is also an important synchronization reference.

[0099] Memory-Mapped Registers: Some registers are accessed through memory mapping, such as I / O registers. The status of these registers can also be used to confirm synchronization.

[0100] Memory address and data: Data in certain key memory areas can also be used to confirm synchronization, especially shared memory areas, to ensure that the operations of two CPUs on the same memory area are consistent.

[0101] In practical applications, the values ​​selected to confirm instruction synchronization depend on the specific application scenario and system design, and are not specifically limited here to meet the needs of different scenarios and improve design flexibility.

[0102] The present application embodiment provides a dual CPU synchronization method, such as Figure 2 As shown, the dual CPU synchronization system described above includes:

[0103] S201, when the internal timer of each CPU overflows, each CPU outputs a pulse signal through the first IO;

[0104] S202, when the first logic module determines that the first IO ports of the two CPUs send pulse signals at the same time, a trigger signal is sent to the first INT ports of the two CPUs;

[0105] S203, after the first INT of the two CPUs receives the trigger signal, the SysTick timer is reset; wherein the internal timer overflow time is set to be the same as the SysTick timer; and the data signal is output through n data IOs;

[0106] S204, when the second logic module determines that the data signals simultaneously transmitted by the n data IOs of the two CPUs are different, a trigger signal is sent to the two second INTs;

[0107] S205 , after the second INTs of the two CPUs receive the trigger signal, they execute CPU reset.

[0108] In this way, when the first IO ports of the two CPUs send out pulse signals at the same time, the first logic module sends a trigger signal to the first INT of the two CPUs to reset the SysTick timer. This mechanism can detect any timer asynchrony, thereby synchronizing the heartbeats of the two CPUs. When the second logic module detects that the data signals transmitted by the two CPUs through n data IOs are inconsistent, a trigger signal is sent to the second INT of the two CPUs to immediately reset the CPU when asynchrony is detected, thereby preventing the accumulation and propagation of errors and achieving synchronization of instructions between the two CPUs.

[0109] In some embodiments, the first logic module includes: an AND gate logic device, whose two input ends are connected to the respective first IOs of the two CPUs, and whose output ends are connected in series with the first monostable trigger and then respectively connected to the respective first INTs of the two CPUs.

[0110] In this way, when the internal timers of the two CPUs overflow, they will output pulse signals through the first IO port, and detect whether the two pulse signals occur at the same time through the first logic module. If it is detected that they occur at the same time, the heartbeat synchronization is considered successful, and a trigger signal is sent to the first INT of the two CPUs, thereby resetting the SysTick timer. In addition, the synchronization control between CPUs is realized through simple logic gates and monostable triggers, without the need for complex hardware equipment or algorithm support, reducing the overall complexity and cost of the system.

[0111] In some embodiments, the second logic module includes: n XOR gate logic devices, wherein the two input ends of each XOR gate logic device are connected to one of the n data IOs of the two CPUs, the output ends of the n XOR gate logic devices are connected to the input end of an OR gate logic device, and the output end of the OR gate logic device is connected in series with a second monostable trigger and then connected to the second INT of the two CPUs respectively.

[0112] In this way, through the detailed design of the second logic module, combined with logic devices such as XOR gates, OR gates and monostable triggers, efficient synchronization verification and error processing of the two CPU data signals are achieved, further improving the synchronization accuracy, reliability and economy of the system.

[0113] For the first logic module and the second logic module, an implementation method is provided above. It is not difficult to understand that other multiple logic devices (AND, NOT, OR, XOR, XNOR and other gate logic devices) or other methods can also be used to build. For example, AND gate, OR gate and NOT gate are the most basic gate logic devices, and AND gate, OR gate and NOT gate can be used to build XOR gate logic devices. For another example, multiple OR gates can be used to build a multi-channel OR gate.

[0114] In some embodiments, the data signals transmitted by the n data IOs include at least one of the following data signals:

[0115] The return address before executing the interrupt service, the top pointer value of the register stack, the value of the CPU status register, and the count value of the SysTick timer.

[0116] In this way, by comparing the data signals transmitted by the two CPUs, any asynchronous situation caused by hardware failure or software error can be detected. When an asynchronous situation is detected, the normal working state of the system can be restored by performing a reset operation, which is conducive to the subsequent synchronization of instructions between the two CPUs.

[0117] In some embodiments, the method further includes: powering on the two CPUs at the same time during the startup process of the devices where the two CPUs are located, and resetting the two CPUs.

[0118] In this way, powering on the two CPUs at the same time when the device starts can ensure that the two CPUs start running from the same initial state, avoiding the asynchronous problem caused by different power-on sequences, and ensuring that the system is in a synchronized state from the beginning. In addition, when the two CPUs are reset, they will be reinitialized under the same conditions, thus ensuring that the states of the two CPUs are consistent after the reset, which helps to quickly restore the synchronous operation of the system after a failure.

[0119] In order to more clearly illustrate the above method, the present application provides a specific embodiment.

[0120] This embodiment is described by taking a system bit width of 16 as an example.

[0121] like Figure 1 As shown, the dual CPU synchronization system includes the following:

[0122] The two identical and independently running CPUs are CPU1 and CPU2, and their respective interfaces include a first IO, a first INT, n data IOs and a second INT.

[0123] The first logic module includes an AND gate logic device, two input ends of which are connected to the first IO of the two CPUs, and an output end of which is connected in series with a first monostable trigger and then connected to the first INT of the two CPUs.

[0124] The second logic module includes: n XOR gate logic devices, wherein two input ends of each XOR gate logic device are connected to one of the n data IOs of the two CPUs, the output ends of the n XOR gate logic devices are connected to the input end of an OR gate logic device, and the output end of the OR gate logic device is connected in series with a second monostable trigger and then connected to the second INT of the two CPUs respectively;

[0125] The number of XOR gate logic devices is related to the system bit width, specifically n=system bit width / 2. In this embodiment, for a 16-bit system, 8 XOR gate logic devices are required (16 / 2=8).

[0126] According to the above dual CPU synchronization system, the dual CPU synchronization method process is as follows:

[0127] Before starting the implementation, make sure all hardware components are properly connected and the circuit schematic is free of faults and anomalies.

[0128] Step 1: During the startup process of the devices where CPU1 and CPU2 are located, they are powered on at the same time and start running;

[0129] Among them, CPU1 and CPU2 have the same clock and peripherals, and are loaded with the same execution program. They start running at the same time when powered on, forming a "2x" architecture.

[0130] Specifically, the crystal oscillator clock refers to the external crystal oscillator clock (Crystal Oscillator), for the following reasons:

[0131] The external crystal oscillator clock provides a highly stable clock signal that is not affected by CPU internal power supply voltage fluctuations or other factors, ensuring that the system clock signal is always accurate;

[0132] The frequency of the crystal oscillator clock is very accurate and usually has high frequency stability, which is very important for applications that require high-precision timing;

[0133] Using the same external crystal clock as the reference clock ensures clock synchronization between multiple CPUs or system components, which is very important for synchronization in a "2 by 2 take 2" system.

[0134] For example, suppose that in an embedded system, a 12MHz external crystal clock is used as the reference clock. This clock signal is distributed to various parts of the system through the system clock tree, including the CPU core, memory controller, peripherals, etc.

[0135] External crystal clock: 12MHz external crystal clock provides a reference clock signal.

[0136] System clock: This 12MHz reference clock signal may be divided by a frequency divider to generate a lower frequency system clock, such as 6MHz.

[0137] CPU core clock: The system clock may be further multiplied to 24MHz as the CPU core working clock. The multiplication means that the synchronization frequency has a finer granularity (it can synchronize at a higher frequency) and the synchronization level (precision) is higher.

[0138] Peripheral clock: The system clock provides appropriate clock signals for peripherals through a divider, such as 3MHz for timers.

[0139] Based on the above, in the "2 times 2 take 2" system, the two CPUs share the same external crystal clock. This means:

[0140] Crystal oscillator clock: CPU1 and CPU2 share the same 12MHz external crystal oscillator clock as the reference clock.

[0141] System clock: The system clock signal (e.g. 6MHz) derived from this reference clock is also shared by the two CPUs.

[0142] CPU core clock: The system clock may be further multiplied to 24MHz as the core operating clock of the two CPUs.

[0143] Peripheral clock: The system clock provides appropriate clock signals for the peripherals of the two CPUs through a divider.

[0144] By sharing the same external crystal clock, the clock signals of the two CPUs can be synchronized, thus achieving more accurate instruction-level synchronization. This is very important for the redundant design in the "2x2 take 2" system, which can improve the reliability and safety of the system.

[0145] Step 2: Set the SysTick timer to 1ms, and set the internal timer overflow time to be the same as the SysTick timer;

[0146] Step 3: When the sysTick timer overflows, the system enters the interrupt service function;

[0147] Step 4: In the interrupt service function, CPU1 and CPU2 use the first IO port (corresponding to Figure 1 IO2 in the outputs a short high-level pulse signal, and the two pulse signals reach the AND gate logic device U12 through lines net4 and net5;

[0148] Specifically, if the pulse signals of the two CPUs are valid at the same time, the AND gate logic device U12 outputs 1 (ie, 1&1=1), and this result is further transmitted to the first monostable trigger U11.

[0149] Step 5: After the first monostable trigger U11 is triggered, it sends a signal to the first INT (corresponding to the first INT) of the two CPUs through the line net3. Figure 1 INT2 in sends a trigger signal;

[0150] Specifically, the trigger signal is used to make the two CPUs reinitialize the initial value of the SysTick timer in the interrupt service function, so that the 1ms timer starts counting again, thereby achieving the effect of synchronizing SysTick.

[0151] Step 6: After the first INT of the two CPUs receives the trigger signal, the SysTick timer is reset;

[0152] Step 7, CPU1 and CPU2 respectively output the following data signals, including the return address before executing the interrupt service, the stack top pointer value of the register stack, the value of the CPU status register, and the count value of the SysTick timer;

[0153] Step 8, the above data signal is input to 8 XOR gate logic devices (U1-U8), and the two input ends of each XOR gate logic device correspond to one of the 8 data IOs of CPU1 and CPU2 respectively;

[0154] Specifically, if the IO outputs of the two CPUs are the same at every moment, the result of each XOR gate logic device should output 0; if the IO data of the two CPUs are different, there must be one or more results of each XOR gate logic device outputting 1.

[0155] Step 9: If the outputs of all XOR gate logic devices are 0, the output of the OR gate logic device U9 is also 0, and the second monostable trigger U10 will not be triggered, indicating that the data of the two CPUs are synchronized;

[0156] Step 10: If the output of the XOR logic device is 1, the output of the OR logic device U9 is 1, triggering the second monostable trigger U10, and sending a trigger signal to the respective second INTs of the two CPUs; after the second INTs of the two CPUs receive the trigger signal, the dual CPUs reset themselves, indicating that the synchronization fails. Return to step 1, that is, reinitialize the SysTick timer.

[0157] The embodiment of the present application provides a method for CPU to execute interrupt service, which is applied to any of the above dual CPU synchronization systems. The method includes: responding to the overflow of the CPU internal timer, executing the following:

[0158] Output a pulse signal through the first IO;

[0159] When a trigger signal is received through the first INT, the SysTick timer is reset; wherein the internal timer overflow time is set to be the same as the SysTick timer;

[0160] Output data signals through n data IOs;

[0161] When a trigger signal is received through the second INT, a CPU reset is executed.

[0162] In this way, by ensuring that the two CPUs output pulse signals synchronously when the internal timer overflows and immediately performing a reset operation when an asynchronous situation is detected, not only the system reliability is improved, but also the fault detection and recovery process is simplified, ensuring data consistency and system stability.

[0163] Figure 3 3 is a schematic diagram of a computing device 300 provided in an embodiment of the present application. The computing device executes the above method, such as Figure 3 As shown, the computing device 300 includes: a processor 310 , a memory 320 , and a communication interface 330 .

[0164] It should be understood that Figure 3The communication interface 330 in the computing device 300 shown may be used to communicate with other devices, and may specifically include one or more transceiver circuits or interface circuits.

[0165] The processor 310 may be connected to a memory 320. The memory 320 may be used to store the program code and data. Therefore, the memory 320 may be a storage unit inside the processor 310, or an external storage unit independent of the processor 310, or a component including a storage unit inside the processor 310 and an external storage unit independent of the processor 310.

[0166] Optionally, the computing device 300 may further include a bus. The memory 320 and the communication interface 330 may be connected to the processor 310 via the bus. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 A line without an arrow is used to represent the bus, but this does not mean that there is only one bus or one type of bus.

[0167] It should be understood that in the embodiment of the present application, the processor 310 can adopt a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. Or the processor 310 uses one or more integrated circuits to execute related programs to implement the technical solutions provided in the embodiments of the present application.

[0168] The memory 320 may include a read-only memory and a random access memory, and provides instructions and data to the processor 310. A portion of the processor 310 may also include a non-volatile random access memory. For example, the processor 310 may also store information on the device type.

[0169] When the computing device 300 is running, the processor 310 executes the computer-executable instructions in the memory 320 to perform any operation step of the above method and any optional embodiment thereof.

[0170] It should be understood that the computing device 300 according to the embodiment of the present application can correspond to the corresponding subject in the method according to each embodiment of the present application, and the above-mentioned and other operations and / or functions of each module in the computing device 300 are respectively for realizing the corresponding process of each method of the present embodiment, which will not be repeated here for the sake of brevity.

[0171] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0172] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0173] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0174] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0175] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0176] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0177] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, it is used to execute the above method, which includes at least one of the solutions described in the above embodiments.

[0178] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive lists) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing programs, which can be used by instruction execution systems, devices or devices or used in combination with them.

[0179] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0180] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0181] Computer program code for performing the operation of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., using an Internet service provider to connect through the Internet).

[0182] In addition, the words "first, second, third, etc." or module A, module B, module C and other similar terms in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that the specific order or sequence can be interchanged where permitted so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0183] In the above description, the numbers representing the steps, such as S110, S120, etc., do not necessarily mean that the steps will be executed accordingly. If permitted, the order of the steps can be interchanged or they can be executed simultaneously.

[0184] The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the features, integers, steps or components mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components and groups thereof. Therefore, the expression "a device comprising means A and B" should not be limited to a device consisting of components A and B only.

[0185] References to "one embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. In addition, in one or more embodiments, the particular features, structures, or characteristics can be combined in any appropriate manner, as would be apparent to one of ordinary skill in the art from this disclosure.

[0186] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present application, all of which belong to the scope of protection of the present application.

Claims

1. A dual CPU synchronization system, characterized in that: include: Two identical and independently running CPUs, each with an interface including a first IO, a first INT, n data IOs, and a second INT; The first logic module is connected to the first IO ports and the first INT ports of the two CPUs, and is used to send a trigger signal to the two first INT ports when it is determined that the first IO ports of the two CPUs send pulse signals at the same time; The second logic module is connected to the n data IOs and the second INTs of the two CPUs, and is used to send a trigger signal to the two second INTs when it is determined that the data signals simultaneously transmitted by the n data IOs of the two CPUs are different; The two CPUs each perform the following interrupt service when their respective internal timers overflow: output a pulse signal through the first IO, and reset the SysTick timer after the first INT receives a trigger signal; wherein the set internal timer overflow time is the same as the SysTick timer; output data signals through n data IOs, and execute CPU reset after the second INT receives a trigger signal.

2. The system according to claim 1, characterized in that The first logic module includes: An AND gate logic device has two input terminals connected to the respective first IOs of the two CPUs, and an output terminal connected in series with a first monostable trigger and then connected to the respective first INTs of the two CPUs.

3. The system according to claim 1, characterized in that The second logic module includes: There are n XOR gate logic devices, wherein the two input ends of each XOR gate logic device are connected to one of the n data IOs of the two CPUs, the output ends of the n XOR gate logic devices are connected to the input end of an OR gate logic device, and the output end of the OR gate logic device is connected in series with a second monostable trigger and then connected to the second INT of the two CPUs respectively.

4. The system according to any one of claims 1 to 3, characterized in that: The data signals transmitted by the n data IOs include at least one of the following data signals: The return address before executing the interrupt service, the top pointer value of the register stack, the value of the CPU status register, and the count value of the SysTick timer.

5. A dual CPU synchronization method, characterized in that: Applied to the dual CPU synchronization system according to any one of claims 1 to 4, the method comprises: When the internal timer of each CPU overflows, the two CPUs output a pulse signal through their first IOs; When the first logic module determines that the first IO ports of the two CPUs send pulse signals at the same time, a trigger signal is sent to the first INT ports of the two CPUs; After the first INT of the two CPUs receives the trigger signal, the SysTick timer is reset; wherein the internal timer overflow time is set to be the same as the SysTick timer; and the data signal is output through n data IOs; When the second logic module determines that the data signals transmitted simultaneously by the n data IOs of the two CPUs are different, a trigger signal is sent to the two second INTs; After the second INTs of the two CPUs receive the trigger signal, the CPUs are reset.

6. The method according to claim 5, characterized in that The first logic module includes: An AND gate logic device has two input terminals connected to the respective first IOs of the two CPUs, and an output terminal connected in series with a first monostable trigger and then connected to the respective first INTs of the two CPUs.

7. The method according to claim 5, characterized in that The second logic module includes: There are n XOR gate logic devices, wherein the two input ends of each XOR gate logic device are connected to one of the n data IOs of the two CPUs, the output ends of the n XOR gate logic devices are connected to the input end of an OR gate logic device, and the output end of the OR gate logic device is connected in series with a second monostable trigger and then connected to the second INT of the two CPUs respectively.

8. The method according to any one of claims 5 to 7, characterized in that: The data signals transmitted by the n data IOs include at least one of the following data signals: The return address before executing the interrupt service, the top pointer value of the register stack, the value of the CPU status register, and the count value of the SysTick timer.

9. The method according to claim 5, characterized in that Also includes: The two CPUs are powered on simultaneously during the startup process, and the two CPUs are reset.

10. A method for CPU to perform interrupt service, characterized in that: Applied to the dual CPU synchronization system according to any one of claims 1 to 4, the method comprises: in response to an overflow of a CPU internal timer, executing the following: Output a pulse signal through the first IO; When a trigger signal is received through the first INT, the SysTick timer is reset; wherein the internal timer overflow time is set to be the same as the SysTick timer; Output data signals through n data IOs; When a trigger signal is received through the second INT, a CPU reset is executed.

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