Simulation acceleration method for triple modular redundancy circuit netlist

Abstract

The invention relates to the technical field of radiation-proof integrated circuit netlist simulation processing methods, and discloses a simulation acceleration method for a triple-modular redundancy circuit netlist, which comprises the following steps: S1, performing intermediate code screening on intermediate representation codes of a triple-modular redundancy circuit IR according to an instruction combination template definition; s2, performing instruction rearrangement on the screened intermediate codes of the triple modular redundancy circuit; s3, performing instruction optimization on the code after instruction rearrangement; s4, binary instruction codes are obtained, and coded data streams are output, the simulation acceleration method has high efficiency and expandability, and therefore support can be provided for a combined netlist-level special simulation tool, and the design efficiency and quality are further improved; the simulation method of the triple-modular redundancy circuit netlist has important practical application value, can provide reliable and efficient support for the design of an anti-radiation integrated circuit, and can improve the simulation efficiency of the triple-modular redundancy circuit netlist and reduce the operation time overhead of a circuit simulator.

Description

Technical Field

[0001] The invention relates to the technical field of radiation-resistant integrated circuit netlist simulation processing methods, and in particular to a simulation acceleration method for a triple-module redundant circuit netlist. Background Art

[0002] Triple-mode redundant design can effectively improve the reliability of radiation-resistant integrated circuits. Circuit netlists are an important carrier of digital design of radiation-resistant integrated circuits. Triple-mode redundant integrated circuits are usually designed on a large scale. Traditional simulation methods will repeatedly simulate triple-mode redundant circuits, leaving room for simulation acceleration optimization. Therefore, a simulation acceleration method for triple-mode redundant circuit netlists is proposed. Summary of the invention

[0003] The purpose of the present invention is to provide a simulation acceleration method for a triple-module redundant circuit netlist to solve the problem that the triple-module redundant integrated circuit proposed in the above background technology is usually designed on a large scale, and the traditional simulation method will repeatedly simulate the triple-module redundant circuit, leaving room for simulation acceleration optimization.

[0004] To achieve the above object, the present invention provides the following technical solution: a simulation acceleration method for a triple-module redundant circuit netlist, comprising the following steps:

[0005] S1, screening the intermediate code of the triple module redundant circuit IR according to the instruction combination template definition;

[0006] S2, reordering the instructions of the screened triple-module redundant circuit intermediate code;

[0007] S3, performing instruction optimization on the code after instruction reordering;

[0008] S4. Get binary instruction code and output the encoded data stream.

[0009] Preferably, in S1 above, the instruction combination template includes load, branch, assignment and write back.

[0010] Preferably, the above-mentioned loading instruction type is represented by Load, and the names of the groups A, B, and C are input according to the triple-module redundant module signal.

[0011] Preferably, the above branch instruction type is represented by Branch, and the sub-branch signal names are b1, b2, b3, ..., bn according to the triple-module redundant module signal input.

[0012] Preferably, the above assignment instruction type is represented by Action, and the sub-assignment signal names are input a1, a2, a3, ..., an according to the triple-module redundant module signal.

[0013] Preferably, the above-mentioned write-back instruction type is represented by Store, and the R voter name is input according to the triple-module redundant module signal.

[0014] Preferably, in S1, during the intermediate code screening process, load, branch, assignment and writeback are classified according to the supported standard instruction set functions, and the intermediate code screening representation is performed;

[0015] The filtered codes of the intermediate code filtering include Load A; Branch b1; Action a1; Load B; Branch b2; Load C; Branch b3; Action a3; ... Branch bn; ... Action an; Store R.

[0016] Preferably, in S2, during the instruction reordering process, the relevant load, branch, assignment, and write-back instructions are relocated according to the instruction combination template;

[0017] The loading instruction relocates the instruction position according to the instruction combination template and forms a code block;

[0018] The branch instruction is relocated according to the instruction combination template and forms a code block;

[0019] The assignment instruction relocates the instruction position according to the instruction combination template and forms a code block;

[0020] The write-back instruction relocates the instruction position according to the instruction combination template and forms a code block;

[0021] The code after the instructions are rearranged includes Load A; Load B; Load C; Branch b1; Branch b2; Branch b3; ... Branch bn; Action a1; Action a2; Action a3; ... Action an; Store R.

[0022] Preferably, in S3, during the instruction optimization process, the loading and assignment instruction code blocks are represented by instruction replacement according to single instruction multiple data;

[0023] The loading instruction code block is represented by instruction replacement according to single instruction multiple data;

[0024] The assignment instruction code block is represented by instruction replacement according to single instruction multiple data;

[0025] The instruction code is rearranged again according to the instruction bubbles;

[0026] The instruction optimized code includes Loadsimd A, B, C; Branch b1; Actionsimd a1, a2, a3, a4; Branch b2; Actionsimd a5, a6, a7, a8; Branch b3; Actionsimd a9, a10, a11, a12; ... Branch bn; Actionsimd an-3, an-2, an-1, an; Store R.

[0027] Preferably, in S4, the instruction code after instruction optimization is represented by binary instruction encoding, and the encoded data stream is output to the waveform generating device.

[0028] Preferably, the above.

[0029] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0030] The invention discloses a simulation acceleration method for a triple-module redundant circuit netlist. The method can significantly improve simulation efficiency, optimize simulation process overhead, and help to combine netlist-level special simulation tools. The method realizes instruction sequence intermediate code screening of the triple-module redundant circuit through instruction combination templates, optimizes the execution order of triple-module redundant circuit netlist instructions through instruction scheduling, establishes a detailed combination of triple-module redundant circuit instructions through instruction rearrangement, realizes instruction optimization through a single instruction multiple data method, and finally completes the triple-module redundant circuit instruction coding representation. In addition, since the simulation acceleration method of the invention has high efficiency and scalability, it can also provide support for combined netlist-level special simulation tools, thereby further improving the efficiency and quality of the design. In short, the simulation method for the triple-module redundant circuit netlist provided by the invention has important practical application value, can provide reliable and efficient support for radiation-resistant integrated circuit design, and can improve the simulation efficiency of the triple-module redundant circuit netlist and compress the circuit simulator running time overhead by using the method. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 It is a schematic diagram of the process of the present invention;

[0033] Figure 2 It is a schematic diagram of the simulation acceleration method of the present invention;

[0034] Figure 3 It is a schematic diagram of instruction optimization of the present invention;

[0035] Figure 4 It is a schematic diagram of a triple-module redundant circuit netlist simulation device of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which this application can be implemented. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the effects and purposes that can be achieved by this application.

[0038] Example

[0039] In the prior art, triple-module redundant integrated circuits are usually designed on a large scale, and traditional simulation methods will repeatedly simulate the triple-module redundant circuits, leaving room for simulation acceleration optimization.

[0040] See also Figure 1-4 The present invention provides a technical solution: a simulation acceleration method for a triple-module redundant circuit netlist, comprising the following steps:

[0041] S1. The intermediate code of the three-module redundant circuit IR is screened according to the definition of the instruction combination template; the instruction combination template definition includes four types: load, branch, assignment and write back, which are represented by the strings Load, Branch, Action and Store respectively. The operands and operation codes of the load template are uniformly represented by A, B or C, corresponding to the name of the three-module redundant module. The branch instruction inputs the sub-branch signal names of b1, b2, b3, ..., bn according to the three-module redundant module signal input. The assignment instruction inputs the sub-assignment signal names of a1, a2, a3, ..., an according to the three-module redundant module signal input. The write back instruction inputs the R voter name according to the three-module redundant module signal input.

[0042] The instruction combination template includes loading, branching, assignment and writing back; the loading instruction type is represented by Load, and the A, B, C group names are input according to the three-module redundant module signal; the branch instruction type is represented by Branch, and the b1, b2, b3, ..., bn sub-branch signal names are input according to the three-module redundant module signal; the assignment instruction type is represented by Action, and the a1, a2, a3, ..., an sub-assignment signal names are input according to the three-module redundant module signal; the write-back instruction type is represented by Store, and the R voter name is input according to the three-module redundant module signal.

[0043] During the intermediate code screening process, load, branch, assignment and writeback are classified according to the supported standard instruction set functions, and the intermediate code screening is performed, and the intermediate code screening results are used for instruction reordering;

[0044] The filtered codes of the intermediate code filtering include Load A; Branch b1; Action a1; Load B; Branch b2; Load C; Branch b3; Action a3; …Branch bn; …Action an; Store R.

[0045] S2, reordering the instructions of the screened triple-module redundant circuit intermediate code;

[0046] During the instruction reordering process, the relevant load, branch, assignment, and write-back instructions are relocated according to the instruction combination template;

[0047] The loading instruction relocates the instruction position according to the instruction combination template and forms a code block;

[0048] The branch instruction relocates the instruction position according to the instruction combination template and forms a code block;

[0049] The assignment instruction relocates the instruction position according to the instruction combination template and forms a code block;

[0050] The write-back instruction relocates the instruction position according to the instruction combination template and forms a code block;

[0051] After the instructions are reordered, the code includes Load A; Load B; Load C; Branch b1; Branch b2; Branch b3; … Branch bn; Action a1; Action a2; Action a3; … Action an; Store R.

[0052] S3, the code after instruction reordering is subjected to instruction optimization; during the instruction optimization process, the loading and assignment instruction code blocks are represented by instruction replacement according to single instruction multiple data;

[0053] The loading instruction code block is represented by instruction replacement according to single instruction multiple data;

[0054] The assignment instruction code block is represented by instruction replacement according to single instruction and multiple data;

[0055] The instruction code is rearranged again according to the instruction bubble;

[0056] The code after instruction optimization includes Loadsimd A, B, C; Branch b1; Actionsimd a1, a2, a3, a4; Branch b2; Actionsimd a5, a6, a7, a8; Branch b3; Actionsimd a9, a10, a11, a12; …Branchbn; Actionsimd an-3, an-2, an-1, an; Store R.

[0057] S4, obtain binary instruction code, and output the code data stream, the instruction code after instruction optimization is represented by binary instruction code, and the code data stream is output to the waveform generating device, such as Figure 4 As shown, a triple-mode redundant circuit netlist simulation device is described, which includes a triple-mode redundant circuit netlist simulator. This article provides a simulator acceleration method and also includes a waveform generation device.

[0058] In summary, the method can significantly improve the simulation efficiency, optimize the simulation process overhead, and help to combine netlist-level special simulation tools, realize the instruction sequence intermediate code screening of the three-module redundant circuit through the instruction combination template, optimize the execution order of the three-module redundant circuit netlist instructions through instruction scheduling, establish the detailed combination of the three-module redundant circuit instructions through instruction rearrangement, realize instruction optimization through the single instruction multiple data method, and finally complete the three-module redundant circuit instruction coding representation; in addition, since the simulation acceleration method of the present invention is efficient and scalable, it can also provide support for the combination of netlist-level special simulation tools, thereby further improving the efficiency and quality of the design; in short, the simulation method of the three-module redundant circuit netlist provided by the present invention has important practical application value, and can provide reliable and efficient support for the design of radiation-resistant integrated circuits. At the same time, the method can improve the simulation efficiency of the three-module redundant circuit netlist and compress the running time overhead of the circuit simulator.

[0059] So far, the embodiments of the present invention have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each component are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0060] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways, even if such combinations and / or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All of these combinations and / or combinations fall within the scope of the present invention.

[0061] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A simulation acceleration method for a triple-module redundant circuit netlist, characterized in that: The following steps are involved: S1, screening the intermediate code of the triple module redundant circuit IR according to the instruction combination template definition; S2, reordering the instructions of the screened triple-module redundant circuit intermediate code; S3, performing instruction optimization on the code after instruction reordering; S4. Get binary instruction code and output the encoded data stream.

2. The method for accelerating the simulation of a triple-module redundant circuit netlist according to claim 1, characterized in that: In S1, the instruction combination template includes load, branch, assignment and writeback.

3. The method for accelerating the simulation of a triple-module redundant circuit netlist according to claim 2, characterized in that: The load instruction type is represented by Load, and the names of the A, B, and C groups are input according to the triple-module redundant module signal.

4. The method for accelerating the simulation of a triple-module redundant circuit netlist according to claim 2, characterized in that: The branch instruction type is represented by Branch, and the sub-branch signal names are b1, b2, b3, ..., bn according to the triple-module redundant module signal input.

5. The method for accelerating the simulation of a triple-module redundant circuit netlist according to claim 2, characterized in that: The assignment instruction type is represented by Action, and the sub-assignment signal names are input according to the triple-module redundant module signal a1, a2, a3, ..., an.

6. The method for accelerating the simulation of a triple-module redundant circuit netlist according to claim 2, characterized in that: The write-back instruction type is represented by Store, and the R voter name is input according to the triple-module redundant module signal.

7. The method for accelerating the simulation of a triple-module redundant circuit netlist according to claim 1, characterized in that: In S1, during the intermediate code screening process, load, branch, assignment and writeback are classified according to the supported standard instruction set functions, and the intermediate code screening representation is performed; The filtered codes of the intermediate code filtering include Load A; Branch b1; Action a1; Load B; Branch b2; Load C; Branch b3; Action a3; ... Branch bn; ... Action an; Store R.

8. The method for accelerating the simulation of a triple-module redundant circuit netlist according to claim 1, characterized in that: In S2, during the instruction reordering process, the relevant load, branch, assignment, and write-back instructions are relocated according to the instruction combination template; The loading instruction relocates the instruction position according to the instruction combination template and forms a code block; The branch instruction performs instruction position relocation according to the instruction combination template and forms a code block; The assignment instruction relocates the instruction position according to the instruction combination template and forms a code block; The write-back instruction relocates the instruction position according to the instruction combination template and forms a code block; The code after the instructions are rearranged includes Load A; Load B; Load C; Branch b1; Branch b2; Branch b3; ... Branch bn; Action a1; Action a2; Action a3; ... Action an; Store R.

9. The method for accelerating the simulation of a triple-module redundant circuit netlist according to claim 1, characterized in that: In S3, during the instruction optimization process, the load and assignment instruction code blocks are represented by instruction replacement according to single instruction multiple data; The loading instruction code block is represented by instruction replacement according to single instruction multiple data; The assignment instruction code block is represented by instruction replacement according to single instruction multiple data; The instruction code is rearranged again according to the instruction bubbles; The instruction optimized code includes Loadsimd A, B, C; Branch b1; Actionsimd a1, a2, a3, a4; Branch b2; Actionsimd a5, a6, a7, a8; Branch b3; Actionsimd a9, a10, a11, a12; ... Branchbn; Actionsimd an-3, an-2, an-1, an; Store R.

10. The method for accelerating the simulation of a triple-module redundant circuit netlist according to claim 1, characterized in that: In S4, the instruction code after the instruction optimization is represented by binary instruction encoding, and the encoded data stream is output to the waveform generating device.

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