Scanning driver and display device including same

Abstract

The invention relates to a scan driver and a display device. Each stage of the scan driver includes: a first control transistor connected between a first input terminal and a first node to operate in response to a clock signal; a second control transistor connected between a second input terminal and a second node to operate in response to the clock signal; a third control transistor connected between the first node and the first control node to operate in response to a first voltage provided through a first voltage terminal; a fourth control transistor connected between a second voltage terminal and a second control node to operate in response to a potential at the first node; a fifth control transistor connected between the second control node and the first voltage terminal to operate in response to a potential at the second node; and a first capacitor connected between the second node and the second control node.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a scan driver and a display device including the same, and more particularly, to a scan driver having a simplified circuit structure and a display device including the same. Background Art

[0002] An emissive display device may use a light emitting diode that generates light through the recombination of electrons and holes. Such an emissive display device may provide a fast response speed and low power consumption.

[0003] An emissive display device may include a display panel having pixels arranged in an effective area. Each pixel generally includes at least one light emitting diode and a pixel circuit unit to control the current flowing through the light emitting diode. Each pixel circuit unit may be connected to a data line to receive a data signal, and connected to a scan line to receive a scan signal. The pixel circuit unit may control the amount of current in response to the data signal so that the current flows from a first driving power source to a second driving power source via the light emitting diode. In this case, the light emitting diode generates light having a specific brightness corresponding to the amount of current flowing through the light emitting diode. Summary of the invention

[0004] Embodiments of the present disclosure may provide a scan driver having a simplified circuit structure, and may reduce power consumption in a display device including the scan driver.

[0005] According to an embodiment, the scan driver includes a plurality of stages connected to each other in sequence. Each of the plurality of stages includes: a first control transistor connected between a first input terminal and a first node to operate in response to a clock signal provided through a clock terminal; a second control transistor connected between a second input terminal and a second node to operate in response to the clock signal; a third control transistor connected between a first node and a first control node to operate in response to a first voltage provided through a first voltage terminal; a fourth control transistor connected between a second voltage terminal and a second control node to operate in response to a potential at the first node; a fifth control transistor connected between a second control node and a first voltage terminal to operate in response to a potential at the second node; a first capacitor connected between a second node and a second control node; and an output circuit configured to output a scan signal in response to a potential at the first control node and a potential at the second control node.

[0006] According to an embodiment, a display device includes a display panel including pixels, a data driver configured to output a data signal to the display panel, and a scan driver including a plurality of stages sequentially connected to each other to output a scan signal to the display panel.

[0007] According to an embodiment, each of the multiple stages includes: a first control transistor connected between a first input terminal and a first node to operate in response to a clock signal provided through a clock terminal; a second control transistor connected between a second input terminal and a second node to operate in response to the clock signal; a third control transistor connected between the first node and a first control node to operate in response to a first voltage provided through a first voltage terminal; a fourth control transistor connected between a second voltage terminal and a second control node to operate in response to a potential at the first node; a fifth control transistor connected between the second control node and the first voltage terminal to operate in response to a potential at the second node; a first capacitor connected between the second node and the second control node; and an output circuit configured to output a scan signal in response to a potential at the first control node and a potential at the second control node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0009] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 2A is an exploded perspective view of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 2B is a cross-sectional view of a display device according to an embodiment of the present disclosure;

[0012] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure;

[0013] Figure 4 is a circuit diagram of a pixel according to an embodiment of the present disclosure;

[0014] Figure 5 is a timing diagram illustrating the operation of a pixel according to an embodiment of the present disclosure;

[0015] Fig. 6A is a block diagram of a scan driver according to an embodiment of the present disclosure;

[0016] Figure 6B yes Fig. 6A A block diagram of a first scan driving circuit shown in ;

[0017] Figure 7 yes Figure 6B The circuit diagram of the jth stage shown in ; and

[0018] Figure 8 It is shown Figure 7The waveform of the operation of the jth stage is shown in . DETAILED DESCRIPTION

[0019] With reference to the accompanying drawings, the present disclosure describes exemplary embodiments. In this specification, a first component (or region, layer, portion, part, etc.) is referred to as being "on" a second component, "connected to" or "coupled to" a second component, meaning that the first component can be directly on, directly connected to or directly coupled to the second component, or that a third component can be interposed between the first component and the second component.

[0020] The same reference numerals used in different drawings and the present disclosure represent the same components. In addition, in the drawings, the thickness, proportion and size of the components may be exaggerated or changed to better and effectively illustrate the technical features.

[0021] Although the terms "first", "second", etc. may be used to describe various components, these components should not be construed as being limited by such terms. These terms are only used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope and spirit of the present disclosure.

[0022] In addition, terms such as "under", "lower", "above", and "upper" are used to describe the relationship between components shown in the drawings. These terms are relative and are described with reference to the directions shown in the drawings.

[0023] It will be further understood that the terms "comprises," "comprising," "includes," or "including," or "having" specify the presence of stated features, quantities, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof. The term "and / or" includes any and all combinations of one or more of the relevant components. The singular is intended to include the plural unless the context clearly indicates otherwise.

[0024] Unless otherwise defined, all terms (including technical terms and scientific terms) used in the specification have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formalized meaning unless clearly defined herein.

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0026] Figure 1 1 is a perspective view of an electronic device ED according to an embodiment of the present disclosure. The electronic device ED may be a device activated in response to an electrical signal. The electronic device ED may be used for various applications or purposes. For example, the electronic device ED may be an electronic device such as a smart phone, a smart watch, a tablet PC, a laptop computer, a computer, a smart television (TV), or a navigation system.

[0027] refer to Figure 1 According to an embodiment of the present disclosure, the electronic device ED may have a rectangular shape having short sides parallel to the first direction DR1 and long sides parallel to the second direction DR2 crossing the first direction DR1. However, the embodiment is not limited thereto, and the electronic device ED may have various shapes such as a circle or a polygon.

[0028] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, the meaning of "when viewed in a plan view" may refer to "when viewed in the third direction DR3".

[0029] The top surface of the electronic device ED may be defined as a display surface IS and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the electronic device ED may be provided to a user through the display surface IS.

[0030] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area in which an image IM is displayed. A user observes the image IM through the transmission area TA. Figure 1 In the example shown in , the transmissive area TA has rounded corners. However, for the purpose of illustration, Figure 1 More generally, the transmission area TA may have various shapes and is not limited to the shapes shown in the drawings.

[0031] The border area BZA is adjacent to the transmission area TA. The border area BZA may have a specific or fixed color. The border area BZA may surround the transmission area TA. Therefore, the shape of the transmission area TA may be substantially defined by the border area BZA. However, the above shape of the border area BZA is provided only as an example. Alternatively, for example, the border area BZA may be provided to be adjacent to only one side of the transmission area TA, or may be omitted.

[0032] The electronic device ED may sense an external input applied from outside the electronic device ED. The external input may include various types of input provided from outside the electronic device ED. For example, the external input may be a contact on the display surface IS of a part of the user's body (such as a hand), or the external input may be generated by the user's hand approaching the electronic device ED or being close to the electronic device ED within a given distance. In addition, the external input may be of various types, such as force, pressure, temperature, and light.

[0033] Figure 2A is an exploded perspective view of an electronic device according to an embodiment of the present disclosure, and Figure 2B is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0034] refer to Figure 2A and Figure 2B , the electronic device ED may include a display device DD, an electronic module and a housing EDC. The display device DD may include a window WM and a display module DM, and may be accommodated in the housing EDC. According to an embodiment, the window WM is coupled to the housing EDC to form the appearance of the electronic device ED.

[0035] The front surface of the window WM may define the display surface IS of the electronic device ED. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films coupled to each other by an adhesive, or may include a glass substrate and a plastic film coupled to each other by an adhesive.

[0036] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image in response to an electrical signal, and the input sensing layer ISL may sense an external input applied from outside the electronic device ED. The external input may be provided in various forms as described above.

[0037] According to an embodiment of the present disclosure, the display panel DP may be an emissive display panel, but the present disclosure is not limited to a specific type of display panel. For example, the display panel DP may be or include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The organic light-emitting display panel may include an organic light-emitting material as a light-emitting layer, and the inorganic light-emitting display panel may include an inorganic light-emitting material as a light-emitting layer. The quantum dot light-emitting display panel may include quantum dots and quantum rods in the light-emitting layer. Hereinafter, the following description focuses on an embodiment in which the display panel DP is an organic light-emitting display panel.

[0038] refer to Figure 2B, the display panel DP includes a base layer BL, a circuit layer DP_CL, an element layer DP_ED, and an encapsulation layer TFE. The display panel DP according to the present disclosure may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel folded around a folding axis, or may be a rigid display panel.

[0039] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer. Alternatively or additionally, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0040] The circuit layer DP_CL is disposed on the base layer BL. The circuit layer DP_CL may be interposed between the base layer BL and the element layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and a structure forming a circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL may be referred to as an intermediate insulating layer. The intermediate insulating layer may include at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel driving circuit and a sensor driving circuit, the pixel driving circuit being included in each of a plurality of pixels to display an image, and the sensor driving circuit being included in each of a plurality of sensors to sense or identify external information. The external information may be biometric information. According to an embodiment of the present disclosure, each of the sensors may include a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood measurement sensor, or an illumination sensor. In addition, each of the sensors may be an optical sensor for optically identifying biometric information. The circuit layer DP_CL may also include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0041] The element layer DP_ED may include one or more light emitting elements for each pixel and one or more light receiving elements for each of the sensors. The light receiving element may be a sensor for sensing light (e.g., light reflected from a user's fingerprint) or a sensor that reacts to light otherwise. According to an embodiment of the present disclosure, each light receiving element may be a photodiode.

[0042] The encapsulation layer TFE encapsulates the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material to protect the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but the present disclosure is not limited thereto. The organic layer may include an organic material and may protect the element layer DP_ED from impurities such as dust particles.

[0043] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. According to an embodiment of the present disclosure, the input sensing layer ISL may be formed on the display panel DP through a series of subsequent processes. In other words, when the input sensing layer ISL is directly disposed on the display panel DP, the adhesive film is not interposed between the input sensing layer ISL and the encapsulation layer TFE. Alternatively, the adhesive film may be interposed between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL and the display panel DP may not be manufactured through subsequent processes. In other words, after the input sensing layer ISL is manufactured through a process separate from the process of forming the display panel DP, the input sensing layer ISL may be fixed on the top surface of the display panel DP by the adhesive film.

[0044] The input sensing layer ISL may sense an external input (e.g., a user's touch), may change the sensed input into a specific input signal, and may provide the input signal to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes to sense the external input. The sensing electrodes may sense the external input using a capacitive type of sensing to generate an input signal. The display panel DP may receive the input signal from the input sensing layer ISL and may generate an image corresponding to the input signal.

[0045] The display module DM may further include an anti-reflection layer ARL. The anti-reflection layer ARL may reduce the reflectivity of the display device DD to external light incident from the upper side of the window WM. According to an embodiment of the present disclosure, the anti-reflection layer ARL may be disposed on the input sensing layer ISL. However, the present disclosure is not limited thereto. Alternatively, the anti-reflection layer ARL may be interposed between the display panel DP and the input sensing layer ISL. The anti-reflection layer ARL may include a plurality of color filters and a black matrix. The arrangement of the color filters may be based on the plurality of pixels PX (see FIG. 1 ) included in the display panel DP. Figure 3 ) is determined by the color of the light generated by the anti-reflection layer ARL. The anti-reflection layer ARL may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type or a liquid crystal coating type. A film type polarizer may include a stretched synthetic resin film, and a liquid crystal coating type polarizer may include liquid crystals arranged in a specific array. The retarder and the polarizer may be implemented in one polarizing film.

[0046] According to an embodiment of the present disclosure, the display device DD may further include an adhesive layer AL. The window WM may be attached to the anti-reflection layer ARL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, or a pressure sensitive adhesive (PSA).

[0047] The display module DM may further include a display driving circuit DIC (or a display driving chip) and a flexible circuit film FCB. According to an embodiment of the present disclosure, the display driving circuit DIC may be a chip and may be mounted on the flexible circuit film FCB. However, the present disclosure is not limited thereto. Alternatively, the display driving circuit DIC may be disposed on the display panel DP.

[0048] The flexible circuit film FCB may be coupled to the display panel DP. The flexible circuit film FCB may be coupled to an end portion of the display panel DP to electrically connect the display driving circuit DIC to the display panel DP.

[0049] The display module DM may further include a touch driving circuit mounted on the flexible circuit film FCB and electrically connected to the input sensing layer ISL.

[0050] The electronic module may include a main circuit board MCB. According to an embodiment of the present disclosure, the main circuit board MCB may be electrically connected to a flexible circuit film FCB through a connector CNT. A main processor MCU and a power management circuit PMIC (or a power management chip) may be disposed on the main circuit board MCB. The main processor MCU and the power management circuit PMIC may be electrically connected to a display drive circuit DIC through a connector CNT.

[0051] The main processor MCU can control the overall operation of the electronic device ED. The main processor MCU may include at least one of a central processing unit (CPU) and an application processor (AP). The main processor MCU may also include at least one of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP). The main processor MCU may provide an image signal and various control signals required to display an image to the display drive circuit DIC.

[0052] The power management circuit PMIC may receive external power (e.g., a battery voltage), and the power management circuit PMIC may generate a voltage to be provided to the display device DD based on the external power. The power management circuit PMIC may include at least one regulator. The at least one regulator may use the external power to generate and output a driving voltage having various voltage levels.

[0053] although Figure 2A An embodiment is shown in which the power management circuit PMIC is a chip mounted on the main circuit board MCB, but the present disclosure is not limited thereto. For example, the power management circuit PMIC may be a component included in the display device DD, for example, a chip mounted on a flexible circuit film FCB.

[0054] In addition to the main circuit board MCB, the main processor MCU and the power management circuit PMIC, the electronic module may also include various functional modules, for example, a camera module or a sensor module.

[0055] The housing EDC may be assembled with the window WM. The housing EDC may be connected to the window WM to provide a specific internal space. The internal space of the housing EDC may receive and accommodate the display device DD and the electronic module. The housing EDC may be made of a material having high rigidity. For example, the housing EDC may include glass, plastic, or metal, or may include a plurality of frames and / or plates composed of a combination thereof. The housing EDC may stably protect the components of the display device DD and the electronic module from external impacts.

[0056] Although not shown, a battery module for supplying power required for the overall operation of the display device DD may be interposed between the display module DM and the case EDC.

[0057] Figure 3 is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0058] The display device DD includes a display panel DP, a panel driver PDD for driving the display panel DP, and a voltage generator 400. According to an embodiment of the present disclosure, the panel driver PDD may include a driving controller 100, a data driver 200, a scan driver 300, and a light emitting driver 350.

[0059] The drive controller 100 receives an input image signal RGB and a control signal CTRL from a host processor. According to an embodiment of the present disclosure, the host processor may be a graphics processing unit (GPU). The drive controller 100 generates image data DATA by converting the data format of the input image signal RGB as needed to comply with the interface specification of the data driver 200. The control signal CTRL may include a vertical synchronization signal, a data enable signal, or a main clock signal. The drive controller 100 may also generate a first drive control signal SCS, a second drive control signal DCS, and a third drive control signal ECS in response to the control signal CTRL.

[0060] The data driver 200 receives the second driving control signal DCS and the image data DATA from the driving controller 100. The data driver 200 converts the image data DATA into a data signal, and then outputs the data signal to a plurality of data lines DL1 to DLm described further below. In this case, "m" may be an integer equal to or greater than "1". The data signal may be an analog voltage corresponding to the grayscale value of the image data DATA.

[0061] The scan driver 300 receives a first driving control signal SCS from the driving controller 100. The scan driver 300 may output a scan signal to the scan line in response to the first driving control signal SCS.

[0062] The voltage generator 400 generates voltages required for the operation of the display panel DP. According to an embodiment, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT.

[0063] The display panel DP may include an active area AA and a non-active area NAA. The active area AA may be defined as an image IM (refer to Figure 1 ) through which the image IM is output from the display panel DP (i.e., the area in which the image IM is displayed). The non-active area NAA may be an area in which the image IM is substantially not displayed. The display panel DP includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, light emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. In this case, "n" may be an integer equal to or greater than "1". The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, the light emission control lines EML1 to EMLn, the data lines DL1 to DLm, and the pixels PX may overlap with the active area AA of the display panel DP or be arranged in the active area AA of the display panel DP. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, and the light emission control lines EML1 to EMLn may extend in the second direction DR2. Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, and emission control lines EML1 to EMLn may be arranged to be spaced apart from each other in the first direction DR1. Data lines DL1 to DLm are arranged to be spaced apart from each other in the second direction DR2 while extending in the first direction DR1.

[0064] The plurality of pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. Each of the pixels PX may be electrically connected to four scan lines. For example, Figure 3As shown in , the pixels PX included in the first row can be connected to the first initialization scan line SIL1, the first compensation scan line SCL1, and the first write scan line SWL1 and the second write scan line SWL2. For example, the pixels PX included in the second row can be connected to the second initialization scan line SIL2, the second compensation scan line SCL2, and the second write scan line SWL2 and the third write scan line SWL3. However, the number of scan lines connected to each pixel PX is not limited to four, but the number of scan lines connected to each pixel PX can vary. Alternatively, each of the plurality of pixels PX can be electrically connected to five scan lines. In this case, the display panel DP may further include a black scan line.

[0065] The scan driver 300 may be disposed in the non-active area NAA of the display panel DP. The scan driver 300 may receive a first drive control signal SCS from the drive controller 100. The scan driver 300 may output an initialization scan signal to the initialization scan lines SIL1 to SILn, a compensation scan signal to the compensation scan lines SCL1 to SCLn, and a write scan signal to the write scan lines SWL1 to SWLn+1 in response to the first drive control signal SCS. The circuit configuration and operation of the scan driver 300 are described in more detail below.

[0066] The light emitting driver 350 receives the third driving control signal ECS from the driving controller 100. The light emitting driver 350 may output the light emitting control signal to the light emitting control lines EML1 to EMLn in response to the third driving control signal ECS. In another embodiment, the scan driver 300 is connected to the light emitting control lines EML1 to EMLn. In this case, the scan driver 300 may output the light emitting control signal to the light emitting control lines EML1 to EMLn.

[0067] Each of the pixels PX may include a light emitting element ED (see Figure 4 ) and pixel circuit unit PXC (see Figure 4 ) to control the light emission from the light emitting element ED. Each pixel circuit unit PXC may include a plurality of transistors and at least one capacitor. The scan driver 300 and the light emitting driver 350 may include transistors formed by the same process as forming the pixel circuit unit PXC.

[0068] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT from the voltage generator 400 .

[0069] Figure 4 is a circuit diagram of a pixel according to an embodiment of the present disclosure, and Figure 5is a timing diagram of a pixel according to an embodiment of the present disclosure.

[0070] Figure 4 Shows Figure 3 An equivalent circuit diagram of one pixel PXij among the plurality of pixels PX is shown in . Since each of the plurality of pixels PX may have the same circuit structure, only the circuit structure of the pixel PXij will be representatively described, and details of the remaining pixels PX will be omitted in the following description.

[0071] refer to Figure 4 , the pixel PXij is connected to the i-th data line DLi (hereinafter referred to as the "data line") among the data lines DL1 to DLm and the j-th light-emitting control line EMLj (hereinafter referred to as the "light-emitting control line") among the light-emitting control lines EML1 to EMLn. In this case, "i" is an integer equal to or greater than "1" and equal to or less than "m", and "j" is an integer equal to or greater than "1" and equal to or less than "n". The pixel PXij is connected to the j-th initialization scan line SILj (hereinafter referred to as the initialization scan line) among the initialization scan lines SIL1 to SILn, the j-th write scan line SWLj (hereinafter referred to as the write scan line) among the write scan lines SWL1 to SWLn+1, and the j-th black scan line SBLj (hereinafter referred to as the black scan line) among a group of n black scan lines. In addition, the pixel PXij is connected to the j-th compensation scan line SCLj (hereinafter referred to as the "compensation scan line") among the compensation scan lines SCL1 to SCLn. Alternatively, the pixel PXij may be connected to the (j+1)th writing scan line instead of the jth black scan line SBLj.

[0072] The pixel PXij includes a light emitting element ED and a pixel circuit unit PXC. The light emitting element ED may include a light emitting diode. The light emitting diode may include an organic light emitting material, an inorganic light emitting material, a quantum dot, or a quantum rod in a light emitting layer.

[0073] Figure 4The pixel circuit unit PXC in the embodiment includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a capacitor Cst. Each of the first transistor T1 to the seventh transistor T7 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first transistor T1 to the seventh transistor T7 may be P-type transistors, and the remaining transistors of the first transistor T1 to the seventh transistor T7 may be N-type transistors. For example, the first transistor T1, the second transistor T2, and the fifth transistor T5 to the seventh transistor T7 of the first transistor T1 to the seventh transistor T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 of the first transistor T1 to the seventh transistor T7 may be N-type transistors including an oxide semiconductor used as a semiconductor layer. However, the configuration of the pixel circuit unit PXC according to the present disclosure is not limited to Figure 4 The embodiment shown in . Figure 4 The pixel circuit unit PXC shown in FIG. 1 is provided for illustrative purposes only. For example, the configuration of the pixel circuit unit PXC may be modified and implemented. For example, all of the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors.

[0074] The initialization scan line SILj, the compensation scan line SCLj, the write scan line SWLj, the black scan line SBLj and the emission control line EMLj can respectively transmit the jth initialization scan signal SIj (hereinafter, the initialization scan signal), the jth compensation scan signal SCj (hereinafter, the compensation scan signal), the jth write scan signal SWj (hereinafter, the write scan signal), the jth black scan signal SBj (hereinafter, the black scan signal) and the jth emission control signal EMj (hereinafter, the emission control signal) to the pixel PXij. The data line DLi transmits the data signal Di to the pixel PXij. The data signal Di may have the same value as that input to the display device DD (see Figure 3 ) The first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3 and the fourth driving voltage line VL4 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT and the second initialization voltage AINT to the pixel PXij, respectively.

[0075] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 through the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting element ED through the sixth transistor T6, and a gate electrode connected to one terminal of the capacitor Cst. The first transistor T1 can receive the data signal Di transmitted through the data line DLi in response to the switching operation of the second transistor T2, and can provide a driving current Id to the light emitting element ED.

[0076] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the write scan line SWLj. The second transistor T2 may be turned on in response to a write scan signal SWj received through the write scan line SWLj, and may then transmit a data signal Di received through the data line DLi to the first electrode of the first transistor T1.

[0077] The third transistor T3 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the gate electrode of the first transistor T1, and a gate electrode connected to the compensation scan line SCLj. The third transistor T3 may be turned on in response to a compensation scan signal SCj transmitted through the compensation scan line SCLj, and then may connect the gate electrode of the first transistor T1 to the second electrode of the first transistor T1, so that the first transistor T1 is diode-connected.

[0078] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third driving voltage line VL3 for transmitting the first initialization voltage VINT, and a gate electrode connected to the initialization scan line SILj. The fourth transistor T4 can be turned on in response to the initialization scan signal SIj received through the initialization scan line SILj. The initialization operation initializes the potential of the gate electrode of the first transistor T1 by transmitting the first initialization voltage VINT to the gate electrode of the first transistor T1 through the fourth transistor T4.

[0079] The fifth transistor T5 may include a first electrode connected to the first driving voltage line VL1 , a second electrode connected to the first electrode of the first transistor T1 , and a gate electrode connected to the light emitting control line EMLj.

[0080] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the light emitting control line EMLj.

[0081] The fifth transistor T5 and the sixth transistor T6 can be turned on at the same time in response to the light emitting control signal EMj received through the light emitting control line EMLj. When the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 receives the first driving voltage ELVDD through the fifth transistor T5 and controls the driving current Id transmitted to the light emitting element ED through the sixth transistor T6. As further described below, the capacitor Cst and the first transistor T1 connected by the diode of the third transistor T3 can be used to compensate for the threshold voltage of the first transistor T1 and provide the driving current Id at a level corresponding to the data signal Di.

[0082] The seventh transistor T7 includes a first electrode connected to the second electrode of the sixth transistor T6 , a second electrode connected to the fourth driving voltage line VL4 for transmitting the second initialization voltage AINT, and a gate electrode connected to the black scan line SBLj.

[0083] One terminal of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the other terminal of the capacitor Cst is connected to the first driving voltage line VL1 as described above. The cathode of the light emitting element ED may be connected to a second driving voltage line VL2 for transmitting a second driving voltage ELVSS.

[0084] refer to Figure 4 and Figure 5 , display panel DP (see Figure 3 ) can display an image during the driving frame DF.

[0085] A plurality of scan signals SIj, SCj, SWj and SBj may be effective during a driving frame DF. Specifically, the initialization scan signal SIj has a high level during a first effective period AP1 of the driving frame DF, and the compensation scan signal SCj has a high level during a second effective period AP2 of the driving frame DF. The write scan signal SWj has a low level during a third effective period AP3 of the driving frame DF, and the black scan signal SBj has a low level during a fourth effective period AP4 of the driving frame DF.

[0086] The light emitting control signal EMj may be disabled during the non-emission period NEP of the driving frame DF. According to an embodiment of the present disclosure, the non-emission period NEP may be a high level period of the light emitting control signal EMj. The non-emission period NEP may overlap with the first effective period AP1, the second effective period AP2, the third effective period AP3, and the fourth effective period AP4.

[0087] When the initialization scan signal SIj at a high level is provided through the initialization scan line SILj during the first effective period AP1, the fourth transistor T4 is turned on in response to the initialization scan signal SIj having a high level. The fourth transistor T4 transmits the first initialization voltage VINT to the gate electrode of the first transistor T1 when turned on, and the gate electrode of the first transistor T1 is initialized to the first initialization voltage VINT.

[0088] Next, when the compensation scan signal SCj of a high level is provided through the compensation scan line SCLj during the second effective period AP2, the third transistor T3 is turned on. During the second effective period AP2, the third transistor T3 makes the first transistor T1 forward biased due to initialization diode-connected. The second effective period AP2 of the compensation scan signal SCj may not overlap with the first effective period AP1 of the initialization scan signal SIj. In addition, the first effective period AP1 of the initialization scan signal SIj may precede the second effective period AP2 of the compensation scan signal SCj.

[0089] According to an embodiment of the present disclosure, the second effective period AP2 of the compensation scan signal SCj is defined as a period in which the compensation scan signal SCj has a high level, and the first effective period AP1 of the initialization scan signal SIj is defined as a period in which the initialization scan signal SIj has a high level. When the third transistor T3 and the fourth transistor T4 are P-type transistors, the second effective period AP2 of the compensation scan signal SCj is defined as a period in which the compensation scan signal SCj has a low level, and the first effective period AP1 of the initialization scan signal SIj is defined as a period in which the initialization scan signal SIj has a low level.

[0090] The second effective period AP2 may overlap with the third effective period AP3 in which the write scan signal SWj is generated at a low level. During the third effective period AP3, the second transistor T2 is turned on by the write scan signal SWj having a low level. Then, a compensation voltage "Di-Vth" obtained by subtracting the data signal Di provided from the data line DLi from the threshold voltage "Vth" of the first transistor T1 is applied to the gate electrode of the first transistor T1. In other words, the potential of the gate electrode of the first transistor T1 may become the compensation voltage "Di-Vth".

[0091] The first driving voltage ELVDD and the compensation voltage “Di-Vth” may be applied at both terminals of the capacitor Cst, and the capacitor Cst may store charges corresponding to a voltage difference between the two terminals of the capacitor Cst.

[0092] Thereafter, during the fourth effective period AP4, the seventh transistor T7 may be turned on in response to the black scan signal SBj having a low level. A portion of the driving current Id may flow out of the seventh transistor T7 while functioning as a bypass current Ibp.

[0093] Even if the minimum driving current of the first transistor T1 flows as the driving current Id, the light-emitting element ED can also emit light, which makes it difficult for the pixel PXij to display a black image normally. Therefore, according to an embodiment of the present disclosure, the seventh transistor T7 in the pixel PXij can move a portion of the minimum driving current of the first transistor T1 used as the bypass current Ibp to a current path other than the current path toward the light-emitting element ED. In this case, the minimum driving current of the first transistor T1 can refer to the current passing through the first transistor T1 under the condition that the first transistor T1 is cut off as the gate-source voltage of the first transistor T1 is less than the threshold voltage "Vth". Therefore, under the condition that the first transistor T1 is cut off, the minimum driving current (for example, a current of about 10pA or less) flowing through the first transistor T1 can be transmitted to the light-emitting element ED, thereby displaying a black image with a black grayscale. Therefore, when displaying a black image, the current (that is, the light-emitting current Ied) flowing through the light-emitting element ED is less than the driving current Id by the amount of the bypass current Ibp flowing out of the seventh transistor T7. Therefore, the light-emitting element ED stably presents a black grayscale. When the pixel PXij presents a black image, the drive current Id is at its minimum value, and when compared with the minimum value of the drive current Id, the bypass current Ibp is relatively large. On the contrary, when an image such as a normal image or a white image is displayed, the bypass current Ibp is relatively small compared to the drive current Id. Therefore, the use of the seventh transistor T7 can allow the pixel PXij to achieve an accurate black grayscale. Therefore, the contrast of the displayed image can be improved.

[0094] At the end of the non-emission period NEP, the light emitting control signal EMj provided from the light emitting control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on in response to the light emitting control signal EMj having a low level. Then, depending on the voltage difference between the gate voltage across the gate electrode of the first transistor T1 and the first driving voltage ELVDD, a driving current Id is generated with a certain magnitude, and the driving current Id is provided to the light emitting element ED through the sixth transistor T6.

[0095] Fig. 6A is a block diagram of a scan driver according to an embodiment of the present disclosure, and Figure 6B yes Fig. 6A A block diagram of a first scan driving circuit is shown in FIG.

[0096] refer to Fig. 6AThe scan driver 300 includes a first scan driving circuit 310 and a second scan driving circuit 320. Figure 3 ) includes a first scan control signal SCS1 applied to the first scan driving circuit 310 and a second scan control signal SCS2 applied to the second scan driving circuit 320. The first scan driving circuit 310 and the second scan driving circuit 320 can output scan signals to the scan lines in response to the first scan control signal SCS1 and the second scan control signal SCS2, respectively. Fig. 6A A configuration is shown in which the scan driver 300 includes two scan driving circuits 310 and 320 , but the number of scan driving circuits included in the scan driver 300 is not limited thereto.

[0097] The first scan driving circuit 310 may output initialization scan signals to the initialization scan lines SIL1 to SILn in response to the first scan control signal SCS1, and output compensation scan signals to the compensation scan lines SCL1 to SCLn. The second scan driving circuit 320 may output write scan signals to the write scan lines SWL1 to SWLn+1 in response to the second scan control signal SCS2.

[0098] Figure 6B FIG. 3 shows a first scanning driving circuit 310. Referring to FIG. Figure 6B , the first scan driving circuit 310 may include a plurality of stages ST1 to STn+1 sequentially connected to each other. Each of the stages ST1 to STn+1 may have substantially the same circuit configuration. For ease of explanation, Figure 6B Six stages ST1, ST2, STj-1, STj, STn and STn+1 are shown. Some of the multiple stages ST1 to STn+1 are connected to the initialization scan lines SIL1 to SILn. Some of the multiple stages ST1 to STn+1 are connected to the compensation scan lines SCL1 to SCLn.

[0099] The second scanning driving circuit 320 (see Fig. 6A ) may have a configuration similar to that of the first scan driving circuit 310. In other words, the second scan driving circuit 320 may include circuits connected to the write scan lines SWL1 to SWLn+1 (see Fig. 6A ) multiple levels.

[0100] Each of the stages ST1 to STn+1 may include a first input terminal IN1 , a second input terminal IN2 , a clock terminal CK, an output terminal OUT, and a carry terminal CR.

[0101] The output terminal OUT may output a scan signal. The scan signal may be an initialization scan signal or a compensation scan signal. The output terminals OUT of the plurality of stages ST1 to STn may be connected to the initialization scan lines SIL1 to SILn, respectively, and the output terminals OUT of the plurality of stages ST2 to STn+1 may be connected to the compensation scan lines SCL1 to SCLn, respectively. The output terminal OUT of each of the stages ST1 to STn may be connected to the first input terminal IN1 of the next stage. In detail, the output terminal OUT of the first stage ST1 is connected to the first input terminal IN1 of the second stage ST2, and the output terminal OUT of the (j-1)th stage STj-1 is connected to the first input terminal IN1 of the jth stage STj.

[0102] The first input terminal IN1 of each of the stages ST2 to STn+1 may receive a scan signal (hereinafter, referred to as a previous scan signal) output from the output terminal OUT of the previous stage. In the first stage ST1, the first start signal STV1 may be input to the first input terminal IN1. The first input terminal IN1 of the second stage ST2 may receive the first scan signal SI1 output from the output terminal OUT of the first stage ST1 as a previous scan signal. The first input terminal IN1 of the (n+1)th stage STn+1 may receive the nth scan signal SIn output from the output terminal OUT of the nth stage STn as a previous scan signal.

[0103] The carry terminals CR of the stages ST1 to STn+1 may output carry signals. The carry terminal CR of each of the stages ST1 to STn may be connected to the second input terminal IN2 of the next stage. In detail, the carry terminal CR of the first stage ST1 is connected to the second input terminal IN2 of the second stage ST2, and the carry terminal CR of the (j-1)th stage STj-1 is connected to the second input terminal IN2 of the jth stage STj.

[0104] The second input terminal IN2 of each of the stages ST2 to STn+1 may receive a carry signal (hereinafter referred to as a previous carry signal) output from the carry terminal CR of the previous stage. In the first stage ST1, the second start signal STV2 may be input to the second input terminal IN2. The second input terminal IN2 of the second stage ST2 may receive the first carry signal CRS1 output from the carry terminal CR of the first stage ST1 as the previous carry signal. The second input terminal IN2 of the (n+1)th stage STn+1 may receive the nth carry signal CRSn output from the carry terminal CR of the nth stage STn as the previous carry signal.

[0105] The clock terminal CK of each of the stages ST1 to STn+1 may receive the first clock signal CLK1 or the second clock signal CLK2. According to an embodiment of the present disclosure, the first clock signal CLK1 may be provided to the clock terminals CK of the odd-numbered stages ST1, STj-1, and STn+1, and the second clock signal CLK2 may be provided to the clock terminals CK of the even-numbered stages ST2, STj, and STn. The first clock signal CLK1 and the second clock signal CLK2 may be provided in the driving frame DF (see Figure 5 ) period has a preset period (for example, a horizontal scanning period of 1H) (see Figure 8 ) According to an embodiment of the present disclosure, the first clock signal CLK1 and the second clock signal CLK2 may have the same period but different phases from each other.

[0106] Each of the stages ST1 to STn+1 may further include a first voltage terminal VT1 (see Figure 7 ) and the second voltage terminal VT2 (see Figure 7 ). The first voltage terminal VT1 may be a terminal provided with a low voltage VGL (or a first voltage), and the second voltage terminal VT2 may be a terminal provided with a high voltage VGH (or a second voltage). Each of the low voltage VGL and the high voltage VGH may have a DC voltage level. The high voltage VGH may be set to a high level of a scan signal, and the low voltage VGL may be set to a low level of a scan signal. The low voltage VGL may have a voltage level lower than that of the high voltage VGH.

[0107] The first voltage terminals VT1 of the stages ST1 to STn+1 may be connected to one another, and the second voltage terminals VT2 of the stages ST1 to STn+1 may be connected to one another.

[0108] In the following, reference will be made to Figure 7 A circuit configuration of a j-th stage STj is described as an example of the stages ST1 to STn+1. Since each of the stages ST1 to STn+1 has the same circuit configuration, descriptions of the circuit configurations of the other stages will be omitted.

[0109] Figure 7 yes Figure 6B The circuit diagram of the jth stage is shown in . Figure 8 It is shown Figure 7 The waveform of the operation of the j-th stage is shown in FIG.

[0110] refer to Figure 6B and Figure 7 , the j-th stage STj includes first to fifth control transistors CT1 to CT5 , first to third capacitors C1 to C3 , and an output circuit OC.

[0111] The first control transistor CT1 is connected between the first input terminal IN1 and the first node N1, the first input terminal IN1 receives the previous scan signal (i.e., the (j-1)th scan signal SIj-1) from the previous stage (i.e., the (j-1)th stage STj-1), and the first control transistor CT1 operates in response to the second clock signal CLK2 provided by the clock terminal CK. The first control transistor CT1 includes a first electrode connected to the first input terminal IN1, a second electrode connected to the first node N1, and a third electrode or gate electrode connected to the clock terminal CK. The second control transistor CT2 is connected between the second input terminal IN2 and the second node N2, the second input terminal IN2 receives the previous carry signal (i.e., the (j-1)th carry signal CRSj-1) from the previous stage (i.e., the (j-1)th stage STj-1), and the second control transistor CT2 operates in response to the second clock signal CLK2 provided by the clock terminal CK. The second control transistor CT2 includes a first electrode connected to the second input terminal IN2, a second electrode connected to the second node N2, and a third electrode or gate electrode connected to the clock terminal CK. According to an embodiment of the present disclosure, each of the first control transistor CT1 and the second control transistor CT2 may include an LTPS semiconductor layer and may be a P-type transistor.

[0112] The third control transistor CT3 is connected between the first node N1 and the first control node QN, and operates in response to the low voltage VGL (or first voltage) provided by the first voltage terminal VT1. The third control transistor CT3 includes a first electrode connected to the first node N1, a second electrode connected to the first control node QN, and a third electrode or gate electrode connected to the first voltage terminal VT1. The fourth control transistor CT4 is connected between the second control node QBN and the second voltage terminal VT2, and operates in response to the potential of the first node N1. The high voltage VGH (or second voltage) is applied to the second voltage terminal VT2. The low voltage VGL may have a voltage level lower than the voltage level of the high voltage VGH. The fourth control transistor CT4 includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the second control node QBN, and a third electrode or gate electrode connected to the first node N1. The carry terminal CR of the jth stage STj is connected to the second control node QBN. According to an embodiment of the present disclosure, each of the third control transistor CT3 and the fourth control transistor CT4 may include an LTPS semiconductor layer and may be a P-type transistor.

[0113] The fifth control transistor CT5 is connected between the second control node QBN and the first voltage terminal VT1, and operates in response to the potential of the second node N2. The fifth control transistor CT5 includes a first electrode connected to the second control node QBN, a second electrode connected to the first voltage terminal VT1, and a third electrode or gate electrode connected to the second node N2. The fifth control transistor CT5 may include an LTPS semiconductor layer and may be a P-type transistor.

[0114] The first capacitor C1 is connected between the second node N2 and the second control node QBN, and the second capacitor C2 is connected between the second control node QBN and the second voltage terminal VT2.

[0115] The output circuit OC includes a first output transistor OT1 and a second output transistor OT2 connected to the output terminal OUT. The first output transistor OT1 is connected between the output terminal OUT and the first voltage terminal VT1, and operates in response to the potential at the first control node QN. The first output transistor OT1 includes a first electrode connected to the output terminal OUT, a second electrode connected to the first voltage terminal VT1, and a third electrode or gate electrode connected to the first control node QN. The second output transistor OT2 is connected between the output terminal OUT and the second voltage terminal VT2, and operates in response to the potential of the second control node QBN. The second output transistor OT2 includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the output terminal OUT, and a third electrode or gate electrode connected to the second control node QBN. According to an embodiment of the present disclosure, each of the first output transistor OT1 and the second output transistor OT2 may include an LTPS semiconductor layer and may be a P-type transistor.

[0116] The third capacitor C3 is connected between the first control node QN and the output terminal OUT.

[0117] refer to Figure 7 and Figure 8, during the low level period of the second clock signal CLK2, the first control transistor CT1 and the second control transistor CT2 are turned on. The first control transistor CT1 provides the previous scan signal (i.e., the (j-1)th scan signal SIj-1) from the first input terminal IN1 to the first node N1 when it is turned on. Therefore, the potential of the first node N1 rises to a high level in response to the (j-1)th scan signal SIj-1 being at a high level. When the potential at the first node N1 rises to a high level, the potential of the first control node QN rises to a high level through the turned-on third control transistor CT3. Even if the second clock signal CLK2 switches to a high level during the high level period of the (j-1)th scan signal SIj-1, the potential at the first node N1 and the first control node QN can also be maintained at a high level, for example, by the third capacitor C3. When the potential at the first node N1 and the first control node QN has a high level, the first output transistor OT1 is turned off.

[0118] When the potential at the first node N1 rises to a high level, the fourth control transistor CT4 may be turned off. When the fourth control transistor CT4 is turned off, the second control node QBN and the second voltage terminal VT2 may be electrically disconnected.

[0119] During the low level period of the second clock signal CLK2, the second control transistor CT2 provides the previous carry signal (ie, the (j-1)th carry signal CRSj-1) from the second input terminal IN2 to the second node N2. N2 Even if the second clock signal CLK2 switches to a high level during the low level period of the (j-1)th carry signal CRSj-1, the potential V N2 It can also be maintained at a low level. When the potential V N2 When the fifth control transistor CT5 is at a low level, it can be turned on. The turned-on fifth control transistor CT5 applies the low voltage VGL to the second control node QBN, and when the fourth control transistor CT4 is turned off, the potential V QBN Can be reduced to a low voltage VGL.

[0120] When the potential V at the second control node QBN QBN When the potential V at the second control node QBN is low, the second output transistor OT2 is turned on. Therefore, the high voltage VGH can be output to the output terminal OUT through the second output transistor OT2 that is then turned on. In other words, the j-th initialization scan signal SIj can be QBN The time point when the voltage drops to a low level and the first control node QN is at a high level is output as a high level.

[0121] In this case, the second control node QBN may be connected to the carry terminal CR of the j-th stage STj. Therefore, the potential V QBN In other words, when the potential V of the second control node QBN is QBN When at a low level, the jth initialization scan signal SIj is output at a high level from the output terminal OUT through the turned-on second output transistor OT2 so that the jth initialization scan signal SIj and the jth carry signal CRSj may have inverted phases.

[0122] When the first control transistor CT1 and the second control transistor CT2 are turned on during the low level period of the second clock signal CLK2 after the (j-1)th scan signal SIj-1 is switched to a low level, the potential at the first node N1 and the potential at the first control node QN may be reduced to a low level. The potential at the first node N1 reduced to a low level turns on the fourth control transistor CT4. When the fourth control transistor CT4 is turned on, the potential V QBN The second output transistor OT2 is responsive to the potential V of the second control node QBN having a high level. QBN The first output transistor OT1 is turned off in response to the potential at the first control node QN having a low level. The turned-on first output transistor OT1 can pull the voltage on the output terminal OUT to the low voltage VGL. Therefore, during the failure period, the j-th initialization scan signal SIj in a low state can be output to the output terminal OUT.

[0123] During a period in which the j-th carry signal CRSj is maintained at a high level (i.e., an inactive period of the j-th initialization scan signal SIj), even if the second clock signal CLK2 is switched from a high level to a low level or from a low level to a high level, the potential V N2It can also be stably maintained in a high state. In this case, the failure period of the jth initialization scan signal SIj can correspond to the high level period (or failure period) of the second node N2. Specifically, even when the second control transistor CT2 is turned on during the low level period of the second clock signal CLK2, the (j-1)th carry signal CRSj-1 is also applied to the second node N2. During the failure period of the jth initialization scan signal SIj, except for one horizontal scanning period 1H, the (j-1)th carry signal CRSj-1 and the jth carry signal CRSj have substantially the same potential. At other times, even if the second clock signal CLK2 switches, the first capacitor C1 may neither charge nor discharge, because the potential difference V between the second node N2 and the second control node QBN N2 -V QBN is maintained at zero “0.” Therefore, power consumption during the inactive period of each of the stages ST1 to STn+1 may be reduced, and the overall power consumption of the scan driver 300 and the display device DD using the scan driver 300 may be reduced.

[0124] According to the present disclosure, in each stage of the scan driver, even if the clock signal is triggered during the inactive period of the second node, since the potential difference between the second node and the second control node is substantially maintained at zero "0", the discharge or charge of the first capacitor does not occur. Therefore, during the inactive period, in each stage, power consumption can be reduced, which reduces the total power consumption of the scan driver and the display device using the scan driver.

[0125] Although the embodiments of the present disclosure are described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications and substitutions are possible without departing from the scope and spirit of the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the claims.

[0126] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. Scan the drive, including: Multiple levels, connected sequentially to each other, Wherein, each of the multiple levels comprises: a first control transistor connected between the first input terminal and the first node, the first control transistor operates in response to a clock signal provided via a clock terminal; a second control transistor connected between the second input terminal and the second node, the second control transistor operates in response to the clock signal; a third control transistor connected between the first node and a first control node, the third control transistor operating in response to a first voltage provided through a first voltage terminal; a fourth control transistor connected between the second voltage terminal and the second control node, the fourth control transistor operating in response to the potential at the first node; a fifth control transistor connected between the second control node and the first voltage terminal, the fifth control transistor operating in response to a potential at the second node; a first capacitor connected between the second node and the second control node; and The output circuit is configured to output a scan signal in response to the potential at the first control node and the potential at the second control node.

2. The scan driver according to claim 1, wherein: The second control node of each of the plurality of stages is connected to a carry terminal, and The carry terminal outputs the potential at the second control node as a carry signal.

3. The scan driver according to claim 2, wherein: The carry terminal is connected to the second input terminal of the next stage.

4. The scan driver according to claim 2, wherein: The potential difference between the second node and the second control node is maintained at zero during a deactivation period of the second node.

5. The scan driver according to claim 2, wherein: The output circuit comprises: a first output transistor connected between an output terminal and the first voltage terminal, the first output transistor operating in response to the potential at the first control node; and A second output transistor is connected between the output terminal and the second voltage terminal, the second output transistor operating in response to the potential at the second control node.

6. The scan driver according to claim 5, wherein: The output terminal is connected to the first input terminal of the next stage.

7. The scan driver according to claim 6, wherein: The first input terminal of a first stage of the plurality of stages receives a first start signal as a previous scan signal, and The second input terminal of the first stage receives a second start signal as a previous carry signal.

8. The scan driver according to claim 6, wherein: Each of the plurality of stages further comprises: a second capacitor connected between the fifth control transistor and the second voltage terminal; and A third capacitor is connected between the first control node and the output terminal.

9. The scan driver according to claim 1, wherein: The first voltage applied to the first voltage terminal has a voltage level lower than a voltage level of a second voltage applied to the second voltage terminal.

10. The scan driver according to claim 1, wherein: The first control transistor comprises: a first electrode connected to the first input terminal; a second electrode connected to the first node; and a third electrode, receiving the clock signal, and Wherein, the second control transistor comprises: a first electrode connected to the second input terminal; a second electrode connected to the second node; and The third electrode receives the clock signal.

11. The scan driver according to claim 10, wherein: The third control transistor comprises: a first electrode connected to the first node; a second electrode connected to the first control node; and a third electrode connected to the first voltage terminal, and Wherein, the fourth control transistor comprises: a first electrode connected to the second voltage terminal; a second electrode connected to the second control node; and A third electrode is connected to the first node.

12. The scan driver according to claim 11, wherein: The fifth control transistor comprises: a first electrode connected to the second control node; a second electrode connected to the first voltage terminal; and a third electrode connected to the second node, and The first capacitor is between the first electrode of the fifth control transistor and the third electrode of the fifth control transistor.

13. The scan driver according to claim 1, wherein: The clock signals include a first clock signal and a second clock signal having phases different from each other, wherein the clock terminals of the odd-numbered stages among the plurality of stages receive the first clock signal, and The clock terminals of the even-numbered stages among the plurality of stages receive the second clock signal.

14. Display equipment, including: Display panel, including pixels; a data driver configured to output a data signal to the display panel; as well as a scan driver including a plurality of stages sequentially connected to each other to output a scan signal to the display panel, Wherein, each of the multiple levels comprises: a first control transistor connected between the first input terminal and the first node, the first control transistor operates in response to a clock signal provided via a clock terminal; a second control transistor connected between the second input terminal and the second node, the second control transistor operates in response to the clock signal; a third control transistor connected between the first node and a first control node, the third control transistor operating in response to a first voltage provided through a first voltage terminal; a fourth control transistor connected between the second voltage terminal and the second control node, the fourth control transistor operating in response to the potential at the first node; a fifth control transistor connected between the second control node and the first voltage terminal, the fifth control transistor operating in response to the potential at the second node; a first capacitor connected between the second node and the second control node; and The output circuit is configured to output a scan signal in response to the potential at the first control node and the potential at the second control node.

15. The display device according to claim 14, wherein: The second control node of each of the plurality of stages is connected to a carry terminal, and The carry terminal outputs the potential at the second control node as a carry signal.

16. The display device according to claim 15, wherein: The carry terminal is connected to the second input terminal of the next stage.

17. The display device according to claim 15, wherein: The potential difference between the second node and the second control node is maintained at zero during a deactivation period of the second node.

18. The display device according to claim 15, wherein: The output circuit comprises: a first output transistor connected between an output terminal and the first voltage terminal, the first output transistor operating in response to the potential at the first control node; and A second output transistor is connected between the output terminal and the second voltage terminal, the second output transistor operating in response to the potential at the second control node.

19. The display device according to claim 18, wherein: The output terminal is connected to the first input terminal of the next stage.

20. The display device according to claim 19, wherein The first input terminal of a first stage of the plurality of stages receives a first start signal as a previous scan signal, and The second input terminal of the first stage receives a second start signal as a previous carry signal.

Images