Embedded dynamic memory, implementation method and integrated circuit
By introducing embedded dynamic memory into the image sensor and using independent readout and write control units to realize multiple working modes, the problem of manufacturing difficulty and cost caused by image sensor silicon wafer separation in the prior art is solved, and the problem of high manufacturing difficulty and cost is realized Parallel read and write operations reduce costs.
Patent Information
- Application Number
- CN202311055999.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-21
- Publication Date
- 2025-02-21
AI Technical Summary
In the prior art, the pixel array, logic processing circuit and DRAM of the image sensor are usually manufactured separately by separate silicon wafers, resulting in high process difficulty and high cost.
An implementation method of embedded dynamic memory is proposed, including at least one memory area, each memory area includes at least one sub-store area, each sub-store area includes an array of memory cells and a set of sensing amplifiers, and the sensing amplifier includes independent reads The output control unit and the independent write control unit are used to control the various operating modes of the memory.
Parallel read and write in the same memory area, and parallel read and write between different memory areas are realized, reducing manufacturing difficulty and cost.
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Figure CN119495336A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to an embedded dynamic memory, an implementation method and an integrated circuit. Background Art
[0002] The data stored in random access memory (RAM) can be read or written on demand, and the speed of reading and writing has nothing to do with the storage location of the data. This type of memory has a fast reading and writing speed, but the stored data will be lost when the power is off, so it is mainly used to store data used for a short time. According to the different storage information, random access memory can be divided into static random access memory (Static RAM, SRAM) and dynamic random access memory (Dynamic RAM, DRAM).
[0003] At present, DRAM and logic circuits are usually manufactured separately on two silicon wafers. For example, for an image sensor, the image data of the image sensor needs to be cached in a storage array. The existing practice is usually to manufacture the pixel array, logic processing circuit and DRAM of the image sensor separately through separate silicon wafers, and then package the three silicon wafers together by stacking. This process is not only difficult, but also significantly increases the cost. Summary of the invention
[0004] Based on the problems existing in the prior art, the present invention provides an implementation method of an embedded dynamic memory, wherein the memory includes at least one storage area; each storage area includes at least one sub-storage area; each sub-storage area includes a storage cell array and a group of sense amplifiers; the sense amplifier includes an independent read control unit and an independent write control unit; and the control of multiple working modes of the memory is realized through the read control unit and the write control unit.
[0005] In some embodiments, the memory further includes an input / output control module; the input / output control module includes a plurality of read control modules and a plurality of write control modules.
[0006] In some embodiments, the plurality of sense amplifiers are coupled to a corresponding independent read control module and a corresponding independent write control module.
[0007] In some embodiments, the control of multiple operating modes of the memory through the read control unit and the write control unit includes: enabling a certain storage area among the multiple storage areas; configuring internal timing to achieve continuous reading, continuous writing, parallel reading and writing, or interleaved reading and writing of the certain storage area.
[0008] In some embodiments, the control of multiple operating modes of the memory through the read control unit and the write control unit includes: interleavingly enabling one of the multiple storage areas; configuring internal timing to achieve continuous reading, continuous writing, or interleaved reading and writing between different storage areas.
[0009] In some embodiments, the control of multiple operating modes of the memory is achieved through the read control unit and the write control unit, including: simultaneously enabling at least two of the multiple storage areas; configuring internal timing to achieve continuous reading, continuous writing, staggered reading and writing of different storage areas, or parallel reading, parallel writing, or parallel reading and writing of different storage areas.
[0010] In some embodiments, a first sub-storage area of the certain storage area is read from / written to in a first time period, and a second sub-storage area of the certain storage area is read from / written to in a second time period, thereby realizing continuous reading, continuous writing, or interleaved reading and writing of the certain storage area; or a part of the first sub-storage area is read from / written to in a first time period, and another part of the first sub-storage area is written to / read from in the first time period, thereby realizing parallel reading and writing of the certain storage area.
[0011] In some embodiments, the first storage area is read / written in a first time period, and the second storage area is read / written in a second time period, so as to realize continuous reading, continuous writing, or interleaved reading and writing of different storage areas. In some embodiments, the first storage area is read / written in a first time period, and the second storage area is read / written in a second time period, so as to realize continuous reading, continuous writing, or interleaved reading and writing of different storage areas, or the first storage area is read / written in a first time period, and the second storage area is read / written in the first time period at the same time, so as to realize parallel reading, parallel writing, or parallel reading and writing of different storage areas.
[0012] In some embodiments, the internal timing includes the address timing of the storage area, the timing of the pre-charging units corresponding to different sub-storage areas of different storage areas, the timing of the read control module and the write control module, the timing of the read control unit and the write control unit, and the timing of the address line of the storage unit.
[0013] In some embodiments, the memory includes at least two storage areas; each storage area includes at least two sub-storage areas.
[0014] In some embodiments, each sensing amplifier also includes an amplification unit and a pre-charging unit coupled to a bit line and a reference bit line; the read control unit includes a first transistor and a second transistor; the gates of the first transistor and the second transistor are coupled and coupled to a read control signal; one end of the first transistor is coupled to the bit line, and the other end of the first transistor is coupled to the read control module; one end of the second transistor is coupled to the reference bit line, and the other end of the second transistor is coupled to the read control module; the write control unit includes a third transistor and a fourth transistor; the gates of the third transistor and the fourth transistor are coupled and coupled to a write control signal; one end of the third transistor is coupled to the bit line, and the other end of the third transistor is coupled to the write control module; one end of the fourth transistor is coupled to the reference bit line, and the other end of the fourth transistor is coupled to the write control module.
[0015] The present invention also provides an embedded dynamic memory, comprising: at least one storage area; each storage area comprises at least one sub-storage area; each sub-storage area comprises a storage cell array and a group of sensing amplifiers; the sensing amplifier comprises an independent read control unit and an independent write control unit.
[0016] In some embodiments, the embedded dynamic memory also includes: an input / output control module; the input / output control module includes multiple independent read control modules and multiple independent write control modules; and the multiple sense amplifiers are coupled to a corresponding independent read control module and a corresponding independent write control module.
[0017] In some embodiments, the memory includes at least two storage areas; each storage area includes at least two sub-storage areas.
[0018] In some embodiments, each sensing amplifier also includes an amplification unit and a pre-charging unit coupled to a bit line and a reference bit line; the read control unit includes a first transistor and a second transistor; the gates of the first transistor and the second transistor are coupled and coupled to a read control signal; one end of the first transistor is coupled to the bit line, and the other end of the first transistor is coupled to the read control module; one end of the second transistor is coupled to the reference bit line, and the other end of the second transistor is coupled to the read control module; the write control unit includes a third transistor and a fourth transistor; the gates of the third transistor and the fourth transistor are coupled and coupled to a write control signal; one end of the third transistor is coupled to the bit line, and the other end of the third transistor is coupled to the write control module; one end of the fourth transistor is coupled to the reference bit line, and the other end of the fourth transistor is coupled to the write control module.
[0019] The present invention also provides an integrated circuit, comprising the embedded dynamic memory.
[0020] Compared with the existing dynamic memory, the embedded dynamic memory proposed by the present invention can realize parallel reading and absorption in the same storage area, and parallel reading and writing between different storage areas. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 The figure is a schematic diagram of the structure of an embedded dynamic memory according to an embodiment of the present invention.
[0022] Figure 2 The present invention is a schematic structural diagram of a storage unit array of an embedded dynamic memory according to an embodiment of the present invention.
[0023] Figure 3 The figure is a schematic structural diagram of a sense amplifier of an embedded dynamic memory according to an embodiment of the present invention.
[0024] Figure 4 It is a schematic diagram of the structure in which multiple sense amplifiers share independent read control lines and independent write control lines according to an embodiment of the present invention.
[0025] Figure 5 Based on Figure 4 A structural diagram of an embedded dynamic memory.
[0026] Figures 6 to 12 1 is a timing diagram of different working modes of an embodiment of the present invention.
[0027] Fig.13 The present invention discloses an integrated circuit including an embedded dynamic memory. DETAILED DESCRIPTION
[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present invention. For ordinary technicians in this field, the present invention can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.
[0029] The present invention proposes an implementation method of an embedded dynamic memory, wherein the memory includes at least one storage area (bank); each storage area includes at least one sub-storage area (sub-bank); each sub-storage area includes a storage cell array and a group of sense amplifiers; the sense amplifier includes an independent read control unit and an independent write control unit; and the control of multiple working modes of the memory is realized through the read control unit and the write control unit.
[0030] The memory also includes an input / output control module; the input / output control module includes multiple independent read control modules and multiple independent write control modules; one or more of the sense amplifiers are coupled to a corresponding read control module and a corresponding write control module.
[0031] Figure 1 The figure is a schematic diagram of the structure of an embedded dynamic memory according to an embodiment of the present invention.
[0032] The dynamic memory 100 includes a memory bank 0, a memory bank 1, and an input / output (I / O) module 10. The memory bank 0 includes sub-memory banks 0-u and sub-memory banks 0-d. The memory bank 1 includes sub-memory banks 1-u and sub-memory banks 1-d.
[0033] Taking sub-storage area 0-u as an example, sub-storage area 0-u includes array 0-1 (also called storage cell array), sense amplifier 0-1 (Sense Amplifier, SA) and address 0-u. Array 0-1 consists of multiple rows and columns of storage cells. The specific structure of the storage cell can be referred to Figure 2 SA0-1 includes multiple sense amplifiers. The specific structure of the sense amplifier can be referred to Figure 3 The address 0-u includes the row address line, column address line and other related address lines of the storage unit. The array 0-1 is distributed in the four corners of the sub-storage area 0-u. The sense amplifier SA0-1 is distributed on both sides of the address 0-u and between the two arrays 0-1.
[0034] Similarly, sub-storage area 0-d, sub-storage area 1-u and sub-storage area 1-d can have the same structural layout as sub-storage area 0-u. It should be noted that the structural layout of the dynamic memory 100 can also be other designs, which are not limited here. The dynamic memory 100 can include more storage areas, for example, 3, 4, 5, 6 or 8 storage areas or more, which are not limited here. Each storage area can include more sub-storage areas, for example, 3, 4, 5, 6 or 8 sub-storage areas or more, which are not limited here.
[0035] Figure 2The present invention is a schematic structural diagram of a storage unit array of an embedded dynamic memory according to an embodiment of the present invention.
[0036] The memory cell array 200 includes a plurality of memory cells 11, a plurality of word lines (WL) (such as Figure 2 WL1, WL2, ...., WLn) and multiple bit lines (Bit Line, BL) (such as Figure 2 BL1, BL2, ..., BLn in FIG. 1 ). The storage unit 11 includes a capacitor 11a and a transistor 11b. One end of the capacitor 11a is coupled to a fixed voltage, for example, to the ground (0V), and the other end of the capacitor 11a is coupled to the source end of the transistor 11b. The drain end of the transistor 11b is coupled to the bit line. The gate end of the transistor 11b is coupled to the word line. The capacitor 11a of the embodiment of the present invention can be a deep trench capacitor, and the transistor 11b can be a vertical transfer transistor, so that the area of the chip can be reduced.
[0037] Figure 3 The figure is a schematic structural diagram of a sense amplifier of an embedded dynamic memory according to an embodiment of the present invention.
[0038] Each sense amplifier 300 includes an amplification unit 31 coupled to a bit line BL and a reference bit line BLB, a precharge unit 32 , a read control unit 33 , and a write control unit 34 .
[0039] The amplifying unit 31 is composed of a PMOS transistor TP1, a PMOS transistor TP2, an NMOS transistor TN1 and an NMOS transistor TN2. For specific connection relationships, refer to Figure 3 .
[0040] The pre-charge unit 32 is composed of a PMOS transistor TP3, a PMOS transistor and a PMOS transistor TP13. The gates of the three transistors are connected to a voltage. For specific connection relationships, refer to Figure 3 The precharge unit 32 can charge the bit line BL and the reference bit line BLB to a certain voltage value, and then charge or discharge the capacitor 21a in the storage unit 21 when reading or writing data.
[0041] The read control unit 33 includes an NMOS transistor TN3 and an NMOS transistor TN4. The gates of TN3 and TN4 are coupled and coupled to a read control signal line E (or represented as RYS). One end of TN3 is coupled to the bit line BL, and the other end of TN3 is coupled to the read control signal line A (or represented as RIOT). One end of TN4 is coupled to the reference bit line BLB, and the other end of TN4 is coupled to the read control signal line B (or represented as RIOB).
[0042] The write control unit 34 includes an NMOS transistor TN5 and an NMOS transistor TN6. The gates of TN5 and TN6 are coupled to a write control signal line F (or represented as WYS).
[0043] One end of TN5 is coupled to the bit line BL, and the other end of TN5 is coupled to the write control signal line C (or WIOT). One end of TN6 is coupled to the reference bit line BLB, and the other end of TN6 is coupled to the write control line D (or WIOB).
[0044] Figure 4 It is a schematic diagram of the structure in which multiple sense amplifiers share independent read control lines and independent write control lines according to an embodiment of the present invention.
[0045] like Figure 4 As shown, the sense amplifier group 41 is coupled to the corresponding upper and lower two memory cell arrays 42. The sense amplifier group 41 is composed of SA0, SA1, SA2, ..., SAn. SA0, SA1, SA2, ..., SAn are commonly coupled to the read control signal line A and the read control signal line B. SA0, SA1, SA2, ..., SAn are commonly coupled to the write control signal line C and the write control signal line D. The read control signal E of SA1, SA2, ..., SAn and the write control signal F of SA1, SA2, ..., SAn are independently controlled.
[0046] Figure 5 Based on Figure 4 A structural diagram of an embedded dynamic memory.
[0047] like Figure 5 As shown, the dynamic memory is divided into storage area 0 and storage area 1. Each storage area includes multiple rows and columns of sense amplifier groups 41 and corresponding storage cell arrays 42 (only one is shown in the figure). Multiple sense amplifier groups 41 in the same column are commonly coupled to a corresponding read control module G (or represented as RIO) through read control signal lines A and B and are commonly coupled to a corresponding write control module H (or represented as WIO) through write control signal lines C and D.
[0048] The read control modules G and write control modules F commonly coupled to the multiple sense amplifier groups 41 in different columns are independent of each other. That is, the I / O module 10 includes multiple independent read control modules G and multiple independent write control modules F. Multiple independent read control modules G are commonly coupled to a control terminal M (or represented as RDQ). Multiple independent write control modules F are commonly coupled to a control terminal N (or represented as WDQ).
[0049] Figures 6 to 12 FIG. 4 is a timing diagram of different read and write modes of the embedded dynamic memory according to an embodiment of the present invention.
[0050] Use Rsel and Wsel to select the required enabled storage area. When Rsel and WSel are both low (0), storage area 0 is enabled. When Rsel and WSel are both low (1), storage area 1 is enabled. When one of Rsel or Wsel is low (0) and the other is high (1), both storage area 0 and storage area 1 are enabled.
[0051] Rcas and Wcas are used to control the reading and writing of the storage area. Rcas is divided into Rcas_u and Rcas_d; Wcas is divided into Wcas_u and Wcas_d. Each storage area includes sub-storage area u and sub-storage area d. Rcas_u represents the read control of sub-storage area u. When Rcas_u is high level (1), it indicates reading. Wcas_u represents the write control of sub-storage area u. When Wcasu is high level (1), it indicates writing. Rcas_d represents the read control of sub-storage area d. When Rcasu is high level (1), it indicates reading. Wcas_d represents the write control of sub-storage area d. When Wcas_u is high level (1), it indicates writing. It should be noted that the timing diagrams of some control signals are omitted. For example, the timing of the pre-charge units in different sub-storage areas is not included. Figures 6 to 13 In the above table, the timing of RIO, WIO, RYS, WYS, etc. is not shown. Figures 6 to 13 It is reflected in.
[0052] In one embodiment, by enabling a certain storage area among a plurality of storage areas and configuring internal timing, continuous reading, continuous writing, parallel reading and writing, or interleaved reading and writing of the certain storage area can be achieved.
[0053] In one embodiment, one of the plurality of storage areas is enabled in an interleaved manner; and the internal timing is configured to achieve continuous reading, continuous writing, or interleaved reading and writing between different storage areas.
[0054] In one embodiment, at least two storage areas among the multiple storage areas are enabled at the same time; the internal timing is configured to realize continuous reading, continuous writing, staggered reading and writing of different storage areas, or parallel reading, parallel writing or parallel reading and writing of different storage areas. The internal timing includes the address timing of the storage area, the timing of the precharge unit corresponding to different sub-storage areas of different storage areas, the timing of the read control module and the write control module, the timing of the read control unit and the write control unit, and the timing of the address line of the storage unit. The following is a detailed description of different read and write modes in conjunction with the relevant drawings.
[0055] Figure 6 , Figure 7 and Figure 8The timing diagram for read and write mode is shown below with only one bank (for example, bank 0) enabled.
[0056] like Figure 6 As shown, in the first time period (t1 to t2), the sub-storage area 0-u of the storage area 0 is read out, in the second time period (t2 to t3), the sub-storage area 0-d of the storage area 0 is read out, and in the third time period (t3 to t4), the sub-storage area 0-u of the storage area 0 is read out, thereby realizing continuous reading of the storage area 0.
[0057] Similarly, refer to Figure 6 In the first time period (t1 to t2), sub-storage area 0-u of storage area 0 can be written, in the second time period (t2 to t3), sub-storage area 0-d of storage area 0 can be written, and in the third time period (t3 to t4), sub-storage area 0-u of storage area 0 can be written, thereby realizing continuous writing to storage area 0.
[0058] like Figure 7 As shown, in the first time period (t1 to t2), sub-storage area 0-u of storage area 0 is read out, in the second time period (t2 to t3), sub-storage area 0-d of storage area 0 is written, and in the third time period (t3 to t4), sub-storage area 0-u of storage area 0 is read out, thereby realizing interleaved reading and writing of storage area 0.
[0059] like Figure 8 As shown, in the first time period (t1 to t2), a part of the sub-storage area 0-u of the storage area 0 (for example, the corresponding upper half of the storage array) is read out, and at the same time, another part of the sub-storage area 0-u of the storage area 0 (for example, the corresponding lower half of the storage array) is written in the first time period (t1 to t2), and in the second time period (t2 to t3), a part of the sub-storage area 0-d of the storage area 0 (for example, the corresponding upper half of the storage array) is written, and at the same time, another part of the sub-storage area 0-d of the storage area 0 (for example, the corresponding lower half of the storage array) is read out in the second time period (t2 to t3), and in the third time period (t3 to t4), a part of the sub-storage area 0-u of the storage area 0 (for example, the corresponding upper half of the storage array) is read out, and at the same time, another part of the sub-storage area 0-u of the storage area 0 (for example, the corresponding lower half of the storage array) is written in the first time period (t1 to t2), thereby realizing parallel reading and writing of the storage area 0.
[0060] Fig. 9 and Fig.10The timing diagram for interleavingly enabling the read and write modes of one of the two storage areas (storage area 0 and storage area 1). Rcas represents the read control of the storage area. When Rcas is high (1), it indicates reading. Wcas represents the write control of the storage area. When Wcas is high (1), it indicates writing.
[0061] like Fig. 9 As shown, storage area 0 is read out in the first time period (t1 to t2), storage area 1 is read out in the second time period (t2 to t3), and storage area 0 is read out in the third time period (t3 to t4), thereby realizing continuous reading of different storage areas.
[0062] Similarly, refer to Fig. 9 , writing to storage area 0 in the first time period (t1 to t2), writing to storage area 1 in the second time period (t2 to t3), and writing to storage area 0 in the third time period (t3 to t4), thereby achieving continuous writing of different storage areas.
[0063] like Fig.10 As shown, storage area 0 is read in the first time period (t1 to t2), storage area 1 is written in the second time period (t2 to t3), and storage area 0 is read in the third time period (t3 to t4), thereby achieving staggered reading and writing of different storage areas.
[0064] Fig.11 and Fig.12 The timing diagram for enabling the read and write modes of two storage areas (storage area 0 and storage area 1) at the same time. Rcas represents the read control of the storage area. When Rcas is high (1), it indicates reading. Wcas represents the write control of the storage area. When Wcas is high (1), it indicates writing.
[0065] like Fig.11 By controlling Rsel, Wsel, Rcas and Wcas, storage area 0 is read in the first time period (t1 to t2), and storage area 1 is read in the first time period (t1 to t2), storage area 0 is read in the second time period (t2 to t3), and storage area 1 is read in the second time period (t2 to t3), storage area 0 is read in the third time period (t3 to t4), and storage area 1 is read in the third time period (t3 to t4), thereby realizing parallel reading of different storage areas. Similarly, parallel writing and staggered reading and writing of different storage areas can also be realized.
[0066] like Fig.12By controlling Rsel, Wsel, Rcas and Wcas, storage area 0 is read in the first time period (t1 to t2), and storage area 1 is written in the first time period (t1 to t2), storage area 0 is written in the second time period (t2 to t3), and storage area 1 is read in the second time period (t2 to t3), storage area 0 is read in the third time period (t3 to t4), and storage area 1 is written in the third time period (t3 to t4), thereby realizing parallel reading and writing of different storage areas and continuous reading and writing between different storage areas.
[0067] It should be noted that the read and write modes of the embedded memory of the embodiment of the present invention can also be implemented by changing the timing of different control signals, which is not limited here.
[0068] Fig.13 The present invention discloses an integrated circuit including an embedded dynamic memory.
[0069] The integrated circuit 500 includes an image sensor 501 , a logic circuit 502 , and an embedded dynamic memory 503 . The embedded dynamic memory 503 may be used to store image data of the image sensor 501 .
[0070] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention.
[0071] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as examples and not limitations, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.
Claims
1. A method for implementing an embedded dynamic memory, characterized in that: The memory includes at least one storage area; each storage area includes at least one sub-storage area; each sub-storage area includes a storage cell array and a group of sense amplifiers; The sense amplifier includes an independent read control unit and an independent write control unit; The control of various working modes of the memory is achieved through the read control unit and the write control unit.
2. The method according to claim 1, characterized in that The memory also includes an input / output control module; The input / output control module includes a plurality of read control modules and a plurality of write control modules.
3. The method according to claim 2, characterized in that The plurality of sense amplifiers are coupled to a corresponding independent read control module and a corresponding independent write control module.
4. The method according to claim 3, characterized in that The control of the multiple working modes of the memory by the read control unit and the write control unit includes: enabling a storage area among the multiple storage areas; By configuring the internal timing, continuous reading, continuous writing, parallel reading and writing, or interleaved reading and writing of the certain storage area can be realized.
5. The method according to claim 4, characterized in that The control of the multiple working modes of the memory by the read control unit and the write control unit includes: interlacedly enabling a certain storage area among the plurality of storage areas; Configuring the internal timing can achieve continuous reading, continuous writing, or interleaved reading and writing between different storage areas.
6. The method according to claim 3, characterized in that The control of the multiple working modes of the memory by the read control unit and the write control unit includes: simultaneously enabling at least two storage areas of the plurality of storage areas; By configuring the internal timing, continuous reading, continuous writing, interleaved reading and writing of different storage areas, or parallel reading, parallel writing, or parallel reading and writing of different storage areas can be achieved.
7. A method according to claim 4, characterized in that: Reading / writing a first sub-storage area of the certain storage area in a first time period, and reading / writing a second sub-storage area of the certain storage area in a second time period, thereby realizing continuous reading, continuous writing, or interleaved reading and writing of the certain storage area; or A portion of the first sub-storage area is read / written in a first time period, and another portion of the first sub-storage area is simultaneously written / read in the first time period, thereby achieving parallel reading and writing of the one storage area.
8. The method according to claim 5, characterized in that The first storage area is read / written in the first time period, and the second storage area is read / written in the second time period, thereby achieving continuous reading, continuous writing or interleaved reading and writing of different storage areas.
9. The method according to claim 6, characterized in that The first storage area is read / written in a first time period, and the second storage area is read / written in a second time period, thereby realizing continuous reading, continuous writing or interleaved reading and writing of different storage areas, or The first storage area is read / written in a first time period, and the second storage area is read / written in the first time period at the same time, thereby achieving parallel reading, parallel writing, or parallel reading and writing of different storage areas.
10. The method according to any one of claims 4 to 9, characterized in that The internal timing includes the address timing of the storage area, the timing of the pre-charging unit corresponding to different sub-storage areas of different storage areas, the timing of the read control module and the write control module, the timing of the read control unit and the write control unit, and the timing of the address line of the storage unit.
11. The method according to claim 1, characterized in that The memory includes at least two storage areas; each storage area includes at least two sub-storage areas.
12. The method according to any one of claims 1 to 11, characterized in that: Each sense amplifier further includes an amplification unit and a precharge unit coupled to the bit line and the reference bit line; The readout control unit includes a first transistor and a second transistor; The gates of the first transistor and the second transistor are coupled to each other and are coupled to a readout control signal; One end of the first transistor is coupled to the bit line, and the other end of the first transistor is coupled to the readout control module; One end of the second transistor is coupled to the reference bit line, and the other end of the second transistor is coupled to the readout control module; The write control unit includes a third transistor and a fourth transistor; The gates of the third transistor and the fourth transistor are coupled to each other and are coupled to a write control signal; One end of the third transistor is coupled to the bit line, and the other end of the third transistor is coupled to the write control module; One end of the fourth transistor is coupled to the reference bit line, and the other end of the fourth transistor is coupled to the write control module.
13. An embedded dynamic memory, characterized in that: include: at least one storage area; each storage area includes at least one sub-storage area; each sub-storage area includes a storage cell array and a set of sense amplifiers; The sense amplifier includes an independent read control unit and an independent write control unit.
14. The embedded dynamic memory according to claim 13, characterized in that: Also includes: Input / output control module; the input / output control module includes multiple read control modules and multiple write control modules; The plurality of sense amplifiers are coupled to a corresponding independent read control module and a corresponding independent write control module.
15. The embedded dynamic memory according to claim 14, characterized in that: The memory includes at least two storage areas; each storage area includes at least two sub-storage areas.
16. The embedded dynamic memory according to claim 15, characterized in that: Each sense amplifier further includes an amplification unit and a precharge unit coupled to the bit line and the reference bit line; The readout control unit includes a first transistor and a second transistor; The gates of the first transistor and the second transistor are coupled to each other and are coupled to a readout control signal; One end of the first transistor is coupled to the bit line, and the other end of the first transistor is coupled to the readout control module; One end of the second transistor is coupled to the reference bit line, and the other end of the second transistor is coupled to the readout control module; The write control unit includes a third transistor and a fourth transistor; The gates of the third transistor and the fourth transistor are coupled to each other and are coupled to a write control signal; One end of the third transistor is coupled to the bit line, and the other end of the third transistor is coupled to the write control module; One end of the fourth transistor is coupled to the reference bit line, and the other end of the fourth transistor is coupled to the write control module.
17. An integrated circuit, characterized in that: Comprising the embedded dynamic memory as claimed in any one of claims 13 to 16.