RDMA data transmission optimization method and system based on FPGA

Abstract

The invention provides an RDMA data transmission optimization method and system based on an FPGA, and relates to the technical field of RDMA communication transmission, and the method comprises the steps: constructing an RDMA communication node network architecture with the FPGA as a core; initializing an RDMA communication node network, and setting a register table for each node; after receiving the data in the RDMA communication node network, the destination node records the current receiving time node while processing the data, and updates the transmitting node register table corresponding to the destination node according to the received transmitting time node in the RDMA communication node network and the current receiving time node; the destination node synchronously transmits the original information of the transmitting time node and the receiving time node while transmitting the feedback signal to the information transmitting node, and when the information transmitting node receives the data feedback signal, the current receiving time node is recorded as well. And a destination node register table corresponding to the information transmitting node is updated according to the transmitting time node information and the receiving time node information in the RDMA transmission information.

Description

Technical Field

[0001] The present disclosure relates to the field of RDMA communication transmission technology, and in particular to an FPGA-based RDMA data transmission optimization method and system. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art.

[0003] Traditional centralized computing architectures are unable to meet the needs of large-scale data processing caused by the exponential growth of data scale. Distributed computing architectures have become the mainstream computing paradigm for big data processing. Among them, network communication has become the main performance bottleneck of distributed computing systems. Efficient data transmission in distributed computing systems faces many challenges such as high bandwidth, low latency, high reliability, and multi-path. As a new transmission protocol, RDMA (Remote Direct Memory Access) technology has been widely used in the data transmission process of distributed computing systems. This technology can realize direct data transmission across host memories, bypass the intervention of the operating system kernel, significantly reduce the CPU burden, and achieve high-speed data communication.

[0004] However, existing RDMA transmission technologies still face many performance bottlenecks. First, existing implementations usually rely on smart network cards to achieve efficient connections between the network and computing nodes, which may lead to performance losses. Specifically, distributed computing nodes are usually equipped with multiple computing devices. The additional introduction of smart network cards not only increases the complexity and cost of the hardware, but also may bring additional CPU scheduling overhead, and requires additional coordination of the interaction between the smart network card and other devices inside the node. Secondly, the current RDMA transmission control mechanism mostly adopts a priority flow control strategy to alleviate network congestion. This strategy implements flow control at the distributed node level. When network congestion occurs, it reduces or temporarily sets the transmission rate of the upstream node to alleviate congestion control pressure. However, this method does not take into account the specific needs of the transmission destination node, nor does it dynamically adjust according to the actual bandwidth requirements of each transmission session, resulting in insufficient accuracy of traffic management, thereby affecting the overall transmission efficiency and performance. Summary of the invention

[0005] In order to solve the above problems, the present disclosure proposes an FPGA-based RDMA data transmission optimization method and system, constructs an FPGA hardware unit of an internalized smart network card, uses the high concurrency characteristics of FPGA and computing units such as GPU to undertake distributed computing node computing acceleration tasks, and builds an RDMA transmission data packet data link according to RDMA transmission requirements to complete the response data sending and receiving work; at the same time, in response to the RDMA network congestion problem, the corresponding register table is maintained for all transmission destination nodes in the FPGA transmission node to achieve flow control and congestion resolution based on the destination node.

[0006] According to some embodiments, the present disclosure adopts the following technical solutions: The FPGA-based RDMA data transmission optimization method includes: Build an RDMA communication node network architecture with FPGA as the core; Initialize the RDMA communication node network, number the nodes in the network according to their physical locations, and set a register table for each node. Each register table entry includes the data transmission time and the data reception time; After receiving the data in the RDMA communication node network, the destination node records the current receiving time node while processing the data, and updates the transmitting node register table corresponding to the destination node according to the transmitting time node in the received RDMA communication node network and the current receiving time node; When the destination node sends a feedback signal to the information transmitting node, it simultaneously transmits the original transmission time node and receiving time node information. When the information transmitting node receives the data feedback signal, it also records the current receiving time node and updates the destination node register table of the corresponding information transmitting node according to the transmission time node and receiving time node information in the RDMA transmission information.

[0007] According to some embodiments, the present disclosure adopts the following technical solutions: FPGA-based RDMA data transmission optimization system, including: Initialization module, used to build the RDMA communication node network architecture with FPGA as the core; RDMA communication node network initialization, numbering the nodes existing in the network according to their physical locations, and setting a register table for each node, each register table entry includes data transmission time and data reception time; The data transmission optimization control module is used for the destination node to receive data in the RDMA communication node network, record the current receiving time node while processing the data, and update the transmitting node register table corresponding to the destination node according to the received transmitting time node in the RDMA communication node network and the current receiving time node; the destination node synchronously transmits the original transmitting time node and receiving time node information while sending a feedback signal to the information transmitting node, and when the information transmitting node receives the data feedback signal, it also records the current receiving time node, and updates the destination node register table corresponding to the information transmitting node according to the transmitting time node and receiving time node information in the RDMA transmission information.

[0008] According to some embodiments, the present disclosure adopts the following technical solutions: A computer program product comprises a computer program, wherein when the computer program is executed by a processor, the FPGA-based RDMA data transmission optimization method is implemented.

[0009] According to some embodiments, the present disclosure adopts the following technical solutions: A non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by a processor, the FPGA-based RDMA data transmission optimization method is implemented.

[0010] According to some embodiments, the present disclosure adopts the following technical solutions: An electronic device comprises: a processor, a memory and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory, so that the electronic device executes and implements the FPGA-based RDMA data transmission optimization method.

[0011] Compared with the prior art, the present invention has the following beneficial effects: The FPGA-based RDMA data transmission optimization method disclosed in the present invention makes full use of the programmability of FPGA to construct an FPGA hardware unit of an internalized smart network card. Specifically, the internal logic of FPGA is divided into two parts. One part is a heterogeneous acceleration module, which is responsible for utilizing the high concurrency characteristics of FPGA and computing units such as GPU to undertake distributed computing node computing acceleration tasks. The other part is an RDMA transmission control module, which is responsible for constructing an RDMA transmission data packet data link according to RDMA transmission requirements and completing the response data receiving and sending work. At the same time, in view of the RDMA network congestion problem, the present invention proposes a transmission optimization solution for network congestion, which maintains corresponding register tables for all transmission destination nodes in the FPGA transmission node to achieve flow control and congestion resolution based on the destination node.

[0012] The FPGA-based RDMA data transmission optimization method disclosed in the present invention fully utilizes the programmability and high concurrency of FPGA, reduces the hardware device complexity and CPU control overhead in distributed computing nodes, and provides a channel for distributed computing nodes to achieve heterogeneous acceleration between remote nodes through RDMA networks. At the same time, in view of the inefficiency of the existing congestion solution for RDMA transmission, a data transmission optimization solution is proposed, which dynamically controls the RDMA network transmission bandwidth according to the change of information transmission time of the information transmitting node-destination node pair, and has an excellent congestion resolution effect while ensuring fine granularity. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings constituting a part of the present disclosure are used to provide a further understanding of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure.

[0014] Figure 1 A schematic diagram of an RDMA communication node network with FPGA as the core according to an embodiment of the present disclosure; Figure 2 A schematic diagram of a transmission optimization solution for RDMA communication node network congestion according to an embodiment of the present disclosure.

[0015] in, Figure 2 (a) is the initialization phase; Figure 2 (b) in the figure is the dynamic allocation stage. DETAILED DESCRIPTION

[0016] The present disclosure is further described below in conjunction with the accompanying drawings and embodiments.

[0017] It should be noted that the following detailed descriptions are all illustrative and are intended to provide further explanation of the present disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present disclosure belongs.

[0018] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0019] Example 1 In one embodiment of the present disclosure, a method for optimizing RDMA data transmission based on FPGA is provided, including: Step 1: Build an RDMA communication node network architecture with FPGA as the core; Step 2: Initialize the RDMA communication node network, number the nodes in the network according to their physical locations, and set a register table for each node. Each register table entry includes the data transmission time and the data reception time. Step 3: After the destination node receives the data in the RDMA communication node network, it records the current receiving time node while processing the data, and updates the transmitting node register table corresponding to the destination node according to the transmitting time node in the received RDMA communication node network and the current receiving time node; Step 4: When the destination node sends a feedback signal to the information transmitting node, it simultaneously transmits the original transmission time node and receiving time node information. When the information transmitting node receives the data feedback signal, it also records the current receiving time node and updates the destination node register table of the corresponding information transmitting node according to the transmission time node and receiving time node information in the RDMA transmission information.

[0020] As an embodiment, the specific implementation process of the FPGA-based RDMA data transmission optimization method disclosed in the present invention includes: Step 1: Build an RDMA communication node network architecture with FPGA as the core; like Figure 1 As shown in the figure, each distributed computing node includes a CPU for comprehensive control inside the computing node, multiple hardware units such as GPUs and FPGAs for computing acceleration, and multiple distributed computing nodes complete the data transmission and reception between local nodes and network nodes through the RDMA transmission control module in the FPGA. Specifically, the FPGA node contains four parts, namely the data calculation processing module, the protocol encapsulation and unpacking module, the optimized congestion control module, and the data transmission and reception module. The latter three modules constitute the RDMA transmission control module inside the FPGA.

[0021] Among them, the data computing processing module, namely the heterogeneous acceleration module, instantiates multiple computing cores internally, and uses the high concurrency characteristics of FPGA and computing units such as GPU to undertake distributed computing node computing acceleration tasks. On the one hand, this module is associated with the local CPU and is responsible for accepting computing acceleration tasks sent from the local CPU. On the other hand, it is associated with the RDMA transmission control module inside the FPGA and is responsible for completing computing acceleration tasks from network nodes. That is, the FPGA heterogeneous acceleration module of this solution supports computing acceleration of local tasks, and also supports remote computing nodes to transmit computing task loads through the RDMA network to achieve computing acceleration of remote tasks.

[0022] The protocol encapsulation and unpacking module is the bottom-level module of the RDMA transmission control module inside the FPGA. It is mainly responsible for three tasks: on the one hand, it is responsible for receiving data information transmitted from the RDMA network, unpacking it into valid data according to the protocol specifications, and directly storing the valid data in the corresponding local CPU memory space; on the other hand, it is responsible for receiving computing task information transmitted from the RDMA network, sending it to the heterogeneous acceleration module inside the FPGA for calculation, and receiving the calculation result information of the heterogeneous computing module, packaging it and sending it back to the RDMA network; at the same time, it is responsible for packaging the valid data information in the local CPU memory into network transmission standard data specifications according to general protocol specifications, and sending it to the RDMA network.

[0023] The optimized congestion control module is the middle module of the RDMA transmission control module inside the FPGA, which is responsible for determining the transmission network bandwidth of the distributed computing node according to the degree of network congestion. In this module, each transmission destination node has a unique register table that maintains the time required for data transmission and reception, and determines the degree of network congestion from the node to the corresponding destination node in the network based on the dynamic change of this time. If the network is congested and hinders the data transmission of this module, the data transmission bandwidth from the distributed computing node to the corresponding destination node is reduced; if the network is restored, the data transmission bandwidth from the distributed computing node to the corresponding destination node is increased.

[0024] The data sending and receiving module is an external module of the RDMA transmission control module inside the FPGA. It is directly associated with the RDMA network and is mainly responsible for completing the data receiving and sending work. Specifically, on the one hand, this module needs to convert and transmit the data encapsulated by the protocol encapsulation and unpacking module or the received RDMA network data according to the corresponding RDMA network physical and electrical standards. On the other hand, the built-in routing unit determines the path of RDMA network transmission. At the same time, it needs to adapt and optimize the transmission bandwidth determined by the congestion control module to determine the data sending and receiving rate.

[0025] Step 2: Transmission optimization process for network congestion like Figure 2First, in the initialization phase of the RDMA network, the destination nodes in the network are numbered 1-n according to their physical locations (taking n other nodes in the RDMA network as an example, n is represented as an arbitrary number), and then a register table is maintained for each destination node. Since the transmission destination node needs to send feedback information to the information transmitting node to inform whether the information is successfully received during the RDMA network transmission process, the register entry of each destination node is divided into two parts, one is the transmission time, and the other is the reception time. During the initialization phase, the register table values ​​of all destination nodes are set to zero, the transmission bandwidth of all destination nodes is evenly distributed, and all destination node data information can be transmitted according to a fixed bandwidth. In addition, while transmitting all destination node data information, it is also necessary to synchronously transmit the current time node, that is, the transmission time node.

[0026] After receiving the data information in the RDMA network, the destination node records the receiving time of the current information, i.e., the receiving time node, while processing the data. Then, a transmitting time is calculated based on the transmitting time node in the received RDMA network and the current receiving time node and stored in the corresponding transmitting node register table in the destination node.

[0027] When the destination node sends a feedback signal to the information transmitting node, it also needs to synchronously transmit the original transmission time node and the newly recorded receiving time node information. When the information transmitting node receives the data feedback signal, it also records the current time node and updates the destination node register table in the corresponding information transmitting node according to the transmission time node and receiving time node information in the RDMA transmission information.

[0028] As an embodiment, the above process is described by taking the information transmitting node 1 sending data to the destination node 4 as an example: First, at time 0, information transmitting node 1 sends data to destination node 4. While transmitting valid data, it also transmits the current time node, i.e., transmitting time node 0. Then, at time 5, the destination node 4 receives the data from the information transmitting node 1 in the RDMA network, records the current time node, i.e., the receiving time node 5, and calculates a transmitting time 5 according to the receiving time node 5 and the transmitting time node 0 and stores it in the transmitting time of the node 1 register table in the destination node 4; Then, the destination node 4 needs to send the information feedback signal to the information transmitting node 1, and simultaneously transmit the receiving time node 5 and the transmitting time node 0 to the information transmitting node 1; Finally, at time 8, the information transmitting node 1 receives the feedback data from the destination node 1 in the RDMA network, records the current time node 8, and calculates the transmission time as 5 and the reception time as 3 based on the reception time node 5 and the transmission time node 0 in the information, and stores them in the transmission time and reception time of the node 4 register table in the information transmitting node 1.

[0029] The above process is continuously performed and the transmission time and reception time between the corresponding information transmission node and the destination node are recorded, and the network transmission bandwidth of the corresponding destination node is determined based on the transmission time and reception time relationship between the information transmission node and the destination node. When the network congestion level remains unchanged, the transmission time and reception time between any two information transmission node and the destination node will not change much, but if the network is congested, the corresponding transmission time and reception time will be greatly increased. At this time, it is necessary to reduce the data bandwidth of the corresponding information transmission node and the destination node, that is, Figure 2 As shown in (b).

[0030] Furthermore, the changes in the transmission time and reception time caused by the change in network congestion can be divided into the following four types: The first type is that both the transmission time and the reception time increase, and the reception time is greater than the transmission time, which indicates that the network from the information transmission node to the corresponding destination node is congested and the congestion is aggravated. At this time, the information transmission node needs to significantly reduce the transmission bandwidth to the corresponding destination node, such as Figure 2 (b) is shown as destination node 4; as in the second case, both the transmission time and the receiving time become longer, but the receiving time is less than the transmission time, which indicates that the network from the information transmitting node to the corresponding destination node is congested but the congestion is less severe. At this time, the information transmitting node can slightly reduce the transmission bandwidth to the corresponding destination node, as shown in Figure 2 (b) as shown in the destination node 3; the third type, the transmission time becomes longer and the reception time becomes shorter, but both are greater than the original transmission time and reception time, which indicates that the network from the information transmitting node to the corresponding destination node is congested but the congestion is gradually improving. At this time, the information transmitting node can maintain the transmission bandwidth to the corresponding destination node, as shown in Figure 2 (b) as shown in the destination node 2; the fourth type, the transmission time and the receiving time are both smaller, but both are greater than the original transmission time and receiving time, which indicates that the network from the information transmitting node to the corresponding destination node is congested but the congestion is improving rapidly. At this time, the information transmitting node can maintain the transmission bandwidth to the corresponding destination node, and after the transmission time and receiving time return to the original time, slightly increase the transmission bandwidth to the corresponding destination node to improve the information transmission efficiency, as shown in Figure 2 As shown in (b), the destination node is 1.

[0031] Example 2 In one embodiment of the present disclosure, a FPGA-based RDMA data transmission optimization system is provided, including: Initialization module, used to build the RDMA communication node network architecture with FPGA as the core; RDMA communication node network initialization, numbering the nodes existing in the network according to their physical locations, and setting a register table for each node, each register table entry includes data transmission time and data reception time; The data transmission optimization control module is used for the destination node to receive data in the RDMA communication node network, record the current receiving time node while processing the data, and update the transmitting node register table corresponding to the destination node according to the received transmitting time node in the RDMA communication node network and the current receiving time node; the destination node synchronously transmits the original transmitting time node and receiving time node information while sending a feedback signal to the information transmitting node, and when the information transmitting node receives the data feedback signal, it also records the current receiving time node, and updates the destination node register table corresponding to the information transmitting node according to the transmitting time node and receiving time node information in the RDMA transmission information.

[0032] Example 3 In one embodiment of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the FPGA-based RDMA data transmission optimization method is implemented.

[0033] Example 4 In one embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium is used to store computer instructions, and when the computer instructions are executed by a processor, the FPGA-based RDMA data transmission optimization method is implemented.

[0034] Example 5 In one embodiment of the present disclosure, an electronic device is provided, including: a processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory, so that the electronic device executes and implements the FPGA-based RDMA data transmission optimization method.

[0035] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0036] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0037] Although the above describes the specific implementation methods of the present disclosure in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present disclosure. Technical personnel in the relevant field should understand that on the basis of the technical solution of the present disclosure, various modifications or variations that can be made by those skilled in the art without creative work are still within the scope of protection of the present disclosure.

Claims

1. The FPGA-based RDMA data transmission optimization method is characterized by: include: Build an RDMA communication node network architecture with FPGA as the core; Initialize the RDMA communication node network, number the nodes in the network according to their physical locations, and set a register table for each node. Each register table entry includes the data transmission time and the data reception time; After receiving the data in the RDMA communication node network, the destination node records the current receiving time node while processing the data, and updates the transmitting node register table corresponding to the destination node according to the transmitting time node in the received RDMA communication node network and the current receiving time node; When the destination node sends a feedback signal to the information transmitting node, it simultaneously transmits the original transmission time node and receiving time node information. When the information transmitting node receives the data feedback signal, it also records the current receiving time node and updates the destination node register table of the corresponding information transmitting node according to the transmission time node and receiving time node information in the RDMA transmission information.

2. The FPGA-based RDMA data transmission optimization method according to claim 1, characterized in that: In the RDMA communication node network architecture with FPGA as the core, each distributed computing node contains a CPU for comprehensive control within the computing node, multiple hardware units such as GPUs and FPGAs for computing acceleration, and multiple distributed computing nodes complete the data transmission and reception between local nodes and network nodes through RDMA transmission control within the FPGA.

3. The FPGA-based RDMA data transmission optimization method according to claim 1, characterized in that: The RDMA communication node with FPGA as the core includes data computing processing, protocol encapsulation, optimized congestion control and data transmission and reception. The data computing processing is heterogeneous acceleration processing. By instantiating multiple computing cores internally, the high concurrency characteristics of FPGA and GPU computing units are used to undertake distributed computing node computing acceleration tasks.

4. The FPGA-based RDMA data transmission optimization method according to claim 3, characterized in that: Protocol encapsulation includes: receiving data information transmitted by the RDMA communication node network, unpacking it to obtain valid data according to the protocol specifications, and directly storing the valid data in the corresponding local CPU memory space; receiving computing task information transmitted by the RDMA network, sending it to the FPGA for heterogeneous accelerated computing, and receiving computing result information, packaging it and sending it back to the RDMA communication node network; at the same time, it is responsible for packaging the valid data information in the local CPU memory into network transmission standard data specifications according to the protocol specifications, and sending it to the RDMA communication node network.

5. The FPGA-based RDMA data transmission optimization method according to claim 1, characterized in that: During the RDMA communication node network transmission process, the transmission destination node needs to send feedback information to the information transmitting node to inform whether the information is successfully received. The register entry of each destination node is divided into two parts, one is the transmission time, and the other is the reception time. During the initialization phase, the register table values ​​of all destination nodes are set to zero, the transmission bandwidth of all destination nodes is evenly distributed, and all destination node data information can be transmitted according to a fixed bandwidth; and while transmitting all destination node data information, the current time node, that is, the transmission time node, is synchronously transmitted.

6. The FPGA-based RDMA data transmission optimization method according to claim 1, characterized in that: There are four types of changes in the transmission time and reception time caused by changes in network congestion: the first type is that both the transmission time and the reception time increase, and the reception time is greater than the transmission time, which indicates that the network from the information transmission node to the corresponding destination node is congested and the congestion is aggravated severely. At this time, the information transmission node reduces the transmission bandwidth to the corresponding destination node; the second type is that both the transmission time and the reception time increase, but the reception time is less than the transmission time, which indicates that the network from the information transmission node to the corresponding destination node is congested but the congestion is slightly aggravated. At this time, the information transmission node slightly reduces the transmission bandwidth to the corresponding destination node; The third type is that the transmission time becomes longer and the receiving time becomes shorter, but both are greater than the original transmission time and receiving time, which indicates that the network from the information transmitting node to the corresponding destination node is congested but the congestion is gradually improving. At this time, the information transmitting node maintains the transmission bandwidth to the corresponding destination node; the fourth type is that both the transmission time and the receiving time become shorter, but both are greater than the original transmission time and receiving time, which indicates that the network from the information transmitting node to the corresponding destination node is congested but the congestion is rapidly improving. At this time, the information transmitting node maintains the transmission bandwidth to the corresponding destination node, and after the transmission time and receiving time return to the original time, the transmission bandwidth to the corresponding destination node is slightly increased.

7. FPGA-based RDMA data transmission optimization system, characterized in that: include: Initialization module, used to build the RDMA communication node network architecture with FPGA as the core; Initialize the RDMA communication node network, number the nodes in the network according to their physical locations, and set a register table for each node. Each register table entry includes the data transmission time and the data reception time; The data transmission optimization control module is used for the destination node to receive data from the RDMA communication node network, record the current receiving time node while processing the data, and update the transmitting node register table corresponding to the destination node according to the transmitting time node in the received RDMA communication node network and the current receiving time node; When the destination node sends a feedback signal to the information transmitting node, it simultaneously transmits the original transmission time node and receiving time node information. When the information transmitting node receives the data feedback signal, it also records the current receiving time node and updates the destination node register table of the corresponding information transmitting node according to the transmission time node and receiving time node information in the RDMA transmission information.

8. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the FPGA-based RDMA data transmission optimization method according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium is used to store computer instructions, and when the computer instructions are executed by the processor, the FPGA-based RDMA data transmission optimization method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: A processor, a memory and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory so that the electronic device executes the FPGA-based RDMA data transmission optimization method as described in any one of claims 1 to 7.

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