Display device and wearable electronic device

Abstract

A display device and a wearable electronic device are provided, the display device including a base layer defining a trench and first and second sub-pixels at opposite sides of the trench, each of the first and second sub-pixels including a first electrode, a first emission structure, a first intermediate layer, a second emission structure, and a second electrode, the first electrode is on the base layer, the first emission structure is on the first electrode, the first emission structure comprises a first hole transport layer, a first emission layer and a first electron transport layer, the thickness of the first hole transport layer is smaller than the depth of the trench, the first intermediate layer is on the first emission structure, and the second emission structure is on the first intermediate layer. The second emission structure comprises a second hole transport layer, a second emission layer and a second electron transport layer, the thickness of the second hole transport layer is larger than the depth of the trench, and the second electrode is arranged on the second emission structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0109002, filed on August 21, 2023, and Korean Patent Application No. 10-2023-0153854, filed on November 8, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to display devices and wearable electronic devices. Background Art

[0004] Organic light emitting diodes (OLEDs) are active light emitting display devices that have a wide viewing angle, excellent contrast, a lightweight and slim profile, a fast response time, and are capable of low voltage driving.

[0005] One pixel may have a structure in which an emission layer is stacked. The emission layer may extend commonly and continuously across sub-pixels within the pixel.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] In a display device (e.g., an ultra-high resolution display device), the spacing between sub-pixels may be narrow. Accordingly, leakage current (or lateral leakage current phenomenon) may occur between adjacent sub-pixels through a common emission layer, and the sub-pixels may not emit light at a desired brightness. In other words, the display quality may be degraded.

[0008] Some aspects of some embodiments of the present disclosure provide a display device (eg, a wearable electronic device) with improved display quality.

[0009] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned herein will be clearly understood by those of ordinary skill in the art from the following description.

[0010] According to some embodiments of the present disclosure, a display device is provided, which includes a base layer defining a groove and a first sub-pixel and a second sub-pixel at opposite sides of the groove, each of the first sub-pixel and the second sub-pixel including a first electrode, a first emission structure, a first intermediate layer, a second emission structure, and a second electrode, the first electrode being on the base layer, the first emission structure being on the first electrode and configured to emit light, the first emission structure including a first hole transport layer, a first emission layer, and a first electron transport layer, the thickness of the first hole transport layer being less than the depth of the groove, the first intermediate layer being on the first emission structure, the second emission structure being on the first intermediate layer and configured to emit light, the second emission structure including a second hole transport layer, a second emission layer, and a second electron transport layer, the thickness of the second hole transport layer being greater than the depth of the groove, and the second electrode being on the second emission structure.

[0011] The trench may include a first trench surrounding the first sub-pixel in a plan view and a second trench surrounding the second sub-pixel in a plan view, and the first trench and the second trench may be spaced apart from each other.

[0012] The depth of the groove can be about to about The width of the groove can be about to about The thickness of the first hole transport layer may be about to about And the thickness of the second hole transport layer may be about to about

[0013] The first hole transport layer may include a material different from that of the second hole transport layer.

[0014] The glass transition temperature of the second hole transport layer may be about 10% to about 30% higher than the glass transition temperature of the first hole transport layer.

[0015] The glass transition temperature of the second hole transport layer may be about 15° C. to about 35° C. higher than the glass transition temperature of the first hole transport layer.

[0016] The thickness of the second electrode may be about to about

[0017] The step of the second electrode on the groove may be about or smaller.

[0018] The thickness of the first emission structure may be smaller than the depth of the trench, and the thickness of the second emission structure may be larger than the depth of the trench.

[0019] The thickness of the first emission structure may be less than or equal to about 70% of the depth of the trench, and the thickness of the second emission structure may be greater than or equal to about 160% of the depth of the trench.

[0020] The depth of the groove can be about to about The width of the groove can be about to about The thickness of the first emitting structure may be about to about And the thickness of the second emitting structure may be about to about

[0021] The first emission structure and the first intermediate layer of the first subpixel may be separated from the first emission structure and the first intermediate layer of the second subpixel at the groove, and at least a portion of the second emission structure of the first subpixel may be connected to at least a portion of the second emission structure of the second subpixel on the groove.

[0022] The first subpixel and the second subpixel may each further include a third emission structure positioned between the first electrode and the first emission structure and configured to emit light, and a second intermediate layer positioned between the third emission structure and the first emission structure, and the third emission structure and the second intermediate layer of the first subpixel may be separated from the third emission structure and the second intermediate layer of the second subpixel at the groove.

[0023] The first emitting structure may be configured to emit light of a first color, and the second emitting structure may be configured to emit light of a second color different from the first color.

[0024] The first emitting structure and the second emitting structure may be configured to emit light of the same color.

[0025] According to other embodiments of the present disclosure, a display device is provided, which includes a first electrode, a first emission structure, an intermediate layer, a second emission structure, and a second electrode, the first electrode being on a base layer, the first emission structure being on the first electrode and configured to emit light, the first emission structure including a first hole transport layer, a first emission layer, and a first electron transport layer, the intermediate layer being on the first emission structure, the second emission structure being on the intermediate layer and configured to emit light, the second emission structure including a second hole transport layer, a second emission layer, and a second electron transport layer, the glass transition temperature of the second hole transport layer being approximately 10% to approximately 30% higher than the glass transition temperature of the first hole transport layer, and the second electrode being on the second emission structure.

[0026] The glass transition temperature of the second hole transport layer may be about 15° C. to about 35° C. higher than the glass transition temperature of the first hole transport layer.

[0027] According to other embodiments of the present disclosure, a wearable electronic device is provided, which includes a display panel configured to emit light and at least one lens on the display panel, the display panel including a base layer defining a groove and a first sub-pixel and a second sub-pixel at opposite sides of the groove, each of the first sub-pixel and the second sub-pixel including a first electrode, a first emission structure, an intermediate layer, a second emission structure, and a second electrode, the first electrode being on the base layer, the first emission structure being on the first electrode and configured to emit light, the first emission structure including a first hole transport layer, a first emission layer, and a first electron transport layer, the thickness of the first hole transport layer being less than the depth of the groove, the intermediate layer being on the first emission structure, the second emission structure being on the intermediate layer and configured to emit light, the second emission structure including a second hole transport layer, a second emission layer, and a second electron transport layer, the thickness of the second hole transport layer being greater than the depth of the groove, and the second electrode being on the second emission structure.

[0028] The glass transition temperature of the second hole transport layer may be about 10% to about 30% higher than the glass transition temperature of the first hole transport layer.

[0029] The glass transition temperature of the second hole transport layer may be about 15° C. to about 35° C. higher than the glass transition temperature of the first hole transport layer.

[0030] Aspects of some other embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0033] Figure 2 It is a diagram showing some embodiments of the present disclosure including Figure 1 Block diagram of a sub-pixel in a display device.

[0034] Figure 3 is a diagram showing some embodiments of the present disclosure Figure 2 Circuit diagram of a sub-pixel.

[0035] Figure 4 is a diagram showing some embodiments of the present disclosure Figure 1 A plan view of a display device.

[0036] Figure 5 is a diagram showing some embodiments of the present disclosure Figure 4 An exploded perspective view of a display device.

[0037] Fig. 6A , Figure 6B and Figure 6C It is a diagram showing some embodiments of the present disclosure including Figure 5 Plan views of some embodiments of pixels in a display device.

[0038] Figure 7 is a diagram showing some embodiments of the present disclosure. Fig. 6A A cross-sectional view of the display device taken along line II'.

[0039] Figure 8 According to some embodiments of the present disclosure Figure 7 An enlarged cross-sectional view of a portion of a display device.

[0040] Fig. 9 It is a diagram showing some embodiments of the present disclosure including Figure 7 A cross-sectional view of an emission structure in a display device.

[0041] Fig.10 is a diagram showing some embodiments of the present disclosure Figure 8 An image of a display device.

[0042] Fig.11 is a diagram showing some embodiments of the present disclosure. Fig. 6A A cross-sectional view of another embodiment of a display device taken along line II'.

[0043] Fig.12 According to some embodiments of the present disclosure Fig.11 An enlarged cross-sectional view of a portion of a display device.

[0044] Fig.13 It is a diagram showing some embodiments of the present disclosure including Fig.11 A cross-sectional view of an emission structure in a display device.

[0045] Fig.14 It is a diagram showing some embodiments of the present disclosure including Figure 5 A plan view of a pixel in a display device.

[0046] Fig.15 is a diagram showing some embodiments of the present disclosure. Fig.14 A cross-sectional view of the display device taken along line II-II'.

[0047] Fig.16 is a diagram showing some embodiments of the present disclosure. Fig.14 A cross-sectional view of the display device taken along line II-II'.

[0048] Fig.17 According to some embodiments of the present disclosure Fig.16An enlarged cross-sectional view of a portion of a display device.

[0049] Fig.18 is a block diagram illustrating a display system according to some embodiments of the present disclosure.

[0050] Fig.19 is a diagram showing some embodiments of the present disclosure Fig.18 A perspective view showing an application example of the display system.

[0051] Fig. 20 is a diagram showing a device worn by a user according to some embodiments of the present disclosure Fig.19 Figure 2 shows an example of an application of . DETAILED DESCRIPTION

[0052] Hereinafter, some embodiments will be described in more detail with reference to the accompanying drawings. It should be noted that only the parts necessary for understanding the operation according to the present disclosure will be described below, and the description of other parts will not be provided so as not to obscure the main idea of ​​the present disclosure. In some embodiments, the present disclosure is not limited to the embodiments described herein and can be implemented in other forms. Hereinafter, the embodiments will be described in more detail so that those of ordinary skill in the art can easily implement the technical ideas of the present disclosure.

[0053] It should be understood that when a part is referred to as being "connected to" another part, it may be "directly connected to" another part or "indirectly connected to" another part across an intervening part. The terms used in this article are intended to describe specific embodiments and are not intended to limit the present disclosure. It should be understood that the terms "include", "comprise" or "have" as used herein specify the presence of the elements stated, but do not exclude the presence or addition of one or more other elements. The expressions "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ, etc.). The terms "or" and "and / or" as used herein include any combination of one or more of the elements.

[0054] It should be understood that although terms such as "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Accordingly, without departing from the scope of the present disclosure, the first element can be referred to as the second element.

[0055] Spatially relative terms such as "below", "above" etc. can be used for descriptive purposes, thereby describing the relationship between an element or feature and another (some) element or feature as shown in the drawings. In addition to the directions depicted in the drawings, spatially relative terms are also intended to include different directions in use, operation and / or manufacture. For example, when the device shown in the figure is turned over, the element depicted as being positioned "below" another element or feature is positioned "above" other elements or features. Accordingly, in some embodiments, the term "below" may include both an upward direction and a downward direction. In some embodiments, the device may be oriented in other directions (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative terms as used in this article should be interpreted accordingly.

[0056] Some embodiments are described with reference to the accompanying drawings related to functional blocks, units and / or modules. It will be understood by those of ordinary skill in the art that these blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and optionally, can be driven by firmware and / or software. In some embodiments, the corresponding blocks, units and / or modules can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions. In some embodiments, within the scope of the present disclosure, blocks, units and / or modules can be physically divided into two or more separate blocks, units and / or modules that interact with each other. In some embodiments, blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0057] Various embodiments are described with reference to the accompanying drawings that schematically illustrate non-limiting embodiments. Accordingly, it is expected that the shapes may vary depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be interpreted as limited to the specific shapes shown, but should be interpreted as including changes in shape that occur, for example, due to manufacturing. Thus, the shapes shown in the accompanying drawings may not depict the actual shape of an area of ​​the device, and the present embodiments are not limited thereto.

[0058] When a specific embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0059] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measurements or calculations recognized by those of ordinary skill in the art. In addition, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0060] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those generally understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly rigid sense unless explicitly defined as such herein.

[0061] Figure 1 is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0062] Reference Figure 1 , the display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0063] The display panel 110 may include subpixels SP. The subpixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The subpixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn. Herein, each of m and n may be a natural number greater than 0.

[0064] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. For example, the light-emitting element may be an organic light-emitting diode having a series structure. Accordingly, each of the sub-pixels SP may generate light of a specific color (such as red, green, blue, cyan, magenta, yellow, etc.). Two or more sub-pixels among the sub-pixels SP may constitute a pixel PXL capable of expressing full color. For example, Figure 1 As shown in FIG. , three sub-pixels may constitute one pixel PXL.

[0065] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In some embodiments, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data signal, and the like.

[0066] In some embodiments, the display panel 110 may further include first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP arranged in the row direction. In this case, similar to the gate signal, the gate driver 120 may output the emission control signal to the first to m-th emission control lines EL1 to ELm. For example, the gate driver 120 may include an emission control driver that outputs the emission control signal.

[0067] The gate driver 120 may be disposed on one side of the display panel 110. However, the present disclosure is not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers. Such a driver may be positioned (or provided) on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side. Thus, according to some embodiments, the gate driver 120 may be arranged around the display panel 110 in various shapes.

[0068] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 receives the image data DATA and the data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In some embodiments, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0069] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn by using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the first to n-th data lines DL1 to DLn. Accordingly, the corresponding sub-pixel SP may generate light corresponding to the data signal. Accordingly, an image may be displayed on the display panel 110.

[0070] In some embodiments, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0071] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may be configured to generate a plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0072] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first power supply voltage VDD and the second power supply voltage VSS may be provided to the sub-pixel SP. The second power supply voltage VSS may have a voltage level lower than that of the first power supply voltage VDD. In some other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by a device outside the display device 100.

[0073] In some embodiments, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied to the sub-pixel SP. For example, during a sensing operation of sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a specific reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate the reference voltage.

[0074] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling display of the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0075] Controller 150 may convert input image data IMG into image data DATA suitable for display device 100 or display panel 110 and output image data DATA. In some embodiments, controller 150 may output image data DATA by aligning input image data IMG to fit sub-pixels SP in row units.

[0076] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140 and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140 and the controller 150 may be functionally separated components within one driver integrated circuit DIC. In some other embodiments, at least one of the data driver 130, the voltage generator 140 and the controller 150 may be provided as a component separated from the driver integrated circuit DIC.

[0077] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense an ambient temperature and generate temperature data TEP representing the sensed temperature. In some embodiments, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0078] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In some embodiments, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first power supply voltage VDD and the second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0079] Figure 2 It is a diagram showing some embodiments of the present disclosure including Figure 1 Block diagram of a sub-pixel in a display device.

[0080] Figure 2 The sub-pixels SPij arranged in an i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and a j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) are shown.

[0081] Reference Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC (or pixel circuit) and a light emitting element LD.

[0082] The light emitting element LD may be connected between the first power supply voltage node VDDN (or the first power supply line) and the second power supply voltage node VSSN (or the second power supply line). Figure 1 The first power supply voltage node VDD and the second power supply voltage node VSSN are configured to transmit Figure 1 A node of a second power supply voltage VSS.

[0083] The anode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode CE of the light emitting element LD may be connected to the second power supply voltage node VSSN. For example, the anode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0084] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the gate lines GL1 to GLm, Figure 1The i-th emission control line ELi among the emission control lines EL1 to ELm and Figure 1 The j-th data line DLj among the data lines DL1 to DLn may be connected to the signal line DL1 and the light emitting element LD may be controlled to generate light according to a signal received through the signal line DL1.

[0085] The i-th gate line GLi may include one or more sub-gate lines (or scan lines). Figure 2 As shown in , the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal (or scan signal) received through the first sub-gate line SGL1 and the second sub-gate line SGL2 (or the first scan line and the second scan line).

[0086] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Accordingly, the light emitting element LD may generate light having a brightness corresponding to the data signal.

[0087] In some embodiments, the sub-pixel SPij may also be connected to the i-th emission control line ELi. The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. For example, the sub-pixel circuit SPC may adjust a current flowing from the first power supply voltage node VDDN through the light emitting element LD to the second power supply voltage node VSSN according to a stored voltage in response to the emission control signal received through the i-th emission control line ELi.

[0088] In some embodiments, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received through a corresponding sub-emission control line.

[0089] Figure 3 is a diagram showing some embodiments of the present disclosure Figure 2 Circuit diagram of a sub-pixel.

[0090] Reference Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0091] The sub-pixel circuit SPC may be connected to the i-th gate line GLi', the i-th emission control line ELi', and the j-th data line DLj. Figure 2 Compared with the i-th gate line GLi, the i-th gate line GLi′ may further include a third sub-gate line SGL3 (or a third scan line). Figure 2Compared with the i-th emission control line ELi, the i-th emission control line ELi′ may include a first sub-emission control line SEL1 and a second sub-emission control line SEL2.

[0092] The sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

[0093] The first transistor T1 may be connected between the first power supply voltage node VDDN and the first node N1. The gate (or gate electrode) of the first transistor T1 may be connected to the second node N2, and thus, the first transistor T1 may be turned on in response to the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0094] The second transistor T2 may be connected between the jth data line DLj and the second node N2. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1, and thus, the second transistor T2 may be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0095] The third transistor T3 may be connected between the first node N1 and the second node N2. A gate of the third transistor T3 may be connected to the second sub-gate line SGL2, and thus, the third transistor T3 may be turned on in response to a gate signal of the second sub-gate line SGL2.

[0096] The fourth transistor T4 may be connected between the first node N1 and the anode AE ​​of the light emitting element LD. A gate of the fourth transistor T4 may be connected to the second sub emission control line SEL2, and thus the fourth transistor T4 may be turned on in response to an emission control signal of the second sub emission control line SEL2.

[0097] The fifth transistor T5 may be connected between the anode AE ​​of the light emitting element LD and the initialization voltage node VINTN (or the initialization voltage line). The initialization voltage node VINTN may be configured to transmit an initialization voltage. In some embodiments, the initialization voltage may be Figure 1 In another embodiment, the initialization voltage may be provided by the display device 100 (see Figure 1 ) is provided by an external device. A gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3, and thus, the fifth transistor T5 may be turned on in response to a gate signal of the third sub-gate line SGL3.

[0098] The sixth transistor T6 may be connected between the first power supply voltage node VDDN and the first transistor T1. A gate of the sixth transistor T6 may be connected to the first sub emission control line SEL1, and thus the sixth transistor T6 may be turned on in response to the emission control signal of the first sub emission control line SEL1.

[0099] The first capacitor C1 may be connected between the second transistor T2 and the second node N2. The second capacitor C2 may be connected between the first power supply voltage node VDDN and the second node N2.

[0100] Thus, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first capacitors C1 and second capacitors C2. However, the present disclosure is not limited thereto. The sub-pixel circuit SPC may be implemented as one of various types (e.g., appropriate types) of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. According to some embodiments of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' may be changed.

[0101] The first transistor T1 to the sixth transistor T6 may each be a P-type transistor. The first transistor T1 to the sixth transistor T6 may each be a metal oxide semiconductor field effect transistor (MOSFET). However, the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the sixth transistor T6 may be replaced with an N-type transistor.

[0102] In some embodiments, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a polycrystalline silicon semiconductor, a single crystal silicon semiconductor, an oxide semiconductor, or the like.

[0103] The light emitting element LD may include an anode AE, a cathode CE, and an emission layer. The emission layer may be arranged between the anode AE ​​and the cathode CE. The first transistor T1 may be turned on in response to the voltage of the second node N2, and the fourth transistor T4 and the sixth transistor T6 may be turned on in response to the emission control signal (e.g., a turn-on voltage level, a low level, etc.) applied to the first sub-emission control line SEL1 and the second sub-emission control line SEL2. Accordingly, a current may flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD may emit light according to the amount of current flowing therethrough.

[0104] Figure 4 is a diagram showing some embodiments of the present disclosure Figure 1 A plan view of a display device.

[0105] Figure 4 A display panel DP constituting the display device is shown.

[0106] Reference Figure 4 , the display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed around the display area DA.

[0107] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0108] When the display panel DP is used as a display screen for a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP may be positioned very close to the user's eyes. In this case, sub-pixels SP having a relatively high degree of integration may be required. In order to increase the degree of integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on a substrate SUB which is a silicon substrate. A display device including a display panel DP formed on a substrate SUB which is a silicon substrate (see Figure 1 100) may be referred to as an OLED-on-silicon (OLEDoS) display device.

[0109] The sub-pixels SP may be arranged in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix form in a first direction DR1 and a second direction DR2 crossing the first direction DR1. However, the present disclosure is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag shape in the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0110] As reference Figure 1 As described above, two or more sub-pixels among the plurality of sub-pixels SP may constitute one pixel PXL.

[0111] A component for controlling the sub-pixel SP may be disposed in the non-display area NDA on the substrate SUB. For example, a line (such as a Figure 1 The first gate lines GL1 to the m-th gate lines GLm and the first data lines DL1 to the n-th data lines DLn) may be disposed in the non-display area NDA.

[0112] In some embodiments, Figure 1 The gate driver 120 may be mounted on the display panel DP and disposed in the non-display area NDA. In another embodiment, the gate driver 120 may be implemented as an integrated circuit separated from the display panel DP.

[0113] The pad PD may be disposed in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be electrically connected to the sub-pixel SP through the first data line DL1 to the nth data line DLn (see Figure 1 ) is connected to the sub-pixel SP.

[0114] The pad PD can connect the display panel DP interface to the display device (see Figure 1 In some embodiments, the pad PD can be used to connect other components of the device. Figure 1 The driver integrated circuit DIC provides voltages and signals required for the operation of components included in the display panel DP. For example, the first to nth data lines DL1 to DLn may be connected to the driver integrated circuit DIC through the pads PD. For example, the driver integrated circuit DIC may receive a first power supply voltage VDD and a second power supply voltage VSS (see Figure 1 ). When the gate driver 120 (see Figure 1 ) is mounted on the display panel DP, the gate control signal GCS (see Figure 1 ) can be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0115] In some embodiments, the circuit board may be electrically connected to the pad PD by using a conductive adhesive member such as an anisotropic conductive film. At this time, the circuit board may be a flexible circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit DIC may be mounted on the circuit board and electrically connected to the pad PD.

[0116] In some embodiments, the display area DA may have various shapes. The display area DA may have a closed loop shape including straight edges and / or curved edges. For example, the display area DA may have a shape such as a polygonal shape, a circular shape, a semicircular shape, or an elliptical shape.

[0117] In some embodiments, the display panel DP may have a flat display surface. In some other embodiments, the display panel DP may have a display surface that is at least partially circular. In some embodiments, the display panel DP may be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB may include a material having a flexible property.

[0118] Figure 5 is a diagram showing some embodiments of the present disclosure Figure 4 An exploded perspective view of a display device.

[0119] For the sake of clarity and brief explanation, Figure 5 The display panel DP (see Figure 4 ) and Figure 4 Portions of the display panel DP corresponding to two pixels PXL1 and PXL2 among the pixels PXL of the display panel DP may be configured in a similar manner.

[0120] Reference Figure 4 and Figure 5, the first pixel PXL1 and the second pixel PXL2 may each include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the present disclosure is not limited thereto. For example, the first pixel PXL1 and the second pixel PXL2 may each include four sub-pixels or two sub-pixels.

[0121] Figure 5 It is shown that the first to third sub-pixels SP1 to SP3 each have a rectangular shape and have the same size when viewed from a third direction DR3 (e.g., a thickness direction) intersecting the first direction DR1 and the second direction DR2. However, the present disclosure is not limited thereto. The first to third sub-pixels SP1 to SP3 may each be modified to have various shapes.

[0122] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0123] In some embodiments, the substrate SUB may include a silicon wafer substrate formed by using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium and / or silicon germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer. In some other embodiments, the substrate SUB may include a glass substrate. In some other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0124] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may each include an insulating layer and a conductive pattern disposed between the insulating layers. For example, the conductive pattern of the pixel circuit layer PCL may be used as at least some of circuit elements, lines, etc. The conductive pattern may include copper, but the present disclosure is not limited thereto.

[0125] The pixel circuit layer PCL may include a sub-pixel circuit SPC of each of the first to third sub-pixels SP1 to SP3 (see Figure 2). For example, the pixel circuit layer PCL may include transistors and capacitors as circuit elements. The transistors may each include a semiconductor pattern including a source region, a drain region and a channel region, a gate electrode overlapping the semiconductor pattern, and a source electrode and a drain electrode connected to the source region and the drain region. In some embodiments, when the substrate SUB is provided as a silicon substrate, the semiconductor pattern may be provided in the substrate SUB, and the gate electrode and the source electrode and the drain electrode may be provided in the pixel circuit layer PCL. In some embodiments, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor pattern, the gate electrode and the source electrode and the drain electrode may be provided in the pixel circuit layer PCL. The capacitors may each include electrodes spaced apart from each other. For example, the capacitors may each include electrodes spaced apart from each other on a plane defined by the first direction DR1 and the second direction DR2. For example, the capacitors may each include electrodes spaced apart from each other via an insulating layer in the third direction DR3.

[0126] The pixel circuit layer PCL may include a signal line connected to each of the first to third sub-pixels SP1 to SP3. For example, the pixel circuit layer PCL may include lines such as gate lines, emission control lines, and data lines. The lines may also include lines connected to Figure 2 In some embodiments, the line may also include a line connected to the first power supply voltage node VDDN. Figure 2 A line to the second power supply voltage node VSSN.

[0127] The light emitting element layer LDL may include an anode AE, an emission structure EU, a cathode CE, and a pixel defining layer PDL.

[0128] The anode AE ​​(or the first electrode) may be disposed on the pixel circuit layer PCL. The anode AE ​​may be connected to a circuit element (eg, Figure 3 The anode AE ​​may include an opaque conductive material capable of reflecting light, but the present disclosure is not limited thereto.

[0129] The pixel defining layer PDL may be disposed on the anode AE. The pixel defining layer PDL may include openings OP respectively exposing portions of the anode AE. The openings OP of the pixel defining layer PDL may be understood as emission regions respectively corresponding to the first to third sub-pixels SP1 to SP3.

[0130] In some embodiments, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x In some other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0131] The emission structure EU may be disposed on the anode AE ​​exposed by the opening OP of the pixel defining layer PDL. The emission structure EU may include an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, and an emission layer in which holes and electrons are recombined to form excitons and generate light.

[0132] In some embodiments, the emission structure EU may fill the opening OP of the pixel defining layer PDL and may be completely disposed on the upper portion of the pixel defining layer PDL. In other words, the emission structure EU may extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, some layers in the emission structure EU may be disconnected or bent at the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the present disclosure is not limited to this. For example, portions of the emission structure EU corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other and may be disposed within the opening OP of the pixel defining layer PDL.

[0133] The cathode CE may be disposed on the emission structure EU. The cathode CE may extend across the first to third sub-pixels SP1 to SP3. Thus, the cathode CE may serve as a common electrode for the first to third sub-pixels SP1 to SP3.

[0134] The cathode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the emission structure EU. The cathode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In some embodiments, the cathode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. However, the material of the cathode CE is not limited thereto.

[0135] One of the anodes AE, the portion of the emission structure EU overlapping with one of the anodes AE, and the portion of the cathode CE overlapping with one of the anodes AE can be understood to constitute a light-emitting element (see Figure 2 LD). In other words, the light emitting elements of the first sub-pixel SP1 to the third sub-pixel SP3 may each include an anode, a portion of the emission structure EU overlapping the anode, and a portion of the cathode CE overlapping the anode. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode AE ​​and electrons injected from the cathode CE are transferred to the emission structure EU to form excitons. When the excitons transition from an excited state to a ground state, light may be generated. The brightness of the light may be determined according to the amount of current flowing through the emission structure EU. The wavelength range of the generated light may be determined according to the configuration of the emission structure EU.

[0136] The encapsulation layer TFE may be disposed on the cathode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent or reduce the occurrence of oxygen and / or moisture penetrating into the light emitting element layer LDL. In some embodiments, the encapsulation layer TFE may include a structure in which one or more inorganic layers are alternately stacked with one or more organic layers. For example, the inorganic layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ). For example, the organic layer may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0137] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include aluminum oxide (AlO x ). The thin film containing aluminum oxide may be formed by atomic layer deposition (ALD). However, the present disclosure is not limited thereto. The encapsulation layer TFE may also include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0138] The optical function layer OFL is disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0139] The color filter layer CFL may be disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the emission structure EU and selectively output light or color light within a wavelength range corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively, and the color filters CF may each allow light within the wavelength range corresponding to the sub-pixel to pass through. For example, the color filter CF corresponding to the first sub-pixel SP1 may allow red light to pass through, the color filter CF corresponding to the second sub-pixel SP2 may allow green light to pass through, and the color filter CF corresponding to the third sub-pixel SP3 may allow blue light to pass through. Depending on the light emitted from the emission structure EU in each sub-pixel, at least some of the color filters CF may not be provided.

[0140] The lens array LA may be disposed on the color filter layer CFL (or the encapsulation layer TFE). The lens array LA may include lenses LS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the lenses LS may improve the light output efficiency by outputting the light emitted from the emission structure EU via an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index of 1.5 to 1.7. However, the refractive index of the lens array LA is not limited thereto, and the refractive index of the lens array LA may vary depending on the design of the system to which the display device is applied. In some embodiments, the lens LS may include an organic material.

[0141] In some embodiments, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be offset in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2 compared to the opening OP of the pixel defining layer PDL. Figure 4 ), the opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. Figure 4 ), the opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. Accordingly, in the center of the display area DA, the light emitted from the emission structure EU may be efficiently output in the normal direction of the display surface, and outside the display area DA, the light emitted from the emission structure EU may be efficiently output in a direction inclined at a specific angle relative to the normal direction of the display surface.

[0142] An outer coating layer OC may be disposed on the lens array LA. The outer coating layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the emission structure EU and / or the pixel circuit layer PCL. The outer coating layer OC may include various materials suitable for protecting the layers therebelow from foreign matter such as dust, moisture, etc. For example, the outer coating layer OC may include an organic insulating layer. For example, the outer coating layer OC may include an epoxy resin, but the present disclosure is not limited thereto. The outer coating layer OC may have a refractive index lower than that of the lens array LA.

[0143] The cover window CW may be disposed on the outer coating layer OC. The cover window CW may be configured to protect the layers thereunder. The cover window CW may have a refractive index higher than that of the outer coating layer OC. The cover window CW may include glass, but the present disclosure is not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect components disposed thereunder. In some other embodiments, the cover window CW may not be provided.

[0144] Fig. 6A , Figure 6B and Figure 6C It is a diagram showing some embodiments of the present disclosure including Figure 5 Plan views of some embodiments of pixels in a display device.

[0145] For the sake of clarity and brief explanation, Fig. 6A Schematically shows Figure 5 The remaining pixels may be configured similarly to the first pixel PXL1.

[0146] First, refer to Figure 4 , Figure 5 and Fig. 6A , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0147] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0148] The first emission area EMA1 may be a region where the emission structure (see Figure 5 The second emission area EMA2 may be an area where light is emitted from a portion of the emission structure EU corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the emission structure EU corresponding to the third sub-pixel SP3. Figure 5 As described, each of the emission regions may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0149] In some embodiments, the grooves TRCH1 to TRCH3 may be disposed between adjacent sub-pixels among the first to third sub-pixels SP1 to SP3. For example, a sub-pixel and an adjacent sub-pixel may be provided with a groove therebetween (for example, at least a portion of the groove may be located between the sub-pixel and the adjacent sub-pixel). Figure 5The arrangement of the emission structure EU, the grooves TRCH1 to TRCH3 can be formed by recessing or penetrating the base layer (for example, the upper surface of the pixel defining layer PDL). For example, in a plan view, the first groove TRCH1 may be arranged to surround the first sub-pixel SP1 along the edge of the first sub-pixel SP1, and may have a closed loop shape corresponding to the planar shape of the first sub-pixel SP1. Similar to the first groove TRCH1, in a plan view, the second groove TRCH2 may be arranged to surround the second sub-pixel SP2 along the edge of the second sub-pixel SP2, and the third groove TRCH3 may be arranged to surround the third sub-pixel SP3 along the edge of the third sub-pixel SP3. In this case, the first groove TRCH1 and the second groove TRCH2 may be arranged in the boundary area (or non-emission area NEA) between the first sub-pixel SP1 and the second sub-pixel SP2, and the second groove TRCH2 and the third groove TRCH3 may be arranged in the boundary area between the second sub-pixel SP2 and the third sub-pixel SP3.

[0150] The grooves TRCH1 to TRCH3 may be separated from each other (e.g., may be spaced apart from each other in the first direction DR1 and / or the second direction DR2) and independent of each other. In this case, the grooves TRCH1 to TRCH3 may each have a uniform width in the extension direction. As will be described below, the cathode remains connected at the top of the grooves TRCH1 to TRCH3 without being disconnected, and the first subpixel SP1 to the third subpixel SP3 may operate normally or emit light. For example, the cathode may extend throughout the grooves TRCH1 to TRCH3 (e.g., may extend continuously).

[0151] On the other hand, although Fig. 6A It is shown that the first to third sub-pixels SP1 to SP3 are disposed in the first direction DR1 and have a rectangular planar shape, but the present disclosure is not limited thereto.

[0152] Reference Figure 6B The first pixel PXL1' may include a first subpixel SP1', a second subpixel SP2', and a third subpixel SP3', the first subpixel SP1' and the second subpixel SP2' may be disposed in the second direction DR2, and the third subpixel SP3' may be disposed in the first direction DR1 relative to each of the first subpixel SP1' and the second subpixel SP2'.

[0153] The second sub-pixel SP2' may have an area larger than that of the first sub-pixel SP1', and the third sub-pixel SP3' may have an area larger than that of the second sub-pixel SP2'. Accordingly, the second emission area EMA2' may have an area larger than that of the first emission area EMA1', and the third emission area EMA3' may have an area larger than that of the second emission area EMA2'. However, the present disclosure is not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same area, and the third sub-pixel SP3' may have an area larger than that of each of the first sub-pixel SP1' and the second sub-pixel SP2'. Thus, in some embodiments, the areas of the first to third sub-pixels SP1' to SP3' may vary. The non-emission area NEA' may be disposed around each of the first to third emission areas EMA1' to EMA3'.

[0154] Reference Figure 6C , the first pixel PXL1" may include a first sub-pixel SP1", a second sub-pixel SP1" and a third sub-pixel SP3". When viewed from the third direction DR3, the first sub-pixel SP1" to the third sub-pixel SP3" may each have a polygonal shape. For example, Figure 6C As shown in FIG. 1 , the first to third sub-pixels SP1 ″ to SP3 ″ may each have a hexagonal shape.

[0155] When viewed from the third direction DR3, the first emission areas EMA1” to the third emission areas EMA3” of the first subpixel SP1” to the third subpixel SP3” may each have a circular shape. However, the present disclosure is not limited thereto. For example, the first emission areas EMA1” to the third emission areas EMA3” may each have other polygonal shapes. The non-emission area NEA” may be disposed around each of the first emission areas EMA1” to the third emission areas EMA3”.

[0156] The first subpixel SP1 ″ and the third subpixel SP3 ″ may be disposed in the first direction DR1 . The second subpixel SP2 ″ may be disposed in a direction (or an oblique direction) inclined at an acute angle with respect to the second direction DR2 with respect to the first subpixel SP1 ″.

[0157] Fig. 6A , Figure 6B and Figure 6C The arrangement of the sub-pixels shown in the figure is an example, and the present disclosure is not limited thereto. Each pixel may include two or more sub-pixels. The sub-pixels may be arranged in various ways. The sub-pixels may each have various shapes, and the emission area may also have various shapes.

[0158] Figure 7 is a diagram showing some embodiments of the present disclosure. Fig. 6AA cross-sectional view of the display device taken along line II'.

[0159] Reference Figure 7 , a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB may be provided.

[0160] The substrate SUB may include a silicon wafer substrate formed by using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon germanium.

[0161] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit included in the first sub-pixel SP1 (see Figure 2 The transistor T_SP2 of the second sub-pixel SP2 may be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. For clear and brief explanation, Figure 7 One of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0162] The transistor T_SP1 of the first subpixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0163] The source region SRA and the drain region DRA may be disposed in the substrate SUB. A well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be spaced apart from each other within the well WL. The region between the source region SRA and the drain region DRA within the well WL may be defined as a channel region.

[0164] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0165] The plurality of layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers, and the conductive patterns may include first conductive patterns CP1 and second conductive patterns CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connection portion DRC penetrating one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connection portion SRC penetrating one or more insulating layers.

[0166] As the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to other circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1 may be provided as one of the transistors of the first subpixel SP1.

[0167] The transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may each be configured similarly to the transistor T_SP1 of the first subpixel SP1 .

[0168] Thus, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3 .

[0169] The via layer VIAL may be disposed on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and may have a flat surface as a whole. The via layer VIAL may be configured to flatten the steps on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), silicon nitride (SiN x ) and at least one of silicon carbonitride (SiCN), but the present disclosure is not limited thereto.

[0170] The light emitting element layer LDL may be disposed on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3 , a planarization layer PLNL, first to third anodes AE1 to AE3 , a pixel defining layer PDL, an emission structure EU, and a cathode CE.

[0171] The first to third reflective electrodes RE1 to RE3 may be respectively disposed in the first to third subpixels SP1 to SP3 on the via layer VIAL. The first to third reflective electrodes RE1 to RE3 may contact circuit elements of the pixel circuit layer PCL through via holes penetrating the via layer VIAL.

[0172] The first to third reflective electrodes RE1 to RE3 may be used as total reflectors that reflect light emitted from the emission structure EU toward the display screen (or the cover window CW). The first to third reflective electrodes RE1 to RE3 may each include a metal material suitable for light reflection. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected therefrom, but the present disclosure is not limited thereto.

[0173] In some embodiments, a buffer electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The buffer electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The buffer electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the present disclosure is not limited thereto. In some embodiments, the corresponding reflective electrode may be positioned between multiple layers of the buffer electrode.

[0174] The buffer pattern BFP may be disposed on at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but the present disclosure is not limited thereto. By providing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the through hole layer VIAL to adjust the height of the first reflective electrode RE1.

[0175] The first to third reflective electrodes RE1 to RE3 may be used as full reflective mirrors, and the cathode CE may be used as a half reflective mirror. The light emitted from the emission structure EU may be amplified at least partially by reflecting back and forth between the corresponding reflective electrodes and the cathode CE, and the amplified light may be output through the cathode CE. Thus, the distance between the corresponding reflective electrodes and the cathode CE may be understood as a resonant distance for the light emitted from the emission structure EU.

[0176] Due to the buffer pattern BFP, the first subpixel SP1 may have a resonance distance shorter than the resonance distances of other subpixels. The resonance distance adjusted in this manner may allow light in a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Accordingly, the first subpixel SP1 may effectively and efficiently output light in the corresponding wavelength range.

[0177] although Figure 7It is shown that the buffer pattern BFP is provided to the first sub-pixel SP1 and is not provided to the second sub-pixel SP2 and the third sub-pixel SP3, but the present disclosure is not limited thereto. The buffer pattern may also be provided in at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively. The distance between the first reflective electrode RE1 and the cathode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode CE. The distance between the second reflective electrode RE2 and the cathode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode CE.

[0178] The planarization layer PLNL (or base layer) may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may planarize the steps between the first to third reflective electrodes RE1 to RE3 and may provide a base surface for the emission structure EU. The planarization layer PLNL may generally cover the first to third reflective electrodes RE1 to RE3 and the via layer VIAL and may have a flat surface. The planarization layer PLNL may include an organic material. In some embodiments, the planarization layer PLNL may not be provided.

[0179] The first to third anodes AE1 to AE3 (or first electrodes) respectively overlapping the first to third reflective electrodes RE1 to RE3 may be disposed on the planarization layer PLNL. When viewed from the third direction DR3, the first to third anodes AE1 to AE3 may have the same Fig. 6A The emission areas EMA1 to EMA3 of the first sub-pixel SP1 to the third sub-pixel SP3 in the planarization layer PLNL are similar in shape. The first anode AE1 to the third anode AE3 may be in direct contact with the emission structure EU (or its semiconductor layer), and an energy barrier may be formed at the interface. The first anode AE1 to the third anode AE3 may be connected to the first reflective electrode RE1 to the third reflective electrode RE3, respectively. The first anode AE1 may be connected to the first reflective electrode RE1 through a first through hole VIA1 penetrating the planarization layer PLNL. The second anode AE2 may be connected to the second reflective electrode RE2 through a second through hole VIA2 penetrating the planarization layer PLNL. The third anode AE3 may be connected to the third reflective electrode RE3 through a third through hole VIA3 penetrating the planarization layer PLNL.

[0180] In some embodiments, the first to third anodes AE1 to AE3 may each include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO). However, the materials of the first to third anodes AE1 to AE3 are not limited thereto. For example, the first to third anodes AE1 to AE3 may each include titanium nitride.

[0181] In some embodiments, an insulating layer may be further provided to adjust the height of one or more of the first anode AE1 to the third anode AE3. The insulating layer may be disposed between one or more of the first anode AE1 to the third anode AE3 and the corresponding reflective electrode. In this case, the planarization layer PLNL and / or the buffer pattern BFP may not be provided. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively. The distance between the first anode AE1 and the cathode CE may be shorter than the distance between the second anode AE2 and the cathode CE. The distance between the second anode AE2 and the cathode CE may be shorter than the distance between the third anode AE3 and the cathode CE.

[0182] The pixel defining layer PDL may be disposed on portions of the first to third anodes AE1 to AE3 and the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing portions of the first to third anodes AE1 to AE3. The opening OP of the pixel defining layer PDL may define emission regions of the first to third sub-pixels SP1 to SP3. Thus, the pixel defining layer PDL may be disposed on Fig. 6A The non-emitting area NEA can be defined as Fig. 6A The first emission area EMA1 to the third emission area EMA3.

[0183] A spacer SPR may be provided in a boundary area BDA between adjacent sub-pixels.

[0184] The spacer SPR may cause a discontinuous portion to be formed in the emission structure EU overlapping the boundary area BDA. For example, due to the spacer SPR, the first emission structure EU1 of the emission structure EU may be disconnected at the boundary area BDA. The spacer SPR may be provided in the pixel defining layer PDL and the planarization layer PLNL, or may be provided on the pixel defining layer PDL.

[0185] In some embodiments, the pixel defining layer PDL may include one or more grooves TRCH1 to TRCH3 as a separator SPR in the boundary area BDA. For example, the one or more grooves TRCH1 to TRCH3 may separate one or more structures of adjacent sub-pixels (for example, may be positioned (or provided) between one or more structures of adjacent sub-pixels). Figure 7As shown in , the first and second trenches TRCH1 and TRCH2 may be provided as spacers SPR in the boundary area BDA between the first and second subpixels SP1 and SP2, and the second and third trenches TRCH2 and TRCH3 may be provided as spacers SPR in the boundary area BDA between the second and third subpixels SP2 and SP3.

[0186] In some embodiments, the grooves TRCH1 to TRCH3 may penetrate the pixel defining layer PDL and partially penetrate the planarization layer PLNL. In some embodiments, the grooves TRCH1 to TRCH3 may penetrate the pixel defining layer PDL and the planarization layer PLNL and may partially penetrate the via layer VIAL. In some embodiments, the pixel defining layer PDL may not be disposed in the grooves TRCH1 to TRCH3, and most of the grooves TRCH1 to TRCH3 may be empty spaces (or gaps). However, the present disclosure is not limited thereto. For example, a portion of the pixel defining layer PDL may be disposed in the grooves TRCH1 to TRCH3.

[0187] although Figure 7 It is shown that two grooves are provided in the boundary area BDA, but the present disclosure is not limited thereto. For example, the pixel defining layer PDL may include one groove in the boundary area BDA (see Fig.15 ). Alternatively, the pixel defining layer PDL may include three or more grooves in the boundary area BDA.

[0188] In some embodiments, the spacer SPR may be provided in various forms so that the emission structure EU has a discontinuous portion in the boundary area BDA. Figures 14 to 17 Some other embodiments of the separator SPR will be described.

[0189] The emission structure EU may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The emission structure EU may fill the opening OP of the pixel defining layer PDL and may be disposed entirely across the first to third sub-pixels SP1 to SP3.

[0190] In some embodiments, the emission structure EU may include a first emission structure EU1 (or a first stack) and a second emission structure EU2 (or a second stack) stacked sequentially. For example, the emission structure EU may have a series structure in which the first emission structure EU1 and the second emission structure EU2 are stacked. The first emission structure EU1 and the second emission structure EU2 may each emit light. The first emission structure EU1 and the second emission structure EU2 may emit light of different colors, but the present disclosure is not limited thereto. The first emission structure EU1 and the second emission structure EU2 may emit light of the same color.

[0191] In some embodiments, the first emission structure EU1 may be disconnected by the partition SPR at the boundary area BDA. For example, the first emission structure EU1 of the first sub-pixel SP1 and the first emission structure EU1 of the second sub-pixel SP2 may be disconnected or separated (e.g., may be spaced apart from each other or may be separated from each other) in the boundary area BDA. Accordingly, when the display panel DP (see Figure 4 ), when the first emission structure EU1 is operated, the current flowing out from each of the first to third sub-pixels SP1 to SP3 through the layers included in the emission structure EU to the adjacent sub-pixels can be reduced. Accordingly, the first to third light-emitting elements LD1 to LD3 can be operated with relatively higher reliability. For example, in a case where the first emission structure EU1 is disconnected at the boundary area BDA, the first to third light-emitting elements LD1 to LD3 can be operated with higher reliability than in a case where the first emission structure EU1 is connected at the boundary area BDA (e.g., continuously extending across the boundary area BDA).

[0192] On the other hand, the second emission structure EU2 may not be disconnected in the boundary area BDA and may be continuous. For example, the second emission structure EU2 of the first subpixel SP1 and the second emission structure EU2 of the second subpixel SP2 may be connected to each other in the boundary area BDA. For example, at least a portion of the second emission structure EU2 of the first subpixel SP1 may extend continuously with the second subpixel SP2 across the boundary area BDA, so that at least a portion of the second emission structure EU2 of the first subpixel SP1 and the second emission structure EU2 of the second subpixel SP2 may be connected on the groove (for example, above). In some embodiments, a portion (for example, the lower portion) of the second emission structure EU2 may be disconnected at the boundary area BDA, but the remainder of the second emission structure EU2 may be continuous (see Figure 8 ).

[0193] The cathode CE (or the second electrode) may be disposed on the emission structure EU. The cathode CE may be provided in common to the first to third sub-pixels SP1 to SP3. The cathode CE may function as a semi-reflective mirror that partially transmits and partially reflects light emitted from the emission structure EU. In order to protect the cathode CE, a covering layer including an inorganic material may also be disposed on the cathode CE (see Fig. 9 of CPL).

[0194] When the second emission structure EU2 is continuous in the boundary area BDA, the cathode CE disposed on the second emission structure EU2 can be continuous in the boundary area BDA without being disconnected. Accordingly, the second power supply voltage can be stably supplied to the first to third subpixels SP1 to SP3, and the first to third light emitting elements LD1 to LD3 can operate normally.

[0195] The first anode AE, the portion of the emission structure EU overlapping with the first anode AE, and the portion of the cathode CE overlapping with the first anode AE ​​may constitute a first light emitting element LD1. The second anode AE2, the portion of the emission structure EU overlapping with the second anode AE2, and the portion of the cathode CE overlapping with the second anode AE2 may constitute a second light emitting element LD2. The third anode AE3, the portion of the emission structure EU overlapping with the third anode AE3, and the portion of the cathode CE overlapping with the third anode AE3 may constitute a third light emitting element LD3.

[0196] The encapsulation layer TFE may be disposed on the cathode CE. The encapsulation layer TFE may prevent or reduce the occurrence of oxygen and / or moisture penetrating into the light emitting element layer LDL.

[0197] The optical function layer OFL may be disposed on the encapsulation layer TFE. In some embodiments, the optical function layer OFL may be bonded to the encapsulation layer TFE through an adhesive layer APL. For example, the optical function layer OFL may be manufactured separately and bonded to the encapsulation layer TFE through an adhesive layer APL. The adhesive layer APL may also perform the function of protecting the lower layer including the encapsulation layer TFE.

[0198] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may allow light of different wavelength ranges to pass through. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may transmit red, green, and blue light, respectively.

[0199] In some embodiments, the first to third color filters CF1 to CF3 may partially overlap in the boundary area BDA. In some other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0200] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include a first lens LS1, a second lens LS2, and a third lens LS3 corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. The first to third lenses LS1 to LS3 may improve light output efficiency by outputting light emitted from the first to third light-emitting elements LD1 to LD3 along a desired path.

[0201] Figure 8 According to some embodiments of the present disclosure Figure 7 An enlarged cross-sectional view of a portion of a display device.

[0202] Figure 8 The emission structure EU and cathode CE in a partial region including the first and second trenches TRCH1 and TRCH2 (eg, a boundary region between the first and second subpixels SP1 and SP2) are shown. For clarity, the planarization layer PLNL, the pixel defining layer PDL, and the encapsulation layer TFE are also shown.

[0203] Fig. 9 It is a diagram showing some embodiments of the present disclosure including Figure 7 A cross-sectional view of an emission structure in a display device.

[0204] Fig. 9 A cathode CE is also included.

[0205] Fig.10 is a diagram showing some embodiments of the present disclosure Figure 8 An image of a display device.

[0206] Reference Figures 7 to 9 The pixel defining layer PDL may include a first inorganic layer PDL1, a second inorganic layer PDL2, and a third inorganic layer PDL3 sequentially stacked on the planarization layer PLNL. The first inorganic layer PDL1 and the third inorganic layer PDL3 may each include silicon nitride (SiN x ), and the second inorganic layer PDL2 may include silicon oxide (SiO x ). However, the present disclosure is not limited thereto. The pixel defining layer PDL including the first inorganic layer PDL1, the second inorganic layer PDL2, and the third inorganic layer PDL3 may be formed at the same position as the opening (see Figure 7 The region adjacent to the OP) has a step-like profile.

[0207] Since the first trench TRCH1 and the second trench TRCH2 are substantially the same, the trench TRCH covering the first trench TRCH1 and the second trench TRCH2 will be described.

[0208] Each of the trenches TRCH may include or may be defined by a penetration portion of the pixel defining layer PDL and a recessed portion of the planarization layer PLNL.

[0209] In some embodiments, the emission structure EU may include a first emission structure EU1 and a second emission structure EU2. The emission structure EU may be configured to Figure 7 The emission structures EU in the first to third light emitting elements LD1 to LD3 are substantially the same. The emission structure EU may be formed by a method such as vacuum deposition or inkjet printing, but the present disclosure is not limited thereto.

[0210] The first emission structure EU1 and the second emission structure EU2 may each include an emission layer that generates light according to an applied current. The first emission structure EU1 may include a first emission layer EML1, a 1-2 functional layer ETR1 (or a first electron transport layer), and a 1-1 functional layer HTR1 (or a first hole transport layer). The first emission layer EML1 may be disposed between the 1-2 functional layer ETR1 and the 1-1 functional layer HTR1. The second emission structure EU2 may include a second emission layer EML2, a 2-2 functional layer ETR2 (or a second electron transport layer), and a 2-1 functional layer HTR2 (or a second hole transport layer). The second emission layer EML2 may be disposed between the 2-2 functional layer ETR2 and the 2-1 functional layer HTR2.

[0211] The 1-1 functional layer HTR1 and the 2-1 functional layer HTR2 may each include at least one of a hole injection layer and a hole transport layer, and if necessary, may further include a hole buffer layer and an electron blocking layer. The 1-1 functional layer HTR1 and the 2-1 functional layer HTR2 may have different configurations.

[0212] The 1-2 functional layer ETR1 and the 2-2 functional layer ETR2 may each include at least one of an electron injection layer and an electron transport layer, and if necessary, may further include an electron buffer layer and a hole blocking layer. The 1-2 functional layer ETR1 and the 2-2 functional layer ETR2 may have the same configuration or different configurations.

[0213] In some embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of different colors. The light emitted from the first emission layer EML1 and the light emitted from the second emission layer EML2 may be mixed and identified as white light. For example, the first emission layer EML1 may generate blue light, and the second emission layer EML2 may generate yellow light. In some embodiments, the second emission layer EML2 may include a structure in which a first sub-emission layer configured to generate red light and a second sub-emission layer configured to generate green light are stacked. Red light and green light may be mixed to provide yellow light. In this case, a layer configured to perform the function of transporting holes and / or blocking the transport of electrons may also be provided between the first sub-emission layer and the second sub-emission layer.

[0214] In some other embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of the same color.

[0215] The intermediate layer CGL (or charge generation layer) may be disposed between the first emission structure EU1 and the second emission structure EU2. The intermediate layer CGL may generate charges and may connect the first emission structure EU1 to the second emission structure EU2. In some embodiments, the intermediate layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the present disclosure is not limited thereto.

[0216] In some embodiments, Figure 8 As shown in , similar to the first emission structure EU1, the intermediate layer CGL may be disconnected (e.g., discontinuous) at the upper portion of the trench TRCH. For example, a first portion of the intermediate layer CGL on the first side of the trench TRCH may be disconnected from a second portion of the intermediate layer CGL on the second side of the trench TRCH (e.g., may be spaced apart or separated from a second portion of the intermediate layer CGL on the second side of the trench TRCH). In this case, the occurrence of current flowing from one sub-pixel through the intermediate layer CGL to another adjacent sub-pixel may be reduced (e.g., may be prevented), and the sub-pixels may operate with relatively higher reliability compared to their operation in the case where the intermediate layer CGL is not disconnected at the trench TRCH.

[0217] In some embodiments, based on the third direction DR3 , the thickness of the first emission structure EU1 may be less than the depth L_T of the trench TRCH, and the thickness of the second emission structure EU2 may be greater than the depth L_T of the trench TRCH.

[0218] In some embodiments, the thickness of the first emission structure EU1 may be about 70% or less of the depth L_T of the trench TRCH, and the thickness of the second emission structure EU2 may be about 160% or more of the depth L_T of the trench TRCH.

[0219] In some embodiments, the ratio of the width W_T of the groove TRCH to the depth L_T of the groove TRCH may be about 1:1.45 to about 1:11. In some embodiments, the ratio of the width W_T of the groove TRCH to the depth L_T of the groove TRCH may be about 1:2.4 to about 1:3.7. For example, the ratio of the width W_T of the groove TRCH to the depth L_T of the groove TRCH may be about 1:3. For example, the depth L_T of the groove TRCH may be about 1.45 times to about 11 times the width W_T of the groove TRCH. In some embodiments, the depth L_T of the groove TRCH may be about 2.4 times to about 3.7 times the width W_T of the groove TRCH. In other words, the width W_T of the groove TRCH may be about 9% to about 70% of the depth L_T of the groove TRCH. In some embodiments, the width W_T of the groove TRCH may be about 25% to about 40% of the depth L_T of the groove TRCH.

[0220] In some embodiments, the thickness of the first emission structure EU1 may be about 19% to about 82% of the depth L_T of the trench TRCH. In some embodiments, the thickness of the first emission structure EU1 may be about 50% to about 76% of the depth L_T of the trench TRCH. For example, the thickness of the first emission structure EU1 may be about 62% of the depth L_T of the trench TRCH.

[0221] In some embodiments, the thickness of the first emission structure EU1 may be about 0.9 to about 2.6 times the width W_T of the trench TRCH. In some embodiments, the thickness of the first emission structure EU1 may be about 1.5 to about 2.3 times the width W_T of the trench TRCH. For example, the thickness of the first emission structure EU1 may be about 1.85 times the width W_T of the trench TRCH.

[0222] In some embodiments, the thickness of the second emission structure EU2 may be about 0.5 to about 2.2 times the depth L_T of the trench TRCH. In some embodiments, the thickness of the second emission structure EU2 may be about 1.3 to about 2 times the depth L_T of the trench TRCH. For example, the thickness of the second emission structure EU2 may be about 1.63 times the depth L_T of the trench TRCH.

[0223] In some embodiments, the thickness of the second emission structure EU2 may be about 2.6 to about 6.8 times the width W_T of the trench TRCH. In some embodiments, the thickness of the second emission structure EU2 may be about 4 to about 6 times the width W_T of the trench TRCH. For example, the thickness of the second emission structure EU2 may be about 4.9 times the width W_T of the trench TRCH.

[0224] In some embodiments, the depth L_T of the trench TRCH may be about to about And the width W_T of the trench TRCH may be about to about In some embodiments, the depth L_T of the trench TRCH may be about to about And the width W_T of the trench TRCH may be about to about The thickness of the first emitting structure EU1 may be about to about and the thickness of the second emission structure EU2 may be in the range of about to about For example, the depth L_T of the trench TRCH may be about The width W_T of the trench TRCH may be approximately The thickness of the first emitting structure EU1 may be about And the thickness of the second emission structure EU2 may be about

[0225] For reference, the depth L_T and width W_T of the trench TRCH and the thickness of the first emission structure EU1 and the second emission structure EU2 can be set in consideration of the cut-off of the intermediate layer CGL and the connection of the cathode CE (and the resonance distance). When or when the width W_T of each trench TRCH is greater than When, like Fig.10 As in the first image IMAGE1 shown in FIG. 1 , the cathode CE may be disconnected at the upper portion of the trench TRCH, and the sub-pixel may not emit light. For example, when the depth L_T of each trench TRCH is less than When or when the width W_T of each trench TRCH is less than When the depth L_T of each trench TRCH is about 100 mm, the intermediate layer CGL may be connected at the upper portion of the trench TRCH without being separated, and side leakage may occur through the intermediate layer CGL. And the width W_T of each trench TRCH is about When, like Fig.10 As in the second image IMAGE2 shown in FIG. 4 , the cathode CE may be connected at the upper portion of the trench TRCH, but the intermediate layer CGL may be separated from the upper portion of the trench TRCH.

[0226] In some embodiments, based on the third direction DR3, the thickness TH1 of the 1-1 functional layer HTR1 (or the first hole transport layer) may be less than the depth L_T of the groove TRCH, and the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) may be greater than the depth L_T of the groove TRCH.

[0227] In some embodiments, the thickness TH2 of the 2-1st functional layer HTR2 (or the second hole transport layer) may be about 0.4 times to about 1.8 times the depth L_T of the trench TRCH. In some embodiments, the thickness TH2 of the 2-1st functional layer HTR2 (or the second hole transport layer) may be about 1 times to about 1.7 times the depth L_T of the trench TRCH. For example, the thickness TH2 of the 2-1st functional layer HTR2 (or the second hole transport layer) may be about 1.33 times the depth L_T of the trench TRCH.

[0228] In some embodiments, the thickness TH2 of the 2-1st functional layer HTR2 (or the second hole transport layer) may be about 2 times to about 5.5 times the width W_T of the trench TRCH. In some embodiments, the thickness TH2 of the 2-1st functional layer HTR2 (or the second hole transport layer) may be about 3.2 times to about 4.8 times the width W_T of the trench TRCH. For example, the thickness TH2 of the 2-1st functional layer HTR2 (or the second hole transport layer) may be about 4 times the width W_T of the trench TRCH.

[0229] In some embodiments, when the depth L_T of the trench TRCH is about And the width W_T of the trench TRCH is about to about When the thickness TH1 of the 1-1 functional layer HTR1 (or the first hole transport layer) is within the range of about to about and the thickness TH2 of the 2-1st functional layer HTR2 (or the second hole transport layer) may be in the range of about to about For example, the thickness TH1 of the 1-1 functional layer HTR1 (or the first hole transport layer) is about And the thickness TH2 of the 2-1st functional layer HTR2 (or the second hole transport layer) may be about

[0230] For reference, the thickness of the first emission layer EML1 may be about to about (For example, about ), the thickness of the first-second functional layer ETR1 may be about to about (For example, about ), the thickness of the intermediate layer CGL may be about to about (For example, about ), the thickness of the second emission layer EML2 may be about to about (For example, about ), and the thickness of the 2-2 functional layer ETR2 may be about to about (For example, about ).

[0231] When the thickness TH1 of the 1-1 functional layer HTR1 is less than the depth L_T of the trench TRCH, the intermediate layer CGL (and the first emission structure EU1) can be stably cut off at the upper portion of the trench TRCH. When the thickness TH2 of the 2-1 functional layer HTR2 is greater than the depth L_T of the trench TRCH, the second emission structure EU2 (and the cathode CE) can be stably connected at the upper portion of the trench TRCH. In some embodiments, when the thickness TH1 of the 1-1 functional layer HTR1 is about to about And the thickness TH2 of the 2-1st functional layer HTR2 is about to about When (based on a to about The first emitting structure EU1 has a thickness of about to about The second emission structure EU2 having a thickness of about 1000 nm can balance the holes and electrons recombined in each of the first emission layer EML1 and the second emission layer EML2, and thus, the luminous efficiency of the first emission structure EU1 and the second emission structure EU2 can be maximized. In addition, when the thickness TH1 of the 1-1 functional layer HTR1 is about to about And the thickness TH2 of the 2-1st functional layer HTR2 is about to about When the first emission layer EML1 and the second emission layer EML2 are connected, the resonance distance of the light emitted from the first emission layer EML1 and the second emission layer EML2 (for example, the distance where the light is emitted from each of the first emission layer EML1 and the second emission layer EML2 and propagates back and forth between the reflective electrodes RE1 and RE2 and the cathode CE) can be optimized, and thus the light generated in the first emission layer EML1 and the second emission layer EML2 can be amplified and output through the cathode CE.

[0232] In some embodiments, the 1-1st functional layer HTR1 and the 2-1st functional layer HTR2 may include different materials. For example, each of the 1-1st functional layer HTR1 and the 2-1st functional layer HTR2 may include a general material constituting a hole transport layer of an organic light emitting diode (e.g., an organic conductive material containing carbon and hydrogen), and the 1-1st functional layer HTR1 and the 2-1st functional layer HTR2 may include materials having different structures.

[0233] In some embodiments, the 1-1 functional layer HTR1 (or the first hole transport layer) may include a plate-type material (or a material having a plate-type structure), and the 2-1 functional layer HTR2 (or the second hole transport layer) may include a relatively bulky material (hereinafter referred to as a "block material") (or a material having a block structure) compared to the plate-type material. The plate-type may refer to a structure in which atoms are arranged in two dimensions or atomic layer thickness, or a structure in which materials are stacked in the form of a thin and flat plate. For example, a plate-type material may have a high specific surface area and a strong bonding strength, but may have a low compressive or tensile strength. The block-type may refer to a structure in which a material exists in the form of a large and thick block, or a structure in which atoms are arranged in three dimensions and the atomic arrangement on the surface matches the atomic arrangement in the block. In other words, the block-type may be a structure in which solid dislocations are minimized when a surface is formed. In other words, the block-type has the characteristic that the spacing between atoms is constant and the spacing is the same for each layer. The block-type may have a low specific surface area and may be strong and rigid, but may have low flexibility or bonding strength.

[0234] Hereinafter, the characteristics (or physical properties, such as Tg, Td, HOMO, LUMO, refractive index) of plate-type materials and bulk materials will be described. Hereinafter, "Tg" (hereinafter referred to as "thermal property (Tg)") refers to the glass transition temperature, which is the temperature at which a polymer changes from a glass state to a polymer body. The thermal property (Tg) can be measured by using a thermal analyzer or differential scanning calorimetry (DSC), which is an analytical technique for measuring the heat released or absorbed when a sample is heated or cooled within a specific temperature range. "Td" refers to the temperature at which a material (or sample) decomposes. "Td (1%)" (hereinafter referred to as "thermal property Td (1%)") is the temperature when the weight decreases by 1% compared to the initial weight, and "Td (5%)" (hereinafter referred to as "thermal property Td (5%)") is the temperature when the weight decreases by 5% compared to the initial weight. "Td" can be measured by thermogravimetric analysis (TGA). The highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) are molecular orbitals representing the electronic structure of a molecule. HOMO refers to a molecular orbital in the highest energy region where electrons can participate in bonding, and LUMO refers to a molecular orbital in the lowest energy region where electrons are located in the anti-bonding region.

[0235] The thermal property (Tg) (or glass transition temperature) of the plate-type material may be about 120 degrees Celsius (° C.) to about 130° C., and the thermal property (Tg) of the bulk material may be about 145° C. to about 155° C. For example, the thermal property (Tg) of the bulk material may be about 15° C. to about 35° C. or about 10% to about 30% higher than the thermal property (Tg) of the plate-type material. As the thermal property (Tg) (or glass transition temperature) decreases, deformation may occur more easily.

[0236] The thermal property (Td(1%)) of the plate type material may be about 320° C. to about 335° C., and the thermal property (Td(1%)) of the bulk material may be about 340° C. to about 365° C. For example, the thermal property (Td(1%)) of the bulk material may be about 5° C. to about 45° C. or about 1.5% to about 15% higher than the thermal property (Td(1%)) of the plate type material.

[0237] The thermal property (Td(5%)) of the plate type material may be about 340° C. to about 365° C., and the thermal property (Td(5%)) of the bulk material may be about 385° C. to about 405° C. For example, the thermal property (Td(5%)) of the bulk material may be about 20° C. to about 65° C. or about 5% to about 20% higher than the thermal property (Td(5%)) of the plate type material.

[0238] The energy of the HOMO molecular orbital of the plate material may be about 5.3 eV to about 5.7 eV, and the energy of the HOMO molecular orbital of the bulk material may be about -5.4 eV to about -4.6 eV. For example, the energy of the HOMO molecular orbital of the bulk material may be about 9.9 eV to about 11.1 eV or about 173% to about 210% lower than the energy of the HOMO molecular orbital of the plate material.

[0239] The energy of the LUMO molecular orbital of the plate material may be about 2.2 eV to about 2.6 eV, and the energy of the LUMO molecular orbital of the bulk material may be about -2.2 eV to about -0.8 eV. For example, the energy of the LUMO molecular orbital of the bulk material may be about 3.0 eV to about 4.8 eV or about 115% to about 220% lower than the energy of the LUMO molecular orbital of the plate material.

[0240] The refractive index of the plate material may be about 1.7 to about 1.9 or about 1.77 to about 1.89, and the refractive index of the bulk material may be about 1.6 to about 1.8 or about 1.7 to about 1.76. For example, the refractive index of the bulk material may be less than that of the plate material.

[0241] In some embodiments, the molecular shape (or geometric optimization) of the plate-type material may be flat, the van der Waals force (or bonding force) of the plate-type material may be about 405 to about 497, the angle of the plate-type material may be about 198 to about 204, and the distortion (or distortion force) of the plate-type material may be about 446 to about 546. The van der Waals force refers to the attraction between molecules (unit: kJ / mol), the angle refers to the angle between two bonds in a molecule (unit: radians), and the distortion refers to the rotation inside a molecule (unit: radians). In some embodiments, the molecular shape of the bulk material may be distorted, the van der Waals force of the bulk material may be about 710 to about 866, the angle of the bulk material may be about 1221 to about 1491, and the distortion of the bulk material may be about 659 to about 805. The van der Waals force, angle, and distortion of the bulk material may be greater than those of the plate-type material, respectively.

[0242] The plate-type material has a flat molecular shape and is therefore deposited regularly. However, since the van der Waals force of the plate-type material is small, the plate-type material (or the plate-type material layer) may be greatly affected by the underlying layer (e.g., voids). The bulk material has a large angle and distortion and is therefore deposited in a distorted form, and the bulk material (or the bulk material layer) may be less affected by the underlying layer (e.g., voids). In some embodiments, since the van der Waals force of the bulk material is large, the bulk material (or the bulk material layer) may cover the underlying layer like a net and maintain its shape even in a scattered deposition state, regardless of the shape of the underlying layer (e.g., voids).

[0243] Due to the flat shape of the plate-type material, the plate-type material may have bonds concentrated in the center of the lattice. For example, the plate-type material may have the shape of stacked bricks. The bulk material may spread like a net in the lattice due to its twisted form. Since the van der Waals force of the bulk material is large, the bulk material may maintain its net shape. When the lattice density is examined, the bulk material may spread wider than the plate-type material, and the possibility that the bulk material covers a specific underlying structure (e.g., a void) may be greater.

[0244] In some embodiments, the plate material may include a p-dopant. In this case, the van der Waals force of the plate material may be about 349 to about 425, and the angle of the plate material may be about 191 to about 233. On the other hand, the bulk material may not include a p-dopant.

[0245] When the 1-1 functional layer HTR1 including a plate material is formed on the groove TRCH, the 1-1 functional layer HTR1 may be bent and disconnected in the groove TRCH. Accordingly, the first emission structure EU1 including the 1-1 functional layer HTR1 and the relatively thin intermediate layer CGL may be disconnected in the groove TRCH. On the contrary, when the 1-1 functional layer HTR1 includes a bulk material, the 1-1 functional layer HTR1 may not be disconnected in the groove TRCH, and therefore, the intermediate layer CGL may be connected at the groove TRCH, and side leakage may occur. On the other hand, when the 2-1 functional layer HTR2 including a bulk material is formed on the groove TRCH, the 2-1 functional layer HTR2 may be connected on the groove TRCH without bending. Accordingly, the second emission structure EU2 including the 2-1 functional layer HTR2 may not be disconnected in the groove TRCH. In some embodiments, a large step may not be formed on the upper surface of the second emission structure EU2 including the 2-1 functional layer HTR2, and therefore, the cathode CE may not be disconnected. In contrast, when the 2-1st functional layer HTR2 includes a plate type material, the 2-1st functional layer HTR2 may be disconnected in the trench TRCH, and thus, the cathode CE may also be disconnected in the trench TRCH.

[0246] In some embodiments, the thickness TH3 of the cathode CE may be about to about within the range of to about In addition, the step (eg, step difference DIFF) of the cathode CE at the upper portion (eg, on or above the upper portion) of the trench TRCH may be approximately or less. As the thickness TH3 of the cathode CE increases, the cathode CE can be more stably connected on the groove TRCH, but the light transmission efficiency of the cathode CE may decrease. When the second emission structure EU2 (or the 2-1st functional layer HTR2) is connected in the groove TRCH without bending, the step of the bent portion of the upper surface of the second emission structure EU2 can be reduced to about or less, and the cathode CE can be used with only about to about (For example, about ) is connected without being disconnected at the upper portion of the trench TRCH.

[0247] As described above, the thickness of the 1-1 functional layer HTR1 (or the first emission structure EU1) may be less than the depth L_T of the groove TRCH, and the thickness of the 2-1 functional layer HTR2 (or the second emission structure EU2) may be greater than the depth L_T of the groove TRCH. In some embodiments, the 1-1 functional layer HTR1 (or the first hole transport layer) may include a plate material, and the 2-1 functional layer HTR2 (or the second hole transport layer) may include a block material. In this case, in the upper part of the groove TRCH, the first emission structure EU1 and the intermediate layer CGL may be disconnected to prevent or reduce the occurrence of side leakage, and the second emission structure EU2 and the cathode CE may be connected so that the sub-pixel is driven normally. For example, the sub-pixel can accurately emit light at the desired brightness, and the display quality can be improved.

[0248] Fig.11 is a diagram showing some embodiments of the present disclosure. Fig. 6A A cross-sectional view of another embodiment of a display device taken along line II'.

[0249] Fig.12 According to some embodiments of the present disclosure Fig.11 An enlarged cross-sectional view of a portion of a display device.

[0250] Fig.12 The emission structure EU' and the cathode CE in a partial region including the first trench TRCH1' and the second trench TRCH2' (eg, a boundary region between the first sub-pixel SP1 and the second sub-pixel SP2) are shown.

[0251] Fig.13 It is a diagram showing some embodiments of the present disclosure including Fig.11 A cross-sectional view of an emission structure in a display device.

[0252] Reference Figures 7 to 13 , in addition to the emission structure EU', Fig.11 The display device can be used with Figure 7 and Figure 8 The display devices of the present invention are substantially the same or similar. Therefore, redundant description will not be repeated.

[0253] The emission structure EU' may have a series structure in which the first emission structure EU1', the second emission structure EU2', and the third emission structure EU3' are stacked. The emission structure EU' may be configured to Fig.11 The first to third light emitting elements LD1 to LD3 are substantially the same.

[0254] like Fig.11As shown in FIG. 1 , the first emission structure EU1′ and the second emission structure EU2′ may be disconnected by a partition SPR (e.g., trenches TRCH1′ to TRCH3′) at a boundary area BDA. For example, the first emission structure EU1′ and the second emission structure EU2′ of the first sub-pixel SP1 may be disconnected or separated from the first emission structure EU1′ and the second emission structure EU2′ of the second sub-pixel SP2 in the boundary area BDA. Accordingly, when the display panel DP (see FIG. 1 ) is Figure 4 ) operation, current flowing out from each of the first to third sub-pixels SP1 to SP3 to adjacent sub-pixels through the layers included in the emission structure EU′ may be reduced.

[0255] On the other hand, the third emission structure EU3' may not be broken in the boundary area BDA and may be continuous. For example, the third emission structure EU3' of the first subpixel SP1 and the third emission structure EU3' of the second subpixel SP2 may be connected to each other in the boundary area BDA.

[0256] The first emission structure EU1' to the third emission structure EU3' may each include an emission layer that generates light according to an applied current. The first emission structure EU1' may include a first emission layer EML1', a 1-2 functional layer ETR1', and a 1-1 functional layer HTR1'. The first emission layer EML1' may be disposed between the 1-2 functional layer ETR1' and the 1-1 functional layer HTR1'. The second emission structure EU2' may include a second emission layer EML2', a 2-2 functional layer ETR2', and a 2-1 functional layer HTR2'. The second emission layer EML2' may be disposed between the 2-2 functional layer ETR2' and the 2-1 functional layer HTR2'. The third emission structure EU3' may include a third emission layer EML3', a 3-2 functional layer ETR3', and a 3-1 functional layer HTR3'. The third emission layer EML3' may be disposed between the 3-2 functional layer ETR3' and the 3-1 functional layer HTR3'.

[0257] The 1-1st functional layer HTR1', the 2-1st functional layer HTR2', and the 3-1st functional layer HTR3' may each include at least one of a hole injection layer and a hole transport layer, and if necessary, may further include a hole buffer layer and an electron blocking layer. Some of the 1-1st functional layer HTR1', the 2-1st functional layer HTR2', and the 3-1st functional layer HTR3' may have different configurations.

[0258] The 1-2 functional layer ETR1', the 2-2 functional layer ETR2' and the 3-2 functional layer ETR3' may each include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer or a hole blocking layer if necessary. The 1-2 functional layer ETR1', the 2-2 functional layer ETR2' and the 3-2 functional layer ETR3' may have the same configuration or different configurations.

[0259] In some embodiments, the first emission layer EML1' to the third emission layer EML3' may generate light of different colors. The light emitted from the first emission layer EML1' to the third emission layer EML3' may be mixed and recognized as white light. For example, the first emission layer EML1' may generate blue light, the second emission layer EML2' may generate green light, and the third emission layer EML3' may generate red light.

[0260] In some other embodiments, two or more of the first to third emission layers EML1 ′ to EML3 ′ may generate light of the same color.

[0261] The first intermediate layer CGL1' (or first charge generation layer) may be disposed between the first emission structure EU1' and the second emission structure EU2'. The second intermediate layer CGL2' (or second charge generation layer) may be disposed between the second emission structure EU2' and the third emission structure EU3'.

[0262] In some embodiments, Fig.12 As shown in , similar to the first emission structure EU1' and the second emission structure EU2', the first intermediate layer CGL1' and the second intermediate layer CGL2' may be disconnected at the upper portion of the trenches TRCH1' to TRCH3'. In this case, the occurrence of current flowing from a sub-pixel through the first intermediate layer CGL1' and the second intermediate layer CGL2' to another adjacent sub-pixel may be reduced (e.g., may be prevented), and the sub-pixel may operate with high reliability.

[0263] In some embodiments, the ratio of the width W_T' to the depth L_T' of the groove TRCH' may be about 1:1.45 to about 1:11. In some embodiments, the ratio of the width W_T' to the depth L_T' of the groove TRCH' may be about 1:4.2 to about 1:6.4. For example, the ratio of the width W_T' to the depth L_T' of the groove TRCH' may be about 1:5.2. In other words, the width W_T' of the groove TRCH' may be about 9% to about 70% of the depth L_T' of the groove TRCH'. In some embodiments, the width W_T' of the groove TRCH' may be about 15% to about 24% of the depth L_T' of the groove TRCH'.

[0264] The total thickness of the first emission structure EU1' and the second emission structure EU2' may be Fig. 9 The thickness of the first emission structure EU1 in FIG. 1 is similar to that of the first emission structure EU1, and the thickness of the third emission structure EU3′ can be similar to that of Fig. 9 The thickness of the second emission structure EU2 is similar.

[0265] In some embodiments, the total thickness of the first emission structure EU1' and the second emission structure EU2' may be about 17% to about 82% of the depth L_T' of the trench TRCH'. In some embodiments, the total thickness of the first emission structure EU1' and the second emission structure EU2' may be about 51% to about 78% of the depth L_T' of the trench TRCH'. For example, the total thickness of the first emission structure EU1' and the second emission structure EU2' may be about 63% of the depth L_T' of the trench TRCH'.

[0266] In some embodiments, the total thickness of the first emission structure EU1' and the second emission structure EU2' may be about 0.8 times to about 2.6 times the width W_T' of the trench TRCH'. In some embodiments, the total thickness of the first emission structure EU1' and the second emission structure EU2' may be about 1.2 to about 1.8 times the width W_T' of the trench TRCH'. For example, the total thickness of the first emission structure EU1' and the second emission structure EU2' may be about 1.53 times the width W_T' of the trench TRCH'.

[0267] In some embodiments, the thickness of the third emission structure EU3' may be about 0.4 times to about 2.5 times the depth L_T' of the trench TRCH'. In some embodiments, the thickness of the third emission structure EU3' may be about 0.6 times to about 1.0 times the depth L_T' of the trench TRCH'. For example, the thickness of the third emission structure EU3' may be about 0.78 times the depth L_T' of the trench TRCH'.

[0268] In some embodiments, the thickness of the third emission structure EU3' may be about 2.4 to about 6.5 times the width W_T' of the trench TRCH'. In some embodiments, the thickness of the third emission structure EU3' may be about 3.3 to about 5.0 times the width W_T' of the trench TRCH'. For example, the thickness of the third emission structure EU3' may be about 4.1 times the width W_T' of the trench TRCH'.

[0269] In some embodiments, the depth L_T' of the trench TRCH' may be about to about And the width W_T' of the trench TRCH' may be about to about In some embodiments, the depth L_T' of the trench TRCH' may be about to about And the width W_T' of the trench TRCH' may be about to about The thickness of the first emitting structure EU1' may be about to about In the range of , the thickness of the second emission structure EU2' can be about to about and the thickness of the third emission structure EU3' may be in the range of about to about For example, the depth L_T' of the trench TRCH' may be about The width W_T' of the trench TRCH' may be about The thickness of the first emitting structure EU1' may be about The thickness of the second emitting structure EU2' may be about And the thickness of the third emission structure EU3' may be about The thickness of the 3-1st functional layer HTR3' can be Fig. 9 The thickness TH2 of the 2-1 functional layer HTR2 is similar.

[0270] In some embodiments, the thickness of the 3-1st functional layer HTR3' (or the third hole transport layer) may be about 0.4 times to about 1.8 times the depth L_T' of the groove TRCH'. In some embodiments, the thickness of the 3-1st functional layer HTR3' (or the third hole transport layer) may be about 0.5 times to about 0.8 times the depth L_T' of the groove TRCH'. For example, the thickness of the 3-1st functional layer HTR3' (or the third hole transport layer) may be about 0.63 times the depth L_T' of the groove TRCH'.

[0271] In some embodiments, the thickness of the 3-1st functional layer HTR3' (or the third hole transport layer) may be about 2 times to about 5.5 times the width W_T' of the trench TRCH'. In some embodiments, the thickness of the 3-1st functional layer HTR3' (or the third hole transport layer) may be about 2.7 times to about 4.1 times the width W_T' of the trench TRCH'. For example, the thickness of the 3-1st functional layer HTR3' (or the third hole transport layer) may be about 3.3 times the width W_T' of the trench TRCH'.

[0272] In some embodiments, when the depth L_T' of the trench TRCH' is about And the width W_T' of the trench TRCH' is about to about When the thickness of the 1-1 functional layer HTR1' (or the first hole transport layer) is within the range of about to about In the range of , the thickness of the 2-1st functional layer HTR2' (or the second hole transport layer) can be about to about and the thickness of the 3-1st functional layer HTR3' (or the third hole transport layer) may be in the range of about to about For example, the thickness of the 1-1 functional layer HTR1' (or the first hole transport layer) may be about The thickness of the 2-1st functional layer HTR2' (or the second hole transport layer) may be about And the thickness of the 3-1st functional layer HTR3' (or the third hole transport layer) may be about

[0273] For reference, the thickness of the first emission layer EML1' may be about to about (For example, about ), the thickness of the first-second functional layer ETR1' may be about to about (For example, about ), the thickness of the first intermediate layer CGL1' may be about to about (For example, about ), the thickness of the second emission layer EML2' may be about to about (For example, about ), the thickness of the 2-2 functional layer ETR2' may be about to about (For example, about ), the thickness of the second intermediate layer CGL2' may be about to about (For example, about ), the thickness of the third emission layer EML3' may be about to about (For example, about ), and the thickness of the 3-2 functional layer ETR3' may be about to about (For example, about ).

[0274] In some embodiments, the 1-1 functional layer HTR1' and the 2-1 functional layer HTR2' (or the first hole transport layer and the second hole transport layer) include a plate material, and the 3-1 functional layer HTR3' (or the third hole transport layer) includes a bulk material. In this case, the first emission structure EU1', the first intermediate layer CGL1', the second emission structure EU2', and the second intermediate layer CGL2' may be disconnected in the grooves TRCH1' to TRCH3', and the third emission structure EU3' and the cathode CE may not be disconnected in the grooves TRCH1' to TRCH3'.

[0275] By cutting off the first intermediate layer CGL1 ′ and the second intermediate layer CGL2 ′, the occurrence of side leakage may be reduced (eg, may be prevented), and the sub-pixel may be normally driven by the connection of the cathode CE.

[0276] Fig.14 It is a diagram showing some embodiments of the present disclosure including Figure 5 A plan view of a pixel in a display device.

[0277] Fig.15 is a diagram showing some embodiments of the present disclosure. Fig.14 A cross-sectional view of the display device taken along line II-II'.

[0278] Reference Fig. 6A , Figure 7 , Fig.14 and Fig.15 , in addition to the trench TRCH (or the spacer SPR), Fig.14 and Fig.15 The display device can be used with Fig. 6A and Figure 7 The display devices of the present invention are substantially the same or similar. Therefore, a redundant description will not be repeated.

[0279] A spacer SPR may be provided in a boundary area BDA between adjacent sub-pixels.

[0280] In some embodiments, the pixel defining layer PDL may include a trench TRCH as a spacer SPR in the boundary area BDA. Fig.14 and Fig.15 As shown in FIG. 1 , a trench TRCH may be provided as a partition in a boundary area BDA between the first sub-pixel SP1 and the second sub-pixel SP2 and in a boundary area BDA between the second sub-pixel SP2 and the third sub-pixel SP3 .

[0281] like Fig.14 As shown in , one trench TRCH may surround each of the first to third sub-pixels SP1 to SP3. The trench TRCH may have a grid corresponding to the sub-pixels. For example, the trench TRCH may have a mesh structure.

[0282] In some embodiments, the groove TRCH may penetrate the pixel defining layer PDL and partially penetrate the planarization layer PLNL. However, the present disclosure is not limited thereto. In some embodiments, the pixel defining layer PDL may not be disposed in the groove TRCH. However, the present disclosure is not limited thereto. For example, the pixel defining layer PDL may be disposed on the side surface and the bottom surface of the groove TRCH so that the groove TRCH is defined by the pixel defining layer PDL.

[0283] Since reference has been Figure 8The specifications (eg, depth, width, etc.) of the trench TRCH are described, and thus a description of the specifications of the trench TRCH will not be provided.

[0284] The first emission structure EU1 may be disconnected by the partition SPR in the boundary area BDA. Figure 4 ) operation, current flowing out from each of the first to third sub-pixels SP1 to SP3 to adjacent sub-pixels through the layers included in the emission structure EU may be reduced.

[0285] On the other hand, the second emission structure EU2 may not be disconnected in the boundary area BDA and may be continuous. In this case, the cathode CE may not be disconnected in the boundary area BDA and may be continuous. Accordingly, the second power supply voltage may be stably supplied to the first to third sub-pixels SP1 to SP3, and the first to third light-emitting elements LD1 to LD3 may operate normally.

[0286] Fig.16 is a diagram showing some embodiments of the present disclosure. Fig.14 A cross-sectional view of the display device taken along line II-II'.

[0287] Fig.17 According to some embodiments of the present disclosure Fig.16 An enlarged cross-sectional view of a portion of a display device.

[0288] Reference Figure 7 , Figure 8 , Fig.14 , Fig.16 and Fig.17 , except that protrusions PRT are provided instead of grooves as separators SPR, Fig.16 and Fig.17 The display device can be used with Figure 7 and Figure 8 The display devices of the present invention are substantially the same or similar. Therefore, a redundant description will not be repeated.

[0289] In some embodiments, the pixel defining layer PDL may include a protrusion PRT protruding from the boundary area BDA in the third direction DR3. The protrusion PRT may form a step in the base layer (i.e., the upper surface of the pixel defining layer PDL) for the arrangement of the first emission structure EU1 in the boundary area BDA, and may disconnect the first emission structure EU1 (and the intermediate layer CGL) in the boundary area BDA.

[0290] The protrusion PRT may include sequentially stacked inorganic insulating patterns. Fig.17As described, the pixel defining layer PDL may include a first inorganic layer PDL1, a second inorganic layer PDL2, and a third inorganic layer PDL3 sequentially stacked. The protrusion PRT may include a first inorganic insulating pattern PRT_L1, a second inorganic insulating pattern PRT_L2, and a third inorganic insulating pattern PRT_L3 (or a fourth inorganic pattern, a fifth inorganic pattern, and a sixth inorganic pattern) sequentially stacked on the third inorganic layer PDL3. The first inorganic insulating pattern PRT_L1 and the third inorganic insulating pattern PRT_L3 may each include silicon oxide (SiO x ), and the second inorganic insulating pattern PRT_L2 may include silicon nitride (SiN x ).

[0291] In some embodiments, based on the first direction DR1, the width of the third inorganic insulating pattern PRT_L3 may be greater than the width of the second inorganic insulating pattern PRT_L2. In some embodiments, the width of the second inorganic insulating pattern PRT_L2 may be less than or equal to the width of the first inorganic insulating pattern PRT_L1. In this case, the protrusion PRT may have a cross-section of an inverted tapered shape, a "T" shape, or an "I" shape.

[0292] The first emission structure EU1 and the intermediate layer CGL may be disconnected in the boundary area BDA according to the shape of the protrusion PRT (or the pixel defining layer PDL). On the other hand, the second emission structure EU2 and the cathode CE may be connected without being disconnected in the boundary area BDA.

[0293] like Fig.17 As shown in , the first emission structure EU1 and the intermediate layer CGL may not be formed (or deposited) on the side of the protrusion PRT, and the first emission structure EU1 and the intermediate layer CGL may be disconnected at the edge of the protrusion PRT.

[0294] In some embodiments, based on the third direction DR3, the thickness of the first emission structure EU1 may be less than the thickness of the protrusion PRT, and the thickness of the second emission structure EU2 may be greater than the thickness of the protrusion PRT. In this case, at the edge of the protrusion PRT, each of the first emission structure EU1 and the intermediate layer CGL may be disconnected or discontinuous, and each of the second emission structure EU2 and the cathode CE may be connected or continuous.

[0295] As reference Fig. 9As described, the first emission structure EU1 may include a first emission layer EML1, a 1-2 functional layer ETR1 (or a first electron transport layer), and a 1-1 functional layer HTR1 (or a first hole transport layer). The first emission layer EML1 may be disposed between the 1-2 functional layer ETR1 and the 1-1 functional layer HTR1. The second emission structure EU2 may include a second emission layer EML2, a 2-2 functional layer ETR2 (or a second electron transport layer), and a 2-1 functional layer HTR2 (or a second hole transport layer). The second emission layer EML2 may be disposed between the 2-2 functional layer ETR2 and the 2-1 functional layer HTR2.

[0296] In some embodiments, the 1-1st functional layer HTR1 (or the first hole transport layer) may include a plate material, and the 2-1st functional layer HTR2 (or the second hole transport layer) may include a block material. In this case, at the edge of the protrusion PRT, the 1-1st functional layer HTR1 may be bent and disconnected, and the 2-1st functional layer HTR2 may not be disconnected. Accordingly, each of the first emission structure EU1 and the intermediate layer CGL may be disconnected or discontinuous, and each of the second emission structure EU2 and the cathode CE may be connected or continuous.

[0297] The occurrence of side leakage may be reduced (eg, may be prevented) by cutting off the intermediate layer CGL, and the sub-pixels may be normally driven by the connection of the cathode CE.

[0298] Fig.18 is a block diagram illustrating a display system according to some embodiments of the present disclosure.

[0299] Reference Fig.18 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0300] The processor 1100 may perform various tasks and calculations. In some embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system and control the components of the display system 1000.

[0301] Fig.18 The display system 1000 is shown to include a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1 and to the second display device 1220 through a second channel CH2.

[0302] The processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 through the first channel CH1. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0303] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 through the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0304] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, or an ultra mobile personal computer (UMPC). In some embodiments, the display system 1000 may include at least one selected from a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0305] Fig.19 It is shown Fig.18 A perspective view showing an application example of the display system.

[0306] Reference Fig.19 , Fig.18 The display system 1000 may be applied to an HMD device 2000. The HMD device 2000 may be a wearable electronic device that can be worn on the head of a user.

[0307] The HMD device 2000 may include a head mounting band 2100 and a display device storage box 2200. The head mounting band 2100 may be connected to the display device storage box 2200. The head mounting band 2100 may include a transverse band and / or a longitudinal band for fixing the HMD device 2000 to the user's head. The transverse band may be configured to surround the side of the user's head, and the longitudinal band may be configured to surround the upper part of the user's head. However, the present disclosure is not limited thereto. For example, the head mounting band 2100 may be implemented in the form of a glasses frame, a helmet, etc.

[0308] The display device storage box 2200 can accommodate Fig.18 The display device storage box 2200 can also accommodate the first display device 1210 and the second display device 1220. Fig.18 Processor 1100.

[0309] Fig. 20 is a diagram showing a device worn by a user according to some embodiments of the present disclosure Fig.19 Figure 2 shows an example of an application of .

[0310] Reference Fig. 20 The HMD device 2000 (or wearable electronic device) may include a display panel that emits light and a lens unit disposed on the display panel (or on a light emission path). The display panel may include a first display device 1210 (see Fig.18 ) of the first display panel DP1 and the second display device 1220 (see Fig.18 ) of the second display panel DP2. The lens unit may include one or more lenses LLNS and RLNS.

[0311] The right-eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user within the display device storage box 2200. The left-eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user within the display device storage box 2200.

[0312] The image output from the first display panel DP1 may be displayed to the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract light from the first display panel DP1 to guide it toward the right eye of the user. The right eye lens RLNS may perform an optical function for adjusting the viewing distance between the first display panel DP1 and the right eye of the user.

[0313] The image output from the second display panel DP2 may be displayed to the user's left eye through the left eye lens LLNS. The left eye lens LLNS may refract light from the second display panel DP2 to guide it toward the user's left eye. The left eye lens LLNS may perform an optical function for adjusting the viewing distance between the second display panel DP2 and the user's left eye.

[0314] In some embodiments, the right-eye lens RLNS and the left-eye lens LLNS may each include an optical lens having a pancake-shaped cross-section. In some embodiments, the right-eye lens RLNS and the left-eye lens LLNS may each include a multi-channel lens including sub-regions having different optical properties. In this case, each display panel may output an image corresponding to a sub-region of the multi-channel lens, and the output image may pass through the corresponding sub-region and may be displayed to the user.

[0315] In a display device and a wearable electronic device according to some embodiments of the present disclosure, each sub-pixel may include a first emission structure, an intermediate layer, and a second emission structure sequentially stacked between a first electrode and a second electrode. In a boundary region of the sub-pixel, the first emission structure and the intermediate layer may be disconnected, and the second emission structure and the cathode may be continuous. Since the intermediate layer is disconnected in the boundary region, leakage current passing through the intermediate layer between sub-pixels can be reduced, and the sub-pixels can emit light with a desired brightness.

[0316] In some embodiments, since the second emission structure and the cathode are continuous in the boundary region, the sub-pixel can be driven normally.

[0317] Effects according to some embodiments are not limited to the description presented above, and more various effects are incorporated in this specification.

[0318] Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made in the embodiments without departing from the spirit and scope of the present disclosure. It should be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically indicated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it should be understood that the foregoing is an illustration of various aspects of the exemplary embodiments and is not to be construed as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other aspects of the exemplary embodiments are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: a base layer defining a groove; as well as a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel being located at opposite sides of the trench, each of the first sub-pixel and the second sub-pixel comprising: a first electrode, the first electrode being located on the base layer; a first emission structure, the first emission structure being located on the first electrode and configured to emit light, the first emission structure comprising a first hole transport layer, a first emission layer and a first electron transport layer, the thickness of the first hole transport layer being less than the depth of the groove; a first intermediate layer, the first intermediate layer being located on the first emitting structure; a second emission structure, the second emission structure being located on the first intermediate layer and configured to emit light, the second emission structure comprising a second hole transport layer, a second emission layer, and a second electron transport layer, the thickness of the second hole transport layer being greater than the depth of the groove; and A second electrode is located on the second emitting structure.

2. The display device according to claim 1, wherein: The groove comprises: a first trench surrounding the first sub-pixel in a plan view; and a second trench surrounding the second sub-pixel in a plan view, and Wherein, the first groove and the second groove are spaced apart from each other.

3. The display device according to claim 1, wherein: The depth of the groove is to The width of the groove is to Wherein, the thickness of the first hole transport layer is to as well as Wherein, the thickness of the second hole transport layer is to 4. The display device according to claim 1, wherein: The first hole transport layer includes a material different from a material of the second hole transport layer.

5. The display device according to claim 4, wherein: The glass transition temperature of the second hole transport layer is 10% to 30% higher than the glass transition temperature of the first hole transport layer.

6. The display device according to claim 5, wherein: The glass transition temperature of the second hole transport layer is 15° C. to 35° C. higher than the glass transition temperature of the first hole transport layer.

7. The display device according to claim 1, wherein: The thickness of the second electrode is to 8. The display device according to claim 7, wherein: The step of the second electrode on the groove is or smaller.

9. The display device according to claim 1, wherein: The thickness of the first emitting structure is less than the depth of the trench, and Wherein, the thickness of the second emission structure is greater than the depth of the groove.

10. The display device according to claim 9, wherein: The thickness of the first emitting structure is less than or equal to 70% of the depth of the trench, and Wherein, the thickness of the second emission structure is greater than or equal to 160% of the depth of the groove.

11. The display device according to claim 9, wherein: The depth of the groove is to The width of the groove is to Wherein, the thickness of the first emitting structure is to as well as Wherein, the thickness of the second emitting structure is to 12. The display device according to claim 1, wherein: The first emission structure and the first intermediate layer of the first sub-pixel are spaced apart from the first emission structure and the first intermediate layer of the second sub-pixel at the groove, and At least a portion of the second emission structure of the first sub-pixel is connected to at least a portion of the second emission structure of the second sub-pixel on the groove.

13. The display device according to claim 12, wherein: The first sub-pixel and the second sub-pixel each further include: a third emitting structure positioned between the first electrode and the first emitting structure and configured to emit light; and a second intermediate layer, the second intermediate layer being positioned between the third emission structure and the first emission structure, The third emission structure and the second intermediate layer of the first sub-pixel are spaced apart from the third emission structure and the second intermediate layer of the second sub-pixel at the groove.

14. The display device according to claim 1, wherein: The first emitting structure is configured to emit light of a first color, and The second emitting structure is configured to emit light of a second color different from the first color.

15. The display device according to claim 1, wherein: The first emitting structure and the second emitting structure are configured to emit light of the same color.

16. A display device, comprising: a first electrode, the first electrode being located on the base layer; a first emission structure, the first emission structure being located on the first electrode and configured to emit light, the first emission structure comprising a first hole transport layer, a first emission layer and a first electron transport layer; an intermediate layer, the intermediate layer being located on the first emitting structure; a second emission structure, the second emission structure being located on the intermediate layer and configured to emit light, the second emission structure comprising a second hole transport layer, a second emission layer, and a second electron transport layer, the glass transition temperature of the second hole transport layer being 10% to 30% higher than the glass transition temperature of the first hole transport layer; as well as A second electrode is located on the second emitting structure.

17. The display device according to claim 16, wherein: The glass transition temperature of the second hole transport layer is 15° C. to 35° C. higher than the glass transition temperature of the first hole transport layer.

18. A wearable electronic device comprising: a display panel configured to emit light; as well as at least one lens, wherein the at least one lens is located on the display panel, and the display panel comprises: a base layer defining a groove; and a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel being located at opposite sides of the trench, each of the first sub-pixel and the second sub-pixel comprising: a first electrode, the first electrode being located on the base layer; a first emission structure, the first emission structure being located on the first electrode and configured to emit light, the first emission structure comprising a first hole transport layer, a first emission layer and a first electron transport layer, the thickness of the first hole transport layer being less than the depth of the groove; an intermediate layer, the intermediate layer being located on the first emitting structure; a second emission structure, the second emission structure being located on the intermediate layer and configured to emit light, the second emission structure comprising a second hole transport layer, a second emission layer, and a second electron transport layer, the thickness of the second hole transport layer being greater than the depth of the groove; and A second electrode is located on the second emitting structure.

19. The wearable electronic device of claim 18, wherein: The glass transition temperature of the second hole transport layer is 10% to 30% higher than the glass transition temperature of the first hole transport layer.

20. The wearable electronic device of claim 18, wherein: The glass transition temperature of the second hole transport layer is 15° C. to 35° C. higher than the glass transition temperature of the first hole transport layer.

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