Display device

Abstract

A display device is provided. The display device includes: a substrate including an emission region and a non-emission region; a via layer on the emission region and the non-emission region of the substrate, and including a first recess toward the substrate in the non-emission region; a first pixel auxiliary layer on the through hole layer and including a protruding tip on one side and extending in a first direction from a side surface of the first recess in the non-emission region; a first pixel electrode on the first pixel auxiliary layer; a separator on the first pixel electrode in the non-emission region; a charge generation layer on the first pixel electrode in the emission region; a charge pattern on the separator and including the same material as that of the charge generation layer; and a common electrode on the charge generation layer and the charge pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0107603 filed in the Korean Intellectual Property Office on August 17, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device. Background Art

[0004] With the development of multimedia technology, display devices are becoming more and more important. Therefore, various display devices such as liquid crystal display devices and / or organic light emitting display devices are currently being developed.

[0005] Recently, virtual reality (VR) display devices and augmented reality (AR) display devices based on head-mounted displays (HMDs) have been attracting attention as next-generation display devices. For VR display devices and AR display devices used relatively closer to the user's eyes, it may be helpful or necessary to suppress or reduce the grid gate effect (SDE) and maintain depth perception. High-speed operation driving may also be helpful or necessary to reduce afterimages during fast movements. In view of the above, a display device with high resolution and high brightness may be desired or required. Summary of the invention

[0006] Aspects according to one or more embodiments of the present disclosure are directed to a display device having high resolution and high brightness.

[0007] These and other aspects, embodiments, and advantages of the present disclosure will become immediately apparent to those of ordinary skill in the art upon reading the detailed description and the appended claims.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a substrate including an emission area and a non-emission area; a through-hole layer, the through-hole layer is positioned on the emission area and the non-emission area of ​​the substrate and includes a first recess in the non-emission area facing the substrate; a first pixel auxiliary layer, the first pixel auxiliary layer is on the through-hole layer and includes a protruding tip extending from a side surface of the first recess in the non-emission area on one side of the first pixel auxiliary layer and in a first direction; a first pixel electrode, the first pixel electrode is positioned on the first pixel auxiliary layer; a separator, the separator is positioned on the first pixel electrode in the non-emission area; a charge generation layer, the charge generation layer is positioned on the first pixel electrode in the emission area; a charge pattern, the charge pattern is positioned on the separator, and the charge pattern and the charge generation layer include the same material; and a common electrode, the common electrode is positioned on the charge generation layer and the charge pattern, wherein the charge generation layer contacts the side surface of the separator, and wherein the charge generation layer and the charge pattern are spaced apart from each other (e.g., spaced apart and / or separated), and the common electrode positioned on the charge generation layer and the common electrode positioned on the charge pattern are provided as a whole.

[0009] According to one or more embodiments, the separation member may include a first surface positioned opposite to the first pixel electrode, and wherein an inclined angle formed by a side surface of the separation member and the first surface may be an acute angle or a right angle.

[0010] According to one or more embodiments, the display device may further include a first emission layer positioned between the charge generation layer and the common electrode, wherein the first emission layer covers the charge generation layer and the charge pattern, and wherein the first emission layer may contact a side surface of the separator.

[0011] According to one or more embodiments, a side surface of the separator may include a first portion contacting the charge generation layer, a second portion overlapping the charge pattern in a direction parallel to the substrate, and a third portion contacting the first emission layer, and wherein the third portion may be positioned between the first portion and the second portion.

[0012] According to one or more embodiments, the charge generation layer may include a conductive material (eg, a conductor), and wherein the first emission layer may not include (eg, exclude) the conductive material (eg, not be a conductor).

[0013] According to one or more embodiments, an undercut portion may be formed between a protruded tip of the first pixel auxiliary layer and a side surface of the first concave portion.

[0014] According to one or more embodiments, the protruding tip of the first pixel auxiliary layer may have a bottom surface facing the first recess and a first side surface connected to the bottom surface, wherein the first pixel electrode may contact the first side surface, and wherein the first pixel electrode may not contact the bottom surface.

[0015] According to one or more embodiments, the display device may further include: a second pixel auxiliary layer arranged in the non-emitting area and separated from the first pixel auxiliary layer with a separator interposed therebetween; and a second pixel electrode positioned on the second pixel auxiliary layer, wherein the first pixel electrode and the third pixel electrode may be spaced apart from each other with a separator interposed therebetween.

[0016] According to one or more embodiments, the display device may also include: a second emission layer positioned between the first pixel electrode and the charge generation layer; and an emission pattern positioned between the separator and the charge pattern, the emission pattern and the second emission layer comprising the same material, wherein the second emission layer and the emission pattern may be in contact with a side surface of the separator.

[0017] According to one or more embodiments, the second emission layer and the emission pattern may be spaced apart from each other.

[0018] According to one or more embodiments, the display device may further include a connecting electrode positioned between the substrate and the via layer in the emission region, wherein the via layer includes a first via layer exposing the connecting electrode and a second via layer spaced apart from the first via layer in a direction parallel to the substrate.

[0019] According to one or more embodiments, the first through-hole layer and the second through-hole layer may be separated from each other by a pixel electrode contact hole in the emission area, and wherein, in a plan view (e.g., when viewed from the top or in a top view), the pixel electrode contact hole may be positioned inside the separator.

[0020] According to one or more embodiments, the first pixel auxiliary layer may also include: a first sub-portion in contact with the first through-hole layer; and a second sub-portion spaced apart (e.g., spaced apart and / or separated) from the first sub-portion by the pixel electrode contact hole and in contact with the second through-hole layer, and wherein the first sub-portion and the second sub-portion may be connected via the first pixel electrode.

[0021] According to one or more embodiments, the separator may have an inverted tapered shape.

[0022] According to one or more embodiments, the first recess may be filled with the same material as that of the separator, and wherein the first recess and the separator are formed or provided as one body (eg, one integral or unitary body).

[0023] According to one or more embodiments, the first surface of the separator may include a second recessed portion facing the substrate.

[0024] According to one or more embodiments of the present disclosure, a display device may include: a substrate including a display area and a non-display area, the display area including an emission area and a non-emission area; a through-hole layer, the through-hole layer is positioned on the substrate and includes a recess in the non-emission area facing the substrate; a first pixel auxiliary layer, the first pixel auxiliary layer is positioned on the through-hole layer and includes a protruding tip on one side of the first pixel auxiliary layer and extending from a side surface of the recess in the non-emission area in a first direction; a first pixel electrode, the first pixel electrode is positioned on the first pixel auxiliary layer; a first pixel electrode pattern, the first pixel electrode pattern is positioned in the recess, the first pixel electrode pattern and the first pixel electrode include the same material, and the first pixel electrode pattern is spaced apart from the first pixel electrode; a separator, the separator is positioned on the first pixel electrode in the non-emission area; and a power electrode, the power electrode is positioned in the non-display area and surrounds the display area, wherein the separator does not overlap with the emission area, and wherein the separator completely surrounds the emission area in a plan view.

[0025] According to one or more embodiments, the first pixel electrode pattern may not overlap the emission region, and wherein the separator and the first pixel electrode pattern have a mesh pattern in a plan view.

[0026] According to one or more embodiments, the first pixel electrode pattern may be connected to a power supply electrode in a non-display area in a plan view.

[0027] According to one or more embodiments, the separator and the first pixel electrode pattern may overlap each other in a plan view.

[0028] According to an embodiment of the present disclosure, a separator defining an emission area of ​​a pixel in a display device is formed in an inverted tapered structure, thereby increasing the aperture ratio of the display area. Therefore, according to an embodiment, a display device with high resolution, high brightness and high efficiency can be provided.

[0029] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0031] Figure 1 is a perspective view showing an electronic device according to an embodiment of the present disclosure.

[0032] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment of the present disclosure.

[0033] Figure 3 is a cross-sectional view showing the structure of a display device according to an embodiment.

[0034] Figure 4 It is schematically shown Figure 3 A floor plan of the display layer.

[0035] Figure 5 It is shown Figure 3 A plan view of the layout of the emission area in the display area.

[0036] Figure 6 is along Figure 5 A cross-sectional view taken along line X1-X1'.

[0037] Figure 7 and Figure 8 It is shown Figure 6 Cross-sectional view of the emission material layer.

[0038] Fig. 9 It is shown Figure 6 An enlarged cross-sectional view of the periphery of a first light-emitting element in a first emission region.

[0039] Fig.10 yes Figure 6 An enlarged cross-sectional view of area A.

[0040] Fig.11 yes Fig.10 An enlarged cross-sectional view of area C1.

[0041] Fig.12 yes Fig.11 An enlarged cross-sectional view of area C3.

[0042] Fig.13 is a plan view showing a separator and a pixel electrode pattern in a display area.

[0043] Fig.14 is a plan view showing a layout of separators in a display area according to another embodiment.

[0044] Fig.15 yes Figure 4 An enlarged plan view of region V.

[0045] Fig.16 yes Figure 6 An enlarged cross-sectional view of another example of region A.

[0046] Fig.17 According to another embodiment Fig.16An enlarged cross-sectional view of region E of FIG. DETAILED DESCRIPTION

[0047] The present disclosure will now be described more fully herein with reference to the accompanying drawings in which some embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0048] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or one or more intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0049] It is to be understood that although the terms "first", "second", etc. may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed herein may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0050] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It is also understood that terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology and are explicitly defined herein unless they are interpreted in an ideal or overly formal sense.

[0051] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0052] Figure 1 is a perspective view showing an electronic device 1 according to an embodiment of the present disclosure.

[0053] Reference Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 may refer to any electronic device that provides a display screen. For example, the electronic device 1 may include a television, a laptop computer, a monitor, an electronic billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic clock, a smart clock, a clock phone, a head-mounted display device, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and a video camera.

[0054] exist Figure 1In the drawings, a first direction (x-axis direction), a second direction (y-axis direction), and a third direction (z-axis direction) are defined. The first direction (x-axis direction) and the second direction (y-axis direction) may be perpendicular to each other (e.g., substantially perpendicular or orthogonal), the first direction (x-axis direction) and the third direction (z-axis direction) may be perpendicular to each other (e.g., substantially perpendicular or orthogonal), and the second direction (y-axis direction) and the third direction (z-axis direction) may be perpendicular to each other (e.g., substantially perpendicular or orthogonal). The first direction (x-axis direction) may refer to the horizontal direction in the drawings, the second direction (y-axis direction) may refer to the vertical direction in the drawings, and the third direction (z-axis direction) may refer to the up and down direction, that is, the thickness direction in the drawings. As used herein, a direction may refer to the direction indicated by an arrow as well as the opposite direction, unless otherwise specifically stated. When it is necessary to distinguish between the two opposite directions, one of the two directions may be referred to as "one side in the direction" and the other direction may be referred to as "the opposite side in the direction". In Figure 1 , a side indicated by an arrow indicating a direction is referred to as a side in the direction, and the opposite side is referred to as an opposite side in the direction.

[0055] In the following description of the surface of the electronic device 1 or the elements of the electronic device 1, for the convenience of explanation, the surface facing the side where the image is displayed (i.e., the side indicated by the arrow in the third direction (z-axis direction)) will be referred to as the upper surface, and the opposite surface will be referred to as the lower surface. However, it should be understood that the present disclosure is not limited to this. The surface and the opposite surface of each of the multiple elements may be referred to as the front surface and the rear surface, respectively, or may be referred to as the first surface and the second surface, respectively. In some embodiments, in the description of the relative positions of the elements of the electronic device 1, the side in the third direction (z-axis direction) may be referred to as the upper side, and the opposite side in the third direction (z-axis direction) may be referred to as the lower side.

[0056] The shape of the electronic device 1 can be modified in various ways. For example, the electronic device 1 may have a shape such as a rectangle with longer lateral sides, a rectangle with longer vertical sides, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc.

[0057] The electronic device 1 may include a display area DA and a non-display area NDA. In the display area DA, an image can be displayed. In the non-display area NDA, no image is displayed. The display area DA may be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may generally occupy the center of the electronic device 1.

[0058] Figure 2 is a perspective view showing a display device 10 included in the electronic device 1 according to an embodiment of the present disclosure.

[0059] Reference Figure 2 According to an embodiment, the electronic device 1 may include a display device 10. The display device 10 may provide a display screen in which an image is displayed in the electronic device 1. Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, a field emission display device, and the like. In the following description, an organic light emitting diode display device is used as an example of the display device 10, but the present disclosure is not limited thereto. Any other display device may be used as long as the technical idea of ​​the present disclosure can be equally applied.

[0060] The display device 10 may have a shape similar to that of the electronic device 1 in a plan view (e.g., when viewed from the top or in a top view). For example, the display device 10 may have a shape similar to a rectangle having a shorter side in a first direction (x-axis direction) and a longer side in a second direction (y-axis direction). The corners where the shorter side in the first direction (x-axis direction) intersects with the longer side in the second direction (y-axis direction) may be rounded with a set or predetermined curvature. However, it should be understood that the present disclosure is not limited to this. The corners may be formed at right angles. The shape of the display device 10 in a plan view is not limited to a quadrilateral shape, but may be formed into a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0061] The display device 10 may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0062] The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include pixels PX (see FIG. Figure 4 ) and a non-display area NDA positioned around the display area DA.

[0063] The display area DA may be configured to emit light from a plurality of emission areas or a plurality of opening areas to be described later. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element. For example, the self-luminous element may include, but is not limited to, an organic light-emitting diode including an organic emission layer, a quantum dot light-emitting diode (quantum LED) including a quantum dot emission layer, an inorganic light-emitting diode (inorganic LED) including an inorganic semiconductor, and at least one of a micro light-emitting diode (micro LED). In the following figures, it is illustrated that the self-luminous element is an organic light-emitting diode.

[0064] The non-display area NDA may be arranged on the outer side of the display area DA. The non-display area NDA may be defined as an edge of the main area MA of the display panel 100. The non-display area NDA may include a line driver supplying a signal to the display area DA and a line connecting the display driver 200 with the display area DA.

[0065] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (e.g., the third direction or the z-axis direction). The sub-region SBA may include a pad connected to the display driver 200 and the circuit board 300. According to another embodiment, the sub-region SBA may be removed, and the display driver 200 and the pad may be arranged in the non-display area NDA.

[0066] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to the data lines DL (see Figure 4 The display driver 200 may apply a power supply voltage to a voltage line (eg, Figure 4 The first voltage line VL1 and the second voltage line VL2 in FIG. 1 may supply a gate control signal to the gate driver 210 (see FIG. 1 ). Figure 4 ). The display driver 200 may be implemented as an integrated circuit (IC) and may be attached to the display panel 100 by a chip on glass (COG) technology, a chip on plastic (COP) technology, or ultrasonic bonding. For example, the display driver 200 may be arranged in the sub-area SBA and may overlap with the main area MA in the thickness direction as the sub-area SBA is bent. As another example, the display driver 200 may be mounted on the circuit board 300.

[0067] The circuit board 300 may be attached to the pad area of ​​the display panel 100 using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pads of the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0068] Figure 3 is a cross-sectional view showing the structure of a display device 10 according to an embodiment.

[0069] Reference Figure 3 , the display panel 100 may include a display layer DPL and a color filter layer 190 . The display layer DPL may include a substrate 110 , a thin film transistor layer 130 , a display element layer 150 , and a thin film encapsulation layer 170 .

[0070] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate 110 may include, but is not limited to, a polymer resin such as polyimide (PI). According to another embodiment, the substrate 110 may include a glass material or a metal material.

[0071] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor TFT (see FIG. 1 ) included in the thin film transistor layer 130 Figure 6 ), gate line GL (see Figure 4 ), data lines DL and voltage lines may be arranged in the display area DA. A plurality of thin film transistors TFT may form a pixel circuit of a pixel PX connected thereto. A gate control line GCL (see Figure 4 ) and fan-out line FOL (see Figure 4 ) may be arranged in the non-display area NDA. A lead line of the thin film transistor layer 130 may be arranged in the sub-area SBA.

[0072] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may include a plurality of light emitting elements ED including a pixel electrode, an emission material layer, and a common electrode to emit light (see Figure 6 ) and a separation member 155 defining a pixel PX (see Figure 6 ). A plurality of light emitting elements ED in the display element layer 150 may be arranged in the display area DA.

[0073] According to an embodiment of the present disclosure, the light emitting element ED may be an organic light emitting element including an organic material. The light emitting element ED may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the pixel electrode receives a voltage through the thin film transistor TFT of the thin film transistor layer 130 and the common electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, so that the holes and electrons are combined in the organic light emitting layer to emit light.

[0074] According to another embodiment, the light emitting elements ED may include quantum dot light emitting diodes each including a quantum dot emission layer, inorganic light emitting diodes each including an inorganic semiconductor, or micro light emitting diodes.

[0075] The thin film encapsulation layer 170 may cover the upper surface and the side surface of the display element layer 150 and can protect the display element layer 150. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the display element layer 150.

[0076] The color filter layer 190 may be arranged on the thin film encapsulation layer 170. The color filter layer 190 may include a plurality of color filters respectively associated with the plurality of emission regions. Each of the plurality of color filters may selectively transmit light of a specific wavelength and block or reduce or absorb light of other wavelengths. The color filter layer 190 may be configured to absorb some of the light introduced from outside the display device 10 to reduce reflection of external light. Therefore, the color filter layer 190 is capable of preventing or reducing the distortion of color caused by reflection of external light.

[0077] Since the color filter layer 190 is directly disposed on the thin film encapsulation layer 170, the display device 10 may not require a separate substrate 110 for the color filter layer 190. Therefore, the thickness of the display device 10 can be relatively small.

[0078] Figure 4 It is schematically shown Figure 3 Schematic plan view of the display layer DPL.

[0079] Reference Figure 4 In the display area DA of the display layer DPL, a plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a second voltage line VL2 may be positioned. Each of the plurality of pixels PX may be defined as a minimum unit of output light.

[0080] The plurality of gate lines GL may supply gate signals received from the gate driver 210 to the plurality of pixels PX. The plurality of gate lines GL may extend in a first direction (x-axis direction) and may be spaced apart (e.g., spaced apart and / or separated) from each other in a second direction (y-axis direction) crossing the first direction (x-axis direction).

[0081] The plurality of data lines DL may supply the plurality of pixels PX with data voltages received from the display driver 200. The plurality of data lines DL may extend in the second direction (y-axis direction) and may be spaced apart from each other in the first direction (x-axis direction).

[0082] The second voltage line VL2 may apply a power supply voltage received from the display driver 200 to the plurality of pixels PX. The power supply voltage may be at least one of a driving voltage, an initialization voltage, and a reference voltage. The plurality of second voltage lines VL2 may extend in the second direction (y-axis direction) and may be spaced apart from each other in the first direction (x-axis direction).

[0083] The non-display area NDA of the display layer DPL may surround the display area DA. In the non-display area NDA, a first voltage line VL1, a gate driver 210, a fan-out line FOL, and a gate control line GCL may be arranged. The gate driver 210 may generate a plurality of gate signals based on the gate control signal, and may sequentially supply the plurality of gate signals to the plurality of gate lines GL in a set or predetermined order.

[0084] The first voltage line VL1 may surround the display area DA and may be disposed in the non-display area NDA. The first voltage line VL1 may apply a power voltage received from the display driver 200 to the plurality of pixels PX. The power voltage may be a low-level power voltage.

[0085] The fan-out line FOL may extend to the display area DA from the display driver 200. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0086] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210. Although the gate driver 210 is arranged only in the non-display area NDA on the left side of the display area DA in the drawings, the present disclosure is not limited thereto. According to some embodiments, the display device 10 may include a plurality of gate drivers 210 respectively arranged on the left and right sides of the display area DA.

[0087] The sub-area SBA of the display layer DPL may include the display driver 200 and a plurality of display pads PD.

[0088] The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 may supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be applied to a plurality of pixels PX, so that the brightness of the plurality of pixels PX may be controlled or selected. The display driver 200 may supply gate control signals to the gate driver 210 through the gate control lines GCL.

[0089] The plurality of display pads PD may be connected to a graphic system through the circuit board 300. The plurality of display pads PD may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0090] Figure 5 It is shown Figure 3 A plan view of a layout of emission regions in a display area DA.

[0091] Reference Figure 5 , the display device 10 may include a plurality of emission areas (e.g., a first emission area EA1, a second emission area EA2, and a third emission area EA3) and a non-emission area NLA disposed in the display area DA. The plurality of first emission areas EA1, second emission areas EA2, and third emission areas EA3 and the non-emission area NLA may be formed by a separation member 155 (see FIG. 1 ) to be described later. Figure 6 )limited.

[0092] A plurality of pixels PX may include a first emission region EA1, a second emission region EA2, and a third emission region EA3 configured to emit light of different colors. For example, the display device 10 may include: a first emission region EA1 configured to emit light of a first color (e.g., red light having a wavelength range of about (e.g., approximately) 610 nm to about 680 nm and a peak wavelength in a range of 610 nm to 650 nm (e.g., about 620 nm to about 623 nm)); a second emission region EA2 configured to emit light of a second color (e.g., green light having a wavelength range of about 500 nm to about 570 nm and a peak wavelength in a range of 510 nm to 550 nm (e.g., about 520 nm to about 530 nm); and a third emission region EA3 configured to emit light of a third color (e.g., blue light having a wavelength range of about 430 nm to about 500 nm and a peak wavelength in a range of 440 nm to 480 nm (e.g., about 450 nm to about 460 nm)). A basic color of light emitted from each of the first emission area EA1 , the second emission area EA2 , and the third emission area EA3 may vary according to the embodiment.

[0093] like Figure 5 As shown in the figure, a plurality of first emission areas EA1, a second emission area EA2, and a third emission area EA3 may be arranged in the display area DA in various layouts. For example, the first emission area EA1 and the third emission area EA3 may be spaced apart from each other in the first direction (x-axis direction), and the second emission area EA2 may be spaced apart from the first emission area EA1 and the third emission area EA3 in the second direction (y-axis direction). A plurality of adjacent second emission areas EA2 may be spaced apart in the first direction (x-axis direction). However, it should be understood that the present disclosure is not limited thereto. The arrangement structure of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be changed in one or more suitable ways.

[0094] A plurality of pixels PX including at least one first emission region EA1, at least two second emission regions EA2, and at least one third emission region EA3 disposed adjacent to each other may form a single pixel group PXG. The pixel group PXG may be a minimum unit configured to emit white light. However, the types or kinds and / or quantities of the first emission region EA1, the second emission region EA2, and the third emission region EA3 forming each pixel group PXG may vary according to the embodiment.

[0095] The display device 10 may include light emitting elements ED (eg, first light emitting element ED1, second light emitting element (not shown), and third light emitting element ED3) arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3 (see Figure 6). The first light emitting element ED1, the second light emitting element and the third light emitting element ED3 may include pixel electrodes respectively arranged in the corresponding first emission area EA1, the second emission area EA2 and the third emission area EA3, a common electrode facing the pixel electrode and commonly arranged across the plurality of first emission areas EA1, the second emission area EA2 and the third emission area EA3, and an emission stack ST interposed between the pixel electrode and the common electrode and including at least one emission layer (see Figure 7 ).

[0096] The emission stack ST according to the present embodiment may generate light of the same color in the plurality of first, second, and third emission areas EA1, EA2, and EA3. As an example, the emission stack ST according to the present embodiment may generate white light, but the present disclosure is not limited thereto.

[0097] In the display device 10, the color filter layer 190 (for example, the first color filter 191, the second color filter (not shown), and the third color filter 193) associated with the color of the light output from the first emission area EA1, the second emission area EA2, and the third emission area EA3 (see Figure 6 ) may be arranged to coincide with a plurality of first emission areas EA1, second emission areas EA2, and third emission areas EA3, respectively. This will be described in more detail later.

[0098] The non-emission area NLA may be positioned so that it surrounds the first, second, and third emission areas EA1, EA2, and EA3. The non-emission area NLA can prevent or reduce mixing of light emitted from the first, second, and third emission areas EA1, EA2, and EA3. The separator 155 may overlap the non-emission area NLA.

[0099] Figure 6 is along Figure 5 A cross-sectional view taken along line X1-X1'.

[0100] As described above, the display device 10 may include the display layer DPL and the color filter layer 190, and the display layer DPL may include the substrate 110, the thin film transistor layer 130, the display element layer 150, and the thin film encapsulation layer 170. The substrate 110 has been described above and will not be described again.

[0101] Reference Figure 6 The thin film transistor layer 130 may include a first buffer layer 111, a second buffer layer 113, a thin film transistor TFT, a gate insulator 115, a first interlayer dielectric layer 117, a second interlayer dielectric layer 119, a first connection electrode CNE1, a first through-hole layer 121, a second connection electrode CNE2 and a second through-hole layer 123.

[0102] The first buffer layer 111 may be arranged on the first substrate 110. The first buffer layer 111 may include an inorganic film capable of preventing or reducing the penetration of air or moisture. For example, the first buffer layer 111 may include a plurality of inorganic films alternately stacked on each other. For example, the first buffer layer 111 may be composed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked on each other.

[0103] The second buffer layer 113 may cover the first buffer layer 111. The second buffer layer 113 may include an inorganic film capable of preventing or reducing the penetration of air or moisture. For example, the second buffer layer 113 may include a plurality of inorganic films alternately stacked with each other. The second buffer layer 113 may include the same material as that of the first buffer layer 111.

[0104] In some embodiments, a bottom metal layer may be included between the first buffer layer 111 and the second buffer layer 113 .

[0105] The thin film transistor TFT may be arranged on the second buffer layer 113. The thin film transistor TFT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The active layer ACT of the thin film transistor TFT includes polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. The active layer ACT may overlap with the gate electrode GE in a third direction (z-axis direction) as the thickness direction of the substrate 110, and the source electrode SE and the drain electrode DE may not overlap with the gate electrode GE in the third direction (z-axis direction). The active layer ACT may be defined as a channel region. The source electrode SE and the drain electrode DE may have conductivity by doping ions or impurities into the silicon semiconductor or the oxide semiconductor.

[0106] The gate insulator 115 may be arranged on the thin film transistor TFT. The gate insulator 115 may cover the thin film transistor TFT and the second buffer layer 113, and may insulate the active layer ACT from the gate electrode GE. The gate insulator 115 may be arranged to have substantially the same thickness along the contour of the thin film transistor TFT. The gate insulator 115 may include a first contact hole CNTH1 through which the first connection electrode CNE1 passes. The gate insulator 115 may include an inorganic insulating material and may be composed of a plurality of layers. For example, the gate insulator 115 may be made of an inorganic material such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0107] The gate electrode GE may be disposed on the gate insulator 115. The gate electrode GE may overlap the active layer ACT, with the gate insulator 115 interposed between the gate electrode GE and the active layer ACT. The gate electrode GE may include a metal. For example, the gate electrode GE may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0108] The first interlayer dielectric layer 117 may be disposed on the gate electrode GE. The first interlayer dielectric layer 117 may include an inorganic insulating material and may be composed of a plurality of layers. For example, the first interlayer dielectric layer 117 may be formed as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer dielectric layer 117 may include a first contact hole CNTH1 through which the first connection electrode CNE1 passes.

[0109] A capacitor electrode CAE may be arranged on the first interlayer dielectric layer 117. The capacitor electrode CAE may overlap with the gate electrode GE of the thin film transistor TFT in the third direction (z-axis direction). Since the first interlayer dielectric layer 117 has a set or predetermined dielectric constant, a capacitor can be formed by the capacitor electrode CAE, the gate electrode GE, and the first interlayer dielectric layer 117 arranged between the capacitor electrode CAE and the gate electrode GE. The capacitor electrode CAE may include a metal. For example, the capacitor electrode CAE may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0110] The second interlayer dielectric layer 119 may be positioned on the first interlayer dielectric layer 117 and the capacitor electrode CAE. The second interlayer dielectric layer 119 may include an inorganic insulating material and may be composed of a plurality of layers. For example, the second interlayer dielectric layer 119 may be formed as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer dielectric layer 119 may include a first contact hole CNTH1 through which the first connection electrode CNE1 passes.

[0111] The first connection electrode CNE1 may be disposed on the second interlayer dielectric layer 119. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a first contact hole CNTH1 formed in the first interlayer dielectric layer 117, the second interlayer dielectric layer 119, and the gate insulator 115 to contact the drain electrode DE of the thin film transistor TFT.

[0112] The first through hole layer 121 may cover the first connection electrode CNE1 and the second interlayer dielectric layer 119. The first through hole layer 121 may provide a flat surface throughout the underlying structure. The first through hole layer 121 may include an organic material. As an example, the first through hole layer 121 may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. The first through hole layer 121 may include a second contact hole CNTH2 through which the second connection electrode CNE2 passes.

[0113] The second connection electrode CNE2 may be disposed on the first through hole layer 121. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first pixel electrode AE1, the second pixel electrode (not shown), and the third pixel electrode AE3 of the first light emitting element ED1, the second light emitting element, and the third light emitting element ED3. The second connection electrode CNE2 may contact the first connection electrode CNE1 through a second contact hole CNTH2 formed in the first through hole layer 121.

[0114] The second through hole layer 123 may be disposed on the second connection electrode CNE2 and the first through hole layer 121. The second through hole layer 123 may be disposed on the second connection electrode CNE2 and the first through hole layer 121. Fig. 9 ) exposes a portion of the second connection electrode CNE2 and may be spaced apart from each other. In other words, the second through hole layer 123 may overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3, and may be connected to the pixel electrode through the pixel electrode contact hole ACNTH (see Fig. 9 ) exposes the second connection electrode CNE2. This will be described in more detail later.

[0115] The second via layer 123 may include a recess R123 recessed toward the first via layer 121 in accordance with the non-emission area NLA. The inside of the recess R123 may be filled with the same material as that of the separation member 155. This will be described in more detail later.

[0116] The second via layer 123 may include an organic material. As an example, the second via layer 123 may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. The second contact hole CNTH2 may be filled with the second via layer 123 .

[0117] The display element layer 150 may be positioned on the second through hole layer 123. The display element layer 150 according to the present embodiment may include a pixel auxiliary layer 153, first, second and third light emitting elements ED1, ED3, a separator 155 and a capping layer 159.

[0118] The pixel auxiliary layer 153 may be positioned on the second through hole layer 123 and the second connection electrode CNE2. The pixel auxiliary layer 153 may expose a portion of the second connection electrode CNE2 and may cover the second through hole layer 123 along the same. The pixel auxiliary layer 153 may cover the second through hole layer 123 along the contour with a constant thickness. Therefore, the pixel auxiliary layer 153 may include a step.

[0119] The pixel auxiliary layer 153 may include an inorganic film. For example, the pixel auxiliary layer 153 may be one of silicon nitride, silicon oxide, and silicon oxynitride.

[0120] According to some embodiments, the pixel auxiliary layer 153 may include a first pixel auxiliary layer 153-1, a second pixel auxiliary layer (not shown), and a third pixel auxiliary layer 153-3 that are consistent with the first emission area EA1, the second emission area EA2, and the third emission area EA3. For example, the pixel auxiliary layer 153 may include the first pixel auxiliary layer 153-1 in the first emission area EA1, the second pixel auxiliary layer in the second emission area EA2, and the third pixel auxiliary layer 153-3 in the third emission area EA3.

[0121] The first pixel auxiliary layer 153-1, the second pixel auxiliary layer, and the third pixel auxiliary layer 153-3 overlapping the corresponding first emission area EA1, the second emission area EA2, and the third emission area EA3 may be spaced apart from each other in the non-emission area NLA. In other words, the first pixel auxiliary layer 153-1, the second pixel auxiliary layer, and the third pixel auxiliary layer 153-3 overlapping the corresponding first emission area EA1, the second emission area EA2, and the third emission area EA3 may be spaced apart from each other in the recess R123 of the second through-hole layer 123. The first pixel auxiliary layer 153-1, the second pixel auxiliary layer, and the third pixel auxiliary layer 153-3 spaced apart from each other may include a protruding tip TIP protruding toward the non-emission area NLA from the inside of the recess R123 of the second through-hole layer 123. The protruding tip TIP of the pixel auxiliary layer 153 may guide the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 of the display device 10 to be formed in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, so that they are spaced apart from each other.

[0122] Although for the convenience of explanation, reference has been made to Figure 6The first and third emission areas EA1 and EA3 are described, but the second pixel auxiliary layer overlapping the second emission area EA2 may include the same structure and features as those of the first and third pixel auxiliary layers 153 - 1 and 153 .

[0123] The first, second, and third light emitting elements ED1, ED3 may be positioned on the pixel auxiliary layer 153 and the second connection electrode CNE2, overlapping the first, second, and third emission areas EA1, EA2, and EA3 and the non-emission area NLA.

[0124] The first light emitting element ED1, the second light emitting element, and the third light emitting element ED3 may be respectively aligned with the first emission area EA1, the second emission area EA2, and the third emission area EA3. For example, the first light emitting element ED1 may be arranged in the first emission area EA1, the second light emitting element may be arranged in the second emission area EA2, and the third light emitting element ED3 may be arranged in the third emission area EA3.

[0125] The first light emitting element ED1, the second light emitting element and the third light emitting element ED3 may include a first pixel electrode AE1, a second pixel electrode and a third pixel electrode AE3 respectively corresponding to the first emission area EA1, the second emission area EA2 and the third emission area EA3, and may include a common emission material layer EL and a common electrode CE. Although the first light emitting element ED1 and the third light emitting element ED3 are shown and described in the drawings for convenience of explanation, the second light emitting element may include the same structure and features.

[0126] The first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may be arranged on the second connection electrode CNE2 and the pixel auxiliary layer 153 in the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NLA. Since the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 are in contact with the second connection electrode CNE2 exposed by the pixel auxiliary layer 153 and the second through hole layer 123, they may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0127] The first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may be respectively aligned with the first emission area EA1, the second emission area EA2, and the third emission area EA3. For example, the first pixel electrode AE1 may be arranged in the first emission area EA1, the second pixel electrode may be arranged in the second emission area EA2, and the third pixel electrode AE3 may be arranged in the third emission area EA3.

[0128] The first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may be a metal having high conductivity. For example, the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may be a metal having high conductivity. 2 O 3 ) and a stacked structure of a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. The layer with a higher work function may be arranged on a layer higher than the reflective material layer, so that it can be closer to the emission material layer EL. For example, the first pixel electrode AE1, the second pixel electrode and the third pixel electrode AE3 may have, but are not limited to, a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag and ITO / Ag / ITO.

[0129] According to some embodiments, the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 in the corresponding first emission area EA1, the second emission area EA2, and the third emission area EA3 may be spaced apart from each other in the non-emission area NLA. As described above, the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 of the display device 10 may be arranged in the corresponding first emission area EA1, the second emission area EA2, and the third emission area EA3 so that they are spaced apart from each other by the protruding tip TIP included in the pixel auxiliary layer 153. Therefore, during the manufacturing process, the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 of the display device 10 may be spaced apart from each other in the corresponding first emission area EA1, the second emission area EA2, and the third emission area EA3 without a mask. In some embodiments, the second pixel electrode may have the same structure and features as those of the first pixel electrode AE1 and the third pixel electrode AE3.

[0130] According to some embodiments, a pixel electrode pattern AEP consistent with the non-emission area NLA may be arranged in the recess R123 of the second through hole layer 123. Since the pixel auxiliary layer 153 includes a protruding tip TIP, the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 are disconnected in the non-emission area NLA, and the pixel electrode pattern AEP as a residue of the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 is formed accordingly. Therefore, the pixel electrode pattern AEP may be spaced apart from the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 in the non-emission area NLA.

[0131] The separator 155 may be positioned on the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 in the non-emission area NLA. The separator 155 may have an overhang structure in which the upper surface is larger than the lower surface. Therefore, the side surface of the separator 155 may have an inverted tapered shape. However, it should be understood that the present disclosure is not limited thereto. The side surface of the separator 155 may be formed to be perpendicular (e.g., substantially perpendicular or orthogonal) to the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3.

[0132] The separator 155 may define the first, second and third emission areas EA1, EA2 and EA3 and the non-emission area NLA of the display device 10, and may assist the deposition of the charge generation layer CGL included in the emission material layer EL so that it is deposited separately. This will be described in more detail later.

[0133] The separator 155 may include an organic material. As an example, the separator 155 may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin. However, it should be understood that the present disclosure is not limited thereto. The separator 155 may include any organic material as long as it can be used for photolithography.

[0134] The emission material layer EL may be arranged on the separator 155 and the first pixel electrode AE1, the second pixel electrode AE3. The emission material layer EL according to the present embodiment may be arranged across the first emission area EA1, the second emission area EA2, the third emission area EA3 and the non-emission area NLA. It should be noted that some elements included in the emission material layer EL may be separated by the separator 155, which will be described in more detail later.

[0135] The common electrode CE may be arranged on the emission material layer EL. The common electrode CE according to the present embodiment may be a common layer arranged across the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NLA. The common electrode CE may include a transparent conductive material so that the light generated in the emission material layer EL can be emitted. The common electrode CE may receive a common voltage or a low-level voltage. When the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 receive a voltage equal to the data voltage and the common electrode CE receives a low-level voltage, a potential difference is formed between the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 and the common electrode CE, so that the emission material layer EL can emit light.

[0136] The common electrode CE may be formed of a transparent conductive material (TCP) such as ITO and IZO capable of transmitting light or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag). When the common electrode CE is formed of a semi-transmissive conductive material (e.g., a semi-transmissive metal material), light extraction efficiency can be improved by utilizing a microcavity.

[0137] The capping layer 159 may be disposed on the common electrode CE. The capping layer 159 may be a common layer disposed across the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NLA. The capping layer 159 can prevent or reduce the first light emitting element ED1, the second light emitting element, and the third light emitting element ED3 from being damaged by external air, and can prevent or reduce peeling of the first light emitting element ED1, the second light emitting element, and the third light emitting element ED3 and the common electrode CE.

[0138] The capping layer 159 may include an inorganic material. As an example, the capping layer 159 may include at least one of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0139] The thin film encapsulation layer 170 may be disposed on the display element layer 150. The thin film encapsulation layer 170 may include at least one inorganic film to prevent or reduce the penetration of oxygen or moisture into the display element layer 150. In some embodiments, the thin film encapsulation layer 170 may include at least one organic film to protect the display element layer 150 from particles such as dust. The thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175. The first encapsulation layer 171 may be disposed on the common electrode CE, the second encapsulation layer 173 may be disposed on the first encapsulation layer 171, and the third encapsulation layer 175 may be disposed on the second encapsulation layer 173.

[0140] The first encapsulation layer 171 and the third encapsulation layer 175 may be inorganic films. For example, each of the first encapsulation layer 171 and the third encapsulation layer 175 may be composed of a plurality of films in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked on each other.

[0141] The second encapsulation layer 173 may be an organic film. As an example, the second encapsulation layer 173 may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0142] A color filter protection layer 185 may be positioned on the thin film encapsulation layer 170. The color filter protection layer 185 may be arranged or provided to completely span the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NLA. The color filter protection layer 185 is capable of protecting the color filter layer 190. The color filter protection layer 185 may be a single layer including an inorganic material or an organic material, or may include a plurality of layers including an inorganic material and an organic material.

[0143] For example, the inorganic material included in the color filter protection layer 185 may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride, etc. The organic material included in the color filter protection layer 185 may include at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0144] The color filter layer 190 may include a first color filter 191, a second color filter, and a third color filter 193 associated with the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. For example, the color filter layer 190 may include a first color filter 191 in the first emission area EA1, a second color filter in the second emission area EA2, and a third color filter 193 in the third emission area EA3.

[0145] As described above, the emission material layer EL herein may be arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3, and may be configured to emit light of the same color. Light of the same color output from the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be converted into light of different colors by the color filter layer 190 overlapping the first emission area EA1, the second emission area EA2, and the third emission area EA3 to be emitted to the outside of the display device 10.

[0146] According to some embodiments, the first color filter 191 may selectively transmit light of the first color. For example, the first color filter 191 may be configured to transmit light of the first color (e.g., red light) and block or reduce or may be configured to absorb light of another color (e.g., green light and blue light). According to an embodiment of the present disclosure, the first color filter 191 may be a red color filter and may include a red colorant. The light (e.g., white light) emitted from each first light-emitting element ED1 may pass through the first color filter 191 and exit to the outside. Therefore, the light of the first color (e.g., red light) may exit from the first emission area EA1.

[0147] The second color filter may selectively transmit light of the second color. For example, the second color filter may be configured to transmit light of the second color (e.g., green light), and may block or reduce or be configured to absorb light of the first color (e.g., red light) and light of the third color (e.g., blue light). According to an embodiment, the second color filter may be a green color filter and may include a green colorant. The light (e.g., white light) emitted from each second light-emitting element may pass through the second color filter and be emitted to the outside. Therefore, the light of the second color (e.g., green light) may be emitted from the second emission area EA2.

[0148] The third color filter 193 may selectively transmit light of a third color. For example, the third color filter 193 may selectively transmit light of a third color (e.g., blue light), and may block or reduce or absorb light of a first color (e.g., red light) and light of a second color (e.g., green light).

[0149] According to an embodiment, the third color filter 193 may be a blue color filter and may include a blue colorant such as a blue dye and a blue pigment. The light (e.g., white light) emitted from each third light emitting element ED3 may pass through the third color filter 193 and exit to the outside. Therefore, the light of the third color (e.g., blue light) may be emitted from the third emission area EA3.

[0150] According to an embodiment, the first color filter 191, the second color filter and the third color filter 193 may include a color filter pattern 190p (e.g., a first color filter 191p, a second color filter pattern (not shown) and a third color filter pattern 193p) overlapping each other in the non-emission area NLA. The color filter pattern 190p may be around the first emission area EA1, the second emission area EA2 and the third emission area EA3 (e.g., may surround the first emission area EA1, the second emission area EA2 and the third emission area EA3) to prevent or reduce color mixing between the first emission area EA1, the second emission area EA2 and the third emission area EA3. The color filter pattern 190p can also be used as a light blocking pattern and block or reduce the transmission of light. The color filter pattern 190p can be formed by adjacent color filter layers 190 in one or more suitable configurations. For example, as Figure 6 As shown in , when the first color filter 191 and the third color filter 193 are adjacent to each other, the color filter pattern 190p may include a stacked structure of the first color filter pattern 191p and the third color filter pattern 193p. Therefore, the color filter pattern 190p may be formed in one or more suitable configurations. Although the first color filter 191 and the third color filter 193 are shown and described in the drawings for convenience of explanation, the second color filter may include the same or similar structures and features. Similarly, the second color filter pattern may include the same or similar structures and features as the first color filter pattern 191p and the third color filter pattern 193p.

[0151] Figure 7 and Figure 8 It is shown Figure 6 A cross-sectional view of the emission material layer EL.

[0152] Reference Figure 7 and Figure 8 According to the present embodiment, the first light emitting element ED1, the second light emitting element and the third light emitting element ED3 may include a first pixel electrode AE1, a second pixel electrode AE3 and a common electrode CE facing each other in a third direction (z-axis direction), and an emission stack ST provided between the first pixel electrode AE1, the second pixel electrode AE3 and the common electrode CE. The emission stack ST may include a high molecular or low molecular organic material configured to emit light of a set or predetermined color. In addition to various organic materials, the emission stack ST may also include a metal-containing compound such as an organic metal compound, an inorganic material such as a quantum dot, etc. Although a three-series structure including three emission stacks ST (i.e., a first emission stack ST1, a second emission stack ST2 and a third emission stack ST3) is shown in the drawings, the present disclosure is not limited thereto.

[0153] The emission stack ST may include at least one emission layer EML. For example, the first emission stack ST1 may include a first emission layer EML1, the second emission stack ST2 may include a second emission layer EML2 consistent with the first emission layer EML1, and the third emission stack ST3 may include a third emission layer EML3 consistent with the first emission layer EML1 and the second emission layer EML2. For example, the first emission layer EML1 may be configured to emit one of the light of the first color, the light of the second color, and the light of the third color, the second emission layer EML2 may be configured to emit one of the light of the first color, the light of the second color, and the light of the third color, and the third emission layer EML3 may be configured to emit one of the light of the first color, the light of the second color, and the light of the third color. According to some embodiments, the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may be configured to emit the same color of light, and the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may be configured to emit different colors of light. For example, the light of the first color may be red light, the light of the second color may be green light, and the light of the third color may be blue light, but the present disclosure is not limited thereto.

[0154] Reference Figure 8According to another embodiment, the first emission layer EML1 may be configured to emit a plurality of lights among the light of the first color, the light of the second color, the light of the third color, and the light of the fourth color, the second emission layer EML2 may be configured to emit a plurality of lights among the light of the first color, the light of the second color, the light of the third color, and the light of the fourth color, and the third emission layer EML3 may be configured to emit a plurality of lights among the light of the first color, the light of the second color, the light of the third color, and the light of the fourth color. For example, when the second emission layer EML2 emits a plurality of lights, the second emission layer EML2 may be composed of a plurality of layers (such as a first sub-emission layer EML2-1 and a second sub-emission layer EML2-2). For example, the light of the first color may be red light, the light of the second color may be green light, the light of the third color may be blue light, and the light of the fourth color may be yellow light, but the present disclosure is not limited thereto.

[0155] Each emission layer EML according to the present embodiment may include a host and a dopant. The emission layer EML may be formed by using a phosphorescent or fluorescent material as a dopant in a host material. The material of the host is not particularly limited herein as long as it is commonly used, and the material of the host may include Alq3 (tris(8-hydroxyquinoline)aluminum), CBP (4,4'-bis(N-carbazolyl)-1,1'-biphenyl), PVK (poly(n-vinylcarbazole)), ADN (9,10-di(naphthalene-2-yl)anthracene), TCTA (4,4',4"-tri(carbazol-9-yl)-triphenylamine), TPBi (1,3,5-tri(N-phenylbenzimidazol-2-yl)benzene), TBADN (3-tert-butyl-9,10-di(naphthalene-2-yl)anthracene), DSA (distyrylanthracene), CDBP (4,4'-bis(9-carbazolyl)-2,2"-dimethyl-biphenyl), MADN (2-methyl-9,10-bis(naphthalene-2-yl)anthracene), and the like. The color of light emitted from the emission layer EML may be determined by a combination of the host material and the dopant material.

[0156] According to an embodiment of the present disclosure, a blue emission layer configured to emit blue light may include a fluorescent material including one selected from the group consisting of spiro-DPVBi, spiro-6P, DSB (distyrylbenzene), DSA (distyrylarylene), PFO (polyfluorene) polymer and PPV (poly(p-phenylene vinylene) polymer. For example, the dopant material included in the blue emission layer may be a metal complex such as (4,6-F2ppy)2Irpic or an organic metal complex. In some embodiments, the blue emission layer may include a phosphorescent material including an organic metal complex such as (4,6-F2ppy)2Irpic.

[0157] According to an embodiment of the present disclosure, a green emission layer configured to emit green light may include a fluorescent material including Alq3 (tris(8-hydroxyquinoline)aluminum). For example, the dopant material included in the green emission layer may be a metal complex or an organic metal complex such as Ir(ppy)3 (fac-tris(2-phenylpyridine)iridium).

[0158] According to an embodiment of the present disclosure, a red emission layer configured to emit red light may include a fluorescent material including PBD:Eu(DBM)3(benzene)(tris(dibenzoylmethane)benzopyrroline europium) or perylene. For example, the dopant material included in the red emission layer may be a metal complex or an organic metal complex such as PIQIr(acac)(bis(1-phenylisoquinoline)iridium acetylacetonate), PQIr(acac)(bis(1-phenylquinoline)iridium acetylacetonate), PQIr(tris(1-phenylquinoline)iridium) and PtOEP(platinum octaethylporphyrin).

[0159] The emission stack ST may further include at least one intermediate layer overlapping the at least one emission layer EML. As an example, the intermediate layer may include a hole injection layer HIL, a hole transport layer HTL, and an electron transport layer ETL. Figure 7 and Figure 8 As shown in , according to some embodiments, the hole transport layer HTL may combine the roles of the hole transport layer HTL and the hole injection layer HIL.

[0160] The hole transport layer HTL may be positioned close to the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3, may facilitate the transport of holes, and may include a hole transport material. The hole transport material may include, but is not limited to, carbazole derivatives such as N-phenylcarbazole and polyvinylcarbazole, fluorene derivatives, triphenylamine derivatives such as TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1-biphenyl]-4,4'-diamine) and TCTA (4,4',4"-tri(N-carbazolyl)triphenylamine), NPB (N,N'-di(naphthalene-1-yl)-N,N'-diphenylbenzidine), TAPC (4,4'-cyclohexylenebis[N,N-bis(4-methylphenyl)benzylamine]), etc. This may also be applied to the hole transport layer HTL included in the second emission stack ST2 and the third emission stack ST3.

[0161] In some embodiments, the electron transport layer ETL may be positioned close to the common electrode CE, may facilitate the transport of electrons, and may include an electron transport material. According to some embodiments, an electron injection layer (not shown) may be arranged between the common electrode CE and the electron transport layer ETL. For example, the electron transport material may include, but is not limited to, an electron transparent material such as Alq3 (tris (8-hydroxyquinolyl) aluminum), TPBi (1,3,5-tris (1-phenyl-1H-benzo [d] imidazole-2-yl) phenyl), BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen (4,7-diphenyl-1,10-phenanthroline), TAZ (3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole) , NTAZ (4-(naphthalene-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD (2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), BAlq (bis(2-methyl-8-quinolyl-N1,O8)-(1,1'-biphenyl-4-oleate)aluminum), Bebq2 (beryllium bis(benzoquinoline-10-oleate), ADN (9,10-di(naphthalene-2-yl)anthracene) and mixtures thereof.

[0162] The charge generation layer CGL may be positioned between the plurality of emission stacks ST.

[0163] The charge generation layer CGL may be a functional layer that controls charge balance between the plurality of emission stacks ST. Therefore, the charge generation layer CGL may provide charges to each of the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3, thereby increasing the light emitting efficiency of the first light emitting element ED1, the second light emitting element, and the third light emitting element ED3 and reducing the driving voltage.

[0164] The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. As an example, the negative charge generation layer nCGL may be disposed on each of the plurality of emission stacks ST, and then the positive charge generation layer pCGL may be disposed on the negative charge generation layer nCGL. The charge generation layer CGL may include a first charge generation layer CGL1 positioned between the first emission stack ST1 and the second emission stack ST2 and a second charge generation layer CGL2 positioned between the second emission stack ST2 and the third emission stack ST3.

[0165] The negative charge generation layer nCGL included in the first charge generation layer CGL1 (for example, may include a conductive material or be a conductor) may be arranged to contact the first emission stack ST1, and may supply electrons to the first emission layer EML1 (and, for example, the first emission layer may not include a conductive material or is not a conductor). The negative charge generation layer nCGL may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. According to an embodiment, the negative charge generation layer nCGL may include an arylamine-based organic compound such as α-NPD, 2-TNATA, TDATA, MTDATA, sprio-TAD, and sprio-NPB.

[0166] The positive charge generation layer pCGL included in the first charge generation layer CGL1 may be arranged to contact the second emission stack ST2, and may supply holes to the second emission layer EML2. The positive charge generation layer pCGL may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. According to an embodiment, the positive charge generation layer pCGL may include a charge generation compound made of a metal, a metal oxide, a carbide, a fluoride, or a mixture thereof. For example, the metal may be cesium (Cs), molybdenum (Mo), vanadium (V), titanium (Ti), tungsten (W), barium (Ba), or lithium (Li). In some embodiments, for example, the oxide, carbide, and fluoride of the metal may be Re 2 O 7 、MoO 3 、V 2 O 5 , WO 3 、TiO 2 , Cs 2 CO 3 , BaF, LiF or CsF.

[0167] In some embodiments, the negative charge generation layer nCGL included in the second charge generation layer CGL2 may contact the second emission stack ST2 and supply electrons to the second emission layer EML2, and the positive charge generation layer pCGL included in the second charge generation layer CGL2 may contact the third emission stack ST3 and supply holes to the third emission layer EML3. No other redundant description will be provided.

[0168] Fig. 9 It is shown Figure 6 An enlarged cross-sectional view of the periphery of the first light emitting element ED1 in the first emission area EA1.

[0169] Reference Fig. 9, the second through hole layer 123 in the first emission area EA1 may include a first portion 123A and a second portion 123B. The first portion 123A and the second portion 123B of the second through hole layer 123 may be formed when the second through hole layer 123 is partially penetrated by the pixel electrode contact hole ACNTH. Therefore, the first portion 123A and the second portion 123B of the second through hole layer 123 may be spaced apart from each other while exposing the second connection electrode CNE2. The first portion 123A of the second through hole layer 123 may be positioned on opposite sides in the first direction (x-axis direction) in the first emission area EA1, and the second portion 123B of the second through hole layer 123 may be positioned on one side positioned in the first direction (x-axis direction) in the first emission area EA1.

[0170] The first pixel auxiliary layer 153-1 in the first emission area EA1 may include a first portion 153-1A and a second portion 153-1B. The first portion 153-1A and the second portion 153-1B of the first pixel auxiliary layer 153-1 may be formed when the first pixel auxiliary layer 153-1 is penetrated by the pixel electrode contact hole ACNTH. Therefore, the first portion 153-1A and the second portion 153-1B of the first pixel auxiliary layer 153-1 may be spaced apart from each other while exposing the second connection electrode CNE2. The first portion 153-1A of the first pixel auxiliary layer 153-1 may be positioned on opposite sides in the first direction (x-axis direction) in the first emission area EA1, and the second portion 153-1B of the first pixel auxiliary layer 153-1 may be positioned on one side in the first direction (x-axis direction) in the first emission area EA1. In some embodiments, the first portion 153 - 1A of the first pixel auxiliary layer 153 - 1 may be positioned on the first portion 123A of the second via layer 123 , and the second portion 153 - 1B of the first pixel auxiliary layer 153 - 1 may be positioned on the second portion 123B of the second via layer 123 .

[0171] The first pixel electrode AE1 in the first emission area EA1 may cover the first portion 153-1A and the second portion 153-1B of the first pixel auxiliary layer 153-1, and may cover the second connection electrode CNE2 exposed by the first pixel auxiliary layer 153-1 and the second through-hole layer 123. The first pixel electrode AE1 may extend on the first portion 153-1A of the first pixel auxiliary layer 153-1, may contact the exposed portion of the second connection electrode CNE2, and may extend from the exposed portion of the second connection electrode CNE2 to the exposed portion of the second portion 153-1B of the first pixel auxiliary layer 153-1.

[0172] In the first emission area EA1, the emission material layer EL, the common electrode CE, the capping layer 159, the first encapsulation layer 171 and the second encapsulation layer 173 may be stacked in this order on the first pixel electrode AE1 in the third direction (z-axis direction). No other redundant description will be provided.

[0173] Fig.10 yes Figure 6 An enlarged cross-sectional view of area A. Fig.11 yes Fig.10 An enlarged cross-sectional view of area C1.

[0174] Reference Fig.10 and Fig.11 As described above, the second through-hole layer 123 of the display device 10 may include a recess R123 in the non-emission area NLA, and the pixel auxiliary layer 153 of the display device 10 may include a first pixel auxiliary layer 153-1 consistent with the first emission area EA1 and a third pixel auxiliary layer 153-3 consistent with the third emission area EA3. The first pixel auxiliary layer 153-1 and the third pixel auxiliary layer 153-3 may be spaced apart from each other in the non-emission area NLA.

[0175] According to some embodiments, the recess R123 and the pixel auxiliary layer 153 included in the display device 10 may be formed via a dry etching process during a manufacturing process. For example, the pixel auxiliary layer 153 may be deposited on the entire surface spanning the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NLA, and may then be spaced apart from each other in the non-emission area NLA by a dry etching process during the manufacturing process. Therefore, the pixel auxiliary layer 153 may include a first pixel auxiliary layer 153-1, a second pixel auxiliary layer, and a third pixel auxiliary layer 153-3 that are respectively consistent with the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0176] In some embodiments, the second via layer 123 may be etched simultaneously (eg, synchronously) with the pixel auxiliary layer 153. Thus, the second via layer 123 may include a recess R123 recessed toward the first via layer 121. For example, the recess R123 may be isotropically etched via a dry etching process.

[0177] like Fig.11 As shown in FIG. , the recess R123 of the second via layer 123 may include (eg, simultaneously include) both a side surface rc and a bottom surface rb formed through a dry etching process.

[0178] According to the present embodiment, the pixel auxiliary layer 153 may include a material having a lower dry etching rate than the second through-hole layer 123, and thus the pixel auxiliary layer 153 may include a protruding tip TIP from the side surface rc of the recess R123 in the first direction (x-axis direction) in the non-emission area NLA. In other words, the side surface rc of the recess R123 may be recessed in the first direction (x-axis direction) than the protruding tip TIP of the pixel auxiliary layer 153. Therefore, an undercut portion UC may be formed between the protruding tip TIP included in the pixel auxiliary layer 153 and the side surface rc of the recess R123. In some embodiments, the protruding tip TIP is on one side of the first pixel auxiliary layer 153-1 and extends from the side surface rc of the recess R123 in the non-emission area NLA in the first direction (e.g., the x-axis direction). More specifically, for example, the protruding tip TIP of the first pixel auxiliary layer 153-1 may include a side surface 1c and a bottom surface 1b, and the protruding tip TIP of the third pixel auxiliary layer 153-3 may include a side surface 3c and a bottom surface 3b. In the non-emission area NLA, the bottom surface 1b of the first pixel auxiliary layer 153-1 and the bottom surface 3b of the third pixel auxiliary layer 153-3 may face the recess R123, and the side surface 1c of the first pixel auxiliary layer 153-1 and the side surface 3c of the third pixel auxiliary layer 153-3 may face each other.

[0179] According to the present embodiment, during the process of manufacturing the display device 10, subsequent processes may be performed using the empty recess R123 of the second via layer 123. The first, second, and third pixel electrodes AE1, AE3 may be formed in the display device 10 after the dry etching process.

[0180] As described above, since the pixel auxiliary layer 153 includes the protruding tip TIP in the display device 10, the pixel electrode may include the first pixel electrode AE1 consistent with the first emission area EA1 and the third pixel electrode AE3 consistent with the third emission area EA3. The first pixel electrode AE1 and the third pixel electrode AE3 may be spaced apart from each other by the respective protruding tips TIP of the pixel auxiliary layer 153.

[0181] For example, in the deposition process of the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 included in the display device 10, the material for forming the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may not be deposited in a third direction (z-axis direction) that is perpendicular (e.g., substantially perpendicular or orthogonal) to the substrate 110, but may be deposited in a direction that is inclined relative to the substrate 110 (i.e., a direction between the first direction (x-axis direction) and the third direction (z-axis direction)). By doing so, the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may be deposited on the side surface 1c and the side surface 3c included in the protruding tip TIP of the pixel auxiliary layer 153, and may be partially deposited inside the recess R123 included in the second through hole layer 123. It should be noted that the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may not contact the bottom surface 1b and the bottom surface 3b included in the protruding tip TIP of the pixel auxiliary layer 153.

[0182] Portions of the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 deposited inside the recess R123 of the second through-hole layer 123 may form a pixel electrode pattern AEP spaced apart from the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3. The pixel electrode pattern AEP may be positioned inside the recess R123 in the non-emission area NLA. For example, the pixel electrode pattern AEP may contact the bottom surface rb of the recess R123.

[0183] Although only the first emission area EA1, the non-emission area NLA and the third emission area EA3 have been described with reference to the accompanying drawings for the convenience of explanation, the second pixel auxiliary layer in the second emission area EA2 may have the same structure and characteristics as the first pixel auxiliary layer 153-1 in the first emission area EA1 and the third pixel auxiliary layer 153-3 in the third emission area EA3, and the second pixel electrode in the second emission area EA2 may have the same structure and characteristics as the first pixel electrode AE1 and the third pixel electrode AE3.

[0184] The separator 155 may be positioned on the first pixel electrode AE1 , the second pixel electrode AE3 , and the third pixel electrode AE3 in the non-emission area NLA.

[0185] like Fig.11As shown in , the separator 155 included in the display device 10 may include a top surface 155a and a side surface 155c. The tilt angle θ1 formed by the top surface 155a and the side surface 155c of the separator 155 may be, but is not limited to, an acute angle. According to some embodiments, the tilt angle θ1 formed by the top surface 155a and the side surface 155c of the separator 155 may include a right angle. The tilt angle θ1 of the separator 155 according to the present embodiment can be adjusted by adjusting the exposure amount of the photolithography of the display device 10.

[0186] According to some embodiments, the separator 155 may define first, second, and third emission areas EA1, EA2, and EA3 and a non-emission area NLA of the display device 10, and may also assist in disconnecting the charge generation layer CGL included in the emission material layer EL.

[0187] Generally, when the first pixel electrode AE1, the second pixel electrode AE3, and the charge generation layer CGL having a conductive property are connected rather than disconnected, a leakage current defect may occur in the display device 10. For this reason, it is important for the display device 10 that the first pixel electrode AE1, the second pixel electrode AE3, and the charge generation layer CGL having a conductive property (e.g., being a conductor) are disconnected or separated.

[0188] In the display device 10 according to the present embodiment, the charge generation layer CGL may be disconnected by the shape of the separator 155 in the first emission area EA1, the second emission area EA2, and the third emission area EA3. In some embodiments, since the pixel auxiliary layer 153 includes the protruding tip TIP in the display device 10 according to the present embodiment, the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may be disconnected in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. Therefore, the leakage current defect can be solved in the display device 10 according to the present embodiment.

[0189] In some embodiments, the display device 10 according to the present embodiment can ensure the largest first emission area EA1, second emission area EA2, and third emission area EA3 because the separator 155 is formed with a minimum area. In this way, the display device 10 according to the present embodiment can be implemented with high resolution.

[0190] According to some embodiments, the separator 155 may be consistent with the recess R123 included in the second via layer 123. As described above, a subsequent process may be performed through the empty recess R123 of the second via layer 123. Therefore, during the process of forming the separator 155, the recess R123 of the second via layer 123 may be filled with a material forming the separator 155. Therefore, the inside of the recess R123 and the separator 155 may be filled with the same material and connected to each other.

[0191] Fig.12 yes Fig.11 An enlarged cross-sectional view of area C3.

[0192] Reference Fig.10 and Fig.12 , the first emission stack ST1, the first charge generation layer CGL1, the second emission stack ST2, and the second charge generation layer CGL2 included in the emission material layer EL may be disconnected due to the separator 155, and thus may not cover the top surface 155a of the separator 155. Therefore, the emission pattern ELp may be formed on the side surface 155c and the top surface 155a of the separator 155. The emission pattern ELp may include a first stack pattern S1p, a first charge pattern C1p, a second stack pattern S2p, and a second charge pattern C2p.

[0193] For example, the first emission stack ST1 may be positioned on the first pixel electrode AE1 and may be in contact with the side surface 155c of the separator 155. The first emission stack ST1 may include a first stack pattern S1p that is separated due to the separation 155 not being connected. The first stack pattern S1p may include the same material as that of the first emission stack ST1. The first stack pattern S1p may be spaced apart from the first emission stack ST1 and in contact with the side surface 155c and the top surface 155a of the separator 155. The first stack pattern S1p may be formed as a result of the first emission stack ST1 not being formed on the entire surface but being separated from each other due to the shape of the separator 155.

[0194] The first charge generation layer CGL1 may be positioned on the first emission stack ST1 and may be in contact with the side surface 155c of the separator 155. The first charge generation layer CGL1 may include first charge patterns C1p that are spaced apart from each other by the separator 155 without being connected. The first charge pattern C1p may include the same material as that of the first charge generation layer CGL1. The first charge pattern C1p may be positioned on the side surface 155c and the top surface 155a of the separator 155 and spaced apart from the first charge generation layer CGL1, and the first charge pattern C1p may be positioned to contact the first stack pattern S1p. The first charge pattern C1p may be formed as a result of the first charge generation layer CGL1 not being formed on the entire surface but being separated from each other due to the shape of the separator 155.

[0195] The second emission stack ST2 may be positioned on the first charge generation layer CGL1 and may be in contact with the side surface 155c of the separator 155. The second emission stack ST2 may include a second stack pattern S2p that is separated due to the separation member 155 not being connected. The second stack pattern S2p may include the same material as that of the second emission stack ST2. The second stack pattern S2p may be spaced apart from the second emission stack ST2 and may be positioned on the side surface 155c and the top surface 155a of the separator 155, and the second stack pattern S2p may be positioned to contact the first charge pattern C1p. The second stack pattern S2p may be formed as a result of the second emission stack ST2 that is not formed on the entire surface but is separated from each other due to the shape of the separator 155.

[0196] The second charge generation layer CGL2 may be positioned on the second emission stack ST2 and may be in contact with the side surface 155c of the separator 155. The second charge generation layer CGL2 may include second charge patterns C2p that are spaced apart from each other without being connected by the separator 155. The second charge pattern C2p may include the same material as that of the second charge generation layer CGL2. The second charge pattern C2p may be spaced apart from the second charge generation layer CGL2 and may be positioned on the side surface 155c and the top surface 155a of the separator 155, and the second charge pattern C2p may be positioned to contact the second stack pattern S2p. The second charge pattern C2p may be formed as a result of the second charge generation layer CGL2 that is not formed on the entire surface but is separated from each other due to the shape of the separator 155.

[0197] The third emission stack ST3 included in the emission material layer EL may be positioned on the second charge generation layer CGL2 and the second charge pattern C2p, and the third emission stack ST3 may be positioned to completely cover the second charge generation layer CGL2 and the second charge pattern C2p. In other words, the third emission stack ST3 may not be disconnected by the separator 155, but may be positioned on the entire surface spanning the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NLA.

[0198] like Fig.12 As shown in FIG. 1 , the side surface 155c of the separator 155 may include: a first portion c1 in contact with the first emission stack ST1, the first charge generation layer CGL1, the second emission stack ST2, and the second charge generation layer CGL2 of the emission material layer EL; a second portion c2 in contact with the first stack pattern S1p of the emission pattern ELp; and a third portion c3 in contact with the third emission stack ST3. The first portion c1 and the second portion c2 included in the side surface 155c of the separator 155 may be spaced apart from each other by the third portion c3.

[0199] Although the emission material layer EL includes the first emission stack ST1, the first charge generation layer CGL1, the second emission stack ST2, the second charge generation layer CGL2, and the third emission stack ST3 in the drawings for convenience of explanation, the present disclosure is not limited thereto. The emission material layer EL of the display device 10 may include any structure including at least two emission stacks ST and at least one charge generation layer CGL positioned between the emission stacks ST, and in such a structure, the charge generation layer CGL is separated by the separator 155. The last emission stack ST positioned toward the common electrode CE may not be disconnected by the separator 155, but may cover the entire surface of the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NLA.

[0200] Fig.13 1 is a plan view showing the separator 155 and the pixel electrode pattern AEP in the display area DA. Fig.15 yes Figure 4 An enlarged plan view of region V.

[0201] Reference Fig.13, the separator 155 may have a grid pattern in a plan view. The separator 155 may define the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NLA in a plan view, and the separator 155 may surround the first emission area EA1, the second emission area EA2, and the third emission area EA3 in a plan view. This may mean that the separator 155 surrounds the first light-emitting element ED1, the second light-emitting element, and the third light-emitting element ED3 that overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. That is, the separator 155 may directly transmit the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 in a plan view.

[0202] In some embodiments, in a plan view, a plurality of structures arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be positioned inside the separator 155. For example, in a plan view, a pixel electrode contact hole ACNTH that coincides with the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be positioned inside the separator 155. In other words, in a plan view, a pixel electrode contact hole ACNTH that coincides with the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be completely surrounded by the separator 155.

[0203] In some embodiments, the pixel electrode pattern AEP may be formed in the non-emission area NLA in a mesh pattern in a plan view. In other words, the pixel electrode pattern AEP may overlap the separator 155 in a plan view.

[0204] Fig.14 is a plan view showing a layout of separators 155 in the display area DA according to another embodiment.

[0205] Reference Fig.14, like the display device 10, the separator 155 in the display device 11 is arranged in the non-emission area NLA and surrounds the first emission area EA1, the second emission area EA2, and the third emission area EA3 in a plan view, but unlike the display device 10, the separator 155 surrounds the corresponding first emission area EA1, the second emission area EA2, and the third emission area EA3 individually in a plan view. As an example, the separator 155 around the first emission area EA1 (e.g., surrounding the first emission area EA1) may be spaced apart from the separator 155 around the third emission area EA3 (e.g., surrounding the third emission area EA3) and the separator 155 around the second emission area EA2 (e.g., surrounding the second emission area EA2). In other words, the separator 155 included in the display device 11 may surround the first light-emitting element ED1, the second light-emitting element, and the third light-emitting element ED3 in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. The separators 155 around the corresponding first light emitting element ED1, the second light emitting element, and the third light emitting element ED3 (e.g., surrounding the corresponding first light emitting element ED1, the second light emitting element, and the third light emitting element ED3) may be spaced apart from each other. In some embodiments, in the cross-sectional view, the display device 11 may have a plurality of separators 155 spaced apart from each other in the non-emission area NLA. For example, in the display device 11 according to the embodiment, two separators 155 may be positioned adjacent to the corresponding first emission area EA1, the second emission area EA2, and the third emission area EA3 in the non-emission area NLA.

[0206] The first emission area EA1, the second emission area EA2, and the third emission area EA3 of the display device 11 according to the embodiment may be defined by a separation member 155 adjacent to the adjacent first emission area EA1, the second emission area EA2, and the third emission area EA3. Fig.15 The pixel electrode pattern AEP formed in the display area DA in a grid pattern in a plan view may be connected to the above Figure 4 Therefore, the pixel electrode pattern AEP included in the display device 11 does not remain as a floating electrode and can be electrically stable.

[0207] Fig.16 yes Figure 6 An enlarged cross-sectional view of another example of region A. Fig.17 According to another embodiment Fig.16 An enlarged cross-sectional view of region E of FIG.

[0208] Reference Fig.16 and Fig.17, the second through hole layer 123 of the display device 30 may include a recess R123 in the second through hole layer 123 in the non-emission area NLA, and the recess R123 of the display device 30 may include (e.g., simultaneously include) both the side surface rc and the bottom surface rb. The side surface rc of the recess R123 may be more recessed in the first direction (x-axis direction) than the protruding tip TIP of the pixel auxiliary layer 153. In some embodiments, the bottom surface rb of the recess R123 may contact the pixel electrode pattern AEP.

[0209] The pixel auxiliary layer 153 of the display device 30 may include a first pixel auxiliary layer 153-1, a second pixel auxiliary layer, and a third pixel auxiliary layer 153-3, respectively arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3. The pixel auxiliary layer 153 of the display device 30 may include a protruding tip TIP protruding from the side surface rc of the recess R123 in the non-emission area NLA. An undercut portion UC may be formed between the protruding tip TIP of the pixel auxiliary layer 153 and the side surface rc of the recess R123. The protruding tip TIP of the first pixel auxiliary layer 153-1 may include a side surface 1c and a bottom surface 1b facing the recess R123, and the protruding tip TIP of the third pixel auxiliary layer 153-3 may include a side surface 3c and a bottom surface 3b facing the recess R123.

[0210] The pixel electrode of the display device 30 may include a first pixel electrode AE1, a second pixel electrode, and a third pixel electrode AE3, respectively arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3. The first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may cover the side surfaces of the first pixel auxiliary layer 153-1, the second pixel auxiliary layer, and the third pixel auxiliary layer 153-3, respectively. Although only the first emission area EA1, the non-emission area NLA, and the third emission area EA3 are described with reference to the accompanying drawings for the convenience of explanation, the second pixel auxiliary layer in the second emission area EA2 may have the same structure and features as the first pixel auxiliary layer 153-1 in the first emission area EA1 and the third pixel auxiliary layer 153-3 in the third emission area EA3, and the second pixel electrode in the second emission area EA2 may have the same structure and features as the first pixel electrode AE1 and the third pixel electrode AE3.

[0211] The separator 155 included in the display device 30 may include a top surface 155a and a side surface 155c. The inclination angle θ2 formed by the top surface 155a and the side surface 155c of the separator 155 included in the display device 30 may be, but is not limited to, an acute angle. According to some embodiments, the inclination angle θ2 formed by the top surface 155a and the side surface 155c of the separator 155 may include a right angle. The inclination angle θ2 of the separator 155 according to the present embodiment may be adjusted by adjusting the exposure amount of the photolithography of the display device 30. No other redundant description will be provided.

[0212] The display device 30 according to the present embodiment is different from the display device 10 according to other embodiments in that the display device 30 includes a recessed portion R155 in the top surface 155 a of the separator 155 .

[0213] According to some embodiments, the recess R123 and the pixel auxiliary layer 153 included in the display device 30 may be formed via a dry etching process during the manufacturing process. Through this process, the pixel auxiliary layer 153 may be spaced apart from each other in the non-emission area NLA, and the pixel auxiliary layer 153 may include a protruding tip TIP in the non-emission area NLA. In addition, in substantially the same process, the recess R123 of the second through-hole layer 123 may be etched. In this process, the subsequent process may be performed using the empty recess R123 of the second through-hole layer 123. The first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 may be formed in the display device 30 after the dry etching process. Since the pixel auxiliary layer 153 includes the protruding tip TIP, the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3 of the display device 30 may include a pixel electrode pattern AEP inside the recess R123. The pixel electrode pattern AEP of the display device 30 may contact the bottom surface rb of the recess R123. The other elements are the same as those described above, and therefore, redundant description will not be provided.

[0214] Subsequently, the display device 30 may form a separator 155 on the first pixel electrode AE1, the second pixel electrode, and the third pixel electrode AE3. The separator 155 may be formed by a photolithography process during a manufacturing process. According to the present embodiment, during a process of forming the separator 155 in the display device 30, the recess R123 may be filled with the same material as the separator 155. In some embodiments, after forming the separator 155, the recess R123 of the second through-hole layer 123 may be filled with the material forming the separator 155 via a subsequent vacuum process. That is, the material forming the separator 155 of the display device 30 may be the same as the material inside the recess R123.

[0215] The recess R155 formed in a portion of the top surface 155a of the separation member 155 in the display device 30 can be formed by the above-mentioned vacuum process. In other words, since the recess R155 is formed in a portion of the top surface 155a of the separation member 155, it can be seen that the vacuum process is included in the process of manufacturing the display device 30.

[0216] According to some embodiments, the separator 155 may define the first emission area EA1, the second emission area EA2, and the third emission area EA3 of the display device 30, and may also assist in disconnecting the charge generation layer CGL included in the emission material layer EL, and the above components may independently be the same structure and features as those in the above-mentioned display device 10. In some embodiments, the emission material layer EL of the display device 30 may be covered by the common electrode CE, the first encapsulation layer 171, and the second encapsulation layer 173. No other redundant description will be provided.

[0217] In the present disclosure, unless the context clearly indicates otherwise, a singular expression may include a plural expression. It will also be understood that the terms "comprise(s)", "include(s)" or "have / has" when used in the present disclosure specify the presence of stated features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof. Depending on the circumstances, the " / " used herein may be interpreted as "and" or as "or".

[0218] Throughout this disclosure, when it is mentioned that a component such as a layer, film, region, or plate is placed "on" another component, it will be understood that it can be directly on the other component, or another component can be interposed therebetween. In some embodiments, "directly on..." may refer to no additional layers, films, regions, plates, etc. between the layer, film, region, plate, etc. and another part. For example, "directly on..." may refer to two layers or two components being arranged without using additional components such as bonding components therebetween.

[0219] In the present disclosure, although the terms "first", "second", etc. may be used herein to describe one or more elements, components, regions and / or layers, these elements, components, regions and / or layers should not be limited by these terms. These terms are only used to distinguish one component from another component.

[0220] Unless the context clearly indicates otherwise, as utilized herein, the singular forms "a," "an," "one," and "the" are intended to include the plural forms as well. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0221] As utilized herein, the terms "substantially," "about," or similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art will recognize. Taking into account the errors associated with the measurements and with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0222] In the present disclosure, "does not include one or any "component", "excludes one or any "component", "does not contain a "component"", etc. means that the "component" is not added, selected or utilized as a "component" in the compound / composition, but due to other impurities and / or external factors in the composition, less than an appropriate amount of the "component" may still be included.

[0223] Any numerical range listed herein is intended to include all subranges of the same numerical precision included in the listed range. For example, the range of "1.0 to 10.0" is intended to include all subranges between the minimum value of 1.0 listed and the maximum value of 10.0 listed (and including the minimum value of 1.0 listed and the maximum value of 10.0 listed), that is, all subranges with a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit listed herein is intended to include all lower numerical limits included therein, and any minimum numerical limit listed in this specification is intended to include all higher numerical limits included therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly list any subranges included in the range explicitly listed herein.

[0224] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expressions "at least one of a, b, or c," "at least one of ac," "at least one of a to c," "at least one of a, b, and / or c," "at least one of a to c," etc., mean only a, only b, only c, both a and b (e.g., simultaneously), both a and c (e.g., simultaneously), both b and c (e.g., simultaneously), all of a, b, and c, or variations thereof.

[0225] In this specification, “including A or B”, “A and / or B”, etc. means A or B, or A and B.

[0226] According to the light-emitting device, display device, electronic device, electronic device or any other related device or component of the embodiment of the present disclosure described herein, any suitable hardware, firmware (e.g., application-specific integrated circuit), software or a combination of software, firmware and hardware can be implemented. For example, the various components of the device can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of the device can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a rigid printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform various functions described herein. Computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as a random access memory (RAM) as an example). Computer program instructions can also be stored in other non-temporary computer-readable media (such as CD-ROM, flash drive, etc. as an example). In addition, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed on one or more other computing devices without departing from the scope of the embodiment of the present disclosure.

[0227] The feature of one or more suitable embodiments of the present disclosure may be combined in part or in whole. As those skilled in the art will clearly recognize, technically, one or more suitable interactions and operations are possible. In addition, one or more suitable embodiments can be put into practice individually or in combination.

[0228] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the described embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: A substrate, the substrate comprising an emitting region and a non-emitting region; a via layer on the emission region and the non-emission region of the substrate and including a first recess in the non-emission region toward the substrate; a first pixel auxiliary layer on the through-hole layer and including a protruding tip extending on one side of the first pixel auxiliary layer and in a first direction from a side surface of the first recess in the non-emission region; a first pixel electrode, wherein the first pixel electrode is on the first pixel auxiliary layer; a separator, the separator being on the first pixel electrode in the non-emitting area; a charge generation layer on the first pixel electrode in the emission region; a charge pattern, the charge pattern being on the separator, the charge pattern and the charge generation layer comprising the same material; as well as a common electrode on the charge generation layer and the charge pattern, wherein the charge generation layer is in contact with a side surface of the separator, and The charge generation layer and the charge pattern are spaced apart from each other, and the common electrode on the charge generation layer and the common electrode on the charge pattern are provided as one body.

2. The display device according to claim 1, wherein: The separator includes a first surface opposite to the first pixel electrode, and Wherein, an inclination angle formed by the side surface of the separation element and the first surface is an acute angle or a right angle.

3. The display device according to claim 2, further comprising: a first emission layer, the first emission layer being between the charge generation layer and the common electrode, wherein the first emission layer covers the charge generation layer and the charge pattern, and Wherein, the first emission layer is in contact with the side surface of the separation element.

4. The display device according to claim 3, wherein: The side surface of the separator includes: a first portion, the first portion being in contact with the charge generation layer; a second portion that overlaps the charge pattern in a direction parallel to the substrate; and a third portion, the third portion being in contact with the first emission layer, and Wherein, the third part is between the first part and the second part.

5. The display device according to claim 4, wherein: The charge generation layer includes a conductive material, and Wherein, the first emission layer does not include conductive material.

6. The display device according to claim 1, wherein: An undercut portion is positioned between the protruding tip of the first pixel auxiliary layer and the side surface of the first recess.

7. The display device according to claim 6, wherein: The protruding tip of the first pixel auxiliary layer has a bottom surface facing the first concave portion and a first side surface connected to the bottom surface, wherein the first pixel electrode is in contact with the first side surface, and Wherein, the first pixel electrode does not contact the bottom surface.

8. The display device according to claim 7, further comprising: a second pixel auxiliary layer in the non-emission region and spaced apart from the first pixel auxiliary layer with the separator interposed therebetween; as well as a second pixel electrode, wherein the second pixel electrode is on the second pixel auxiliary layer, The first pixel electrode and the second pixel electrode are spaced apart from each other, and the separator is interposed between the first pixel electrode and the second pixel electrode.

9. The display device according to claim 1, further comprising: a second emission layer, the second emission layer being between the first pixel electrode and the charge generation layer; as well as an emission pattern between the separator and the charge pattern and including the same material as that of the second emission layer, Wherein, the second emission layer and the emission pattern are in contact with the side surface of the separation member.

10. The display device according to claim 9, wherein: The second emission layer and the emission pattern are spaced apart from each other.

11. The display device according to claim 1, further comprising: a connecting electrode, wherein the connecting electrode is located between the substrate and the through-hole layer in the emitting region, The through-hole layer includes a first through-hole layer exposing the connection electrode and a second through-hole layer spaced apart from the first through-hole layer in a direction parallel to the substrate.

12. The display device according to claim 11, wherein: The first through hole layer and the second through hole layer are spaced apart from each other by a pixel electrode contact hole in the emission area, and Wherein, in the plan view, the pixel electrode contact hole is inside the separator.

13. The display device according to claim 12, wherein: The first pixel auxiliary layer further includes: a first sub-portion, the first sub-portion being in contact with the first via layer; and a second sub-portion, the second sub-portion being separated from the first sub-portion by the pixel electrode contact hole and contacting the second through-hole layer, and The first sub-portion and the second sub-portion are connected via the first pixel electrode.

14. The display device according to claim 1, wherein: The separation piece has an inverted tapered shape.

15. The display device according to claim 14, wherein: The first recess is filled with the same material as that of the separator, and Wherein, the first recess and the separation element are formed as one body.

16. The display device according to claim 2, wherein: The first surface of the separator includes a second recessed portion facing the substrate.

17. A display device comprising: A substrate, the substrate comprising a display area and a non-display area, the display area comprising an emission area and a non-emission area; a via layer on the substrate and including a recessed portion in the non-emitting region facing the substrate; a first pixel auxiliary layer on the through-hole layer and including a protruding tip extending on one side of the first pixel auxiliary layer and in a first direction from a side surface of the recess in the non-emission region; a first pixel electrode, wherein the first pixel electrode is on the first pixel auxiliary layer; a first pixel electrode pattern, the first pixel electrode pattern being in the concave portion, the first pixel electrode pattern and the first pixel electrode comprising the same material, and the first pixel electrode pattern being spaced apart from the first pixel electrode; a separator, the separator being on the first pixel electrode in the non-emitting area; as well as a power supply electrode in the non-display area and surrounding the display area, wherein the separation element does not overlap with the emission area, and Wherein, the separation element completely surrounds the emission area in a plan view.

18. The display device according to claim 17, wherein: The first pixel electrode pattern does not overlap with the emission area, and Wherein, in the plan view, the separator and the first pixel electrode pattern have a grid pattern.

19. The display device according to claim 18, wherein: In the plan view, the first pixel electrode pattern is connected to the power electrode in the non-display area.

20. The display device according to claim 19, wherein: The separator and the first pixel electrode pattern overlap each other in the plan view.

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