Proportional valve driver with flutter function

Abstract

The invention discloses a proportional valve driver with a flutter function. The proportional valve driver comprises a microprocessor, a proportional valve control signal input circuit, a fundamental wave generation circuit, a PWM wave generation circuit, a triangular wave generation circuit, an AND gate circuit, a comparison circuit, a proportional valve control signal output circuit and a communication circuit. The input ends of the fundamental wave generating circuit, the PWM wave generating circuit and the triangular wave generating circuit are all connected with the microprocessor, the output ends of the fundamental wave generating circuit and the PWM wave generating circuit are respectively connected with the input end of the AND gate circuit, and the output end of the triangular wave generating circuit and the output end of the AND gate circuit are respectively connected with the input end of the comparison circuit. The output end of the comparison circuit is connected with the input end of the proportional valve control signal output circuit, and the output end of the proportional valve control signal output circuit is connected with an electromagnet of the proportional valve; one end of the communication circuit is connected with the microprocessor, and the other end of the communication circuit is connected with target equipment.

Description

Technical Field

[0001] The present application relates to the field of industrial automation control technology, and in particular to a proportional valve driver with a dither function. Background Art

[0002] With the continuous development of industrial automation control technology, hydraulic systems have been widely used in various industrial fields. As an important control component, hydraulic proportional valves are used to accurately control the pressure and flow in hydraulic systems by converting electrical signals into corresponding forces or displacements. Existing hydraulic proportional valves are generally driven by DC proportional solenoids, but in actual applications, they have problems such as slow response speed, low control accuracy, and large hysteresis effect, which seriously affect the dynamic response and control stability of the system.

[0003] Traditional hydraulic proportional valve drivers usually use low-frequency PWM waves as drive signals. This drive method is prone to static friction when the valve core is stationary, causing the valve core to lag when starting, resulting in slow system response. In addition, since the control signal cannot change dynamically, the system may experience viscosity and friction lag during operation, affecting the overall response speed and sensitivity. Summary of the invention

[0004] To this end, the present application provides a proportional valve driver with a dither function to solve the problems of slow response speed and low control accuracy of hydraulic proportional valves in the prior art due to static friction and hysteresis effect.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A proportional valve driver with a dither function, comprising a microprocessor, a proportional valve control signal input circuit, a fundamental wave generating circuit, a PWM wave generating circuit, a triangle wave generating circuit, an AND gate circuit, a comparison circuit, a proportional valve control signal output circuit, and a communication circuit;

[0007] The input end of the proportional valve control signal input circuit is connected to the 0 to 10V voltage output end, and the output end of the proportional valve control signal input circuit is connected to the microprocessor;

[0008] The input ends of the fundamental wave generating circuit, the PWM wave generating circuit and the triangular wave generating circuit are all connected to the microprocessor, the output ends of the fundamental wave generating circuit and the PWM wave generating circuit are respectively connected to the input end of the AND gate circuit, the output end of the triangular wave generating circuit and the output end of the AND gate circuit are respectively connected to the input end of the comparison circuit, the output end of the comparison circuit is connected to the input end of the proportional valve control signal output circuit, and the output end of the proportional valve control signal output circuit is connected to the electromagnet of the proportional valve;

[0009] One end of the communication circuit is connected to the microprocessor, and the other end of the communication circuit is connected to the target device.

[0010] Optionally, the microprocessor includes a first chip U1A, and the first chip U1A is a STM32F103VET6 chip.

[0011] Optionally, the proportional valve control signal input circuit includes an eighth resistor R8 and a ninth resistor R9;

[0012] One end of the eighth resistor R8 is connected to the 0 to 10V voltage output terminal, the other end of the eighth resistor R8 is connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded;

[0013] The connection end of the eighth resistor R8 and the ninth resistor R9 is connected to the 32nd pin of the first chip U1A.

[0014] Optionally, the fundamental wave generating circuit and the PWM wave generating circuit are timer circuits inside the microprocessor; and the triangle wave generating circuit is a DAC peripheral circuit inside the microprocessor.

[0015] Optionally, the AND gate circuit includes a second chip U2A, and the second chip U2A is a 74F08 chip;

[0016] The first pin of the second chip U2A is connected to the 67th pin of the first chip U1A; the second pin of the second chip U2A is connected to the 63rd pin of the first chip U1A; the third pin of the second chip U2A is connected to the input end of the comparison circuit;

[0017] Among them, the 67th pin of the first chip U1A is the output end of the fundamental wave generating circuit, and the 63rd pin of the first chip U1A is the output end of the PWM wave generating circuit.

[0018] Optionally, the comparison circuit includes a third chip U3A, and the third chip U3A is a LM339A chip;

[0019] The 5th pin of the third chip U3A is connected to the 3rd pin of the second chip U2A; the 4th pin of the third chip U3A is connected to the 29th pin of the first chip U1A; the 2nd pin of the third chip U3A is connected to the input end of the proportional valve control signal output circuit;

[0020] The third pin of the third chip U3A is connected to the 3.3V power supply output terminal, and the 12th pin of the third chip U3A is grounded;

[0021] Among them, the 29th pin of the first chip U1A is the output end of the triangle wave generating circuit.

[0022] Optionally, the proportional valve control signal output circuit includes a first resistor R1 and a first transistor Q1;

[0023] One end of the first resistor R1 is connected to the second pin of the third chip U3A, and the other end of the first resistor R1 is connected to the base of the first transistor Q1;

[0024] The collector of the first transistor Q1 is connected to the second pin of the first connection terminal P1, and the emitter of the first transistor Q1 is grounded;

[0025] The first pin of the first connection terminal P1 is connected to a 12V power output terminal.

[0026] Optionally, the first transistor Q1 is an NPN type high-power transistor.

[0027] Optionally, the communication circuit includes a fourth chip U4, and the fourth chip U4 is an SP3485 chip;

[0028] The first pin of the fourth chip U4 is connected to the 26th pin of the first chip U1A; the second pin of the fourth chip U4 is connected to the third pin of the fourth chip U4; the third pin of the fourth chip U4 is connected to the 24th pin of the first chip U1A; the fourth pin of the fourth chip U4 is connected to the 25th pin of the first chip U1A; the fifth pin of the fourth chip U4 is grounded; the sixth pin of the fourth chip U4 is connected to one end of the fourth resistor R4; the seventh pin of the fourth chip U4 is connected to one end of the third resistor R3; the eighth pin of the fourth chip U4 is connected to the output end of the 3.3V power supply;

[0029] The other end of the fourth resistor R4 is divided into five paths, the first path is connected to one end of the seventh resistor R7, the second path is connected to one end of the fifth resistor R5, the third path is connected to one end of the second TVS tube T2, the fourth path is connected to one end of the third TVS tube T3, and the fifth path is connected to one end of the second fuse F2; the other end of the seventh resistor R7 is connected to the 3.3V power supply output end; the other end of the third TVS tube T3 is grounded; the other end of the second fuse F2 is an external 485 communication interface line A;

[0030] The other end of the third resistor R3 is divided into five paths, the first path is connected to the other end of the fifth resistor R5, the second path is connected to one end of the sixth resistor R6, the third path is connected to one end of the first TVS tube T1, the fourth path is connected to the other end of the second TVS tube T2, and the fifth path is connected to one end of the first fuse F1; the other end of the sixth resistor R6 is connected to the 3.3V power supply output end; the other end of the first TVS tube T1 is grounded; the other end of the first fuse F1 is an external 485 communication interface line B.

[0031] Optionally, the fundamental wave output by the fundamental wave generating circuit is a square wave with a high frequency duty cycle fixed at 50%, and the frequency of the fundamental wave is 4 kHz.

[0032] Compared with the prior art, this application has at least the following beneficial effects:

[0033] The present application provides a proportional valve driver with a dither function, comprising a microprocessor, a proportional valve control signal input circuit, a fundamental wave generating circuit, a PWM wave generating circuit, a triangular wave generating circuit, an AND gate circuit, a comparison circuit, a proportional valve control signal output circuit, and a communication circuit. The input ends of the fundamental wave generating circuit, the PWM wave generating circuit, and the triangular wave generating circuit are all connected to the microprocessor, the output ends of the fundamental wave generating circuit and the PWM wave generating circuit are respectively connected to the input end of the AND gate circuit, the output end of the triangular wave generating circuit and the output end of the AND gate circuit are respectively connected to the input end of the comparison circuit, the output end of the comparison circuit is connected to the input end of the proportional valve control signal output circuit, and the output end of the proportional valve control signal output circuit is connected to the electromagnet of the proportional valve. The present application generates a fundamental wave, a PWM wave and a low-frequency triangular wave through a microprocessor, and performs superposition control on the fundamental wave, PWM wave and the low-frequency triangular wave in an AND gate circuit and a comparison circuit, thereby realizing an adjustable dither signal. This independent and adjustable dither signal can maintain a small and continuous movement of the valve core, effectively reducing static friction and making the system respond faster; at the same time, the dither function enables the valve core to avoid the hysteresis effect caused by static friction when it is in motion, so that the system can more smoothly and accurately adjust the valve opening, thereby improving the control accuracy and stability; in addition, the dynamic response speed of the proportional valve is also enhanced to ensure that the proportional valve can respond quickly and accurately to changes in the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more intuitively illustrate the prior art and the present application, exemplary drawings are given below. It should be understood that the specific shapes and structures shown in the drawings should not generally be regarded as limiting conditions for implementing the present application; for example, those skilled in the art are capable of easily making conventional adjustments or further optimizations to the addition / reduction / attribution division, specific shapes, positional relationships, connection methods, dimensional ratios, etc. of certain units (components) based on the technical concepts and exemplary drawings disclosed in the present application.

[0035] Figure 1 A circuit principle block diagram of a proportional valve driver with a dither function provided in an embodiment of the present application;

[0036] Figure 2 A circuit schematic diagram of a microprocessor provided in an embodiment of the present application;

[0037] Figure 3 A circuit schematic diagram of a proportional valve control signal input circuit provided in an embodiment of the present application;

[0038] Figure 4 A circuit schematic diagram of an AND gate circuit, a comparison circuit and a proportional valve control signal output circuit provided in an embodiment of the present application;

[0039] Figure 5 A circuit schematic diagram of a communication circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The present application is further described below in detail through specific embodiments in conjunction with the accompanying drawings.

[0041] In the description of this application: unless otherwise specified, the meaning of "plurality" is two or more. The terms "first", "second", "third", etc. in this application are intended to distinguish the objects referred to, and do not have special meanings in terms of technical connotations (for example, they should not be understood as emphasizing the importance or order, etc.). Expressions such as "including", "comprising", "having", etc. also mean "not limited to" (certain units, components, materials, steps, etc.).

[0042] The terms such as "upper", "lower", "left", "right", "middle", etc. cited in this application are usually used to indicate the general relative position relationship for the purpose of intuitive understanding by referring to the drawings, and are not absolute limitations on the position relationship in the actual product.

[0043] The full name of the proportional valve is the electro-hydraulic proportional control valve. It is a hydraulic valve that converts the input electrical signal into force or displacement in proportion, thereby continuously controlling parameters such as pressure and flow. The proportional valve consists of two parts: a DC proportional electromagnet and a hydraulic valve. With the continuous improvement of the degree of automation, the stability and reliability of the performance of the solenoid valve as a key component for controlling the fluid path are particularly important. However, traditional solenoid valve drivers often have problems such as slow response speed and low control accuracy, which affect the operation effect of the entire system. At present, the drive controller directly uses a low-frequency PWM wave as the proportional valve drive signal. The valve core displacement or thrust of the hydraulic proportional valve electromagnet is proportional to the current of the flow path coil. If this wave is fixed, the valve core position is also fixed. When the current is changed, the valve core must overcome static friction and start to move from a static state, which helps to produce the so-called sticky effect, increase the hysteresis, and reduce the response speed and sensitivity. For this reason, the present application applies a small amplitude vibration signal to the valve core to keep it in motion at all times, converting static friction into dynamic friction, thereby improving the response speed and response sensitivity and reducing hysteresis. This small amplitude vibration is called "flutter". Therefore, the present invention aims to provide a novel solenoid valve driver with a dither function to solve the problems of slow response speed and low control accuracy of hydraulic proportional valves in the prior art due to static friction and hysteresis effect.

[0044] like Figure 1 As shown, a proportional valve driver with a dither function includes a microprocessor, a proportional valve control signal input circuit, a fundamental wave generating circuit, a PWM wave generating circuit, a triangle wave generating circuit, an AND gate circuit, a comparison circuit, a proportional valve control signal output circuit, and a communication circuit;

[0045] The input end of the proportional valve control signal input circuit is connected to the 0 to 10V voltage output end, and the output end of the proportional valve control signal input circuit is connected to the microprocessor;

[0046] The input ends of the fundamental wave generating circuit, the PWM wave generating circuit and the triangular wave generating circuit are all connected to the microprocessor, the output ends of the fundamental wave generating circuit and the PWM wave generating circuit are respectively connected to the input end of the AND gate circuit, the output end of the triangular wave generating circuit and the output end of the AND gate circuit are respectively connected to the input end of the comparison circuit, the output end of the comparison circuit is connected to the input end of the proportional valve control signal output circuit, and the output end of the proportional valve control signal output circuit is connected to the electromagnet of the proportional valve;

[0047] One end of the communication circuit is connected to the microprocessor, and the other end of the communication circuit is connected to the target device.

[0048] The present application discloses a proportional valve driver, which has the characteristics of fast response and high-precision control. The system includes a microprocessor, a microprocessor communication interface, a drive power supply part, a signal input end, a signal superposition circuit, a drive output end and the like. Its working principle is independent PWM dithering, using a high-frequency PWM (constant amplitude pulse width modulation) wave as a carrier, the carrier frequency is relatively high, and a lower frequency triangular wave is superimposed on the carrier. It belongs to independent dithering. The frequency and amplitude of the dithering can be adjusted separately.

[0049] In the prior art, there are the following problems: for closed-loop control systems, excessive hysteresis of proportional valves will cause system vibration and closed-loop control failure; hysteresis mainly comes from the friction between the valve core and the valve body and the static fluid force. For direct-drive valves driven by proportional solenoids, the hysteresis and friction hysteresis of the proportional solenoids are also important sources of proportional valve hysteresis; superimposed independent flutter: a triangular wave is superimposed on the linear drive current, which is often used for servo valve drive with a smaller coil current. It belongs to independent flutter, but the drive efficiency is low and the heat is serious; parasitic PWM flutter: the charge and discharge waveform (approximately a triangular wave) generated by direct PWM wave (50-500HZ) drive is used as the source of flutter, which belongs to parasitic flutter, and the amplitude of the flutter is not independently adjustable; the solenoid valve generates high heat, has low working efficiency, and has serious hysteresis.

[0050] Compared with the existing technology, the proportional valve driver with dither function provided in this application can effectively reduce the hysteresis effect; improve control accuracy; reduce power consumption and extend the service life of the solenoid valve; improve the stability and accuracy of the fluid control system; and is suitable for various industrial scenarios and has a high market promotion value.

[0051] The present application provides a proportional valve driver with a dither function, comprising a microprocessor, a proportional valve control signal input circuit, a fundamental wave generating circuit, a PWM wave generating circuit, a triangular wave generating circuit, an AND gate circuit, a comparison circuit, a proportional valve control signal output circuit, and a communication circuit. The input ends of the fundamental wave generating circuit, the PWM wave generating circuit, and the triangular wave generating circuit are all connected to the microprocessor, the output ends of the fundamental wave generating circuit and the PWM wave generating circuit are respectively connected to the input end of the AND gate circuit, the output end of the triangular wave generating circuit and the output end of the AND gate circuit are respectively connected to the input end of the comparison circuit, the output end of the comparison circuit is connected to the input end of the proportional valve control signal output circuit, and the output end of the proportional valve control signal output circuit is connected to the electromagnet of the proportional valve. The present application generates a fundamental wave, a PWM wave and a low-frequency triangular wave through a microprocessor, and performs superposition control on the fundamental wave, PWM wave and the low-frequency triangular wave in an AND gate circuit and a comparison circuit, thereby realizing an adjustable dither signal. This independent and adjustable dither signal can maintain a small and continuous movement of the valve core, effectively reducing static friction and making the system respond faster; at the same time, the dither function enables the valve core to avoid the hysteresis effect caused by static friction when it is in motion, so that the system can more smoothly and accurately adjust the valve opening, thereby improving the control accuracy and stability; in addition, the dynamic response speed of the proportional valve is also enhanced to ensure that the proportional valve can respond quickly and accurately to changes in the control signal.

[0052] like Figure 2 As shown, in a possible embodiment, the microprocessor includes a first chip U1A, and the first chip U1A is a STM32F103VET6 chip.

[0053] In this embodiment, the microprocessor adopts a high-performance 32-bit ARM microprocessor. On-chip serial communication, analog-to-digital conversion, general IO and other rich peripherals meet functional requirements, and is the main controller for core algorithms, waveform signal generation and output and other functions.

[0054] like Figure 3 As shown, in a possible embodiment, the proportional valve control signal input circuit includes an eighth resistor R8 and a ninth resistor R9;

[0055] One end of the eighth resistor R8 is connected to the 0 to 10V voltage output terminal, the other end of the eighth resistor R8 is connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded;

[0056] The connection end of the eighth resistor R8 and the ninth resistor R9 is connected to the 32nd pin of the first chip U1A.

[0057] In this embodiment, the proportional valve control signal input circuit is used for analog input signal acquisition, and a 0-10 volt voltage input signal is used to control the opening of the proportional valve.

[0058] In a possible embodiment, the fundamental wave generating circuit and the PWM wave generating circuit are timer circuits inside the microprocessor; and the triangle wave generating circuit is a DAC peripheral circuit inside the microprocessor.

[0059] In this embodiment, the fundamental wave generating circuit utilizes the timer of the microprocessor to generate a high-frequency square wave with a fixed duty cycle of 50%, and its frequency is set to 4KHz; the PWM wave generating circuit utilizes the timer function of the microprocessor to generate a square wave signal with an adjustable duty cycle, which is used to adjust the electrical signal of the proportional valve opening; the triangle wave generating circuit utilizes the DAC peripheral inside the microprocessor to generate a triangle wave signal for superimposing on the fundamental wave.

[0060] like Figure 4 As shown, in a possible embodiment, the AND gate circuit includes a second chip U2A, and the second chip U2A is a 74F08 chip;

[0061] The first pin of the second chip U2A is connected to the 67th pin of the first chip U1A; the second pin of the second chip U2A is connected to the 63rd pin of the first chip U1A; the third pin of the second chip U2A is connected to the input end of the comparison circuit;

[0062] Among them, the 67th pin of the first chip U1A is the output end of the fundamental wave generating circuit, and the 63rd pin of the first chip U1A is the output end of the PWM wave generating circuit.

[0063] In this embodiment, the PWM wave and the fundamental wave are superimposed using an AND gate circuit.

[0064] like Figure 4 As shown, in a possible embodiment, the comparison circuit includes a third chip U3A, and the third chip U3A is a LM339A chip;

[0065] The 5th pin of the third chip U3A is connected to the 3rd pin of the second chip U2A; the 4th pin of the third chip U3A is connected to the 29th pin of the first chip U1A; the 2nd pin of the third chip U3A is connected to the input end of the proportional valve control signal output circuit;

[0066] The third pin of the third chip U3A is connected to the 3.3V power supply output terminal, and the 12th pin of the third chip U3A is grounded;

[0067] Among them, the 29th pin of the first chip U1A is the output end of the triangle wave generating circuit.

[0068] In this embodiment, the signal obtained by superimposing the PWM wave and the fundamental wave and the triangular wave is output through a voltage comparator to output a waveform after the three waveforms are superimposed.

[0069] like Figure 4 As shown, in a possible embodiment, the proportional valve control signal output circuit includes a first resistor R1 and a first transistor Q1;

[0070] One end of the first resistor R1 is connected to the second pin of the third chip U3A, and the other end of the first resistor R1 is connected to the base of the first transistor Q1;

[0071] The collector of the first transistor Q1 is connected to the second pin of the first connection terminal P1, and the emitter of the first transistor Q1 is grounded;

[0072] The first pin of the first connection terminal P1 is connected to a 12V power output terminal.

[0073] In a possible embodiment, the first transistor Q1 is an NPN type high-power transistor.

[0074] In this embodiment, the first transistor Q1 is used as the rear-stage power output to drive the electromagnet to control the opening of the proportional valve.

[0075] like Figure 5 As shown, in a possible embodiment, the communication circuit includes a fourth chip U4, and the fourth chip U4 is an SP3485 chip;

[0076] The first pin of the fourth chip U4 is connected to the 26th pin of the first chip U1A; the second pin of the fourth chip U4 is connected to the third pin of the fourth chip U4; the third pin of the fourth chip U4 is connected to the 24th pin of the first chip U1A; the fourth pin of the fourth chip U4 is connected to the 25th pin of the first chip U1A; the fifth pin of the fourth chip U4 is grounded; the sixth pin of the fourth chip U4 is connected to one end of the fourth resistor R4; the seventh pin of the fourth chip U4 is connected to one end of the third resistor R3; the eighth pin of the fourth chip U4 is connected to the output end of the 3.3V power supply;

[0077] The other end of the fourth resistor R4 is divided into five paths, the first path is connected to one end of the seventh resistor R7, the second path is connected to one end of the fifth resistor R5, the third path is connected to one end of the second TVS tube T2, the fourth path is connected to one end of the third TVS tube T3, and the fifth path is connected to one end of the second fuse F2; the other end of the seventh resistor R7 is connected to the 3.3V power supply output end; the other end of the third TVS tube T3 is grounded; the other end of the second fuse F2 is an external 485 communication interface line A;

[0078] The other end of the third resistor R3 is divided into five paths, the first path is connected to the other end of the fifth resistor R5, the second path is connected to one end of the sixth resistor R6, the third path is connected to one end of the first TVS tube T1, the fourth path is connected to the other end of the second TVS tube T2, and the fifth path is connected to one end of the first fuse F1; the other end of the sixth resistor R6 is connected to the 3.3V power supply output end; the other end of the first TVS tube T1 is grounded; the other end of the first fuse F1 is an external 485 communication interface line B.

[0079] In this embodiment, the communication circuit is used to generate a data communication interface, and the opening of the proportional valve is controlled through the data interface.

[0080] In a possible embodiment, the fundamental wave output by the fundamental wave generating circuit is a square wave with a high frequency duty cycle fixed at 50%, and the frequency of the fundamental wave is 4 kHz.

[0081] The technical features of the above embodiments may be arbitrarily combined (as long as there is no contradiction in the combination of these technical features). To make the description concise, not all possible combinations of the technical features in the above embodiments are described; these embodiments that are not explicitly written should also be considered to be within the scope of this specification.

Claims

1. A proportional valve driver with a dither function, characterized in that: The proportional valve driver includes a microprocessor, a proportional valve control signal input circuit, a fundamental wave generating circuit, a PWM wave generating circuit, a triangle wave generating circuit, an AND gate circuit, a comparison circuit, a proportional valve control signal output circuit, and a communication circuit; The input end of the proportional valve control signal input circuit is connected to the 0 to 10V voltage output end, and the output end of the proportional valve control signal input circuit is connected to the microprocessor; The input ends of the fundamental wave generating circuit, the PWM wave generating circuit and the triangular wave generating circuit are all connected to the microprocessor, the output ends of the fundamental wave generating circuit and the PWM wave generating circuit are respectively connected to the input end of the AND gate circuit, the output end of the triangular wave generating circuit and the output end of the AND gate circuit are respectively connected to the input end of the comparison circuit, the output end of the comparison circuit is connected to the input end of the proportional valve control signal output circuit, and the output end of the proportional valve control signal output circuit is connected to the electromagnet of the proportional valve; One end of the communication circuit is connected to the microprocessor, and the other end of the communication circuit is connected to the target device.

2. A proportional valve driver with a dither function according to claim 1, characterized in that: The microprocessor includes a first chip U1A, and the first chip U1A is a STM32F103VET6 chip.

3. A proportional valve driver with a dither function according to claim 2, characterized in that: The proportional valve control signal input circuit includes an eighth resistor R8 and a ninth resistor R9; One end of the eighth resistor R8 is connected to the 0 to 10V voltage output terminal, the other end of the eighth resistor R8 is connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded; The connection end of the eighth resistor R8 and the ninth resistor R9 is connected to the 32nd pin of the first chip U1A.

4. A proportional valve driver with a dither function according to claim 2, characterized in that: The fundamental wave generating circuit and the PWM wave generating circuit are timer circuits inside the microprocessor; the triangle wave generating circuit is a DAC peripheral circuit inside the microprocessor.

5. A proportional valve driver with a dither function according to claim 4, characterized in that: The AND gate circuit includes a second chip U2A, and the second chip U2A is a 74F08 chip; The first pin of the second chip U2A is connected to the 67th pin of the first chip U1A; the second pin of the second chip U2A is connected to the 63rd pin of the first chip U1A; the third pin of the second chip U2A is connected to the input end of the comparison circuit; Among them, the 67th pin of the first chip U1A is the output end of the fundamental wave generating circuit, and the 63rd pin of the first chip U1A is the output end of the PWM wave generating circuit.

6. A proportional valve driver with a dither function according to claim 5, characterized in that: The comparison circuit includes a third chip U3A, and the third chip U3A is a LM339A chip; The 5th pin of the third chip U3A is connected to the 3rd pin of the second chip U2A; the 4th pin of the third chip U3A is connected to the 29th pin of the first chip U1A; the 2nd pin of the third chip U3A is connected to the input end of the proportional valve control signal output circuit; The third pin of the third chip U3A is connected to the 3.3V power supply output terminal, and the 12th pin of the third chip U3A is grounded; Among them, the 29th pin of the first chip U1A is the output end of the triangle wave generating circuit.

7. A proportional valve driver with a dither function according to claim 6, characterized in that: The proportional valve control signal output circuit includes a first resistor R1 and a first transistor Q1; One end of the first resistor R1 is connected to the second pin of the third chip U3A, and the other end of the first resistor R1 is connected to the base of the first transistor Q1; The collector of the first transistor Q1 is connected to the second pin of the first connection terminal P1, and the emitter of the first transistor Q1 is grounded; The first pin of the first connection terminal P1 is connected to a 12V power output terminal.

8. A proportional valve driver with a dither function according to claim 7, characterized in that: The first transistor Q1 is an NPN type high power transistor.

9. A proportional valve driver with a dither function according to claim 2, characterized in that: The communication circuit includes a fourth chip U4, and the fourth chip U4 is an SP3485 chip; The first pin of the fourth chip U4 is connected to the 26th pin of the first chip U1A; the second pin of the fourth chip U4 is connected to the third pin of the fourth chip U4; the third pin of the fourth chip U4 is connected to the 24th pin of the first chip U1A; the fourth pin of the fourth chip U4 is connected to the 25th pin of the first chip U1A; the fifth pin of the fourth chip U4 is grounded; the sixth pin of the fourth chip U4 is connected to one end of the fourth resistor R4; the seventh pin of the fourth chip U4 is connected to one end of the third resistor R3; the eighth pin of the fourth chip U4 is connected to the output end of the 3.3V power supply; The other end of the fourth resistor R4 is divided into five paths, the first path is connected to one end of the seventh resistor R7, the second path is connected to one end of the fifth resistor R5, the third path is connected to one end of the second TVS tube T2, the fourth path is connected to one end of the third TVS tube T3, and the fifth path is connected to one end of the second fuse F2; the other end of the seventh resistor R7 is connected to the 3.3V power supply output end; the other end of the third TVS tube T3 is grounded; the other end of the second fuse F2 is an external 485 communication interface line A; The other end of the third resistor R3 is divided into five paths, the first path is connected to the other end of the fifth resistor R5, the second path is connected to one end of the sixth resistor R6, the third path is connected to one end of the first TVS tube T1, the fourth path is connected to the other end of the second TVS tube T2, and the fifth path is connected to one end of the first fuse F1; the other end of the sixth resistor R6 is connected to the 3.3V power supply output end; the other end of the first TVS tube T1 is grounded; the other end of the first fuse F1 is an external 485 communication interface line B.

10. A proportional valve driver with a dither function according to claim 1, characterized in that: The fundamental wave output by the fundamental wave generating circuit is a square wave with a high frequency duty cycle fixed at 50%, and the frequency of the fundamental wave is 4 kHz.

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