Test system

Abstract

The embodiment of the invention provides a testing system, and relates to the technical field of testing. The test system comprises at least one I / O unit, a plurality of modules and a sharing unit. The sharing unit is used for receiving an operation instruction sent by any first module in the multiple modules, and the operation instruction comprises target data needing to be shared by the first module in the process of testing the tested piece; the sharing unit is also used for enabling the target data to be stored in a target memory of at least one specified module in the plurality of modules, and the at least one specified module comprises a second module in the plurality of modules; and the second module is used for reading at least part of target data required by testing from the target memory of the second module. In the invention, the module configured with the target memory in the test system can directly read at least part of data required by the test from the local memory, so that the data reading efficiency is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a testing system. Background Art

[0002] In cars, new energy vehicles and other vehicles, the electronic and electrical architecture of the entire vehicle is becoming more and more complex. The number of electronic control units (ECUs), data bandwidth, and the processing power of CPUs and GPUs have all changed by an order of magnitude compared to before.

[0003] Hardware-in-the-Loop (HIL) testing can verify the functions of various domain controllers, ECUs, CPUs and other controllers in the vehicle in advance to shorten the development cycle of the controllers.

[0004] In the existing HIL test system, the equipment with data storage and processing capabilities (such as real-time machines, or industrial computers, Real-time Parameter Controls, RTPC) and I / O cards in the HIL test system are used to perform test tasks to complete the test of the device under test; generally speaking, in the HIL system, no matter what equipment is integrated, data sharing is usually required between the devices. In the prior art, data sharing between I / O cards and RTPCs is usually achieved through Ethernet, which is inefficient and affects the test efficiency. Summary of the invention

[0005] The purpose of the present invention is to provide a test system, in which a module configured with a target memory can directly read at least part of the data required for the test from the local memory, thereby effectively improving the data reading efficiency.

[0006] Furthermore, if the test system is configured with a shared memory for storing all data, then for data that needs to be repeatedly read by multiple modules (which may include real-time computing modules and / or I / O processing modules), the module configured with the target memory can read these data directly from the local memory without having to read from the shared memory through a shared unit, effectively reducing the processing burden of the shared unit and helping to improve the processing efficiency of the shared unit.

[0007] To achieve the above-mentioned purpose, the present invention provides a test system, comprising: at least one I / O unit, multiple modules and a sharing unit; the multiple modules include at least one real-time computing module and at least one I / O processing module, the I / O processing module is connected to at least one of the I / O units, and the I / O unit is directly or indirectly connected to a device under test; the sharing unit is used to receive an operation instruction sent by any first module among the multiple modules, and the operation instruction includes: target data that needs to be shared by the first module during the test of the device under test; the sharing unit is also used to store the target data in a target memory of at least one designated module among the multiple modules, and the at least one designated module includes a second module among the multiple modules; the second module is used to read at least part of the target data required for the test from the target memory of the second module. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a test system according to a first embodiment of the present invention;

[0009] Figure 2 yes Figure 1 Detailed schematic diagram of the test system in FIG.

[0010] Figure 3 is a schematic diagram of a test system according to a first embodiment of the present invention;

[0011] Figure 4 yes Figure 3 Detailed schematic diagram of the test system in FIG.

[0012] Figure 5 is a schematic diagram of a process of sharing target data W between multiple modules in a test system according to the first embodiment of the present invention;

[0013] Figure 6 is a schematic diagram of a test system according to a first embodiment of the present invention;

[0014] Figure 7 is a schematic diagram of a second module according to a second embodiment of the present invention;

[0015] Figure 8 yes Figure 7 Schematic diagram of the second module;

[0016] Fig. 9 is a schematic diagram of a real-time computing module in a test system according to a second embodiment of the present invention sharing target data X with an I / O processing module;

[0017] Fig.10is a schematic diagram of an I / O processing module in a test system according to a second embodiment of the present invention sharing target data Y with a real-time computing module;

[0018] Fig.11 is a schematic diagram of a first real-time computing device and a second real-time computing module in a test system according to a second embodiment of the present invention sharing target data Z;

[0019] Fig.12 is a schematic diagram of an I / O processing module in a test system not configured with a target memory sharing target data K with a real-time computing module in a second embodiment of the present invention;

[0020] Fig.13 is a schematic diagram of a real-time computing module in a test system according to a second embodiment of the present invention sharing target data A1 with an I / O processing module through a data operation unit, wherein the I / O processing module includes: a data transfer unit and a processing unit;

[0021] Fig.14 is a schematic diagram of an I / O processing module in a test system according to a second embodiment of the present invention sharing target data A2 with a real-time computing module through a data operation unit, wherein the I / O processing module includes: a data transfer unit and a processing unit;

[0022] Fig.15 is a schematic diagram of a real-time computing module in a test system according to a second embodiment of the present invention sharing data with an I / O processing module through a data operation unit, wherein the I / O processing module includes an FPGA circuit;

[0023] Fig.16 is a schematic diagram of an I / O processing module in a test system according to a second embodiment of the present invention sharing data with a real-time computing module through a data operation unit, wherein the I / O processing module includes an FPGA circuit;

[0024] Fig.17 is a schematic diagram of a third real-time computing module in a test system according to a second embodiment of the present invention sharing data with a fourth real-time computing module through a data operation unit;

[0025] Fig.18 is a schematic diagram of a test system according to an embodiment of the present invention being a HIL system. DETAILED DESCRIPTION

[0026] The following will be described in detail with reference to the accompanying drawings to provide a clearer understanding of the purpose, features and advantages of the present invention. It should be understood that the embodiments shown in the accompanying drawings are not intended to limit the scope of the present invention, but are only intended to illustrate the essential spirit of the technical solution of the present invention.

[0027] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details. In other cases, well-known modules, structures, and techniques associated with the present application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0028] Unless the context requires otherwise, throughout the specification and claims, the word "comprise" and variations such as "include" and "have" should be construed in an open, inclusive sense, ie, should be interpreted as "including, but not limited to."

[0029] References throughout the specification to "one embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any manner in one or more embodiments.

[0030] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It should be noted that the term "or" is generally employed in its sense including "or / and" unless the context clearly dictates otherwise.

[0031] In the following description, in order to clearly show the structure and working mode of the present invention, many directional words will be used for description, but the words "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", "down", etc. should be understood as convenient terms and should not be understood as restrictive terms.

[0032] In an existing test system, all devices are connected in a star shape, that is, they are all connected to a shared memory unit, and the data to be shared is synchronized to the shared memory of the shared memory unit. Each device can also read the required target data from the shared memory, and the devices share data through the read and write operations on the shared memory. However, each device needs to read the data from the shared memory when reading data, and the data reading efficiency is not high; and for the same data that needs to be read repeatedly by different devices, the multiple reading process will increase the burden of the shared memory unit, affect the efficiency of the shared memory unit, and also affect the overall test efficiency.

[0033] The embodiment of the present invention relates to a test system, please refer to Figure 1 and Figure 2 The test system includes: a shared unit 1, multiple modules 2 and at least one I / O unit 3.

[0034] The multiple modules 2 include at least one real-time computing module 21 and at least one I / O processing module 22 ( Figure 2 In the figure, only multiple real-time computing modules 21 and multiple I / O processing modules 22 are shown as examples); the I / O processing module 22 is connected to at least one I / O unit 3, and the I / O unit 3 is directly or indirectly connected to the device under test (the device under test is not shown in the figure). Among them, an I / O processing module 22 can exchange data with one or more I / O units 3. For example, each I / O unit 3 is respectively connected to different terminals of the I / O processing module 22. For another example, each I / O unit 3 is first cascaded and then connected to the I / O processing module 22 (this embodiment and subsequent embodiments are all based on the cascade of each I / O unit 3 as an example), and communicate through EtherCAT Ethernet and other methods. Regardless of how the connection is made, the interaction between the I / O processing module 22 and the I / O unit 3 can be finally realized. The I / O processing module 22 and the I / O unit 3 can be directly connected or connected through other circuits. The I / O unit 3 is used to connect the device under test, and the device under test connected to the entire test system at the same time can be one or more.

[0035] The I / O processing module 22 can also be understood as an I / O processing device, or a collection of partial circuits in the I / O processing device, such as a circuit portion of the I / O processing device used to implement the functions involved in this application. The real-time computing module 21 can also be understood as a real-time computing device, or an RTPC in a HIL system, or a collection of partial circuits of a real-time computing device and RTPC, such as a circuit portion of a real-time computing device used to implement the functions involved in this application. Furthermore, the module 2 can be understood as part or all of the corresponding device.

[0036] The module 2 may be a circuit, or a device including a circuit board of the circuit, or a device including the circuit board and a housing (or bracket) for loading the circuit board.

[0037] The first module is any one module 2 among multiple modules 2, which can be a real-time computing module 21 or an I / O processing module 22; during the testing of the device under test, if the first module needs to share target data, it generates an operation instruction including the target data to be shared, and sends the operation instruction to the sharing unit 1.

[0038] The sharing unit 1 is used to receive an operation instruction sent by any first module among the multiple modules 2, and the operation instruction includes: target data that needs to be shared by the first module during the process of testing the device under test.

[0039] The sharing unit 1 is also used to make the target data be stored in the target memory of at least one designated module among the multiple modules 2, and the at least one designated module includes the second module among the multiple modules. Specifically, the sharing unit 1 sends the operation instruction or the target data corresponding to the operation instruction to at least one designated module, and the designated module is configured with a target memory, so that the target data can be stored in its own target memory. In other words, the sharing unit 1 will send some operation instructions or the target data corresponding to the operation instructions to the designated module, so that the designated module can store the target data locally.

[0040] At least some of the modules 2 among the multiple modules 2 are designated modules, and the designated modules are configured with target memory, which can be understood as the local memory of the designated module. The local memory can be a memory located in the designated module or a memory external to the designated module. As long as data writing and reading are implemented locally, they can be understood as local memory. In the above process, the designated module receiving the target data needs to include the target memory so as to store the target data in the target memory of the designated module.

[0041] The designated module includes a second module that needs to receive target data. In other words, the second module is module 2 that needs to read at least part of the target data during the test. The second module can also be a real-time computing module 21 or an I / O processing module 22. The number of second modules can be one or more. If the number of second modules is multiple, the real-time computing module 21 and / or the I / O processing module 22 can be included.

[0042] Furthermore, the target data may be understood as data that needs to be transmitted between multiple real-time computing modules 21 , or data that needs to be transmitted between a real-time computing module 21 and an I / O processing module 22 , or data that needs to be transmitted between multiple I / O processing modules 22 .

[0043] As described above, the sharing unit 1 can directly write the target data into the target memory of each designated module, or forward the operation instruction to each designated module, and each designated module executes the operation instruction to store the target data into its configured target memory.

[0044] If the designated module includes a second module that needs to receive the target data, the target data is also stored in the target memory of the second module. If the second module needs to use part or all of the target data during the test, it can directly read at least part of the required target data from the target memory of the second module; the target data is the data that needs to be transferred between the first module and at least one second module of the multiple modules 2 during the test.

[0045] In one example, the test system also includes: a shared memory, which can be configured in the shared unit 1 or can be a memory externally connected to the shared unit 1; the shared memory can be a single DDR memory or a storage pool including multiple DDR memories, some or all of the DDR memories can be set in one cabinet, and the DDR memory can also be cross-cabinet, for example, distributed in different cabinets.

[0046] At this time, the shared unit 1 is also used to write the target data in the shared memory by executing the operation instruction, so that the modules in the multiple modules can read the target data from the shared memory. That is to say, the target data required for the test is also stored in the shared memory, and any module in the multiple modules 2 can read at least part of the target data required for the test from the shared memory through the shared unit 1. For example, at least one third module in the multiple modules 2 is used to read at least part of the target data required for the test from the shared memory through the shared unit 1. The third module is any one module 2 in the multiple modules 2, which can be a module 2 configured with a target memory or a module 2 not configured with a target memory, and can read the target data from the shared memory through the shared unit 1 when the target data needs to be read during the test.

[0047] In some embodiments, the second module can read all the data required for the test from the local target memory, but is not limited to this. It can also read part of the data required for the test from the local target memory, and read the other part of the data required for the test from the shared memory through the shared unit 1.

[0048] In this embodiment, the target memory can be configured in some or all of the modules 2 included in the test system; for example, if some modules need to frequently read certain fixed data, the target memory can be configured in these modules, and these fixed data are stored in the target memory of each module. Among them, the target memory can be understood as the local memory of the module, and the local memory can be a memory set in the module or a memory external to the module. As long as the writing and reading of data are realized locally, it can be understood as local memory.

[0049] In some embodiments, the shared memory is part of the shared unit 1, please refer to Figure 3 and Figure 4 The sharing unit 1 includes: a sharing operation unit 11 and a shared memory 12. It should be noted that when the sharing unit 1 does not include a shared memory, it can be understood that the functions performed by the sharing operation unit 11 can all be implemented by the sharing unit 1.

[0050] The first module is used to obtain an operation instruction for performing a target operation on the shared memory 12, and send the operation instruction to the shared operation unit 11, that is, the operation instruction is used to perform a target operation on the shared memory 12, and the target operation is used to write target data to the shared memory 12; the target data is the data that needs to be transferred between the first module and at least one second module among the multiple modules 2 during the test process.

[0051] The shared operation unit 11 is used to: receive the operation instruction sent by the first module; and write the target data into the target memory of the designated module; specifically, the shared operation unit 11 sends the operation instruction or the target data corresponding to the operation instruction to at least one designated module, that is, the shared operation unit 11 can directly write the target data into the target memory of each designated module, or forward the operation instruction to each designated module, and each designated module executes the operation instruction to store the target data in its configured target memory. If the designated module includes a second module that needs to receive the target data, the target data is also stored in the target memory of the second module.

[0052] The shared operation unit 11 is used to execute the operation instruction and write the target data into the shared memory; that is, the target data required for the test is also stored in the shared memory. At this time, at least one third module among the multiple modules 2 is used to read at least part of the target data required for the test from the shared memory through the shared operation unit 11. The third module is any one of the multiple modules 2, which can be a module 2 configured with a target memory or a module 2 not configured with a target memory, and can read the target data from the shared memory through the shared operation unit 11 when the target data needs to be read during the test.

[0053] As described above, the second module can read all the data required for the test from the local target memory, but is not limited to this. It can also read part of the data required for the test from the local target memory, and read the other part of the data required for the test from the shared memory through the shared operation unit 11.

[0054] In some embodiments, the shared operation unit 11 is used to store the target data in the target memory of at least one designated module among the multiple modules 2 when the target data corresponding to the operation instruction meets the preset condition. That is, during the test process, whether the shared operation unit 11 sends the received operation instruction (or the target data corresponding to the operation instruction) to the designated module depends on whether the target data corresponding to the operation instruction meets the preset condition, and the preset condition defines whether the target data needs to be sent to the designated module.

[0055] In one example, when the first module obtains the target data that needs to be shared, it can first determine whether the target data meets the preset conditions, and send the indication information characterizing whether the target data meets the preset conditions together with the operation instructions for writing the target data to the shared memory to the shared operation unit 11. The shared operation unit 11 can then determine whether the target data meets the preset conditions based on the indication information, and upon receiving the first indication information characterizing that the target data meets the preset conditions, determine that the target data needs to be sent to the designated module; upon receiving the indication information characterizing that the target data does not meet the preset conditions, determine that the target data does not need to be sent to the designated module.

[0056] In another example, when the shared operation unit 11 receives an operation instruction, it independently determines whether the target data meets the preset conditions. When it is determined that the target data meets the preset conditions, it is determined that the target data needs to be sent to the designated module; when it is determined that the target data does not meet the preset conditions, it is determined that the target data does not need to be sent to the designated module. In one example, when the shared operation unit 11 receives each operation instruction, it first determines whether the operation instruction is a write operation instruction, and if so, it then determines whether the operation instruction meets the preset conditions.

[0057] In the above two methods, the preset conditions include any one or any combination of the following:

[0058] The target data is derived from the first designated module in at least one real-time computing module or the first designated port of the real-time computing module; for example, after obtaining the target data, the real-time computing module determines whether it is the first designated module, and if so, determines that the target data meets the preset conditions; if not, determines that the target data does not meet the preset conditions. Alternatively, after receiving the operation instruction, the sharing unit 1 determines whether the port in the real-time computing module sending the operation instruction is the first designated port, and if so, determines that the target data meets the preset conditions; if not, determines that the target data does not meet the preset conditions.

[0059] The target data needs to be sent to the second designated module in at least one real-time computing module or the second designated port of the real-time computing module; that is, whether the object with which the target data needs to be shared is the second designated module or the second designated port of the real-time computing module. If so, it is determined that the target data meets the preset conditions; if not, it is determined that the target data does not meet the preset conditions.

[0060] The target data is the data that needs to be transferred between real-time computing modules; that is, the shared operation unit 11 receives an operation instruction for writing the target data to the shared memory from a real-time computing module, and the target data corresponding to the operation instruction needs to be shared with another real-time computing module, then it is determined that the target data meets the preset conditions; if not, it is determined that the target data does not meet the preset conditions.

[0061] The target data originates from a first designated I / O unit in at least one I / O unit or a third designated port of the I / O unit; that is, if the target data is sent by the first designated I / O unit or the third designated port of any I / O unit, it is determined that the target data meets the preset condition; if not, it is determined that the target data does not meet the preset condition.

[0062] The target data needs to be sent to the second designated I / O unit in at least one I / O unit or the fourth designated port of the I / O unit; that is, whether the object with which the target data needs to be shared is the second designated I / O unit or the fourth designated port of any I / O unit. If so, it is determined that the target data meets the preset conditions; if not, it is determined that the target data does not meet the preset conditions.

[0063] The target data is used to be written to a specified address; for example, the operation instruction generated by the first module for writing the target data to the shared memory includes the target address pointed to, then it can be determined whether the target address is the specified address, if so, it is determined that the target data meets the preset conditions; if not, it is determined that the target data does not meet the preset conditions.

[0064] The target data is located in the first preset data list; that is, the first preset data list is preset in the module or shared operation unit 11, similar to the data whitelist, and the target data in the first preset data list meets the preset conditions; the target data outside the first preset data list does not meet the preset conditions.

[0065] The target data is outside the second preset data list; that is, a second preset data list is preset in the module or shared operation unit 11, similar to a data blacklist, and the target data in the second preset data list does not meet the preset conditions; the target data outside the second preset data list meets the preset conditions.

[0066] The acquisition frequency of the target data is less than the preset frequency threshold; that is, the target data whose acquisition frequency is less than the preset frequency threshold is determined to meet the preset condition, and the target data whose acquisition frequency reaches the preset frequency threshold is determined to not meet the preset condition. The acquisition frequency may refer to the frequency at which the real-time computing module generates the target data, or the frequency at which the shared operation unit 11 receives the target data, or the frequency at which the I / O unit reports the data acquired by the I / O processing module; however, it is not limited thereto, and the target data whose acquisition frequency is greater than the set threshold may be determined to not meet the preset condition, and the target data whose acquisition frequency is less than the set threshold may be determined to meet the preset condition.

[0067] For example, during the test, the real-time computing module A will need to periodically share target data with the device under test connected to the I / O processing module B through the I / O unit. For example, after the real-time computing module A simulates the speed data of the speed sensor, it needs to periodically send it to the device under test (such as ECU). If the speed data is generated at a high frequency (i.e., the sending cycle is short), the following situation is likely to occur: the operation instruction R generated by the real-time computing module A for writing the speed data p(n) to the shared memory p(n) (or vehicle speed data p(n)) is sent to the shared operation unit 11, written into the shared memory by the shared operation unit 11 and sent to the I / O processing module B and written into the local target memory by the I / O processing module B. The real-time calculation module A generates new vehicle speed data p(n+1) and sends the operation instruction R for writing the vehicle speed data p(n+1) into the shared memory. p(n+1) The shared operation unit 11 sends the operation instruction R to the shared memory, and the shared operation unit 11 writes the operation instruction R to the shared memory. p(n+1) It also takes time for the I / O processing module B to share the vehicle speed data (or vehicle speed data p(n+1)) with the I / O processing module B and write it into the local target memory. During this period, if the I / O processing module B needs to share the vehicle speed data with the ECU under test, if the I / O processing module B reads from the shared memory, the vehicle speed data p(n+1) is read, while the vehicle speed data read from the local memory is the vehicle speed data p(n). This may cause the vehicle speed data sent to the ECU under test to not be the latest vehicle speed data p(n+1). It is also possible that the vehicle speed data p(n) has not yet been sent to the ECU under test, but the vehicle speed data p(n+1) has been sent to the ECU under test, that is, the vehicle speed data sent to the ECU under test is not the most timely and accurate data, which may affect the accuracy of the test. Therefore, the preset condition can be configured that the acquisition frequency of the target data is less than the preset frequency threshold, so that the I / O processing module B only reads from the local memory for data with a frequency lower than the preset frequency threshold, which can help avoid or reduce the possibility of the above situation. Based on similar reasons, the device under test may also need to periodically report data to the simulation model running in the real-time computing module through the I / O unit, and may also use a limited acquisition frequency to determine whether certain target data is read locally.

[0068] When the target data needs to be sent to multiple second modules, that is, when the target data has multiple sharing objects, it is determined that the target data meets the preset condition; otherwise, it is determined that the target data does not meet the preset condition.

[0069] For example, during the test, especially in the scenario of joint testing of multiple real-time computing modules, the following situations may occur: the data provided by a real-time computing module may need to be shared with other real-time computing modules and some I / O units connected to the I / O processing module; the data of an I / O unit needs to be shared with multiple different real-time computing modules; the data provided by a real-time computing module may need to be given to multiple other real-time computing modules, or even I / O processing modules. For example, a real-time computing module needs to synchronize the clocks of other real-time computing modules and I / O processing modules, and then needs to send corresponding timing information to the real-time computing modules. computing module and I / O processing module; in the above situation, there will be a target data to be shared with multiple other modules, that is, there will be a situation where the target data is written once and read by multiple ends. Therefore, the preset condition can be configured that the target data needs to be sent to multiple second modules. At this time, the shared operation unit 11 will send the operation instruction (or the target data corresponding to the operation instruction) to at least these multiple second modules. These multiple second modules can all read the target data from the local memory, avoiding the process of multiple second modules reading the target data from the shared memory for multiple times, thereby avoiding the problems of reduced efficiency and increased burden of the shared operation unit 11 caused by this.

[0070] It should be noted that the above-mentioned various preset conditions can be used in combination with each other without conflict.

[0071] In one embodiment, the shared operation unit 11 is further used to: refuse to transmit the target data or operation instruction to the preset port, so that the target data cannot be written into the target memory of the preset module among the multiple modules through the preset port. The preset port is the port through which the shared operation unit 11 is connected to the preset module. The preset module is a module configured with a target memory, which can be a real-time computing module or an I / O processing module. When the shared operation unit 11 receives the operation instruction, if it is determined that the operation instruction or the target corresponding to the operation instruction needs to be sent to the preset module through the preset port, it refuses to send it. At this time, the target data will not be stored in the target memory of the preset module.

[0072] The test system includes N modules (N is greater than 1), and the multiple modules 1 are modules among the N modules that are divided to perform the current test task, and may be all or part of the N modules. In addition, the test system may also execute multiple current test tasks in parallel, and then, for different current test tasks, the multiple modules 1 divided may be different, overlapping, or even the same, which is related to the computing resources provided by the modules and the needs of users.

[0073] When the shared operation unit 11 determines that the target data needs to be sent to a designated module, it also needs to determine the designated module that receives the operation instruction or the target data corresponding to the operation instruction; that is, determine which designated modules the operation instruction or the target data corresponding to the operation instruction needs to be broadcast to for local storage. The designated modules are all modules configured with a target memory, including the second module to which the target data needs to be transferred.

[0074] In an example, when it is determined that the target data needs to be sent to a designated module, the shared operation unit 11 is used to determine at least one designated module from a plurality of modules and send the target data to the designated modules.

[0075] In another example, after obtaining the operation instruction, the first module determines at least one designated module from multiple modules, and sends second indication information representing the at least one designated module determined by the first module to the shared operation unit 11, that is, the second indication information specifies the object to receive the target data. The shared operation unit 11 can obtain the designated modules to which the target data needs to be sent from the second indication information, and send the target data to these designated modules.

[0076] In the above two modes, the first module or the shared operation unit 11 determines at least one designated module from multiple modules in any one of the following ways:

[0077] At least one designated module is all modules among multiple modules, and all modules used to execute the current test task are regarded as designated modules; specifically, at least part of the N modules in the test system are divided to execute the current test task, and these modules that execute the current test task are all regarded as designated modules (including the first module that issues the operation instruction).

[0078] At least one designated module is a real-time computing module; that is, all real-time computing modules in the multiple modules executing the current test task are designated modules.

[0079] The first module is a real-time computing module, and at least one designated module includes all I / O processing modules in the multiple modules. That is, in the multiple modules executing the current test task, the target data from the real-time computing module is stored in the target memory of the I / O processing module.

[0080] The first module is an I / O processing module, and at least one designated module includes all real-time computing modules in the multiple modules. That is, in the multiple modules executing the current test task, the target data from the I / O processing module is stored in the target memory of the real-time computing module.

[0081] The at least one designated module includes a module corresponding to the target data among the multiple modules, that is, only the second module that needs to use the target data is used as the designated module.

[0082] It should be noted that the above-mentioned multiple methods of selecting designated modules can be used in combination with each other without conflict. In addition, the above-mentioned example is to execute a current test task in the test system. If the current test task is completed and the next test task is started, the modules selected from N modules to execute the test task and / or the designated modules in the modules to execute the test task can be changed. If the test system executes multiple test tasks at the same time, the designated modules in the modules to execute each test task can be selected in the above-mentioned manner.

[0083] For each designated module, when it receives an operation instruction sent by the shared operation unit 11 or target data corresponding to the operation instruction, it can directly store the target data in the local target memory, or it can also determine whether the target data is the required data and only store the required target data locally.

[0084] In one example, the designated module is configured to prohibit writing to the target memory of the designated module, or: configured to prohibit writing to the target address space of the target memory of the designated module, the target address space including the storage address for storing the target data. That is to say, in the designated module, its target memory can be used entirely to store the target data, or a target address space can be divided in the target memory to be used exclusively for storing the target data, but only supports the shared operation unit 11 to write data to the target memory of the designated module or the target address space of the target memory, and the designated module also prohibits writing to the target memory or the target address space of the target memory, thereby ensuring the data consistency in the target memory of each designated module.

[0085] Furthermore, at least one designated module also includes a first module; the first module is further used to: read target data from a target memory of the first module. That is, if the first module is configured with a target memory, when it needs to read target data required for the target test during the test, it also needs to read from the local target memory.

[0086] For the second module, it will store the target data in the local target memory; if all the data required by the second module are stored in the local target memory, then the second module can store the target data from the local target memory when it needs to read the target data; if only part of the data required by the second module is stored in the local target memory, then when the second module needs to read the specified data required for the test, it will first determine whether to read the specified data from the target memory of the second module. If it is determined to read the specified data from the target memory of the second module, then the specified data is read from the target memory; if it is determined not to read the specified data from the target memory of the second module, then the specified data is read from the shared memory through the shared operation unit 11.

[0087] The second module determines whether to read the specified data from the local target memory or from the shared memory in the following manner:

[0088] When the designated data is within the preset data range, it is determined to read the designated data from the target memory of the second module, that is, the data that can be read from the local memory is preset in advance in each module, and then it is determined where the data required for the test is to be read from. For example, according to the data type, one or more types of data are configured to be read from the local target memory, and other types of designated data are configured to be read from the shared memory through the shared operation unit 11; at this time, it is also necessary to cooperate with the preset conditions of the previous target data, such as configuring these types of data to be sent to the designated module, or not limiting the type of the target data.

[0089] When the designated data is the target data stored in the target memory, it is determined to read the designated data from the target memory of the second module, that is, each module will record the data stored in the local target memory, and determine that these data are read from the local. When the designated data needs to be read, first determine whether the designated data is the data stored locally. If so, read the designated data from the local target memory; if not, read the designated data from the shared memory.

[0090] Exemplarily, the configuration may also be as follows: for each module in the test system, when it needs to read the specified data required for the test, if the module is configured with a target memory and the target data has been written into the target memory, the specified data is read from the target memory; if the module is not configured with a target memory or the target data has not been written into the target memory configured in the module, the specified data is read from the shared memory through the shared operation unit 11. That is, if each module in the test system stores the target data locally, it only reads the specified data required for the test from the local memory; if it does not store the target data locally, it needs to read the specified data from the shared memory through the shared operation unit 11.

[0091] Combine the following Figure 5 The flowchart and the above process are used to illustrate the specific process of I / O processing module M sharing target data W, which is as follows:

[0092] The I / O processing module M obtains the target data W generated by the test piece obtained by the specified I / O unit (or the target data W generated by the specified I / O unit), and generates an operation instruction R for writing the target data W into the shared memory. W (Operation instruction R W Points to the storage address address_w) and sends it to the shared operation unit 11, and the shared operation unit 11 executes the operation instruction R W , write the target data W to the storage address address_w of the shared memory; then determine the operation instruction R W is to write the operation instruction, and then determine whether the target data W meets the preset conditions. Taking the target data W meeting the preset conditions as an example, that is, the target data W needs to be sent to the designated module, and the designated module receiving the target data W is determined to be the real-time computing module S1, and the operation instruction R W Or the target data W is sent to the real-time computing module S1, and the real-time computing module S1 writes the target data W into the local target memory; when the real-time computing module S1 needs to read the target data W, it generates an operation instruction R to read the target data W. dw1 First, determine whether the target data W can be read from the local target memory. If it is determined that the target data can be read from the local target memory, execute the operation instruction R. dw1 , read the target data W from the local target memory.

[0093] When the target data W needs to be read, the other real-time computing module S2 generates an operation instruction R to read the target data W. dw2 First, determine whether the target data W can be read from the local target memory, determine whether the target data cannot be read from the local target memory, and then change the operation instruction R dw2 The target data W is sent to the shared operation unit 11, and the shared operation unit 11 reads the target data W from the shared memory and sends it to the real-time calculation module S2.

[0094] During the test process, the module equipped with the target memory in the test system can directly read at least part of the data required for the test from the local memory, effectively improving the data reading efficiency; especially for data that needs to be repeatedly read by multiple modules (which may include real-time computing modules and / or I / O processing modules), these multiple modules can read these data directly from the local memory without having to read from the shared memory through the shared operation unit 11, effectively reducing the processing burden of the shared operation unit 11 and helping to improve the processing efficiency of the shared operation unit 11.

[0095] In one example, the shared operation unit 11 has the corresponding shared memory, and the shared operation unit 11 has the corresponding module 2; that is, the number of shared operation units 11 can be multiple, and the multiple shared operation units 11 are communicatively connected (for example, the multiple shared operation units 11 are cascaded in sequence or connected in a ring shape), and the number of shared memories 12 can also be one or more, each shared operation unit 11 can correspond to one or more shared memories 12 and be connected, and each shared operation unit 11 can correspond to one or more modules 2 and be connected.

[0096] The shared operation unit 11 is used to read and write the shared memory 12 corresponding to the shared operation unit 11, including reading and writing the target data. That is to say, the shared operation unit 11 can perform read and write operations on the corresponding shared memory 12, including executing the received write operation instruction to write the target data into the connected shared memory 12, the write operation instruction can come from the corresponding module 2, or other shared operation units 11 that are directly or indirectly connected in communication; the shared operation unit 11 can also read the specified data from the connected shared memory 12 and feed it back to the module 2 that sent the read operation instruction based on the received read operation instruction, the read operation instruction comes from the module 2 corresponding to the shared operation unit 11.

[0097] The shared operation unit 11 is further used to: receive the operation instruction issued by the module 2 corresponding to the shared operation unit 11, and: when the corresponding module is the designated module, store the target data in the target memory corresponding to the designated module.

[0098] As described above, the shared unit 1 includes multiple shared operation units 11. Taking one of the shared operation units 11 as an example, the shared operation unit 11 can accept the operation instruction sent by the corresponding module 2, and execute the operation instruction to write the target data into the shared memory 12 corresponding to the shared operation unit 11; if the module 2 corresponding to the shared operation unit 11 includes a designated module, the shared operation unit 11 will also make the target data be stored in the target memory of the corresponding designated module; if the module 2 corresponding to the shared operation unit 11 does not include the designated module, the shared operation unit 11 can also send the operation instruction to other shared operation units 11. When receiving the operation instruction, the other shared operation units 11 perform similar operations, that is, execute the operation instruction to write the target data into the shared memory 12 corresponding to the shared operation unit 11, and when the corresponding module 2 includes the designated module, make the target data be stored in the target memory of the corresponding designated module.

[0099] For an example, see Figure 6 The sharing unit 1 includes a plurality of shared operation units 11 and a plurality of shared memories 12, wherein the plurality of shared operation units 11 correspond to and are connected to the plurality of modules 2 in a one-to-one manner; the plurality of shared operation units 11 correspond to and are connected to the plurality of shared memories 12 in a one-to-one manner; the plurality of shared operation units 11 are communicatively connected to each other, for example, the plurality of shared operation units 11 are sequentially cascaded or ring-connected; Figure 6 In the example, multiple shared operation units 11 are cascaded in sequence.

[0100] The data of the multiple shared memories 12 are kept synchronous, and each shared operation unit 11 executes the same operation instruction to write to the corresponding shared memory 12. In other words, all shared operation units 11 execute the same operation instruction, so that each shared operation unit 11 writes the same target data in the corresponding shared memory 12, so that all shared memories 12 can keep data synchronous.

[0101] For each shared operation unit 11, it will receive the operation instructions for performing target operations on the shared memory 12 sent by the corresponding module 2, and will also receive the operation instructions for performing target operations on the shared memory 12 from other modules 2. Each shared operation unit 11 will execute these operation instructions to write the target data into the corresponding shared memory 12, thereby maintaining data synchronization of all shared memories 12. During the test process, this process will be repeated continuously, and the shared operation unit will periodically collect the operation instructions of each module. Each shared operation unit will perform the same operation on the shared memory based on the collected operation instructions, and then the data synchronization of each shared memory can be achieved after each repetition.

[0102] For each shared operation unit 11, if its corresponding module 2 is a designated module, after executing the operation instruction for performing the target operation on the shared memory 12, it will also store the target data in the target memory of the corresponding designated module; thus, the target data that each module 2 needs to share will be stored in the target memory of the designated module.

[0103] The multiple shared operation units 11 can maintain data synchronization of the multiple shared memories by means of reflective memory, as follows:

[0104] Reflective memory is an existing shared memory system that enables multiple independent modules to share data. Figure 6Taking the multiple shared operation units 11 cascaded in sequence as an example, the multiple shared operation units 11 can use multiple reflective memory nodes. For each shared operation unit 11, when it needs to store new data in the corresponding shared memory, after storing the new data, it sends the new data to the next shared operation unit 11, and each subsequent shared operation unit 11 will also store the new data in the corresponding shared memory and send it to the next shared operation unit 11, until the new data is stored in the shared memories of all shared operation units 11, thereby maintaining the data synchronization of the multiple shared memories corresponding to the multiple shared operation units 11; for the multiple shared operation units 11 connected in a ring, the data to be stored can be transmitted from the current shared operation unit 11 along the ring network for one circle and then stop transmitting, so that all shared operation units 11 complete data storage; for the multiple shared operation units 11 connected in an open loop, the current shared operation unit 11 of the data to be stored will transmit the data simultaneously along the forward and reverse directions of the cascade, and stop transmitting after the data is transmitted to the first and last shared operation units 11, so that all shared operation units 11 complete data storage in the corresponding shared memories.

[0105] It should be noted that, regardless of whether there is one or more shared operation units 11, each shared operation unit 11 can read and write data to the connected shared memory; and store the target data in the target memory of the connected designated module. Even if there are more than one shared operation units 11, a single shared operation unit 11 can still perform the above:

[0106] When the target data corresponding to the operation instruction meets the preset condition, the target data is stored in the target memory of the corresponding at least one designated module.

[0107] When it is determined that the target data needs to be sent to the designated module, it is determined whether there is a designated module that needs to store the target data from the designated modules 2 included in the corresponding module, and the target data is sent to these designated modules. The shared operation unit 11 determines whether there is a designated module that needs to store the target data in a similar manner to the aforementioned shared operation unit 11 determining at least one designated module from multiple modules, which will not be repeated here.

[0108] The second embodiment of the present invention relates to a test system. Compared with the first embodiment, this embodiment provides multiple implementation methods for a module configured with a target memory in the test system to implement local data reading.

[0109] Please refer to Figure 7The second module configured with a target memory includes: a designation unit 211 and a target memory 212 that are communicatively connected to each other; the designation unit 211 is used to receive operation instructions or target data from the sharing unit 1, send the target data to the target memory of the second module for storage, and read at least part of the target data required for the test from the target memory 212.

[0110] For example, the designation unit 211 of the second module includes a data transmission unit; the data transmission unit is used to receive the target data from the sharing unit and send the target data to the target memory of the second module.

[0111] For another example, the designating unit 211 of the second module includes: a processing unit; the processing unit is used to read at least part of the target data required for the test from the target memory of the second module.

[0112] In some examples, the designation unit 211 may be an FPGA circuit or an ASIC circuit, that is, the storage and reading of the target data to the target memory 212 are implemented by the FPGA or ASIC.

[0113] In another example, see Figure 8 The designation unit 211 includes: a data transfer unit 2111 and a processing unit 2112, the data transfer unit 2111 is respectively communicatively connected with the processing unit 2112 and the target memory 212; wherein the processing unit 2112 may be a CPU processor.

[0114] The data transfer unit 2111 is used to receive operation instructions or target data from the sharing unit 1, and send the target data to the target memory of the second module for storage.

[0115] The processing unit 21 is used to read at least part of the target data required for the test from the target memory of the second module.

[0116] Please refer to Fig. 9 Taking the test system including a shared memory, the first module is a real-time computing module 21, and the second module is an I / O processing module 22 as an example, wherein the real-time computing module 21 includes a data transmission unit, a processing unit and a target memory, and the designated module of the I / O processing module 22 is an FPGA circuit, and the FPGA circuit is connected to one or more I / O units 3.

[0117] If there is target data X that needs to be shared to at least one designated I / O unit among the I / O units connected to the I / O processing module 22, the real-time computing module 21 first generates an operation instruction R for writing the target data X into the shared memory. X , and the operation instruction R XThe data transmission unit sends the data to the shared unit 1. After receiving the operation instruction R X After that, get the operation instruction R that needs to be received X The designated module includes at least an I / O processing module 22, such as Figure 7 The shared unit 1 can simultaneously send the operation instruction R X (or target data X) is sent to the real-time computing module 21 (data transfer unit) and the I / O processing module 22 (FPGA circuit). The data transfer unit in the real-time computing module 21 can directly store the target data X in the target memory to which it is connected, and the FPGA circuit of the I / O processing module 22 will also store the target data X in the connected target memory. When the I / O processing module 22 needs to use the target data X, its FPGA circuit reads the target data X from the local target memory and sends the target data X to the specified I / O unit. The target data X can be the data required by the specified I / O unit or the data required by the test piece connected to the specified I / O unit.

[0118] Please refer to Fig.10 Taking the test system including a shared memory, the first module is an I / O processing module 22, and the second module is a real-time computing module 21 as an example, wherein the real-time computing module 21 includes a data transfer unit, a processing unit and a target memory, and the I / O processing module 22 includes: a data transfer unit, a processing unit and a target memory, and the processing unit is connected to one or more I / O units 3.

[0119] The designated I / O unit in the I / O unit 3 connected to the processing unit of the I / O processing module 22 needs to share the target data Y to the real-time computing module 21. The target data Y can be data generated by the designated I / O unit or data generated by the test piece connected to the designated I / O unit. The processing unit of the I / O processing module 22 obtains the target data Y from the designated I / O unit and generates an operation instruction R for writing the target data Y into the shared memory. Y , and the operation instruction R Y The data transmission unit sends the data to the shared unit 1. After receiving the operation instruction R X After that, get the operation instruction R that needs to be received Y The designated module includes at least a real-time computing module 21, such as Figure 8 The shared unit 1 can simultaneously send the operation instruction R Y(or target data Y) is sent to the real-time computing module 21 (data transfer unit) and the I / O processing module 22 (data transfer unit). The data transfer unit in the real-time computing module 21 can directly store the target data Y in the target memory to which it is connected, and the data transfer unit in the I / O processing module 22 can directly store the target data Y in the target memory to which it is connected; when the real-time computing module 21 needs to use the target data Y, its processing unit reads the target data Y from the local target memory.

[0120] Please refer to Fig.11 , taking the test system including a shared memory, the first module is a real-time computing module, recorded as the first real-time computing module, and the second module is a real-time computing module, recorded as the second real-time computing module as an example, wherein the first real-time computing module includes a data transmission unit, a processing unit and a target memory, and the second real-time computing module includes: a data transmission unit, a processing unit and a target memory.

[0121] The first real-time computing module needs to share the target data Z with the second real-time computing module. The processing unit of the first real-time computing generates an operation instruction R for writing the target data Z into the shared memory. Z , and the operation instruction R Z The data transmission unit sends the data to the shared unit 1. After receiving the operation instruction R Z After that, get the operation instruction R that needs to be received Z The designated module includes at least a second real-time computing module, such as Figure 8 The shared unit 1 can simultaneously send the operation instruction R Z (or target data Z) is sent to the first real-time computing module (data transfer unit) and the second real-time computing module (data transfer unit). The data transfer unit in the first real-time computing module can directly store the target data Z to the target memory to which it is connected, and the data transfer unit in the second real-time computing module can directly store the target data Z to the target memory to which it is connected; when the second real-time computing module needs to use the target data Z, its processing unit reads the target data Z from the local target memory.

[0122] It should be noted that Fig.11 Taking the example that both the first module and the second module are real-time computing modules, data sharing between real-time computing modules is realized. By way of example, the first module and the second module can also be I / O processing modules, and data sharing between I / O units can be realized. The data transmission unit and the processing unit are combined to realize the function of the specified module, and can also be realized by FPGA circuit or ASCI circuit. The specific data sharing process is similar and will not be repeated here.

[0123] It should be noted that the drawings of this embodiment and subsequent embodiments only exemplify the first module and the second module of the target data to be transmitted, and the number of modules in the test system, and are not limited to this. In addition, line 1 in the drawings represents the path for writing data, line 2 represents the path for the shared unit to send an operation instruction or the target data corresponding to the operation instruction to the specified module, and line 3 represents the path for reading data.

[0124] It can be seen that the above-mentioned data transmission unit is, for example, an IO hub; it can be used to transmit operation instructions (mainly refers to transmitting the operation instructions to the shared unit), and / or transmit the data read by the shared unit (mainly refers to transmitting the read data to the corresponding module). On this basis, the data transmission unit can also arbitrate the transmission order of the incoming operation instructions and the output operation instructions, and store data in the local target memory to which it is connected.

[0125] In some embodiments, please refer to Fig.12 , the I / O processing module 22 as the first module is not configured with a target memory, the designated module is an FPGA circuit, the processing unit is connected to one or more I / O units 3, and the real-time computing module 21 includes a data transfer unit, a processing unit and a target memory; the I / O processing module 22 can also store the target data K in the target memory in the real-time computing module 21 in a similar manner, and the specific process is as follows:

[0126] The specified I / O unit in the I / O unit 3 connected to the FPGA circuit of the I / O processing module 22 needs to share the target data K to the real-time computing module 21. The target data K can be data generated by the specified I / O unit or data generated by the test piece connected to the specified I / O unit. The FPGA circuit of the I / O processing module 22 obtains the target data K from the specified I / O unit and generates an operation instruction R for writing the target data K into the shared memory. K , and the operation instruction R K Sent to shared unit 1, shared unit 1 receives the operation instruction R K After that, get the operation instruction R that needs to be received K Since the target memory is not configured in the I / O processing module 22, Fig.10 The shared unit 1 only sends the operation instruction R K (or target data K) is sent to the real-time computing module 21 (data transfer unit). The data transfer unit in the real-time computing device 21 can directly store the target data K in the target memory to which it is connected; when the real-time computing device 21 needs to use the target data K, its processing unit reads the target data K from the local target memory.

[0127] In this embodiment, for data that cannot be read from the local target memory or for modules that are not configured with a local target memory, the required data must be read from the shared memory through a shared unit, which is explained below separately, taking the case where neither the first module nor the second module is configured with a local target memory as an example. Even if the first module and the second module are configured with a local target memory, the required data can be read from the shared memory in the following manner.

[0128] like Fig.13 and Fig.14 As shown, the real-time computing module 21 includes a data transmission unit and a processing unit, and the I / O processing module 22 includes: a data transmission unit and a processing unit, and the processing unit is connected to one or more I / O units 3.

[0129] exist Fig.13 In the test, the real-time computing module 21 shares the data A1 to the designated I / O unit connected to the I / O processing module 22. The specific process is as follows: the processing unit of the real-time computing module 21 can generate the data A1 that needs to be sent to the designated I / O unit during the test, and generate an operation instruction R for writing the data A1 into the shared memory. A1 (may be one or more operation instructions), the processing unit will operate the instruction R A1 After being given to the corresponding data transmission unit, the data transmission unit can A1 to the shared unit 1, and then the shared unit 1 can execute the operation instruction R A1 Write data A1 to the shared memory.

[0130] After data A1 is written into the shared memory, data A1 needs to be transferred to a designated I / O unit so as to send data A1 (or other data obtained by the designated I / O unit based on data A1) to the device under test. In this case, the I / O processing module 22 corresponding to the designated I / O unit needs to read data A1. At this time, the processing unit of the I / O processing module 22 can generate an operation instruction R for reading data A1. dA1 (which can be one or more operation instructions), the processing unit will operate the instruction R dA1 After being given to the corresponding data transmission unit, the data transmission unit can dA1 to the shared unit 1, and then the shared unit 1 can execute the operation instruction R dA1 The data A1 is read out from the shared memory and returned to the data transfer unit of the I / O processing module 22, and then returned to the corresponding processing unit via the data transfer unit. The processing unit can give the data A1 to the corresponding designated I / O unit, and the designated I / O unit can send the data A1 (or other data obtained by the designated I / O unit based on the data A1) to the device under test.

[0131] exist Fig.14 In the example, the I / O processing module 22 shares the data A2 with the real-time computing module 21. The specific process is as follows: the processing unit of the I / O processing module 22 obtains the data A2 generated by the test piece obtained by the specified I / O unit (or the data A2 generated by the specified I / O unit), and generates an operation instruction R for writing the data A2 into the shared memory. A2 (may be one or more operation instructions), the processing unit will operate the instruction R A2 After being given to the corresponding data transmission unit, the data transmission unit can A2 to the shared unit 1, and then the shared unit 1 can execute the operation instruction R A2 Write data A2 to the shared memory.

[0132] After data A2 is written into the shared memory, if data A2 needs to be transferred to the real-time computing module 21, the real-time computing module 21 needs to read data A2. At this time, the processing unit of the real-time computing module 21 can generate an operation instruction R for reading data A2. dA2 (which can be one or more operation instructions), the processing unit will operate the instruction R dA2 After being given to the corresponding data transmission unit, the data transmission unit can dA2 to the shared unit 1, and then the shared unit 1 can execute the operation instruction R dA2 The data A2 is read out from the shared memory and returned to the data transmission unit of the real-time computing module 21 , so that the processing unit of the real-time computing module 21 can obtain the data A2 .

[0133] like Fig.15 and Fig.16 As shown, the real-time computing module 21 includes a data transmission unit and a processing unit, and the I / O processing module 22 includes: an FPGA circuit, and the FPGA circuit is connected to one or more I / O units 3.

[0134] exist Fig.15 In the example, the real-time computing module 21 shares data with the designated I / O unit connected to the I / O processing module 22, and the FPGA circuit in the I / O processing module 22 can realize Fig.11 The functions of the data transfer unit and the processing unit in the I / O processing module 22, the specific process and Fig.11 Similar, no further elaboration is required here.

[0135] exist Fig.16 In the example, the I / O processing module 22 shares data with the real-time computing module 21, and the FPGA circuit in the I / O processing module 22 can realize Fig.11The functions of the data transfer unit and the processing unit in the I / O processing module 22, the specific process and Fig.12 Similar, no further elaboration is required here.

[0136] like Fig.17 As shown, the third real-time computing module and the fourth real-time computing module both include a data transmission unit and a processing unit. When the third real-time computing module shares data A3 with the fourth real-time computing module, the processing unit of the first real-time computing generates an operation instruction R for writing data A3 into the shared memory. A3 , and the operation instruction R A3 The data is sent to the shared unit 1 through the data transmission unit, and the shared unit 1 executes the operation instruction R A3 , write data A3 into the shared memory. After data A3 is written into the shared memory, if data A3 needs to be transferred to the fourth real-time computing module, the fourth real-time computing module needs to read data A2. At this time, the processing unit of the fourth real-time computing module can generate an operation instruction R for reading data A3. dA3 (which can be one or more operation instructions), the processing unit will operate the instruction R dA3 After being given to the corresponding data transmission unit, the data transmission unit can dA3 to the shared unit 1, and then the shared unit 1 can execute the operation instruction R dA3 The data A3 is read out from the shared memory and returned to the data transmission unit of the fourth real-time computing module, so that the processing unit of the fourth real-time computing module can obtain the data A3.

[0137] Fig.17 The example of sharing data between two real-time computing modules is taken here, but it is not limited to this. Based on a similar method, data that needs to be shared between two I / O units can also be transferred between two I / O processing modules, which will not be repeated here.

[0138] It should be noted that in the test system of the present application, the sharing unit can be configured as needed to determine whether to send the target data to the designated module for local storage; for example, the sharing unit only sends the target data shared between at least two real-time computing modules to the real-time computing module that needs to use the target data for local storage, and these target data can be data that need to be interacted between the test models running in the real-time computing module; for the target data that needs to be shared between the real-time computing module and the I / O processing module, it will not be sent to the I / O processing module for local storage.

[0139] In the first or second embodiment of the present application, the sharing unit receives an operation instruction from any one of the multiple modules (referred to as a target module), the operation instruction is used to write target data to the shared memory or read at least part of the target data already in the shared memory, the sharing unit executes the operation instruction sent by the target module, if the operation instruction is used to write the target data to the shared memory, then the operation instruction contains the target data to be written, the sharing unit executes the operation instruction, and writes the target data contained in the operation instruction to the shared memory; if the operation instruction is used to read at least part of the target data already in the shared memory, then the operation instruction contains identification information of the target data to be read, the identification information represents the module from which the target data originates, the sharing unit executes the operation instruction, reads the target data corresponding to the identification information in the operation instruction, and feeds back the read target data to the target module that sent the operation instruction; or, the operation instruction contains location information (for example, an address range) of the target data to be read in the shared memory, the sharing unit executes the operation instruction, reads the target data indicated by the location information of the operation instruction in the shared memory, and feeds back the read target data to the target module that sent the operation instruction.

[0140] In an example, each module in the test system is connected to a shared unit through a PCIe bus, that is, the shared unit is connected to each module through a PCIe connector, so that each module can map the target data to be shared to a segment of address in the shared memory, and each module can read data from the shared memory by accessing local memory data, thereby realizing read and write access of each module to the same memory data, and realizing the sharing of target data among multiple modules.

[0141] Among them, the shared unit is used as a standard PCIe device, which can convert the operation instructions of the target module in multiple modules into high-speed serial signals in the future, and transmit the high-speed serial signals representing the operation instructions through a high-speed serial bus. The shared unit executes the operation instructions to read and write target data to the shared memory.

[0142] In one embodiment, the sharing unit may be implemented using FPGA.

[0143] In one embodiment, the shared unit can also be implemented by using a memory expansion controller MXC. The memory expansion controller MXC is a memory controller that supports the Compute Express Link (CXL) protocol. The memory expansion controller MXC supports and complies with the JEDEC standards for DDR4 and DDR5. It complies with the specifications of CXL2.0 and CXL3.0, and supports the transmission speed of PCIE5.0. The memory expansion controller MXC can achieve high-bandwidth, low-latency communication interconnection between each module 2 and the CXL device, allowing each module 2 to achieve higher data sharing performance through shared memory. Among them, when using the memory expansion controller MXC to implement the shared unit, the memory expansion controller MXC can be customized based on the data sharing method between multiple modules 2 in this embodiment. Function and parameter adjustment to better share data.

[0144] Specifically, the shared unit includes a CXL submodule and a memory connection submodule. The CXL submodule is provided with an MXC controller and a CXL controller that are interconnected; the memory connection submodule is provided with a memory DDR4 / 5 memory controller and a DDR4 / 5 slot; the CXL controller is connected to the real-time computing module and the I / O processing module through a PCIE interface; the CXL controller is also connected to the shared memory through the memory connection submodule; it should be noted that the shared unit also includes: GPIO interface, JTAG interface, clock / reset interface, SPI interface and other peripheral circuits, which will not be repeated here.

[0145] In one example, the test system in this application is a HIL system, please refer to Fig.18 The HIL system includes: the above-mentioned shared unit 1 and shared memory; the HIL system also includes the above-mentioned multiple modules 2 and multiple I / O units 3, the multiple modules 2 include: real-time computing module 21 and I / O processing module 22, Fig.18 In the example, the number of real-time computing modules 21 is multiple and the number of I / O processing modules 22 is one. The multiple real-time computing modules 21 form a computing resource pool 20, and the multiple I / O units 3 form an I / O pool 30.

[0146] The I / O processing module 22 is communicatively connected to the real-time computing module 21 in the computing resource pool 20. The I / O processing module 22 is also communicatively connected to each I / O unit 3 in the I / O pool 30 respectively. Each I / O unit 3 is directly or indirectly connected to the device under test 6, and the number of the device under test 6 can be one or more.

[0147] The I / O processing module 22 is connected to each I / O unit 3 as the same EtherCAT network, wherein the I / O unit 3 is connected to the I / O processing module 22 in a cascade manner and communicates based on EtherCAT, and the use of EtherCAT can basically meet the demand for low latency. In addition, the I / O unit can also be plugged into the control module, for example, connected to the control module through the data bus of the control module (such as a PCIe bus).

[0148] The I / O unit 3 can be understood as an input / output unit.

[0149] Specifically, it can be understood that the I / O unit 3 satisfies at least one of the following:

[0150] Able to input data relative to the device under test 6;

[0151] Capable of outputting data relative to the device under test 6;

[0152] Able to input data relative to the real-time computing module 21;

[0153] Able to output data relative to the real-time computing module 21;

[0154] The data A input and / or output of the I / O unit 3 relative to the device under test 6 and the data B input and / or output of the I / O unit 3 relative to the industrial computer may be related or unrelated.

[0155] Specifically, data A and data B may be data of different forms with the same content, for example, a digital signal with a certain content is received from the real-time computing module 21, and an analog signal with the same content is sent to the device under test 6, or vice versa, for another example, a signal before the fault is injected is received from the real-time computing module 21, and a signal after the fault is injected into the I / O unit 3 is sent to the device under test 6;

[0156] Data A and data B may also be data with the same content and the same format;

[0157] Data A and data B may also be data of different contents. For example, data A and data B are respectively a trigger signal for triggering the I / O unit 3 to generate a certain Sign1 signal and the Sign1 signal. For another example, the I / O unit 3 needs to obtain a certain conditional signal from the real-time calculation module 21 to simulate the Sing2 signal that needs to be sent to the device under test 6. At this time, the conditional signal and the Sign2 signal are respectively data A and data B.

[0158] The I / O unit 3 may refer to a circuit, a circuit board, or a device including a circuit board and other assemblies.

[0159] Fig.18In the example, the I / O unit 3 is directly connected to the device under test 6, that is, the device under test 6 is directly connected to the port of each I / O unit 3 through a connector to realize signal transmission; in other examples, a switching matrix is ​​set in the HIL system, and the switching matrix is ​​connected between the I / O unit 3 and the device under test 6, that is, each I / O unit 3 is indirectly connected to the corresponding device under test 6 through the switching matrix.

[0160] In one example, the I / O unit 3 can interact with the real-time computing module via the I / O processing module, and can also interact with the device under test (such as a vehicle controller) directly or via a switching matrix.

[0161] The I / O unit 3 may only implement input and / or output functions. In some examples, the transmitted signal may also be processed during the input and / or output process, such as signal conversion, fault simulation, information simulation, signal generation, on / off control, etc. It can be seen that whether or not other functions are integrated can be used as an implementation method of the I / O unit 3.

[0162] The I / O unit 3 may be an I / O board, for example, a board supporting at least one of the following functions: digital signal input, analog signal input, digital signal output, analog signal output, PWM signal input, PWM signal output, high-side power output, and low-side power output. It can further realize the acquisition and output of high-speed signals. In addition, it can realize flexible configuration of board resources according to requirements. The board accuracy and sampling frequency indicators brought by this technology have reached the industry-leading level.

[0163] The I / O board is, for example, at least one of the following: an AD PWM-IN board, a DAC board, a FIU board, a PWM-OUT board, a RELAY-IO board, an RC board, etc.;

[0164] The I / O board may also be, for example, at least one of the following special boards: a current output board, a thermocouple board, a battery simulator, a temperature simulator, a motor board, and an IO_HUB board.

[0165] Based on the above examples, it can be seen that the I / O unit is a unit that communicates with the device under test based on a non-public standard bus protocol such as CAN, LIN, Flexray, DSI (such as DSI3), PSI (such as PSI5), SENT, etc.

[0166] In one example, the HIL system may also include a cluster server, or: at least one module among the multiple modules (for example, one of the real-time computing modules) is used as a cluster server, the cluster server is used to determine the data transmission information (for example, data transmission relationship) under each test task, such as the data transmission relationship information under the target test task, the data transmission relationship information is used to determine: the real-time computing module and I / O unit used to execute the target test task.

[0167] When the HIL system executes a target test task, the target data may be transmitted between the real-time computing module 21 , the I / O processing module 22 , and the I / O unit 3 based on the data transmission relationship.

[0168] In the HIL system, the cluster server in the HIL system determines the data transmission relationship (also described as the allowed transmission range) between at least part of the I / O units 3 and at least part of the real-time computing modules 21 for the current test task. The cluster server can be connected to a computer of each real-time computing module 21, or any real-time computing module 21 can be configured as a cluster server.

[0169] The data transmission relationship can be understood as: used to determine the real-time computing modules 21 and I / O units 3 that may need to directly or indirectly share data with each other when executing the corresponding test task. Further, it can at least indicate: one or more real-time computing modules 21 (i.e., at least some of the real-time computing modules 21) and one or more I / O units 3 (i.e., at least some of the I / O units 3) are allowed to transmit data and thus jointly participate in the corresponding test task, that is, used to define the scope of the real-time computing modules 21 and I / O units 3 that are allowed to transmit data under the corresponding test task. How to transmit data specifically can be configured separately.

[0170] Different data transmission relationships can be determined for different test tasks, and different test tasks can be executed simultaneously or sequentially.

[0171] After the cluster server determines the data transmission relationship between at least part of the I / O units 3 and at least part of the real-time computing modules 21, there are multiple ways to complete the data transmission between the I / O units 3 and the real-time computing modules 21 that satisfy the data transmission relationship based on the data transmission relationship.

[0172] Assume that data needs to be shared between module A and module B within the scope defined by the data transmission relationship.

[0173] For example, the address space of some or all modules can be preset.

[0174] When the address space of module B is known, when module A wants to transfer the target data that needs to be shared to module B, it can write the target data to the corresponding address space of module B. Module B can periodically obtain data from its own corresponding address space in the memory. When module A obtains the target data from module B, it can also obtain the data from the corresponding address space or address subspace of module B.

[0175] When the address space of module A is known, module A can obtain the target data from module B, and module B can also write the target data to the corresponding address space of module A. Module A can periodically obtain the target data from its corresponding address space in the memory.

[0176] In addition, at the same time, the I / O units 3 connected to a single I / O processing module 22 may all be used for the same test task, or may be partially used for one test task and partially used for other test tasks. The I / O processing module 22 can obtain the required data transmission relationship separately or together.

[0177] In addition, other switching circuits, interfaces, etc. may also be provided between the device under test and the I / O unit, such as a DB9 interface, an EDAC interface, a BOB module, etc.

[0178] It should be noted that Fig.18 The number of I / O processing modules 22 is taken as an example, but is not limited to this. The number of I / O processing modules 22 can also be multiple, each I / O processing module 22 corresponds to one or more I / O units 3, each I / O unit 3 corresponds to only one I / O processing module 22, and each I / O processing module 22 is connected to the corresponding I / O unit 3.

[0179] It can be seen that in order to realize the corresponding communication between the real-time computing module 21, the I / O unit 3, and the device under test 6 and realize the transmission of the target data, in the case of a switching matrix, it is necessary to configure the switching matrix and the data transmission relationship of the I / O processing module 22. In this way, the connection method of the device under test when accessing is more flexible and free, and it is only necessary to configure the switching matrix according to the actual access situation. For example, after the I / O processing module 22 is configured, if the switching matrix is ​​not set, it is necessary to find out which I / O units the device under test should be connected to and how to connect according to the configuration results. In the case of setting the switching matrix, the device under test can be connected to the switching matrix more freely, and then the data transmission required for the test can be achieved by only configuring the switching matrix.

[0180] It should be noted that the above-mentioned test system is an HIL system as an example, but it is not limited to this. The test system can also be a system used in other application scenarios. For example, the test system can be a simulation injection system that can realize the simulation injection of virtual video. At this time, the real-time computing module may not only be an industrial computer, but also a computer for generating simulated video images (which can be understood as a simulation server), which can simulate the injection of virtual video into the device under test connected to the I / O processing module through the I / O unit. In addition, the device under test tested by the test system can be an ECU or a test bench, which can be an ECU, test bench, etc. for vehicles, or a controller or test bench for drones, aircraft, ships, etc.

[0181] Preferred embodiments of the present invention have been described above in detail, but it should be understood that aspects of the embodiments can be modified, if necessary, to employ aspects, features and concepts of the various patents, applications and publications to provide further embodiments.

[0182] These and other changes can be made to the embodiments in light of the above detailed description.In general, in the claims, the terms used should not be considered limited to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which these claims are entitled.

Claims

1. A testing system, characterized in that: The test system comprises: at least one I / O unit, a plurality of modules and a sharing unit; The multiple modules include at least one real-time computing module and at least one I / O processing module, the I / O processing module is connected to at least one of the I / O units, and the I / O unit is used to directly or indirectly connect to the device under test; the sharing unit is used to receive an operation instruction sent by any first module among the multiple modules, and the operation instruction includes: target data that needs to be shared by the first module during the process of testing the device under test; The sharing unit is further used to make the target data be stored in a target memory of at least one designated module among the multiple modules, wherein the at least one designated module includes a second module among the multiple modules; The second module is used to read at least part of the target data required for testing from the target memory of the second module.

2. The test system according to claim 1, characterized in that: The sharing unit is further used to write the target data into the shared memory by executing the operation instruction, so that a module among the multiple modules can read the target data from the shared memory.

3. The test system according to claim 2, characterized in that: The sharing unit includes: a shared operation unit and a shared memory; The shared operation unit is used for: receiving the operation instruction sent by the first module; Writing the target data into the target memory of the designated module; The operation instruction is used to perform a target operation on the shared memory, and the target operation is used to write target data into the shared memory; The shared operation unit is used to execute the operation instruction and write the target data into the shared memory.

4. The test system according to claim 3, characterized in that: The shared operation unit has the corresponding shared memory, and the shared operation unit has the corresponding module; The shared operation unit is used to read and write the shared memory corresponding to the shared operation unit, including reading and writing the target data; The shared operation unit is further used for: receiving the operation instruction issued by the module corresponding to the shared operation unit, and: when the corresponding module is the designated module, allowing the target data to be stored in the target memory of the corresponding designated module.

5. The test system according to claim 4, characterized in that: The number of the shared operation units and the shared memories are both multiple, and the multiple shared operation units correspond to and are connected to the multiple modules one by one; the multiple shared operation units correspond to and are connected to the multiple shared memories one by one; The data of the multiple shared memories are kept synchronous, and each shared operation unit writes into the corresponding shared memory by executing the same operation instruction.

6. The test system according to claim 1, characterized in that: The second module includes: a data transfer unit and a target memory; The data transfer unit is used to receive the target data from the sharing unit and send the target data to the target memory of the second module.

7. The test system according to any one of claims 1 to 6, characterized in that: The second module includes: a processing unit and a target memory; The processing unit is used to read at least part of the target data required for testing from the target memory of the second module.

8. The test system according to claim 1, characterized in that: The at least one designated module also includes the first module; The first module is used to read the target data from the target memory of the first module.

9. The test system according to claim 2, characterized in that: The second module is used for: When it is necessary to read designated data required for the test, determining whether to read the designated data from the target memory of the second module; If so, reading the specified data from the target memory; If not, the designated data is read from the shared memory through the sharing unit.

10. The test system according to claim 1, characterized in that: The second module is used for: When it is necessary to read designated data required for the test, determining whether to read the designated data from the target memory of the second module; If so, reading the specified data from the target memory; If not, the designated data is read from the shared memory through the shared operation unit corresponding to the second module.

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