High-performance AI multi-core processor architecture based on RISC-V instruction set

Abstract

According to the high-performance AI multi-core processor architecture based on the RISC-V instruction set, on the basis of a processor of the RISC-V architecture, classic operation CNN in an AI scene is used as an acceleration object, the characteristic of the modular instruction set of the RISC-V architecture is utilized, on the basis of the basic instruction set, a VPU vector processing unit is added, and common nonlinear operation instructions in the CNN are expanded, so that the high-performance AI multi-core processor architecture is obtained. And a single basic CPU unit of the multi-core processor is formed. On the basis, each CPU is provided with a special direct data access unit for CNN operation to assist in completing CNN large-scale data handling and data arrangement tasks. And the two are combined and arrayed to form an array unit of the multi-core processor, so that a core unit of the multi-core processor is formed. On the basis, a plurality of peripheral units are connected through an AXI bus interface to form a system. According to the method, the computing power bottleneck caused by large-scale data calculation in the CNN is relieved, the core computing unit in the CPU is fully utilized, and meanwhile, the problem of hardware overhead redundancy caused by a special accelerator is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of hardware system architecture, and in particular to a high-performance AI multi-core processor architecture based on the RISC-V instruction set. Background Art

[0002] With the development of artificial intelligence, big models and the Internet of Things, application scenarios have higher and higher requirements for hardware performance in data processing. Although dedicated accelerators can meet the requirements for computing speed, they bring huge hardware overhead. At the same time, due to the rapid update and iteration speed of algorithms in AI-related scenarios, and the long cycle from hardware design to mass production, it is difficult to fully apply scenario algorithm iteration using only dedicated accelerators. Therefore, using large-scale array general-purpose processors to process algorithms not only reduces the hardware overhead brought by dedicated accelerators, but also can better be compatible with new scenario algorithms.

[0003] In terms of processor architecture, compared with traditional ARM, X86, etc., RISCV makes the processor more customizable through modular instruction sets. At the same time, its instruction set is open source and the required instructions can be expanded as needed. Therefore, the high-performance processor architecture based on RISCV architecture has become the best solution for processor arrays in AI-related scenarios. Summary of the invention

[0004] The present invention provides a high-performance AI multi-core processor architecture based on the RISC-V instruction set. The architecture uses the vector processing unit of each CPU as the computing unit of CNN in the AI ​​scenario, adds data handling and arrangement modules based on convolution operations, and expands each CPU to provide nonlinear computing instructions in vector mode, so that the calculations involved in the entire CNN can run at high speed in the architecture.

[0005] The technical solution adopted by the present invention to achieve the above-mentioned purpose is: a high-performance AI multi-core processor architecture based on the RISC-V instruction set, including:

[0006] A multi-core processor is a homogeneous processor that includes several symmetrical RISC-V instruction sets; including CPU0 and multiple other CPUs;

[0007] Direct data access unit, configured with a CPU; used to read the data to be calculated from the storage unit or the DTCM of the CPU to the internal BUFFER through ConvDMA, and move the data to the DTCM inside the CPU in the order required by the CNN calculation;

[0008] The nonlinear operation unit corresponds to a CPU and is used to perform nonlinear operations on batch data of the vector processing unit VPU and store the calculation results back into the DTCM inside the CPU.

[0009] The CPU0 and any one of the other multiple CPUs include:

[0010] The vector processing unit VPU is used to write data into vector registers in batches, perform vector product calculations of multiplication and accumulation on vector data, and add the calculation results to the previous vector product calculation results through addition instructions and temporarily store them in general registers; the complete vector product operation results calculated by each group of vector registers are loaded into vector registers in batches, and sent to the nonlinear operation unit, DTCM, through nonlinear operation instructions, for CPU access to data;

[0011] General registers are used to store intermediate data generated by the accumulation process in convolution operations;

[0012] Vector registers are used to store vector data in convolution calculations and to store convolution result data in nonlinear calculations.

[0013] A method for implementing a high-performance AI multi-core processor architecture based on the RISC-V instruction set includes the following steps:

[0014] 1) When the multi-core processor recognizes CNN calculation, CPU0 acts as the master core, identifies the data to be calculated, and distributes the calculation according to the number of CPUs;

[0015] 2) After CPU0 is allocated, ConvDMA moves the data according to the allocation situation; at the same time, other CPUs start calculating;

[0016] 3) Determine whether all calculations assigned by CPU0 to the current CPU have been completed; if not, return to step 2) other CPUs start to calculate, so that the uncalculated data completes the data operation, until all the assigned data are calculated, at which time a suspend signal is sent to CPU0 to wait for the command of CPU0;

[0017] 4) CPU0 waits for the suspend signal sent by all other CPUs, that is, the current layer calculation is completed;

[0018] 5) CPU0 determines whether the current layer is the last layer;

[0019] If it is not the last layer, CPU0 sends commands to each CPU and returns to step 2) other CPUs start calculating and continue calculating the next layer;

[0020] If the current layer is the last layer, CPU0 integrates the calculation results of each CPU and sends them to the off-chip memory in sequence.

[0021] The method of allocating the calculation according to the number of CPUs comprises the following steps:

[0022] When calculating the allocation, the single-channel pixel points of the CNN output layer are used as the division basis. The single-channel pixel points are divided into blocks according to the number of CPUs. The pixel points at the same position of each channel of the CNN output layer are divided into one group; each channel of the CNN output layer corresponds to each group of weight data of the input layer, and the same position of different groups of weight data should be divided together as much as possible;

[0023] When the data of a single-channel pixel in the CNN output layer is less than the number of CPUs, different channels at the same position in the CNN output layer are evenly distributed to each CPU; in actual calculation, a set of vector registers of each CPU is used to calculate a complete multiplication-accumulation operation, that is, the value of a pixel in the CNN output layer.

[0024] After the CPU0 allocation is completed, ConvDMA moves the data according to the allocation situation, including the following steps:

[0025] For weight data, all weight data are stored in the storage unit. Each time the convolution operation of the corresponding layer is performed, the data is read from the storage unit to the BUFFER through ConvDMA, and the data is sent to the DTCM in sequence through ConvSC according to the assigned convolution operation form;

[0026] For feature data, the feature data of the first layer is stored in the storage unit, and for data of other layers, the data is stored in DTCM. ConvDMA selects the feature data reading location according to the number of layers.

[0027] The other CPUs start to perform calculations, including the following steps:

[0028] While the DTCM data is being written, the current CPU identifies the data to be vectored, and writes the data in batches into the vector registers through the vector load instruction of the VPU; after the loading is completed, the vector data is multiplied and accumulated by the VMAC of the VPU, and the result of the calculation is added to the previous vector product calculation result through the addition instruction and temporarily stored in the general register until a complete vector product operation is completed; then, the complete vector product operation results calculated by each group of vector registers are batched into the vector register through the vector load instruction of the VPU, and sent to the nonlinear operation unit through the nonlinear operation instruction, the nonlinear operation of the data is completed in batches, and the calculation results are stored back in the DTCM to complete the calculation of the current CPU

[0029] The present invention has the following beneficial effects and advantages:

[0030] The present invention completes the CNN calculations involved in the AI ​​scenario through the multi-core processor. Under the premise of ensuring the basic functions of the CPU, the advantages of the RISC-V modular instruction set are utilized. On the basis of the basic instruction set of the CPU, the instruction set module required for CNN calculation acceleration is expanded, which alleviates the computing power bottleneck caused by large-scale data calculations in CNN, fully utilizes the core computing units in the CPU, and reduces the hardware overhead redundancy problem caused by dedicated accelerators. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a multi-core processor architecture diagram.

[0032] Figure 2 Input structure diagram of vector data for nonlinear operation unit.

[0033] Figure 3 CNN computing implementation method for multi-core processor architecture.

[0034] Figure 4 The data flow graph for the vector product operation.

[0035] Figure 5 Schematic diagram of the method for prioritizing computational data partitioning.

[0036] Figure 6 Schematic diagram of other methods for partitioning calculation data. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0038] A high-performance AI multi-core processor architecture based on the RISC-V instruction set, including a RISC-V homogeneous multi-core processor, a CNN (convolutional neural network, a classic algorithm in AI) dedicated direct data access unit, and other peripheral units required for integration (such as Figure 1 ),in,

[0039] The customized RISC-V homogeneous multi-core processor is the processing unit of the core operation of the entire architecture, and includes several symmetrical RISC-V instruction set homogeneous processors for executing various instructions specified in the program. The CPU is a RISC-V instruction set, and the extensible instructions are the attributes of RISC-V. The extended instructions in the present invention are nonlinear operation instructions.

[0040] The CNN-specific direct data access unit, as a processing unit to assist CNN operations in AI scenarios, includes a ConvDMA data handling module, a ConvSC data reordering module, and a BUFFER data caching module.

[0041] Other peripheral units required for integration, including peripheral modules necessary for processor integration, include storage units (DDR / SD, etc.) for storing data required in the CNN calculation process; communication interfaces (I2C / SPI / UART, etc.) for connecting the processor to external devices via necessary protocols; multimedia processing units (JPEG / H264, etc.) for basic pre-processing of images, audio and other data involved in AI scenarios.

[0042] The customized RISC-V homogeneous multi-core processor includes several processors designed based on the RISC-V instruction set.

[0043] Each processor designed based on the RISC-V instruction set must include the following necessary structures in addition to the general structure:

[0044] Contains DTCM (Tightly Coupled Data Memory) for higher performance access to processor data.

[0045] Contains VPU (vector processing unit), which is used to process large-scale convolution calculations involved in CNN (convolutional neural network) in AI scenarios. VPU contains multiple vector registers, and each vector product calculation requires two vector registers, that is, two vector registers form a group, and a VPU contains multiple groups.

[0046] It includes vector registers and general registers. Vector registers are used to store vector data in large-scale convolution calculations and convolution result data in nonlinear calculations. General registers are used to store intermediate data generated by the accumulation process in convolution operations.

[0047] It includes a NICE (instruction extension) interface for connecting the processor to the ALU (logic operation unit) that adds nonlinear operation instructions involved in CNN based on the RISC-V instruction set.

[0048] The ALU for nonlinear operation instructions includes hardware implementations of nonlinear operations that are not directly included in the common processor instruction set in CNN and need to be implemented through software libraries (such as sigmoid functions, etc.), which are used to complete nonlinear operations in the shortest cycle.

[0049] The number of hardware units for the same nonlinear operation instruction is consistent with the number of registers in the vector register. The data to be nonlinearly operated comes from multiple groups of data in the vector register. The nonlinear operation of all register data on the vector register can be completed in one instruction cycle (such as Figure 2 ).

[0050] The CNN-dedicated direct data access unit reads the data to be calculated from the storage unit (DDR, etc.) or the DTCM inside the processor to the internal BUFFER through ConvDMA (convolutional direct memory access), and moves the data to the DTCM inside the processor in the order required for CNN calculation.

[0051] The CNN-specific direct data access unit, whose ConvDMA can access the DTCM of each CPU, can accelerate the rapid data transfer when the feature data to be calculated is in the DTCM of other CPUs during the intermediate layer calculation.

[0052] A method for implementing a high-performance AI multi-core processor architecture based on the RISC-V instruction set (such as Figure 3 ), including the following steps:

[0053] CPU0 identifies CNN calculations and allocates the computing tasks to each CPU at full load.

[0054] CMDA reads the data from its storage location to BUFFER, and ConvSC rearranges it in the order required for calculation and sends it to DTCM.

[0055] While the data is being written, the CPU loads the data in batches into the vector register through the VPU, and the VMAC performs vector product calculations and temporarily stores the intermediate accumulated results in the general register until a complete vector product operation is completed (such as Figure 4 ).

[0056] The complete vector product operation results obtained by each group of calculations are batch loaded into the vector registor and sent to the nonlinear operation unit to complete the nonlinear operation of the data in batches.

[0057] Wait for all CPUs to complete the current CNN layer calculation (CNN contains multiple layers of calculation, and the next layer of calculation will be entered after the current layer of calculation is completed), synchronized by CPU0, and each CPU enters the next layer of calculation.

[0058] Wait for the last layer of CNN to be calculated, which will be integrated by CPU0 and sent to the memory, and the entire CNN calculation is completed.

[0059] The method of dividing the calculation according to the number of CPUs is that a group of vector registers of each CPU (two in a group, one CPU contains several groups) is used to calculate a complete multiplication and accumulation operation (that is, the value of a pixel point corresponding to the output layer).

[0060] The pixels of a single channel in the output layer are divided into blocks according to the number of CPUs, and the pixels of the same position in each channel of the output layer are divided into a group (such as Figure 5 ). This ensures that when calculating between different layers, for the input feature data, the processing efficiency problem caused by data transfer between different CPUs is minimized.

[0061] When the number of pixels in a single channel of the output layer is less than the number of CPUs, different channels at the same position of the output layer can be evenly distributed to each CPU (such as Figure 6 ).

[0062] The present invention is based on a processor of RISC-V architecture, takes the classic operation CNN in AI scenarios as the acceleration object, utilizes the characteristics of the modular instruction set of RISC-V architecture, adds a VPU vector processing unit on the basis of the basic instruction set, and expands the instructions of nonlinear operations commonly used in CNN to form a single basic CPU unit of a multi-core processor. On this basis, each CPU is equipped with a dedicated direct data access unit for CNN operations to assist in completing large-scale data handling and data arrangement tasks of CNN. The two are combined and arrayed to form an array unit of a multi-core processor, thereby forming the core unit of the multi-core processor. On this basis, a number of peripheral units are connected through an AXI bus interface to form a system.

[0063] The present invention includes a customized RISC-V homogeneous multi-core processor, which is a processing unit for the core operation of the entire architecture, and includes a plurality of homogeneous processors with symmetrical RISC-V instruction sets, which are used to execute various instructions specified in the program, and expand modular instructions adapted to CNN calculations while ensuring the basic processor functions; includes a CNN-specific direct data access unit, which is used as a processing unit to assist in CNN calculations in AI scenarios, including a ConvDMA data handling module, a ConvSC data rearrangement module, and a BUFFER data cache module; includes other peripheral units required for integration, including peripheral modules necessary for processor integration, including a storage unit (DDR / SD, etc.) for storing data required in the CNN calculation process, a communication interface (I2C / SPI / UART, etc.) as a necessary protocol connection interface for running the processor and external devices, and a multimedia processing unit (JPEG / H264, etc.) for performing basic preprocessing on images, audio and other data involved in AI scenarios.

[0064] In the present invention, each CPU includes a DTCM based on the architecture of the basic instruction set. Compared with the off-chip memory, this part has a higher access efficiency. Therefore, in order to speed up the calculation of the entire CNN, this part is added to temporarily store the process data during the CNN calculation.

[0065] In addition, it also includes VPU, which is used to process the large-scale convolution calculations involved in CNN in AI scenarios. Since the main part of CNN operations is convolution operations, and the core of convolution operations is multiplication and accumulation operations, the speed of this part of the operation directly affects the calculation speed of the entire CNN. Therefore, in order to speed up the calculation of this part, each CPU is equipped with a vector processing unit and supports basic instructions for vector data loading and vector product operations, so that the calculation efficiency of multiplication and accumulation is improved.

[0066] In addition, it also includes vector register and general register, wherein the vector register is a special register equipped with the VPU unit, which is used to store vector data of vector operations. Here, when the processor performs CNN calculations, the register will be used to store vector data in large-scale convolution calculations and store convolution result data in nonlinear calculations. The former is the feature data and weight data loaded into the vector register in advance before the vector product calculation is performed to prepare for the vector product calculation. The latter is when the vector product operation calculation of the current layer is completed and the nonlinear operation is prepared. Since the extended nonlinear operation of the present invention supports batch calculation in the form of vectors, it is necessary to use vector register to store the data to be subjected to nonlinear calculation. The general register is used to store the intermediate data generated by the accumulation process in the convolution operation. Since each set of vector products obtains an output result, the data only needs to be stored through the general register. However, since the vector product calculation involved in a complete convolution operation is relatively long, this part can only be divided into several small vector product operations, and these results are accumulated to form a complete convolution operation. Therefore, for the general register, after each small vector product calculation is completed, it is necessary to accumulate the result data obtained by the previous calculation originally stored in the general register. Therefore, the vector product data is usually transferred to the general register through the addition instruction.

[0067] In addition, a NICE interface is also included for connecting the processor and the ALU that adds the nonlinear operation instructions involved in CNN based on the RISC-V instruction set. Due to the modularization of the RISC-V instruction set, when the modular instruction set is combined to form a complete CPU, the CPU will also reserve an interface for further extending the instruction on this basis, and the calculation logic corresponding to the instruction is directly connected to the ALU inside the CPU through the NICE interface, so that the instruction can be implemented on the pipeline of the CPU. For the software part, the instruction function can be implemented by embedded assembly. The instructions extended by the present invention are nonlinear operations (such as sigmoid functions, etc.) that are not directly included in the instruction set of the common processor in CNN and need to be implemented by the software library, and are used to complete the nonlinear operation in the shortest cycle. For a complex nonlinear calculation, when it is only implemented by the software library, the actual calculation cycle of the hardware is relatively long. In order to complete the calculation of a layer of CNN as soon as possible, the present invention extends the nonlinear calculation commonly used in CNN to the CPU as an instruction, so that the nonlinear calculation can be completed in the shortest hardware cycle. In addition, for the data processed by the same CPU, the data to be processed by the CPU at one time is relatively large. In order to complete the nonlinear operation faster, the present invention combines the nonlinear operation with the vector processing. The hardware unit of the nonlinear operation can receive multiple groups of data in the vector register at one time and complete the nonlinear operation. The number of hardware units for the same nonlinear operation is consistent with the number of registers in the vector register. The data to be processed by the nonlinear operation comes from multiple groups of data in the vector register. The nonlinear operation of all register data on the vector register can be completed within one instruction cycle.

[0068] The CNN-specific direct data access unit of the present invention reads the data to be calculated from the storage unit (DDR, etc.) or the DTCM inside the processor to the internal BUFFER through ConvDMA, and transports the data to the DTCM inside the processor in the order required by the CNN calculation. Since the data arrangement order required for the convolution calculation of the CNN is inconsistent with the data arrangement order of the actual data in the memory, it is necessary to rearrange the data according to the requirements of the CNN. Therefore, the present invention realizes the rearrangement of data in the process of data transportation through the unit, so that the CPU does not need to deal with the problem of data arrangement when performing data calculation, thereby accelerating the convolution calculation process of the CNN. The specific arrangement division standard is described in the implementation method. In addition, in order to speed up the access to data during the calculation of the intermediate layer, the feature data of the intermediate layer generated is directly stored back in the DTCM, but since this part of the data may be used by other CPUs when the next layer is calculated, the present invention traverses the DTCM access interface of ConvDMA to each CPU, that is, ConvDMA can access the DTCM of each CPU to accelerate the calculation of the intermediate layer, and the feature data to be calculated is in the DTCM of other CPUs for data transportation.

[0069] The present invention provides a method for implementing a high-performance AI multi-core processor architecture based on the RISC-V instruction set, and the implementation process is as follows:

[0070] When the processor recognizes that CNN-related calculations are being performed, CPU0, as the main control core, identifies the data information to be calculated and divides the calculation according to the number of CPUs so that each CPU can process data at full load. Other CPUs wait for the allocation of CPU0 to end and start calculations. As for the allocation method, since ConvDMA may access feature data from other CPUs when calculating the intermediate layer, in order to minimize the access to this part, when calculating the allocation, the single-channel pixel points of the output layer are used as the division basis, and the single-channel pixel points are divided into blocks according to the number of CPUs, and the pixel points at the same position of each channel of the output layer are divided into a group. In this way, when calculating between different layers, for the input feature data, the processing efficiency problem caused by data transfer between different CPUs is minimized. Here, since each channel of the output layer corresponds to each group of weight data of the input layer, the same position of different groups of weight data should be divided together as much as possible during the actual division. When the data of the single-channel pixel points of the output layer is less than the number of CPUs, in order to ensure that each CPU can work at full load, different channels at the same position of the output layer can be evenly distributed to each CPU. In actual calculation, a set of vector registers of each CPU (two in a set, one CPU contains several sets) is used to calculate a complete multiplication-accumulation operation, that is, the value of a pixel point corresponding to the output layer.

[0071] After the allocation is completed, ConvDMA will move the data according to the allocation. For weight data, all weight data are stored in the storage unit. Each time the convolution operation of the corresponding layer is performed, the data needs to be read from the storage unit to the BUFFER through ConvDMA, and the data is sent to DTCM in sequence through ConvSC according to the allocated convolution operation form. For feature data, the feature data of the first layer is stored in the storage unit, and for data of other layers, the data is stored in DTCM. ConvDMA needs to select the feature data reading location according to the number of layers.

[0072] While writing DTCM data, each CPU recognizes that the data to be calculated is ready, and writes the data in batches into the vector registor through the vector load instruction of the VPU. After the loading is completed, the vector product calculation of multiplication and accumulation is performed on the vector data through the VMAC of the VPU, and the result of the calculation is added to the previous vector product calculation result through the addition instruction and temporarily stored in the general register until a complete vector product operation is completed. After a complete vector product operation is completed, the complete vector product operation results obtained by each group of calculations are batch loaded into the vector registor through the vector load instruction of the VPU, and sent to the nonlinear operation unit through the nonlinear operation instruction, the nonlinear operation of the data is completed in batches, and the calculation results are stored back in the DTCM.

[0073] Determine whether all calculations assigned to the current CPU by CPU0 have been completed. If not, repeat the above process again for the uncalculated data to complete the data operation until all the assigned data are calculated. At this time, a suspend signal is sent to CPU0 to wait for the command of CPU0. CPU0 waits for the suspend signal sent by all CPUs, that is, the calculation of the current layer is completed, and CPU0 determines whether the current layer is the last layer. If it is not the last layer, CPU0 sends commands to each CPU to continue the calculation of the next layer. When the current layer is the last layer, CPU0 integrates the calculation results of each CPU and sends them to the off-chip memory (DDR) in sequence.

Claims

1. High-performance AI multi-core processor architecture based on RISC-V instruction set, characterized by: include: A multi-core processor is a homogeneous processor that includes several symmetrical RISC-V instruction sets; including CPU0 and multiple other CPUs; Direct data access unit, configured with a CPU; used to read the data to be calculated from the storage unit or the DTCM of the CPU to the internal BUFFER through ConvDMA, and move the data to the DTCM inside the CPU in the order required by the CNN calculation; The nonlinear operation unit corresponds to a CPU and is used to perform nonlinear operations on batch data of the vector processing unit VPU and store the calculation results back into the DTCM inside the CPU.

2. The high-performance AI multi-core processor architecture based on the RISC-V instruction set according to claim 1, characterized in that: The CPU0 and any one of the other multiple CPUs include: The vector processing unit VPU is used to write data into vector registers in batches, perform vector product calculations of multiplication and accumulation on vector data, and add the calculation results to the previous vector product calculation results through addition instructions and temporarily store them in general registers; the complete vector product operation results calculated by each group of vector registers are loaded into vector registers in batches, and sent to the nonlinear operation unit through nonlinear operation instructions. DTCM, used to implement CPU access to data; General registers are used to store intermediate data generated by the accumulation process in convolution operations; Vector registers are used to store vector data in convolution calculations and to store convolution result data in nonlinear calculations.

3. A method for implementing a high-performance AI multi-core processor architecture based on the RISC-V instruction set, characterized in that: The following steps are involved: 1) When the multi-core processor recognizes CNN calculation, CPU0 acts as the master core, identifies the data to be calculated, and distributes the calculation according to the number of CPUs; 2) After CPU0 is allocated, ConvDMA moves the data according to the allocation situation; at the same time, other CPUs start calculating; 3) Determine whether all calculations assigned by CPU0 to the current CPU have been completed; if not, return to step 2) other CPUs start to calculate, so that the uncalculated data completes the data operation, until all the assigned data are calculated, at which time a suspend signal is sent to CPU0 to wait for the command of CPU0; 4) CPU0 waits for the suspend signal sent by all other CPUs, that is, the current layer calculation is completed; 5) CPU0 determines whether the current layer is the last layer; If it is not the last layer, CPU0 sends commands to each CPU and returns to step 2) other CPUs start calculating and continue calculating the next layer; If the current layer is the last layer, CPU0 integrates the calculation results of each CPU and sends them to the off-chip memory in sequence.

4. The method for implementing a high-performance AI multi-core processor architecture based on the RISC-V instruction set according to claim 3 is characterized in that: The method of allocating the calculation according to the number of CPUs comprises the following steps: When calculating the allocation, the single-channel pixel points of the CNN output layer are used as the division basis. The single-channel pixel points are divided into blocks according to the number of CPUs. The pixel points at the same position of each channel of the CNN output layer are divided into one group; each channel of the CNN output layer corresponds to each group of weight data of the input layer, and the same position of different groups of weight data should be divided together as much as possible; When the data of a single-channel pixel in the CNN output layer is less than the number of CPUs, different channels at the same position in the CNN output layer are evenly distributed to each CPU; in actual calculation, a set of vector registers of each CPU is used to calculate a complete multiplication-accumulation operation, that is, the value of a pixel in the CNN output layer.

5. The method for implementing a high-performance AI multi-core processor architecture based on the RISC-V instruction set according to claim 3, characterized in that: After the CPU0 allocation is completed, ConvDMA moves the data according to the allocation situation, including the following steps: For weight data, all weight data are stored in the storage unit. Each time the convolution operation of the corresponding layer is performed, the data is read from the storage unit to the BUFFER through ConvDMA, and the data is sent to the DTCM in sequence through ConvSC according to the assigned convolution operation form; For feature data, the feature data of the first layer is stored in the storage unit, and for data of other layers, the data is stored in DTCM. ConvDMA selects the feature data reading location according to the number of layers.

6. The method for implementing a high-performance AI multi-core processor architecture based on the RISC-V instruction set according to claim 3, characterized in that: The other CPUs start to perform calculations, including the following steps: While the DTCM data is being written, the current CPU identifies the data to be vector-calculated, and writes the data in batches into the vector registers through the vector load instructions of the VPU; after the loading is completed, the vector data is multiplied and accumulated by the VMAC of the VPU, and the result of the calculation is added to the previous vector product calculation result through the addition instruction and temporarily stored in the general register until a complete vector product operation is completed; then, the complete vector product operation results calculated by each group of vector registers are batch-loaded into the vector register through the vector load instructions of the VPU, and sent to the nonlinear operation unit through the nonlinear operation instructions, the nonlinear operation of the data is completed in batches, and the calculation results are stored back in the DTCM to complete the calculation of the current CPU.

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