A chip defect visual detection method

Abstract

The present invention discloses a chip defect visual detection method, which relates to the technical field of chip defect detection. The present invention realizes real-time correction of optical path deviation in the image acquisition stage through a multi-angle shooting strategy and an adaptive optical adjustment mechanism, thereby enhancing the comprehensiveness and consistency of image data. In the denoising stage, a deep denoising network based on a convolutional autoencoder (CAE) is introduced to learn the feature distribution of noise-free images, and to remove random noise in the acquired images in a targeted manner while retaining important detail features of the solder joint area. In the enhancement stage, adaptive enhancement technology and histogram equalization are combined to optimize low-contrast areas, making the edge characteristics of the solder joint more prominent, thereby significantly improving the visual clarity and feature visibility of the image. In the feature extraction stage, a multi-scale convolutional network is used to capture the edge changes of solder joint cracks and the texture characteristics of material degradation, while focusing on the detail changes of potential defect areas through an attention mechanism, thereby improving the accuracy and efficiency of feature extraction.

Description

Technical Field

[0001] The present invention relates to the technical field of chip defect detection, and in particular to a chip defect visual detection method. Background Art

[0002] In the manufacturing and packaging process of semiconductor chips, defect detection is an important link to ensure product quality and reliability. Traditional methods use optical microscopy technology combined with automated inspection based on machine vision to identify obvious defects on the chip surface through high-resolution imaging and feature extraction technology, thereby reducing the defect rate.

[0003] With the improvement of chip integration and the complexity of manufacturing processes, many hidden defects have gradually become key factors affecting chip performance and life. Among them, fatigue degradation in the solder joint area is a typical minor defect, which manifests as fine cracks or material degradation. Such defects are difficult to identify using traditional rule matching algorithms and are easily affected by environmental conditions and noise from detection equipment. Existing methods address these problems by optimizing hardware resolution or strengthening image preprocessing to improve detection effects. However, this approach is highly dependent on resources and equipment. For defects in low-contrast areas such as solder joints, the detection effect is still limited, and it is easy to miss detection because the signal is masked by noise. This has become a technical bottleneck that urgently needs to be solved in chip defect detection. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] The present invention provides a chip defect visual detection method to solve the problem that fatigue degradation in the solder joint area is difficult to identify through traditional rule matching algorithms, and is easily interfered by environmental conditions and detection equipment noise. Traditional solutions have limited effect on defect detection in low-contrast areas such as solder joint areas.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a chip defect visual detection method, which includes:

[0008] Step S1, collecting image information of the chip surface and interior by an imaging device;

[0009] During the acquisition process, a multi-angle shooting strategy is used to capture image data, and an adaptive optical adjustment mechanism is combined to correct the optical path deviation;

[0010] Step S2, performing denoising and enhancement processing on the collected image information to generate a feature map;

[0011] In the denoising stage, a deep denoising network based on convolutional autoencoder (CAE) is introduced to learn the feature distribution of noise-free images, remove noise and retain the details of the solder joint area;

[0012] In the enhancement stage, adaptive enhancement technology is used to process low-contrast areas to improve the visibility of features at the edges of solder joints;

[0013] Step S3, extracting microscopic characteristics of the solder joint area from the feature map using a deep learning model;

[0014] In step S3, a multi-scale convolutional network is used to capture the edge changes of the solder joint crack and the texture characteristics of material degradation to form the microscopic features of the solder joint. At the same time, an attention mechanism is combined to focus on the detailed changes in the solder joint area and concentrate computing resources on potential defect areas.

[0015] Step S4: classify and identify defects in the extracted microscopic characteristics through a classification model to determine whether the solder joint has fatigue degradation or other problems, and generate a test result.

[0016] As a preferred embodiment of the chip defect visual detection method of the present invention, the step of collecting image information of the chip surface and interior is as follows:

[0017] During the acquisition process, the shooting angle set is defined as Θ={θ1,θ2,…,θ n}, the image corresponding to each shooting angle is I(θ i ), the complete collection image set is I set :

[0018] I set ={I(θ1),I(θ2),…,I(θ n )},

[0019] Among them, θ i represents the i-th shooting angle, n represents the total number of shooting angles,

[0020] Construct an optical path deviation correction model and define the optical path deviation distortion function as D(x, y, t). This describes the pixel offset introduced by the optical path deviation during the acquisition process. The model formula is:

[0021] D(x,y,t)=α1x 2 +α2y 2 +βt,

[0022] Where x and y are the horizontal and vertical coordinates of the pixel point, t is the acquisition time step, α1 and α2 represent the horizontal and vertical optical distortion coefficients respectively, and β represents the time-related distortion correction coefficient.

[0023] As a preferred embodiment of the chip defect visual detection method of the present invention, the step of collecting image information of the chip surface and interior also includes:

[0024] Perform image correction, the correction formula is:

[0025] I c (x,y,θ i )=f c (I(x′,y′,θ i )),

[0026] Among them, I(x′,y′,θ i ) is the original image, I c (x,y,θ i ) is the corrected image, f c (·) is the correction function, and the coordinates of the corrected position (x′, y′) are:

[0027]

[0028] in,

[0029] and are the partial derivatives of the distortion function D(x,y,t) with respect to the x and y coordinates, respectively, used to describe the correction amount of the optical path deviation in the x and y directions.

[0030] The corrected multi-angle image set is denoted as I set,c :

[0031] I set,c ={I c (x,y,θ1),I c (x,y,θ2),…,I c (x,y,θ n )},

[0032] Among them, I c (x,y,θ i ) is the angle θ i The corrected image below.

[0033] As a preferred embodiment of the chip defect visual detection method of the present invention, in the denoising stage of the step of denoising and enhancing the collected image information to generate a feature map:

[0034] The convolutional autoencoder is introduced to establish a denoising network, and the mapping relationship is:

[0035]

[0036] Among them, I is the input image, I dis the denoised image, Represents the nonlinear mapping function of the network, parameter W is the network weight matrix, b is the bias vector,

[0037] The encoder is used to extract features. The CAE encoder converts the input image I into features F e , the formula is:

[0038] F e =σ(W e I+b e ),

[0039] Among them, F e represents the encoding feature, W e represents the convolution weight of the encoder, b e is the bias of the encoder, σ represents the activation function, using the ReLU function,

[0040] The decoder passes F e Reconstruct denoised image I d , the reconstruction formula is:

[0041] I d =σ(W d ·F e +b d ),

[0042] Among them, W d is the deconvolution weight of the decoder, b d is the bias,

[0043] The loss function is introduced for optimization, and the loss function L is:

[0044] L=|I d -I clean | 2 +λ|F e -F e,clean | 2 ,

[0045] Among them, I clean is a noise-free image, F e,clean is the ideal feature distribution, and λ is the feature retention weight.

[0046] As a preferred solution of the chip defect visual detection method of the present invention, in the enhancement stage of the step of denoising and enhancing the collected image information to generate a feature map:

[0047] For the denoised image I d Adaptive enhancement technology is used for optimization, and the enhanced image is I e , the enhancement formula is:

[0048] Ie (x,y)=I d (x,y)·(1+γ(x,y)),

[0049] Among them, γ(x,y) is the enhancement coefficient, which describes the local contrast and is defined as:

[0050]

[0051] Where k is the enhancement factor,

[0052] Histogram equalization is used to optimize low-contrast areas, and the enhancement formula is:

[0053]

[0054] Among them, H c (I e ) is the input image I e After histogram equalization, the mapping value P(I) represents the normalized probability distribution of image pixel intensity, and the calculation formula is:

[0055]

[0056] I e is the input enhanced image, and dI represents the integral variable.

[0057] As a preferred embodiment of the chip defect visual detection method of the present invention, the step of extracting the microscopic characteristics of the solder joint area from the feature map using the deep learning model is as follows:

[0058] The features of the solder joint area are extracted through a multi-scale convolutional network, and the feature mapping formula is:

[0059]

[0060] Among them, F s represents the multi-scale feature map, W k is the kth convolution kernel, K represents the total number of convolution kernels, * represents the convolution operation, I e is the input enhanced image,

[0061] Calculate the edge gradient strength and capture the edge change characteristics. The calculation formula is:

[0062]

[0063] in, Indicates the gradient strength of edge changes,

[0064] and They are feature maps F sPartial derivatives in the x and y coordinate directions,

[0065] The texture characteristics of material degradation are extracted using the local texture descriptor. The formula is:

[0066]

[0067] Among them, T(x,y) represents the texture feature value, N represents the number of directions of texture calculation, i is the direction index of the current calculation, G i is the weighting factor of the i-th direction, φ(F s ,x,y) means the coordinate (x,y) is based on the feature F s Nonlinear texture transformation function.

[0068] As a preferred solution of the chip defect visual detection method of the present invention, in step S3, an attention mechanism is introduced:

[0069] By focusing on the detail changes in the solder joint area through the attention mechanism, the adjusted feature mapping formula is:

[0070] F a (x,y)=A(x,y)·F s (x,y),

[0071] Among them, F a (x, y) represents the feature map after attention mechanism adjustment, A(x, y) is the attention weight, W a is the weight parameter of the attention mechanism, F s (x,y) is the multi-scale eigenvalue at (x,y),

[0072] ∑ (x′,y′) exp(W a ·F s (x′, y′)) is a normalization factor used to perform weighted summation of features at all positions (x′, y′) on the entire feature map;

[0073] Combining multi-scale features, edge gradient features and texture features, we get the final comprehensive feature F out (x,y):

[0074]

[0075] Among them, F out (x, y) is the comprehensive feature of the final output, λ1, λ2, λ3 are weighting coefficients, which measure the importance of multi-scale features, edge gradients and texture features respectively.

[0076] As a preferred solution of the chip defect visual detection method described in the present invention, in the process of defect classification and discrimination, solder joint defect comparison samples are introduced into the classification model, and the solder joint area is visually marked, and the marking content includes the defect location and its severity.

[0077] As a preferred embodiment of the chip defect visual detection method of the present invention, the step of classifying and distinguishing defects of the extracted microscopic characteristics by using a classification model is as follows:

[0078] Define the classification model, and input the comprehensive feature F into the model out , the defect category C is predicted by the classification model, the formula is:

[0079] C=argmax(σ(W c ·F out +b c )),

[0080] Among them, C is the classification result, W c is the weight matrix of the classification model, b c is the classification bias, σ is the activation function,

[0081] In the process of classification model training, comparative samples of solder joint defects are introduced to optimize the loss function L c , the formula is:

[0082]

[0083] Among them, L c is the classification loss, N is the number of samples, y i represents the true label of sample i, p i is the defect probability predicted by the model.

[0084] As a preferred embodiment of the chip defect visual detection method of the present invention, the step of generating the detection result is:

[0085] The solder joint defects are displayed by generating a visual annotation diagram. The annotation formula is:

[0086] I v (x,y)=I(x,y)+α·M(x,y),

[0087] Among them, I v (x,y) represents the visualized image after superimposition and annotation, I(x,y) is the original image, M(x,y) is the defect mask, α is the transparency factor,

[0088] The annotation content includes the defect location and its severity. The defect location is calculated using the mask:

[0089] If (x, y) belongs to the defect area, then M(x, y) = 1, otherwise M(x, y) = 0,

[0090] The severity S is defined as the ratio of the defect area to the total area of ​​the solder joint:

[0091]

[0092] The beneficial effects of the present invention are as follows: the present invention realizes real-time correction of optical path deviation in the image acquisition stage through a multi-angle shooting strategy and an adaptive optical adjustment mechanism, eliminates pixel offset problems caused by equipment errors or optical distortion, and enhances the comprehensiveness and consistency of image data. In the denoising stage, a deep denoising network based on convolutional autoencoder CAE is introduced to learn the feature distribution of noise-free images, specifically remove random noise in the acquired images, and retain important detail features in the solder joint area, thereby avoiding the problem of detail loss that may be caused by noise processing in traditional methods.

[0093] In the enhancement stage, the present invention combines adaptive enhancement technology and histogram equalization to optimize low-contrast areas, making the edge characteristics of solder joints more prominent and significantly improving the visual clarity and feature visibility of the image; in the feature extraction stage, a multi-scale convolutional network is used to capture the edge changes of solder joint cracks and the texture characteristics of material degradation. At the same time, the attention mechanism is used to focus on the detailed changes in potential defect areas, concentrating computing resources on key parts, improving the accuracy and efficiency of feature extraction, and making up for the limitations of traditional methods in processing subtle solder joint characteristics; in the defect classification stage, the classification model is optimized in combination with solder joint defect comparison samples, and high-precision defect classification is achieved through the classification and discrimination of microscopic features. The defect location and severity are intuitively displayed through visual annotation, providing users with clearer detection results. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0095] Figure 1 Schematic diagram of the process of the chip defect visual detection method of the present invention. DETAILED DESCRIPTION

[0096] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0097] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0098] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive of other embodiments.

[0099] Example 1, reference Figure 1 , this embodiment provides a chip defect visual detection method, comprising the following steps:

[0100] Step S1, collecting image information of the chip surface and interior by an imaging device;

[0101] During the acquisition process, a multi-angle shooting strategy is used to capture image data, and an adaptive optical adjustment mechanism is combined to correct the optical path deviation;

[0102] The steps for collecting image information on the chip surface and inside are:

[0103] During the acquisition process, the shooting angle set is defined as Θ={θ1,θ2,…,θ n}, the image corresponding to each shooting angle is I(θ i ), the complete collection image set is I set :

[0104] I set ={I(θ1),I(θ2),…,I(θ n )},

[0105] Among them, θ i represents the i-th shooting angle, n represents the total number of shooting angles,

[0106] Construct an optical path deviation correction model and define the optical path deviation distortion function as D(x, y, t). This describes the pixel offset introduced by the optical path deviation during the acquisition process. The model formula is:

[0107] D(x,y,t)=α1x 2 +α2y 2 +βt,

[0108] Among them, x, y are the horizontal and vertical coordinates of the pixel point, t is the acquisition time step, α1, α2 represent the horizontal and vertical optical distortion coefficients respectively, and β represents the time-related distortion correction coefficient.

[0109] The step of collecting image information of the chip surface and interior also includes,

[0110] Perform image correction, the correction formula is:

[0111] I c (x,y,θ i )=f c (I(x′,y′,θ i )),

[0112] Among them, I(x′,y′,θ i ) is the original image, I c (x,y,θ i ) is the corrected image, f c (·) is the correction function, and the coordinates of the corrected position (x′, y′) are:

[0113]

[0114] in,

[0115] and are the partial derivatives of the distortion function D(x,y,t) with respect to the x and y coordinates, respectively, used to describe the correction amount of the optical path deviation in the x and y directions.

[0116] The corrected multi-angle image set is denoted as I set,c :

[0117] I set,c ={I c (x,y,θ1),I c (x,y,θ2),…,I c (x,y,θ n )},

[0118] Among them, I c (x,y,θ i ) is the angle θ i The corrected image below;

[0119] Specifically, a multi-angle shooting strategy is used to cover detailed information at different angles on the chip surface and inside, combined with optical path correction technology to effectively solve the pixel offset problem introduced by optical deviation or equipment error during the acquisition process. The correction process is based on the partial derivative mathematical model to quantitatively compensate for the distortion, so that the multi-angle images remain consistent in space, improve the accuracy and completeness of the data, and significantly reduce the impact of the external environment on the detection accuracy.

[0120] Step S2, performing denoising and enhancement processing on the collected image information to generate a feature map;

[0121] In the denoising stage, a deep denoising network based on convolutional autoencoder (CAE) is introduced to learn the feature distribution of noise-free images, remove noise and retain the details of the solder joint area;

[0122] In the enhancement stage, adaptive enhancement technology is used to process low-contrast areas to improve the visibility of features at the edges of solder joints;

[0123] The collected image information is denoised and enhanced to generate the feature map in the denoising stage:

[0124] The convolutional autoencoder is introduced to establish a denoising network, and the mapping relationship is:

[0125]

[0126] Among them, I is the input image, I d is the denoised image, Represents the nonlinear mapping function of the network, parameter W is the network weight matrix, b is the bias vector,

[0127] The encoder is used to extract features. The CAE encoder converts the input image I into features F e , the formula is:

[0128] F e =σ(W e I+b e ),

[0129] Among them, F e represents the encoding feature, W e represents the convolution weight of the encoder, b e is the bias of the encoder, σ represents the activation function, using the ReLU function,

[0130] The decoder passes F e Reconstruct denoised image I d , the reconstruction formula is:

[0131] I d =σ(W d ·F e +b d ),

[0132] Among them, W d is the deconvolution weight of the decoder, b d is the bias,

[0133] The loss function is introduced for optimization, and the loss function L is:

[0134] L=|I d -I clean | 2 +λ|F e -Fe,clean | 2 ,

[0135] Among them, I clean is a noise-free image, F e,clean is the ideal feature distribution, λ is the feature retention weight;

[0136] The collected image information is denoised and enhanced to generate the feature map in the enhancement stage:

[0137] For the denoised image I d Adaptive enhancement technology is used for optimization, and the enhanced image is I e , the enhancement formula is:

[0138] I e (x,y)=I d (x,y)·(1+γ(x,y)),

[0139] Among them, γ(x,y) is the enhancement coefficient, which describes the local contrast and is defined as:

[0140]

[0141] Where k is the enhancement factor,

[0142] Histogram equalization is used to optimize low-contrast areas, and the enhancement formula is:

[0143]

[0144] Among them, H c (I e ) is the input image I e After histogram equalization, the mapping value P(I) represents the normalized probability distribution of image pixel intensity, and the calculation formula is:

[0145]

[0146] I e is the input enhanced image, dI represents the integral variable;

[0147] Specifically, the denoising stage uses a convolutional autoencoder to remove random noise from the captured image while retaining the key detail features of the solder joint area. The enhancement stage combines adaptive enhancement technology to improve the overall clarity of the image.

[0148] Step S3, extracting microscopic characteristics of the solder joint area from the feature map using a deep learning model;

[0149] In step S3, a multi-scale convolutional network is used to capture the edge changes of the solder joint crack and the texture characteristics of material degradation to form the microscopic features of the solder joint. At the same time, an attention mechanism is combined to focus on the detailed changes in the solder joint area and concentrate computing resources on potential defect areas.

[0150] The steps of extracting the microscopic characteristics of the solder joint area from the feature map using the deep learning model are as follows:

[0151] The features of the solder joint area are extracted through a multi-scale convolutional network, and the feature mapping formula is:

[0152]

[0153] Among them, F s represents the multi-scale feature map, W k is the kth convolution kernel, K represents the total number of convolution kernels, * represents the convolution operation, I e is the input enhanced image,

[0154] Calculate the edge gradient strength and capture the edge change characteristics. The calculation formula is:

[0155]

[0156] in, Indicates the gradient strength of edge changes,

[0157] and They are feature maps F s Partial derivatives in the x and y coordinate directions,

[0158] The texture characteristics of material degradation are extracted using the local texture descriptor. The formula is:

[0159]

[0160] Among them, T(x,y) represents the texture feature value, N represents the number of directions of texture calculation, i is the direction index of the current calculation, G i is the weighting factor of the i-th direction, φ(F s ,x,y) means the coordinate (x,y) is based on the feature F s Nonlinear texture transformation function;

[0161] In step S3, the attention mechanism is introduced:

[0162] By focusing on the detail changes in the solder joint area through the attention mechanism, the adjusted feature mapping formula is:

[0163] F a (x,y)=A(x,y)·F s (x,y),

[0164] Among them, F a (x, y) represents the feature map after attention mechanism adjustment, A(x, y) is the attention weight, W a is the weight parameter of the attention mechanism, F s (x,y) is the multi-scale eigenvalue at (x,y),

[0165] ∑ (x′,y′) exp(W a ·F s (x′, y′)) is a normalization factor used to perform weighted summation of features at all positions (x′, y′) on the entire feature map;

[0166] Combining multi-scale features, edge gradient features and texture features, we get the final comprehensive feature F out (x,y):

[0167]

[0168] Among them, F out (x, y) is the comprehensive feature of the final output, λ1, λ2, λ3 are weighting coefficients, which measure the importance of multi-scale features, edge gradients and texture features respectively;

[0169] Specifically, a multi-scale convolutional network is used to capture the microscopic characteristics of the solder joint area, edge gradient calculation is used to extract crack changes, local texture descriptors are combined to model material degradation characteristics, and an attention mechanism is used to focus on key details of potential defect areas. Finally, multi-scale characteristics, edge information and texture features are fully integrated to construct comprehensive features.

[0170] Step S4, using a classification model to classify and identify defects in the extracted microscopic characteristics, determine whether the solder joint has fatigue degradation or other problems, and generate a test result;

[0171] During the defect classification and identification process, solder joint defect comparison samples are introduced into the classification model, and the solder joint area is visually annotated, including the defect location and severity.

[0172] The steps of defect classification and identification of extracted microscopic features through classification model are as follows:

[0173] Define the classification model, and input the comprehensive feature F into the model out , the defect category C is predicted by the classification model, the formula is:

[0174] C=argmax(σ(W c ·F out +b c )),

[0175] Among them, C is the classification result, W c is the weight matrix of the classification model, b c is the classification bias, σ is the activation function,

[0176] In the process of classification model training, comparative samples of solder joint defects are introduced to optimize the loss function L c , the formula is:

[0177]

[0178] Among them, L c is the classification loss, N is the number of samples, y i represents the true label of sample i, p i The defect probability predicted by the model;

[0179] The steps to generate the test results are:

[0180] The solder joint defects are displayed by generating a visual annotation diagram. The annotation formula is:

[0181] I v (x,y)=I(x,y)+α·M(x,y),

[0182] Among them, I v (x,y) represents the visualized image after superimposition and annotation, I(x,y) is the original image, M(x,y) is the defect mask, α is the transparency factor,

[0183] The annotation content includes the defect location and its severity. The defect location is calculated using the mask:

[0184] If (x, y) belongs to the defect area, then M(x, y) = 1, otherwise M(x, y) = 0,

[0185] The severity S is defined as the ratio of the defect area to the total area of ​​the solder joint:

[0186]

[0187] Specifically, the classification model analyzes the microscopic features of the solder joints and optimizes training based on comparative samples to achieve the classification of solder joint defects. At the same time, it uses visualization technology to intuitively display the detection results, including the defect location and severity. Combined with the deep fusion of data-driven and image features, it not only improves the accuracy of defect classification, but also provides users with detection results.

[0188] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A chip defect visual detection method, characterized by: include, Step S1, collecting image information of the chip surface and interior by an imaging device; During the acquisition process, a multi-angle shooting strategy is used to capture image data, and an adaptive optical adjustment mechanism is combined to correct the optical path deviation; Step S2, performing denoising and enhancement processing on the collected image information to generate a feature map; In the denoising stage, a deep denoising network based on convolutional autoencoder (CAE) is introduced to learn the feature distribution of noise-free images, remove noise and retain the details of the solder joint area; In the enhancement stage, adaptive enhancement technology is used to process low-contrast areas to improve the visibility of features at the edges of solder joints; Step S3, extracting microscopic characteristics of the solder joint area from the feature map using a deep learning model; In step S3, a multi-scale convolutional network is used to capture the edge changes of the solder joint crack and the texture characteristics of material degradation to form the microscopic features of the solder joint. At the same time, an attention mechanism is combined to focus on the detailed changes in the solder joint area and concentrate computing resources on potential defect areas. Step S4, using a classification model to classify and identify defects in the extracted microscopic characteristics, determine whether the solder joint has fatigue degradation or other problems, and generate a test result; During the defect classification and identification process, a comparison sample of solder joint defects is introduced into the classification model, and the solder joint area is visually annotated, including the defect location and severity. The steps of classifying and distinguishing defects of the extracted microscopic characteristics by using the classification model are as follows: Define the classification model, and input the comprehensive feature F into the model out , the defect category C is predicted by the classification model, the formula is: C=argmax(σ(W c ·F out +b c )), Among them, C is the classification result, W c is the weight matrix of the classification model, b c is the classification bias, σ is the activation function, In the process of classification model training, comparative samples of solder joint defects are introduced to optimize the loss function L c , the formula is: Among them, L c is the classification loss, N is the number of samples, y i represents the true label of sample i, p i The defect probability predicted by the model; The steps of generating the test result are: The solder joint defects are displayed by generating a visual annotation diagram. The annotation formula is: I v (x,y)=I(x,y)+α·M(x,y), Among them, I v (x, y) represents the visualized image after superimposition and annotation, I(x, y) is the original image, M(c, y) is the defect mask, α is the transparency factor, The annotation content includes the defect location and its severity. The defect location is calculated using the mask: If (x, y) belongs to the defect area, then M(x, y) = 1, otherwise M(x, y) = 0, The severity S is defined as the ratio of the defect area to the total area of ​​the solder joint: S = defect area / total area of ​​solder joint; The step of collecting image information on the surface and interior of the chip is: During the acquisition process, the shooting angle set is defined as Θ={θ1,θ2,…,θ n }, the image corresponding to each shooting angle is I(θ i ), the complete collection image set is I set : I set ={I(θ1),I(θ2),…,I(θ n )}, Among them, θ i represents the i-th shooting angle, n represents the total number of shooting angles, Construct an optical path deviation correction model and define the optical path deviation distortion function as D(x, y, t). This describes the pixel offset introduced by the optical path deviation during the acquisition process. The model formula is: D(x,y,t)=α1x 2 +α2y 2 +βt, Where x and y are the horizontal and vertical coordinates of the pixel point, t is the acquisition time step, α1 and α2 represent the horizontal and vertical optical distortion coefficients respectively, and β represents the time-related distortion correction coefficient.

2. The chip defect visual detection method according to claim 1, wherein: The step of collecting image information of the chip surface and interior also includes: Perform image correction, the correction formula is: I c (x,y,θ i )=f c (I(x',y',θ i )), Among them, I(x',y',θ i ) is the original image, I c (x,y,θ i ) is the corrected image, f c (·) is the correction function, and the coordinates of the corrected position (x', y') are: in, and are the partial derivatives of the distortion function D(x,y,t) with respect to the x and y coordinates, respectively, used to describe the correction amount of the optical path deviation in the x and y directions. The corrected multi-angle image set is denoted as I set,c : I set,c ={I c (x,y,θ1),I c (x,y,θ2),…,I c (x,y,θ n )}, Among them, I c (x,y,θ i ) is the angle θ i The corrected image below.

3. The chip defect visual detection method according to claim 2, wherein: In the denoising stage of the step of performing denoising and enhancement processing on the collected image information to generate a feature map: The convolutional autoencoder is introduced to establish a denoising network, and the mapping relationship is: Where I is the input image, I d is the denoised image, Represents the nonlinear mapping function of the network, parameter W is the network weight matrix, b is the bias vector, The encoder is used to extract features. The CAE encoder converts the input image I into features F e , the formula is: F e =σ(W e ·I+b e ), Among them, F e represents the encoding feature, W e represents the convolution weight of the encoder, b e is the bias of the encoder, σ represents the activation function, using the ReLU function, The decoder passes F e Reconstruct denoised image I d , the reconstruction formula is: I d =σ(W d ·F e +b d ), Among them, W d is the deconvolution weight of the decoder, b d is the bias, The loss function is introduced for optimization, and the loss function L is: L=|I d -I clean | 2 +λ|F e -F e,clean | 2 , Among them, I clean is a noise-free image, F e,clean is the ideal feature distribution, and λ is the feature retention weight.

4. The chip defect visual detection method according to claim 3, wherein: In the enhancement phase of the step of performing denoising and enhancement processing on the collected image information to generate a feature map: For the denoised image I d Adaptive enhancement technology is used for optimization, and the enhanced image is I e , the enhancement formula is: I e (x,y)=I d (x,y)·(1+γ(x,y)), Among them, γ(x,y) is the enhancement coefficient, which describes the local contrast and is defined as: Where k is the enhancement factor, Histogram equalization is used to optimize low-contrast areas, and the enhancement formula is: Among them, H c (I e ) is the input image I e After histogram equalization, the mapping value P(I) represents the normalized probability distribution of image pixel intensity, and the calculation formula is: I e is the input enhanced image, and dI represents the integral variable.

5. The chip defect visual detection method according to claim 4, characterized in that: The step of extracting the microscopic characteristics of the solder joint area from the feature map using the deep learning model is as follows: The features of the solder joint area are extracted through a multi-scale convolutional network, and the feature mapping formula is: Among them, F s represents the multi-scale feature map, W k is the kth convolution kernel, K represents the total number of convolution kernels, * represents the convolution operation, I e is the input enhanced image, Calculate the edge gradient strength and capture the edge change characteristics. The calculation formula is: in, Indicates the gradient strength of edge changes, and They are feature maps F s Partial derivatives in the x and y coordinate directions, The local texture descriptor is used to extract the texture characteristics of material degradation. The formula is: Among them, T(x,y) represents the texture feature value, N represents the number of directions of texture calculation, i is the direction index of the current calculation, G i is the weighting factor of the i-th direction, φ(F s ,x,y) means the coordinate (x,y) is based on the feature F s Nonlinear texture transformation function.

6. The chip defect visual detection method according to claim 5, wherein: In step S3, the attention mechanism is introduced: By focusing on the detail changes in the solder joint area through the attention mechanism, the adjusted feature mapping formula is: Among them, F a (x, y) represents the feature map after attention mechanism adjustment, A(x, y) is the attention weight, W a is the weight parameter of the attention mechanism, F s (x,y) is the multi-scale eigenvalue at (x,y), ∑ (x',y') exp(W a ·F s (x',y')) is a normalization factor used to perform weighted summation of features at all positions (x',y') on the entire feature map; Combining multi-scale features, edge gradient features and texture features, we get the final comprehensive feature F out (x,y): Among them, F out (x, y) is the comprehensive feature of the final output, λ1, λ2, λ3 are weighting coefficients, which measure the importance of multi-scale features, edge gradients and texture features respectively.

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