Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes multiple bonding terminals located in a bonding area. The bonding terminals in the bonding area are divided into multiple units. The bonding terminals in the same unit are divided into a first terminal group, a second terminal group, a third terminal group, and a fourth terminal group. Each of the first, second, third, and fourth terminal groups includes multiple bonding terminals. The bonding terminals of the first, second, and third terminal groups are configured to be bonded to the output terminals of a test chip, and the bonding terminals of the fourth terminal group are configured to be bonded to the input terminals of the test chip. In the same unit, the second terminal group is located on the side of the first terminal group furthest from the display area, the fourth terminal group is located on the side of the second terminal group furthest from the display area, the third terminal group is located on the side of the second terminal group furthest from the display area, and the fourth terminal group is located on the side of the fourth terminal group closest to the display area. This allows for a narrow bezel design of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a display device. Background Technology

[0002] With the development of display technology, consumers have an increasingly strong demand for narrow bezels in display panels. The bezel area of ​​the display panel houses a test chip. The test circuitry on the chip is used to detect defects such as short circuits or open circuits, improving the panel's yield. This test circuitry includes multiple rows of switching transistors, occupying a significant portion of the bezel area. To achieve narrow bezels, one approach is to reduce the space occupied by the switching transistors, further minimizing the size of the test chip. One solution employed in related technologies is to adjust the manufacturing process to reduce the size of the switching transistors, ensuring the same number of transistors can be placed within the limited space after bezel reduction. However, process adjustments increase manufacturing complexity and may even reduce production yield. Summary of the Invention

[0003] This application addresses the shortcomings of related technologies by proposing a display panel and display device to solve the problem in related technologies of how to reduce the size of test chips while placing a constant number and size of switching transistors within a limited space.

[0004] This application provides a display panel, which includes a display area and a non-display area located on at least one side of the display area; the non-display area includes a binding area located on one side of the display area;

[0005] The display panel includes multiple bonding terminals located in the bonding area. The multiple bonding terminals in the bonding area are divided into multiple units, each unit including multiple bonding terminals. The bonding terminals of each unit are bonded to a test chip. The bonding terminals in the same unit are divided into a first terminal group, a second terminal group, a third terminal group, and a fourth terminal group. The first terminal group, the second terminal group, the third terminal group, and the fourth terminal group each include multiple bonding terminals. The bonding terminals of the first terminal group, the second terminal group, and the third terminal group are configured to be bonded to the output terminals of the test chip, and the bonding terminals of the fourth terminal group are configured to be bonded to the input terminals of the test chip.

[0006] In the same unit, the second terminal group is located on the side of the first terminal group away from the display area, the fourth terminal group is located on the side of the second terminal group away from the display area, and the third terminal group is located on the side of the second terminal group away from the display area and the side of the fourth terminal group close to the display area; the direction from the display area to the binding area is the first direction, and the binding terminals of the first terminal group and the binding terminals of the second terminal group are arranged along a second direction intersecting the first direction.

[0007] In some embodiments, in the same unit, the first terminal group, the second terminal group and the third terminal group are arranged in the direction from the display area to the binding area.

[0008] In some embodiments, the distance between the third terminal group and the second terminal group is less than the distance between the third terminal group and the fourth terminal group.

[0009] In some embodiments, the bonding area includes a first side and a second side opposite to each other in the second direction; in the unit adjacent to the first side, the bonding terminal of the third terminal group is located on the side of the second terminal group facing the first side away from the display area; and / or, in the unit adjacent to the second side, the bonding terminal of the third terminal group is located on the side of the second terminal group facing the second side away from the display area.

[0010] In some embodiments, the third terminal group includes at least two sub-terminal groups arranged along the second direction, each of the sub-terminal groups including a plurality of bonding terminals arranged along the first direction.

[0011] This embodiment also provides a display device, including the aforementioned display panel and a test chip located in the bonding area of ​​the display panel. The test chip is provided with a test circuit, which includes a plurality of electrically connected switching transistors. Each switching transistor is configured to be connected to a corresponding output terminal of the test chip. The width of the switching transistor is T, the width of the trace connected to the switching transistor is W, the minimum distance between the centerlines of two adjacent traces is S, and the distance in the second direction between the geometric center of the bonding terminal of the first terminal group and the geometric center of the bonding terminal of the second terminal group adjacent to the bonding terminal is p1.

[0012] In some embodiments, the multiple switching transistors of the same test circuit include a first switching transistor group and a second switching transistor group. The multiple switching transistors in the first switching transistor group and the multiple switching transistors in the second switching transistor group are alternately distributed in the second direction, and the switching transistors in the first switching transistor group and the adjacent switching transistors in the second switching transistor group are staggered in the first direction. In the same unit, when the first terminal group, the second terminal group and the third terminal group are arranged in the direction from the display area to the bonding area, the multiple bonding terminals in the first terminal group, the second terminal group and the third terminal group are alternately distributed in the second direction, and the bonding terminals in the first terminal group and the adjacent bonding terminals in the second terminal group are staggered in the first direction. The bonding terminals in the second terminal group and the adjacent bonding terminals in the third terminal group are staggered in the first direction. Each switching transistor is connected to a corresponding bonding terminal.

[0013] In some embodiments, the bonding terminals of the third terminal group are arranged along a second direction intersecting the first direction; the orthographic projections of the plurality of switching transistors on the surface of the display panel facing the test chip are all located between the third terminal group and the fourth terminal group; the plurality of switching transistors in the first switching transistor group and the plurality of switching transistors in the second switching transistor group are arranged along a second direction intersecting the first direction; the geometric center of the bonding terminal of the second terminal group is adjacent to the bonding terminal and is located at a distance p2 from the geometric center of the bonding terminal of the third terminal group in the second direction.

[0014] In some embodiments, the plurality of switching transistors are disposed on the side of the fourth terminal group near the display area.

[0015] In some embodiments, the bonding area includes a first side and a second side opposite to each other in the second direction, and in a unit adjacent to the first side, when the bonding terminal of the third terminal group is located on the side of the second terminal group facing the first side away from the display area, the first orthographic projections of the plurality of switching transistors connected to the bonding terminals of the first terminal group and the second terminal group on the surface of the display panel facing the test chip are all located between the second terminal group and the fourth terminal group, and the second orthographic projections of the plurality of switching transistors connected to the bonding terminals of the third terminal group on the surface are located on the side of the first orthographic projection facing the first side away from the display area;

[0016] And / or, the bonding area includes a first side and a second side opposite to each other in the second direction, and in a unit adjacent to the second side, when the bonding terminal of the third terminal group is located on the side of the second terminal group facing the second side away from the display area; the first orthographic projections of the plurality of switching transistors connected to the bonding terminals of the first terminal group and the second terminal group on the surface of the display panel facing the test chip are all located between the second terminal group and the fourth terminal group, and the second orthographic projections of the plurality of switching transistors connected to the bonding terminals of the third terminal group on the surface are located on the side of the first orthographic projection facing the second side away from the display area.

[0017] In some embodiments, the third terminal group includes a first sub-terminal group and a second sub-terminal group arranged along the second direction. Both the first and second sub-terminal groups include multiple bonding terminals arranged along the first direction. The bonding terminals in the first sub-terminal group and the bonding terminals in the second sub-terminal group are alternately distributed along the first direction, and the bonding terminals in the first sub-terminal group and their adjacent bonding terminals in the second sub-terminal group are staggered along the second direction. The geometric center of a bonding terminal in the first sub-terminal group is adjacent to the bonding terminal, and the distance along the first direction from the geometric center of the bonding terminal in the second sub-terminal group is p3.

[0018] In some embodiments, the orthographic projection of the third terminal group on the first side of the bonding area at least partially overlaps with the orthographic projection of the fourth terminal group on the first side of the bonding area.

[0019] The beneficial effects of this application include:

[0020] In this embodiment, the bonding terminals bound to the output terminals of the test chip in each unit are arranged as a first terminal group, a second terminal group, and a third terminal group. The third terminal group is located on the side of the second terminal group away from the display area and the side of the fourth terminal group close to the display area. Compared with the scheme of only arranging one terminal group or two terminal groups, the number of bonding terminals in the first terminal group and the second terminal group can be reduced without changing the number of bonding terminals bound to the output terminals of the test chip. This allows the distance p between the geometric center of the bonding terminal in the first terminal group and the geometric center of the bonding terminal in the second terminal group in the second direction to be increased. Furthermore, the arrangement of the switching transistors on the test chip can be changed accordingly, increasing the density of the switching transistor arrangement. This allows the number and size of the switching transistors to be arranged on a smaller test chip, thereby further reducing the area of ​​the bonding area of ​​the display panel and facilitating the narrowing of the display panel bezel.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] Figure 1 The diagram shown is an exemplary structural schematic of a display panel;

[0024] Figure 2 The diagram shown is a schematic representation of the layout structure of the bonding area of ​​a display panel / display device provided in an exemplary embodiment of this application.

[0025] Figure 3 The diagram shown is a schematic representation of the layout structure of the bonding area of ​​a display panel / display device provided in an exemplary embodiment of this application.

[0026] Figure 4 The diagram shown is a schematic representation of the layout structure of the bonding area of ​​a display panel / display device provided in an exemplary embodiment of this application.

[0027] Figure 5 As shown Figure 4 A comparison diagram of the enlarged layout structure diagram at point A in the middle and the layout structure diagram of the display panel provided in an exemplary embodiment;

[0028] Figure 6 The image shows a comparison of the layout structure data of the display panel in the related technology and an exemplary embodiment of this application.

[0029] In the diagram: 100 - Bonding terminal; 10 - First terminal group; 20 - Second terminal group; 30 - Third terminal group; 31 - First sub-terminal group; 32 - Second sub-terminal group; 40 - Fourth terminal group; 200 - Switching transistor; 50 - First switching transistor group; 60 - Second switching transistor group; 1 - First scan signal bonding unit; 2 - Data signal bonding unit; 3 - Second scan signal bonding unit; AA - Display area; NA - Non-display area; BA - Bonding area; L1 - First side; L2 - Second side. Detailed Implementation

[0030] The display panel and display device in the embodiments of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments may complement or combine with each other.

[0031] This application embodiment provides a display panel, combined with Figures 1 to 5 As shown, where, Figure 1The diagram shown is a schematic of the display panel layout. Figures 2 to 4 The diagram shown is a schematic representation of the layout structure of the binding area BA of the display panel in several exemplary embodiments provided in this application. Figure 5 As shown Figure 4 A comparison diagram of the enlarged structural schematic diagram at point A in the middle and a schematic diagram of the layout structure of a display panel provided in an exemplary embodiment. For example... Figure 1 As shown, the display panel includes a display area AA and a non-display area NA located on at least one side of the display area AA; the non-display area NA includes a bonding area BA located on one side of the display area AA; as Figure 2 As shown, the display panel includes multiple bonding terminals 100 located in the bonding area BA. The bonding terminals 100 in the bonding area BA are divided into multiple units, each unit including multiple bonding terminals 100. Each unit's bonding terminals 100 are bonded to a test chip. The bonding terminals 100 in the same unit are divided into a first terminal group 10, a second terminal group 20, a third terminal group 30, and a fourth terminal group 40. The first terminal group 10, second terminal group 20, third terminal group 30, and fourth terminal group 40 each include multiple bonding terminals 100. The bonding terminals 100 of the first terminal group 10, second terminal group 20, and third terminal group 30 are configured to bond with a test chip. The output terminals of the test chip are bonded, and the bonding terminals 100 of the fourth terminal group 40 are configured to bond with the input terminals of the test chip. In the same unit, the second terminal group 20 is located on the side of the first terminal group 10 away from the display area AA, the fourth terminal group 40 is located on the side of the second terminal group 20 away from the display area AA, and the third terminal group 30 is located on the side of the second terminal group 20 away from the display area AA and the side of the fourth terminal group 40 close to the display area AA. The direction from the display area AA to the bonding area BA is the first direction y, and the bonding terminals 100 of the first terminal group 10 and the bonding terminals 100 of the second terminal group 20 are arranged along the second direction x, which intersects with the first direction y.

[0032] In this embodiment, the bonding terminals bound to the output terminals of the test chip in each unit are arranged as a first terminal group 10, a second terminal group 20, and a third terminal group 30. The third terminal group 30 is located on the side of the second terminal group 20 away from the display area AA and the side of the fourth terminal group 40 close to the display area AA. Compared with the scheme of only arranging one terminal group or two terminal groups, the number of bonding terminals 100 in the first terminal group and the second terminal group can be reduced without changing the number of bonding terminals bound to the output terminals of the test chip. This allows the distance p between the geometric center of the bonding terminal 100 in the first terminal group 10 and the geometric center of the bonding terminal 100 in the second terminal group 20 in the second direction x to be increased. This can further change the arrangement of the switching transistors 200 on the test chip, increase the density of the switching transistors 200, and enable the same number and size of switching transistors 200 to be arranged on a smaller test chip. This further reduces the area of ​​the bonding area BA of the display panel, which is beneficial for the narrow bezel of the display panel.

[0033] For example, in this embodiment, by increasing p, the arrangement of the switching transistors 200 on the test chip can be further changed, combined with Figure 5 As shown, the stepped array arrangement of three adjacent switching transistors 200 in three rows in a specific exemplary embodiment of the related technology is improved to the stepped array arrangement of two adjacent switching transistors 200 in two rows in this embodiment. This improves the arrangement without changing the size of the switching transistors 200 themselves or the line width and spacing of the traces connected to them, while reducing the length occupied by the switching transistors 200 in the first direction y. Furthermore, due to the increased density of the switching transistors 200, the overall length occupied by the switching transistors 200 in the second direction x changes less when arranging the same number of switching transistors 200. Moreover, the reduced length of the test chip in the first direction y is beneficial for achieving narrower bezels in the display panel.

[0034] In one example, such as Figure 6 The table shown is a comparison of structural parameters between related technologies and an exemplary embodiment of this application. Figure 5As shown, the width T of the switching transistor 200 remains unchanged at 14μm; the line width W of the line connecting the switching transistor 200 remains unchanged at 16μm; and the line spacing S remains unchanged at 5μm. The distance p between the geometric center of the bonding terminal 100 in the first terminal group 10 and the geometric center of the bonding terminal 100 adjacent to it in the second terminal group 20 in the second direction x increases from 14μm in related technologies to 15μm. The arrangement of the switching transistors 200 changes from 3 rows to 2 rows. The length occupied by the test chip in the first direction y decreases from 333μm to 220μm, a reduction of 113μm, indicating a significant decrease in the length of the test chip in the first direction y. Simultaneously, the length occupied by the switching transistor 200 in the second direction x increases from 84μm to 90μm. This shows that the overall increase in the length of the switching transistor 200 in the second direction x is relatively small, having a minor impact on the overall size in the second direction x. In summary, by increasing p, the size of the test chip can be reduced, further improving the overall narrow bezel of the display panel.

[0035] In some embodiments, such as Figure 2 As shown, the multiple binding terminals 100 of the binding area BA are divided into a first scan signal binding unit 1, a data signal binding unit 2, and a second scan signal binding unit 3. Each unit includes multiple binding terminals 100, and the binding terminals 100 of each unit are respectively bound to the corresponding test chip. The binding terminals of the first terminal group 10, the second terminal group 20, and the third terminal group 30 in the first scan signal binding unit 1 and the second scan signal binding unit 3 are connected to the scan line on the side closest to the display area AA, and the side furthest from the display area AA is used to connect to the corresponding switching transistor 200 in the test circuit on the test chip for circuit testing. Similarly, the first terminal group 10, the second terminal group 20, and the third terminal group 30 in the data signal binding unit 2 are connected to the data line on the side closest to the display area AA, and the side furthest from the display area AA is used to connect to the corresponding switching transistor 200 in the test circuit on the test chip for circuit testing.

[0036] In some embodiments, the switching transistor 200 connected to the binding terminal 100 in the first scan signal binding unit 1 is connected to the gate drive signal line (GO), the switching transistor 200 connected to the binding terminal 100 in the second scan signal binding unit 3 is connected to the gate enable signal line (GE), and the switching transistor 200 connected to the binding terminal 100 in the data signal binding unit 2 is connected to the data output signal line (DO) and the timing control signal line (DE).

[0037] In some embodiments, the display panel may be an electronic paper display panel, an LCD (liquid crystal display) or an OLED (organic light-emitting diode).

[0038] In some embodiments, the bonding terminals 100 of the first terminal group 10 and the bonding terminals 100 of the second terminal group 20 are respectively arranged at intervals along the second direction x.

[0039] In some embodiments, the lengths of the bonding terminals 100 in the first terminal group 10 and / or the second terminal group 20 are the same in the first direction y. In other embodiments, the lengths of the bonding terminals 100 in the first terminal group 10 and / or the second terminal group 20 are not the same in the first direction y.

[0040] In some embodiments, the lengths of the bonding terminals 100 in the first terminal group 10 and / or the second terminal group 20 are the same in the second direction x. In other embodiments, the lengths of the bonding terminals 100 in the first terminal group 10 and / or the second terminal group 20 are not the same in the second direction x.

[0041] In some embodiments, each bonding terminal 100 in the first terminal group 10 and / or the second terminal group 20 is a bonding pad.

[0042] In some embodiments, the projection shape of each bonding terminal 100 in the first terminal group 10 and / or the second terminal group 20 on the display panel is rectangular.

[0043] In some embodiments, such as Figure 2 As shown, in the same unit, the first terminal group 10, the second terminal group 20 and the third terminal group 30 are arranged in the direction from the display area AA to the binding area BA.

[0044] In this embodiment, a first terminal group 10, a second terminal group 20, and a third terminal group 30 are arranged sequentially in the same direction in each unit. The arrangement of the first terminal group 10, the second terminal group 20, and the third terminal group 30 is relatively regular, and the wiring arrangement connected to the multiple binding terminals 100 in the first terminal group 10, the second terminal group 20, and the third terminal group 30 is relatively consistent. This makes it easier to wire and bind to the test chip, avoiding signal crosstalk caused by overlapping wiring.

[0045] In some embodiments, considering that the arrangement of the third terminal group 30 will increase the area occupied by the bonding terminal 100 in the first direction y, the length L of the bonding terminal 100 in the first terminal group 10 and the second terminal group 20 in the first direction y can be reduced. At the same time, in order to ensure the bonding contact area requirement of the chip bonding terminal 100, the width W of the bonding terminal 100 in the first terminal group 10 and the second terminal group 20 in the second direction x can be further increased to keep the area of ​​the bonding terminal 100 approximately unchanged.

[0046] In some examples, such as Figure 2As shown, the area of ​​the bonding terminal 100 in this embodiment is 1125 μm. 2 ≤W*L≤1300μm 2 The values ​​of W and L are respectively: W≥13μm, 70μm≤L≤75μm.

[0047] In some embodiments, such as Figure 2 As shown, the distance between the geometric center of the bonding terminal 100 in the first terminal group 10 and the geometric center of the bonding terminal 100 in the second terminal group 20 located in the second direction x is p1, 15μm≤p1≤16μm.

[0048] In some embodiments, the distance between the geometric center of the bonding terminal 100 in the second terminal group 20 and the geometric center of the bonding terminal 100 in the third terminal group 30, which is adjacent to the bonding terminal 100, and located in the second direction x, is p2, where 15μm≤p2≤16μm.

[0049] In some embodiments, the distance between the third terminal group 30 and the second terminal group 20 is less than the distance between the third terminal group 30 and the fourth terminal group 40.

[0050] In this embodiment, the switching transistor 200 can be arranged between the third terminal group 30 and the fourth terminal group 40, so that the third terminal group 30, the second terminal group 20 and the first terminal group 10 are all located on the side of the switching transistor 200 close to the display area AA, so that the bonding terminal 100 can be directly connected to the switching transistor 200. This facilitates the design of straight wiring without bending, saves wiring space, and improves the space utilization of the bonding area BA of the display panel.

[0051] In some embodiments, the multiple bonding terminals 100 of the same unit also include a fifth terminal group (not shown in the figure) located on the side of the third terminal group 30 near the fourth terminal group 40, so as to further increase the spacing between adjacent bonding terminals 100, so as to flexibly configure the arrangement of the switching transistors 200.

[0052] In some embodiments, such as Figure 3 As shown, the bonding area BA includes a first side L1 and a second side L2 opposite to each other in the second direction x; in the unit adjacent to the first side L1, the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the first side L1 away from the display area AA; and / or, in the unit adjacent to the second side L2, the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the second side L2 away from the display area AA.

[0053] In this embodiment, the multiple bonding terminals 100 of the third terminal group 30 are located in the side space, which can prevent the third terminal group 30 from occupying the space on the side of the second terminal group 20 away from the display area AA. It can further prevent the space occupied by the third terminal group 30 from increasing the overall length of the multiple bonding terminals 100 in the first direction y. Therefore, the space of the non-display area NA can be fully utilized while improving the narrow bezel of the display panel.

[0054] In addition, in this embodiment, in the unit adjacent to the first side L1, the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the first side L1 away from the display area AA. This allows the bonding terminals 100 in the third terminal group 30 and the bonding terminals 100 in the second terminal group 20 to be connected to the switching transistor 200 via straight traces. Specifically, multiple bonding terminals 100 in the second terminal group 20 can be connected to the switching transistor 200 on the test chip via traces extending along the first direction y, and multiple bonding terminals 100 in the third terminal group 30 can be connected to the switching transistor 200 on the test chip via traces extending along the second direction x. Similarly, in the unit adjacent to the second side L2, when the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the second side L2 away from the display area AA, it has the same beneficial effect. Further details are omitted here.

[0055] In some embodiments, the bonding area BA includes a first side L1 and a second side L2 that are opposite each other in the second direction x; in the unit adjacent to the first side L1, the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the first side L1 away from the display area AA.

[0056] In some embodiments, the bonding area BA includes a first side L1 and a second side L2 that are opposite each other in the second direction x; in the unit adjacent to the second side L2, the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the second side L2 away from the display area AA.

[0057] In some embodiments, such as Figure 3 As shown, the bonding area BA includes a first side L1 and a second side L2 opposite to each other in the second direction x; in the unit adjacent to the first side L1, the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the first side L1 away from the display area AA. In the unit adjacent to the second side L2, the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the second side L2 away from the display area AA.

[0058] In some embodiments, the third terminal group 30 includes at least two sub-terminal groups arranged along the second direction x, and each sub-terminal group includes multiple bonding terminals 100 arranged along the first direction y. This embodiment is adaptable to situations where the test chip is bonded to the bonding area BA, and the test chip is provided with multiple sets of switching transistors 200, and the multiple sub-terminal groups arranged along the second direction x in the third terminal group 30 can be respectively connected to each set of switching transistors 200.

[0059] In some embodiments, such as Figure 3 As shown, the third terminal group 30 includes a first sub-terminal group 31 and a second sub-terminal group 32 arranged along the second direction x. The test chip bound to the binding area BA has two sets of staggered switching transistors 200. Multiple binding terminals 100 in the first sub-terminal group 31 are respectively connected to one set of switching transistors 200, and multiple binding terminals 100 in the second sub-terminal group 32 are respectively connected to the remaining set of switching transistors 200.

[0060] Based on the same inventive concept, this embodiment also provides a display device, such as... Figure 2 As shown, the device includes the aforementioned display panel and a test chip located on the bonding area BA of the display panel. The test chip is equipped with a test circuit, which includes multiple electrically connected switching transistors 200. Each switching transistor 200 is configured to be connected to the output terminal of the corresponding test chip. The width of the switching transistor 200 is T, the width of the trace connected to the switching transistor 200 is W, the minimum distance between the centerlines of two adjacent traces is S, and the distance between the geometric center of the bonding terminal 100 of the first terminal group 10 and the geometric center of the bonding terminal 100 of the second terminal group 20 in the second direction x is p1.

[0061] This embodiment can achieve the most compact arrangement of the switching transistors 200 by setting the value range of p1, thereby reducing the length occupied by multiple switching transistors 200 in the first direction y, thus reducing the size of the test chip and improving the narrow bezel of the display panel.

[0062] In one example, the width T of the switching transistor 200 is 14 μm, the line width W of the line connecting the switching transistor 200 is 6 μm, the line spacing S is 5 μm, and p1 ≥ 15 μm.

[0063] In some embodiments, such as Figure 2As shown, the multiple switching transistors 200 in the same test circuit include a first switching transistor group 50 and a second switching transistor group 60. The multiple switching transistors 200 in the first switching transistor group 50 and the multiple switching transistors 200 in the second switching transistor group 60 are alternately distributed in the second direction x. The switching transistors 200 in the first switching transistor group 50 and the adjacent switching transistors 200 in the second switching transistor group 60 are staggered in the first direction y. In the same unit, when the first terminal group 10, the second terminal group 20 and the third terminal group 30 are arranged in the direction from the display area to the bonding area, the multiple bonding terminals in the first terminal group 10, the second terminal group 20 and the third terminal group 30 are alternately distributed in the second direction x. The bonding terminals 100 in the first terminal group 10 and the adjacent bonding terminals 100 in the second terminal group 20 are staggered in the first direction y. The bonding terminals in the second terminal group 20 and the adjacent bonding terminals 100 in the third terminal group 30 are staggered in the first direction y. Each switching transistor 200 is connected to the corresponding bonding terminal 100.

[0064] In this embodiment, the multiple switching transistors 200 in the first switching transistor group 50 and the second switching transistor group 60 are alternately staggered, and the multiple bonding terminals 100 in the first terminal group 10, the second terminal group 20 and the third terminal group 30 can be arranged more compactly, making full use of the space of the test chip. As a result, the size of the test chip can be reduced, and the narrow bezel of the display panel can be further improved.

[0065] In some embodiments, a plurality of switching transistors 200 are disposed on the side of the fourth terminal group 40 near the display area AA.

[0066] In this embodiment, the switching transistor 200 can be connected to the first terminal group 10, the second terminal group 20, and the third terminal group 30 through a trace extending along the first direction y, which is compact and conducive to the narrow bezel of the display panel.

[0067] In some embodiments, such as Figure 2 As shown, the bonding terminals 100 of the third terminal group 30 are arranged along a second direction x intersecting the first direction y. The orthographic projections of multiple switching transistors 200 on the surface of the display panel facing the test chip are all located between the third terminal group 30 and the fourth terminal group 40. Multiple switching transistors 200 in the first switching transistor group 50 and multiple switching transistors 200 in the second switching transistor group 60 are also arranged along a second direction x intersecting the first direction y. The geometric center of the bonding terminal 100 of the second terminal group 20 is adjacent to the geometric center of the bonding terminal 100 of the third terminal group 30 in the second direction x, and the distance between them and the geometric center in the second direction x is p2. Similarly to the previous embodiments, in this embodiment, by increasing p2, the arrangement of the switching transistors 200 can be flexibly adjusted, the compactness of the switching transistors 200 can be improved, thereby reducing the size of the test chip and improving the narrow bezel of the display panel.

[0068] In some embodiments, such as Figure 3 As shown, the bonding area BA includes a first side L1 and a second side L2 opposite to each other in the second direction x; and in the unit adjacent to the first side L1, when the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the first side L1 away from the display area AA, the first orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located on the side of the first orthographic projection facing the first side L1 and away from the display area AA;

[0069] And / or, the bonding area BA includes a first side L1 and a second side L2 opposite to each other in the second direction x; in the unit adjacent to the second side L2, when the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the second side L2 away from the display area AA, the first orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located on the side of the first orthographic projection facing the second side L2 away from the display area AA.

[0070] In this embodiment, multiple switching transistors 200 connected to the bonding terminals 100 of the first terminal group 10 and the second terminal group 20 can be connected to the multiple bonding terminals 100 of the first terminal group 10 and the second terminal group 20 through traces extending along the first direction y. Multiple switching transistors 200 connected to the bonding terminals 100 of the third terminal group 30 can be connected to the multiple bonding terminals 100 of the third terminal group 30 through traces extending along the second direction x. Therefore, it is possible to connect the switching transistors 200 and the bonding terminals 100 with shorter traces, which can simplify the wiring process and save wiring costs.

[0071] In some embodiments, the bonding area BA includes a first side L1 and a second side L2 opposite to each other in the second direction x; and in the unit adjacent to the first side L1, when the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the first side L1 away from the display area AA, the first orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located on the side of the first orthographic projection facing the first side L1 and away from the display area AA.

[0072] In some embodiments, the bonding area BA includes a first side L1 and a second side L2 opposite to each other in the second direction x; in the unit adjacent to the second side L2, when the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the second side L2 away from the display area AA, the first orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located on the side of the first orthographic projection facing the second side L2 away from the display area AA.

[0073] In some embodiments, the bonding area BA includes a first side L1 and a second side L2 opposite to each other in the second direction x; and in the unit adjacent to the first side L1, when the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the first side L1 away from the display area AA, the first orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located in the area where the first orthographic projection faces the first side L1 and away from the display area AA. One side of A; the bonding area BA includes a first side L1 and a second side L2 opposite to each other in the second direction x; in the unit adjacent to the second side L2, when the bonding terminal 100 of the third terminal group 30 is located on the side of the second terminal group 20 facing the second side L2 away from the display area AA, the first orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switching transistors 200 connected to the bonding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located on the side of the first orthographic projection facing the second side L2 away from the display area AA.

[0074] In some embodiments, such as Figure 3 As shown, the third terminal group 30 includes a first sub-terminal group 31 and a second sub-terminal group 32 arranged along the second direction x. Both the first sub-terminal group 31 and the second sub-terminal group 32 include multiple bonding terminals 100 arranged along the first direction y. The bonding terminals 100 in the first sub-terminal group 31 and the bonding terminals 100 in the second sub-terminal group 32 are alternately distributed along the first direction y, and the bonding terminals 100 in the first sub-terminal group 31 and their adjacent bonding terminals 100 in the second sub-terminal group 32 are staggered along the second direction. The distance between the geometric center of a bonding terminal 100 in the first sub-terminal group 31 and the geometric center of the bonding terminal 100 in the second sub-terminal group 32 along the first direction y is p3.

[0075] Similarly to the previous embodiment, in this embodiment, by increasing p, the arrangement of multiple switching transistors 200 in the second switching transistor section 202 located in the side space can be adjusted to make the arrangement of the switching transistors 200 more compact, avoid occupying too much layout space, and leave more space for the layout of other devices.

[0076] In some embodiments, the orthographic projection of the third terminal group 30 on the first side L1 of the bonding area BA at least partially overlaps with the orthographic projection of the fourth terminal group 40 on the first side L1 of the bonding area BA. This allows for a more compact layout of the third terminal group 30 and the fourth terminal group 40, making full use of the space in the bonding area BA of the display panel, shortening the wiring, and saving wiring costs.

[0077] In some embodiments, such as Figure 4 As shown, in this embodiment, the third terminal group 30 can be simultaneously disposed between the second terminal group 20 and the fourth terminal group 40 and in the side space of the second terminal group 20. Its beneficial effects are the same as those in the aforementioned embodiment, and will not be repeated here.

[0078] It should be noted that the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," "third," or "fourth" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

Claims

1. A display device, comprising a display panel and a test chip located in a bonding area of the display panel, the display panel comprising a display area and a non-display area located at least one side of the display area; the non-display area comprising a bonding area located at one side of the display area; The display panel includes a plurality of binding terminals located at the binding area, the plurality of binding terminals of the binding area are divided into a plurality of units, each unit includes a plurality of binding terminals, and the binding terminals of each unit are bound with one test chip. bonding terminals of the same unit are divided into a first terminal group, a second terminal group, a third terminal group and a fourth terminal group; the first terminal group, the second terminal group, the third terminal group and the fourth terminal group each comprise a plurality of bonding terminals, the bonding terminals of the first terminal group, the second terminal group and the third terminal group are configured to be bonded with output terminals of the test chip, and the bonding terminals of the fourth terminal group are configured to be bonded with input terminals of the test chip; in the same unit, the second terminal group is located at a side of the first terminal group away from the display area, the fourth terminal group is located at a side of the second terminal group away from the display area, and the third terminal group is located at a side of the second terminal group away from the display area and a side of the fourth terminal group close to the display area; a direction in which the display area points to the bonding area is a first direction, and the bonding terminals of the first terminal group and the bonding terminals of the second terminal group are arranged along a second direction intersecting the first direction; The test chip is provided with a test circuit, the test circuit comprises a plurality of electrically connected switching transistors, each of the switching transistors is configured to be connected with a corresponding output terminal of the test chip, the width of the switching transistor is T, the width of the wire connected with the switching transistor is W, the minimum distance between the central axes of two adjacent wires is S, the distance between the geometric center of the binding terminal of the first terminal group and the geometric center of the binding terminal adjacent to the binding terminal of the second terminal group in the second direction is p1, p1≥ .

2. The display device according to claim 1, wherein in the same unit, the first terminal group, the second terminal group and the third terminal group are arranged in the direction in which the display area points to the bonding area.

3. The display device according to claim 2, wherein The distance between the third terminal group and the second terminal group is less than the distance between the third terminal group and the fourth terminal group.

4. The display device according to claim 1, wherein The bonding area comprises a first side and a second side opposite in the second direction; in the unit adjacent to the first side, the bonding terminals of the third terminal group are located at a side of a region of the second terminal group facing the first side away from the display area; and / or in the unit adjacent to the second side, the bonding terminals of the third terminal group are located at a side of a region of the second terminal group facing the second side away from the display area.

5. The display device according to claim 4, wherein The third terminal group comprises at least two sub-terminal groups arranged along the second direction, and each of the sub-terminal groups comprises a plurality of bonding terminals arranged along the first direction.

6. The display device according to claim 1, wherein The plurality of switch transistors of the same test circuit comprises a first group of switch transistors and a second group of switch transistors, the plurality of switch transistors in the first group of switch transistors and the plurality of switch transistors in the second group of switch transistors are alternately arranged in the second direction, and the switch transistors in the first group of switch transistors and the switch transistors adjacent to the switch transistors in the second group of switch transistors are staggered arranged in the first direction; in the same unit, when the first terminal group, the second terminal group and the third terminal group are arranged in the direction of the display area pointing to the binding area, the plurality of binding terminals in the first terminal group, the second terminal group and the third terminal group are alternately arranged in the second direction, and the binding terminals in the first terminal group and the binding terminals adjacent to the binding terminals in the second terminal group are staggered arranged in the first direction, the binding terminals in the second terminal group and the binding terminals adjacent to the binding terminals in the third terminal group are staggered arranged in the first direction, and each of the switch transistors is connected with the corresponding binding terminal.

7. The display device according to claim 6, wherein The binding terminals of the third terminal group are arranged along a second direction intersecting the first direction, the orthographic projections of the plurality of switch transistors on the surface of the display panel facing the test chip are all located between the third terminal group and the fourth terminal group, and the plurality of switch transistors in the first switch transistor group and the plurality of switch transistors in the second switch transistor group are both arranged along the second direction intersecting the first direction; the geometric center of the binding terminal of the second terminal group is adjacent to the geometric center of the binding terminal of the third terminal group in the second direction, and the distance between the geometric center of the binding terminal of the second terminal group and the geometric center of the binding terminal of the third terminal group in the second direction is p2, p2≥ .

8. The display device according to claim 1, wherein A plurality of switch transistors are arranged on the side of the fourth terminal group close to the display area.

9. The display device according to claim 1, wherein The binding area comprises a first side and a second side opposite in the second direction, and in the unit adjacent to the first side, when the binding terminals of the third terminal group are located on the side away from the display area of the region of the second terminal group facing the first side, the first projections of the plurality of switch transistors connected with the binding terminals of the first terminal group and the second terminal group on the surface of the display panel facing the test chip are all located between the second terminal group and the fourth terminal group, and the second projections of the plurality of switch transistors connected with the binding terminals of the third terminal group on the surface are located on the side away from the display area of the region of the first projections facing the first side. And / or, the binding area comprises a first side and a second side opposite in the second direction, and in the unit adjacent to the second side, when the binding terminals of the third terminal group are located on the side away from the display area of the region of the second terminal group facing the second side; the first projections of the plurality of switch transistors connected with the binding terminals of the first terminal group and the second terminal group on the surface of the display panel facing the test chip are all located between the second terminal group and the fourth terminal group, and the second projections of the plurality of switch transistors connected with the binding terminals of the third terminal group on the surface are located on the side away from the display area of the region of the first projections facing the second side.

10. The display device according to claim 9, wherein The third terminal set comprises a first sub-terminal set and a second sub-terminal set arranged along the second direction, and each of the first sub-terminal set and the second sub-terminal set comprises a plurality of bundled terminals arranged along the first direction; the bundled terminals in the first sub-terminal set and the bundled terminals in the second sub-terminal set are alternately distributed along the first direction, and the bundled terminals in the first sub-terminal set and the bundled terminals adjacent to the bundled terminals in the second sub-terminal set are staggered arranged along the second direction; the distance between the geometric center of the bundled terminal in the first sub-terminal set and the geometric center of the bundled terminal adjacent to the bundled terminal in the second sub-terminal set in the first direction is p3, and p3≥ .

11. The display device according to claim 9, wherein The projection of the third terminal group on the first side of the binding area at least partially overlaps with the projection of the fourth terminal group on the first side of the binding area.

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