Sense amplifier flip-flop and method of generating data output by latching data input based on clock signal

Abstract

A sense amplifier flip-flop and a method of generating a data output by latching a data input based on a clock signal are provided. The sense amplifier flip-flop includes a first stage configured to generate a first latch signal and a second latch signal by pulling down a first pull-down node or a second pull-down node according to a data input and an inverted data input in response to a rising edge of a clock signal, where the first stage includes: a bridge circuit configured to generate a first latch signal and a second latch signal by pulling down the first pull-down node or the second pull-down node according to the data input and the inverted data input; the first pull-down node and the second pull-down node are electrically connected with each other in response to an activated bridge signal; and a control circuit configured to activate the bridge signal when the data input transitions when the clock signal is logically high.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0110792 filed on August 23, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0185068 filed on December 18, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present application relates to a flip-flop, and more particularly, to a sense amplifier flip-flop and a method of generating a data output by latching a data input based on a clock signal. Background Art

[0003] An integrated circuit that processes a digital signal may include a flip-flop. The flip-flop may latch an input based on a clock signal and output the latched input. The flip-flop may include a transistor and may have various structures according to applications. According to the demand for the integrated circuit, a flip-flop designed to have a high operating speed may consume high power. The power consumption of the integrated circuit may depend on the power consumption of the flip-flop, and therefore, a flip-flop with a high operating speed and reduced power consumption may be required. Summary of the invention

[0004] Disclosed are a sense amplifier trigger having high operating speed and reduced power consumption and an integrated circuit including the sense amplifier trigger.

[0005] According to the disclosed aspects, a sense amplifier trigger is provided, which includes: a first stage, configured to: generate a first latch signal and a second latch signal by pulling down a first pull-down node or a second pull-down node according to a data input and an inverted data input in response to a rising edge of a clock signal; and a second stage, configured to: generate a data output based on the first latch signal and the second latch signal, wherein the first stage includes: a bridge circuit, configured to: electrically connect the first pull-down node and the second pull-down node to each other in response to an activated bridge signal; and a control circuit, configured to: activate the bridge signal when the data input transitions when the clock signal is logic high.

[0006] According to another aspect of the disclosure, a sense amplifier trigger is provided, which includes: a first stage, configured to: generate a first latch signal and a second latch signal by pulling down a first pull-down node or a second pull-down node according to a data input and an inverted data input in response to a rising edge of a clock signal; and a second stage, configured to: generate a data output based on the first latch signal and the second latch signal, wherein the first stage is configured to: electrically connect the first pull-down node and the second pull-down node to each other when the data input transitions when the clock signal is logic high.

[0007] According to another aspect of the disclosure, a method for generating a data output by latching a data input based on a clock signal is provided, the method comprising: generating a first latch signal and a second latch signal by pulling down a first pull-down node or a second pull-down node according to a data input and an inverted data input in response to a rising edge of a clock signal; and generating a data output based on the first latch signal and the second latch signal, wherein the step of generating the first latch signal and the second latch signal comprises: detecting a transition of the data input when the clock signal is logic high; and electrically connecting the first pull-down node and the second pull-down node to each other when the transition of the data input is detected. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram illustrating a trigger according to some embodiments;

[0010] Figure 2 is a block diagram illustrating a second stage of a flip-flop according to some embodiments;

[0011] Figure 3 is a circuit diagram showing a first stage of a flip-flop according to some embodiments;

[0012] Figure 4 is a timing diagram illustrating signals of a flip-flop according to some embodiments;

[0013] Figure 5A and Figure 5B is a circuit diagram showing an example of a control circuit according to some embodiments;

[0014] Figure 6 is a circuit diagram illustrating a flip-flop according to some embodiments;

[0015] Figure 7 is a circuit diagram illustrating a flip-flop according to some embodiments;

[0016] Figure 8 is a flow chart illustrating the operation of a trigger according to some embodiments;

[0017] Fig. 9 is a flow chart illustrating the operation of a trigger according to some embodiments;

[0018] Fig.10 is a flow chart illustrating a method of manufacturing an integrated circuit according to some embodiments; and

[0019] Fig.11 is a block diagram illustrating a system on a chip according to some embodiments. DETAILED DESCRIPTION

[0020] Figure 1 is a block diagram showing a flip-flop 10 according to some embodiments. In some embodiments, the flip-flop 10 may be included in an integrated circuit manufactured by a semiconductor process. Figure 1 As shown in , the trigger 10 includes a first stage 11 and a second stage 12. Here, unless otherwise specified, it is assumed that the signal is a high-active signal having a logic high when "activated" and a logic low when "deactivated", but it is noted that the embodiment is not limited thereto. Here, the logic high may correspond to the positive power supply voltage VDD and may be represented as "1". In addition, the logic low may correspond to the negative power supply voltage VSS and may be represented as "0".

[0021] like Figure 1 As shown in , the flip-flop 10 can latch the data input D based on the clock signal CK and generate the data output Q corresponding to the latched data input D. In some embodiments, the flip-flop 10 can be a single-ended type, and the inverted data input DB can be generated from the data input D by an inverter included in the flip-flop 10. In some embodiments, the flip-flop 10 can be a differential type, and can receive the data input D and the inverted data input DB, and generate the data output Q and the inverted data output (for example, Figure 2 The flip-flop 10 may be a positive edge triggered flip-flop that latches the data input D in response to the rising edge of the clock signal CK, or a negative edge triggered flip-flop that latches the data input D in response to the falling edge of the clock signal CK. Here, it is assumed that the flip-flop 10 is a positive edge triggered flip-flop, but it is noted that the embodiment is not limited thereto.

[0022] The first stage 11 may receive the data input D and the clock signal CK and generate the first latch signal L1 and the second latch signal L2. In some embodiments, the first stage 11 may generate the first latch signal L1 and the second latch signal L2 by pulling down the first pull-down node or the second pull-down node according to the data input D and the inverted data input DB. For example, as will be described below with reference to Figure 3 As described, the first stage 11 may include a sense amplifier structure, pull down the first pull-down node or the second pull-down node according to the data input D and the inverted data input DB in response to the rising edge of the clock signal CK, and generate a first latch signal L1 and a second latch signal L2 that are complementary to each other. In this way, the trigger 10 including the sense amplifier structure may be referred to as a sense amplifier trigger (SAFF).

[0023] like Figure 1As shown in FIG. 1 , the first stage 11 includes a bridge circuit 11_1 and a control circuit 11_2. The bridge circuit 11_1 may be connected to a first pull-down node and a second pull-down node that are pulled down according to a data input D and an inverted data input DB in the first stage 11. Figure 3 As described above, after a current path is formed by the clock signal CK, the voltages of the first pull-down node and the second pull-down node may be pulled down according to the data input D and the inverted data input DB, and therefore, the first latch signal L1 and the second latch signal L2 may change according to the change of the data input D and the inverted data input DB during the holding period. Figure 1 As shown in , the bridge circuit 11_1 may receive a bridge signal CB from the control circuit 11_2 and electrically connect the first pull-down node to the second pull-down node in response to the activated bridge signal CB, thereby preventing changes in the first latch signal L1 and the second latch signal L2.

[0024] The control circuit 11_2 may generate a bridge signal CB provided to the bridge circuit 11_1. When the bridge circuit 11_1 always electrically connects the first pull-down node and the second pull-down node to each other (i.e., when the bridge signal CB, which is always activated, is provided to the bridge circuit 11_1), a current path may be formed in both the first pull-down node and the second pull-down node at the rising edge of the clock signal CK, and therefore, a sampling error of the data input D may occur. In addition, when the bridge signal CB is synchronized to the clock signal CK or to both the first latch signal L1 and the second latch signal L2 independently of the data input D, the bridge signal CB may be switched for each cycle of the clock signal CK, and unnecessary power consumption may occur. As will be described below with reference to the accompanying drawings, the control circuit 11_2 may generate an activated bridge signal CB when the data input D (or the inverted data input DB) transitions “when the clock signal CK is logic high”. Therefore, the first pull-down node and the second pull-down node may be electrically connected to each other through the bridge circuit 11_1 only when necessary, and the flip-flop 10 may have not only high operational reliability but also reduced power consumption.

[0025] The second stage 12 may receive the first latch signal L1 and the second latch signal L2 from the first stage 11 and generate a data output Q. In some embodiments, as described below with reference to Figure 6 and Figure 7 As described above, the second stage 12 may also receive not only the first latch signal L1 and the second latch signal L2, but also at least one of the clock signal CK, the data input D and the inverted data input DB. Figure 2 , Figure 6 and Figure 7 An example of the second stage 12 is described.

[0026] Figure 2is a block diagram illustrating the second stage of a trigger according to some embodiments. For example, Figure 2 The block diagram shows the SR latch 20 as Figure 1 An example of the second level 12. In the following, reference is made to Figure 1 right Figure 2 Provide explanation.

[0027] In some embodiments, the second stage 12 includes an SR latch 20. For example, the first latch signal L1 may correspond to the inverted reset signal RB, and the second latch signal L2 may correspond to the inverted set signal SB. When the inverted reset signal RB is 1 and the inverted set signal SB is 0 (RB=1, SB=0), the SR latch 20 may generate a data output Q of 1 and an inverted data output QB of 0 (Q=1, QB=0). When the inverted reset signal RB is 0 and the inverted set signal SB is 1 (RB=0, SB=1), the SR latch 20 may generate a data output Q of 0 and an inverted data output QB of 1 (Q=0, QB=1). When the inverted reset signal RB is 1 and the inverted set signal SB is 1 (RB=1, SB=1), the SR latch 20 may maintain the data output Q and the inverted data output QB.

[0028] Figure 3 is a circuit diagram showing a first stage 30 of a flip-flop according to some embodiments. For example, Figure 3 The circuit diagram shows that the first stage 30 generates an inverted reset signal RB and an inverted set signal SB as Figure 1 The first latch signal L1 and the second latch signal L2. Figure 3 As shown in FIG. 1 , the first stage 30 includes a first transistor M1 to a ninth transistor M9, a bridge circuit 31, and a control circuit 32. The first transistor M1 to the fourth transistor M4 may be a p-channel field effect transistor (PFET), and the fifth transistor M5 to the ninth transistor M9 may be an n-channel field effect transistor (NFET). Figure 1 and Figure 2 explain Figure 3 .

[0029] As mentioned above Figure 1 As described above, the first stage 30 can generate the inverted reset signal RB and the inverted set signal SB by pulling down the first pull-down node or the second pull-down node according to the data input D and the inverted data input DB. Figure 3, the sixth transistor M6 and the eighth transistor M8 may receive the data input D and the inverted data input DB, respectively, and may have a source connected to the "drain of the ninth transistor M9 receiving the clock signal CK", respectively. The second transistor M2, the third transistor M3, the fifth transistor M5, and the seventh transistor M7 may correspond to the two inverters cross-coupled. The first transistor M1 and the fourth transistor M4 receiving the clock signal CK may be connected to the nodes to which the two inverters are connected, respectively. Each of the first transistor M1 to the fourth transistor M4 may have a source connected to a node (referred to as the first power supply node) to which a positive power supply voltage VDD is applied. The ninth transistor M9 may have a source connected to a node (referred to as the second power supply node) to which a negative power supply voltage VSS is applied.

[0030] The bridge circuit 31 may be connected to the first pull-down node NA1 and the second pull-down node NA2. Figure 3 As shown in , the first pull-down node NA1 may correspond to the drain of the sixth transistor M6 receiving the data input D, and the second pull-down node NA2 may correspond to the drain of the eighth transistor M8 receiving the inverted data input DB. Figure 3 As shown in , the bridge circuit 31 includes a tenth transistor M10 as an NFET, and the tenth transistor M10 may have a gate receiving the bridge signal CB. Therefore, the bridge circuit 31 may electrically connect the first pull-down node NA1 and the second pull-down node NA2 to each other in response to the activated bridge signal CB (i.e., the bridge signal CB of logic high).

[0031] The control circuit 32 can generate the bridge signal CB based on the data input D, the inverted data input DB, the inverted reset signal RB and the inverted set signal SB. Figure 1 As described above, in order to generate the activated bridge signal CB when the data input D changes "when the clock signal CK is logic high", the control circuit 32 can receive the data input D, the inverted data input DB, the inverted reset signal RB and the inverted set signal SB, and generate the bridge signal CB. Figure 5A , Figure 5B , Figure 6 and Figure 7 An example of the control circuit 32 is described.

[0032] Figure 4 is a timing diagram illustrating the operation of a flip-flop according to some embodiments. For example, Figure 4 The timing diagram in FIG. 1 shows the data input D, the inverted data input DB, the clock signal CK, the inverted reset signal RB, the inverted set signal SB, the bridge signal CB and the data output Q over time. Figure 2 and Figure 3 explain Figure 4 .

[0033] Reference Figure 4 , the clock signal CK may be 0 before time t01. Since the clock signal CK is 0, the ninth transistor M9 may be turned off, and thus, the current path flowing through the negative power supply voltage VSS may be blocked. In addition, since the clock signal CK is 0, the first transistor M1 and the fourth transistor M4 may be turned on, and thus, as shown in FIG. Figure 4 As shown in , the inverted reset signal RB and the inverted set signal SB may be precharged to 1 (eg, converted to logic high). Figure 4 As shown in , the bridge signal CB may be 0, and thus, the bridge circuit 31 may electrically disconnect the first pull-down node NA1 and the second pull-down node NA2 from each other.

[0034] At time t01, a rising edge of the clock signal CK may occur. Due to the rising edge of the clock signal CK, the ninth transistor M9 may be turned on, and the first transistor M1 and the fourth transistor M4 may be turned off. Therefore, the first stage 30 may operate similarly to a sense amplifier. Figure 4 As shown in , since the data input D is 1 and the inverted data input DB is 0 at time t01, the inverted reset signal RB may maintain 1, and the inverted set signal SB may turn to 0 due to the current path including the first pull-down node NA1 being pulled down. Therefore, the SR latch 20 may generate the data output Q which is 1. The bridge signal CB may maintain 0, and therefore, the bridge circuit 31 may electrically disconnect the first pull-down node NA1 and the second pull-down node NA2 from each other.

[0035] At time t02, a falling edge of the clock signal CK may occur. Due to the falling edge of the clock signal CK, the ninth transistor M9 may be turned off, and the first transistor M1 and the fourth transistor M4 may be turned on. Therefore, the inverted reset signal RB and the inverted set signal SB may be precharged to 1, and the SR latch 20 may maintain the data output Q.

[0036] At time t03, a rising edge of the clock signal CK may occur. Due to the rising edge of the clock signal CK, the ninth transistor M9 may be turned on, and the first transistor M1 and the fourth transistor M4 may be turned off. Therefore, the first stage 30 may operate similarly to a sense amplifier. Figure 4 As shown in , since the data input D is 1 and the inverted data input DB is 0 at time t03, the inverted reset signal RB may remain at 1, and the inverted set signal SB may turn to 0 due to the current path including the first pull-down node NA1 being pulled down. Therefore, the SR latch 20 may generate the data output Q which is 1. The bridge signal CB may remain 0, and therefore, the bridge circuit 31 may electrically disconnect the first pull-down node NA1 and the second pull-down node NA2 from each other.

[0037] At time t04, the data input D and the inverted data input DB may be transformed. When the bridge circuit 31 is omitted, because the clock signal CK is 1, the inverted reset signal RB and the inverted set signal SB may also be transformed according to the transformed data input D and the inverted data input DB. In order to prevent the transformation of the inverted reset signal RB and the inverted set signal SB, the bridge signal CB may be 1, and thus, the bridge circuit 31 may electrically connect the first pull-down node NA1 and the second pull-down node NA2 to each other. Therefore, even if the clock signal CK is 1, the first stage 30 may not operate as a sense amplifier, and as Figure 4 As shown in , the inverted reset signal RB and the inverted set signal SB may be maintained.

[0038] At time t05, a falling edge of the clock signal CK may occur. Due to the falling edge of the clock signal CK, the ninth transistor M9 may be turned off, and the first transistor M1 and the fourth transistor M4 may be turned on. Therefore, the inverted reset signal RB and the inverted set signal SB may be precharged to 1, and the SR latch 20 may maintain the data output Q. In addition, the bridge signal CB may be converted back to 0.

[0039] At time t06, a rising edge of the clock signal CK may occur. Due to the rising edge of the clock signal CK, the ninth transistor M9 may be turned on, and the first transistor M1 and the fourth transistor M4 may be turned off. Therefore, the first stage 30 may operate similarly to a sense amplifier. Figure 4 As shown in , since the data input D is 0 and the inverted data input DB is 1 at time t06, the inverted set signal SB may remain at 1, and the inverted reset signal RB may turn to 0 due to the current path including the second pull-down node NA2 being pulled down. Therefore, the SR latch 20 may generate the data output Q which is 0. The bridge signal CB may remain 0, and therefore, the bridge circuit 31 may electrically disconnect the first pull-down node NA1 and the second pull-down node NA2 from each other.

[0040] At time t07, a falling edge of the clock signal CK may occur. Due to the falling edge of the clock signal CK, the ninth transistor M9 may be turned off, and the first transistor M1 and the fourth transistor M4 may be turned on. Therefore, the inverted reset signal RB and the inverted set signal SB may be precharged to 1, and the SR latch 20 may maintain the data output Q.

[0041] At time t08, a rising edge of the clock signal CK may occur. Due to the rising edge of the clock signal CK, the ninth transistor M9 may be turned on, and the first transistor M1 and the fourth transistor M4 may be turned off. Therefore, the first stage 30 may operate similarly to a sense amplifier. Figure 4As shown in , since the data input D is 0 and the inverted data input DB is 1 at time t08, the inverted set signal SB may remain at 1, and the inverted reset signal RB may turn to 0 due to the current path including the second pull-down node NA2 being pulled down. Therefore, the SR latch 20 may generate the data output Q which is 0. The bridge signal CB may remain 0, and therefore, the bridge circuit 31 may electrically disconnect the first pull-down node NA1 and the second pull-down node NA2 from each other.

[0042] At time t09, the data input D and the inverted data input DB may transition. In order to prevent the transition of the inverted reset signal RB and the inverted set signal SB, the bridge signal CB may be 1, and thus, the bridge circuit 31 may electrically connect the first pull-down node NA1 and the second pull-down node NA2 to each other. Therefore, even if the clock signal CK is 1, the first stage 30 may not operate as a sense amplifier, and as Figure 4 As shown in , the inverted reset signal RB and the inverted set signal SB may be maintained.

[0043] At time t10, a falling edge of the clock signal CK may occur. Due to the falling edge of the clock signal CK, the ninth transistor M9 may be turned off, and the first transistor M1 and the fourth transistor M4 may be turned on. Therefore, the inverted reset signal RB and the inverted set signal SB may be precharged to 1, and the SR latch 20 may maintain the data output Q. In addition, the bridge signal CB may be converted back to 0.

[0044] Figure 5A and Figure 5B are circuit diagrams showing examples of control circuits 50a and 50b, respectively, according to some embodiments. Figure 3 As described above, the control circuits 50a and 50b can both generate the bridge signal CB based on the data input D, the inverted data input DB, the inverted reset signal RB and the inverted set signal SB.

[0045] Reference Figure 5A , the control circuit 50a includes a first transistor M11 to an eighth transistor M18. The first transistor M11 to the fourth transistor M14 may be a PFET, and the fifth transistor M15 to the eighth transistor M18 may be an NFET. Each of the first transistor M11 to the eighth transistor M18 may include a gate that receives one of a data input D, an inverted data input DB, an inverted reset signal RB, and an inverted set signal SB.

[0046] The first transistor M11 may receive an inverted data input DB, and the second transistor M12 may receive an inverted reset signal RB. The first transistor M11 and the second transistor M12 may be connected in series with each other between a first power supply node to which a positive power supply voltage VDD is applied and an output node NO generating a bridge signal CB. In some embodiments, the first transistor M11 and the second transistor M12 may be connected in series with each other. Figure 5A The third transistor M13 may receive a data input D, and the fourth transistor M14 may receive an inverted set signal SB. The third transistor M13 and the fourth transistor M14 may be connected in series with each other between the first power supply node and the output node NO. In some embodiments, the third transistor M13 and the fourth transistor M14 may be connected in series with each other in an order different from the order shown in FIG. Figure 5A The different orders shown in FIG. 1 are connected in series with each other.

[0047] The fifth transistor M15 may receive an inverted data input DB, and the sixth transistor M16 may receive an inverted set signal SB. The fifth transistor M15 and the sixth transistor M16 may be connected in series with each other between the output node NO and a second power supply node to which a negative power supply voltage VSS is applied. In some embodiments, the fifth transistor M15 and the sixth transistor M16 may be connected in series with each other. Figure 5A The seventh transistor M17 may receive a data input D, and the eighth transistor M18 may receive an inverted reset signal RB. The seventh transistor M17 and the eighth transistor M18 may be connected in series with each other between the output node NO and the second power supply node. In some embodiments, the seventh transistor M17 and the eighth transistor M18 may be connected in series with each other in an order different from the order shown in FIG. Figure 5A The different orders shown in FIG. 1 are connected in series with each other.

[0048] Reference Figure 5B , the control circuit 50b includes a first transistor M11 to a sixth transistor M16. The first transistor M11 and the second transistor M12 may be PFETs, and the third transistor M13 to the sixth transistor M16 may be NFETs. Each of the first transistor M11 to the sixth transistor M16 may include a gate that receives one of a data input D, an inverted data input DB, an inverted reset signal RB, and an inverted set signal SB.

[0049] The first transistor M11 may have a gate receiving an inverted reset signal RB, a source receiving a data input D, and a drain connected to the output node NO. The second transistor M12 may have a gate receiving an inverted set signal SB, a source receiving an inverted data input DB, and a drain connected to the output node NO. Figure 5ACompared with the control circuit 50a, two PFETs may be omitted, and thus, the control circuit 50b may include a reduced number of transistors.

[0050] The third transistor M13 may receive an inverted data input DB, and the fourth transistor M14 may receive an inverted set signal SB. The third transistor M13 and the fourth transistor M14 may be connected in series with each other between the output node NO and a second power supply node to which a negative power supply voltage VSS is applied. In some embodiments, the third transistor M13 and the fourth transistor M14 may be connected in series with each other. Figure 5B The fifth transistor M15 may receive a data input D, and the sixth transistor M16 may receive an inverted reset signal RB. The fifth transistor M15 and the sixth transistor M16 may be connected in series with each other between the output node NO and the second power supply node. In some embodiments, the fifth transistor M15 and the sixth transistor M16 may be connected in series with each other in an order different from the order shown in FIG. Figure 5B The different orders shown in FIG. 1 are connected in series with each other.

[0051] Figure 6 is a circuit diagram showing a flip-flop 60 according to some embodiments. For example, Figure 6 The circuit diagram of FIG. 1 shows a control circuit 61 included in the first stage and a second stage 62 in the flip-flop 60. In some embodiments, the control circuit 61 may share at least one transistor with the second stage 62, and thus, the flip-flop 60 may include a reduced number of transistors. Note that Figure 1 The control circuit 11_2 and the second stage 12 are not limited to Figure 6 The control circuit 61 and the second stage 62 in.

[0052] Reference Figure 6 , the control circuit 61 generating the bridge signal CB at the output node NO includes a first transistor M21 to a fifth transistor M25. The first transistor M21 and the second transistor M22 may be PFETs, and the third transistor M23 to the fifth transistor M25 may be NFETs. Each of the first transistor M21 to the fifth transistor M25 may include a gate receiving one of the data input D, the inverted data input DB, the inverted reset signal RB, and the inverted set signal SB.

[0053] The first transistor M21 may have a gate receiving an inverted reset signal RB, a drain receiving a data input D, and a source connected to the output node NO. The second transistor M22 may have a gate receiving an inverted set signal SB, a drain receiving an inverted data input DB, and a source connected to the output node NO. In some embodiments, the control circuit 61 may also include a control circuit as described above with reference to Figure 5A The two PFETs are between the first power supply node and the output node NO.

[0054] The third transistor M23 may receive an inverted data input DB, and the fourth transistor M24 may receive an inverted set signal SB. The third transistor M23 and the fourth transistor M24 may be connected in series with each other between the output node NO and a second power supply node to which a negative power supply voltage VSS is applied. In some embodiments, the third transistor M23 and the fourth transistor M24 may be connected in series with each other. Figure 6 The fifth transistor M25 may include a gate receiving the data input D, a drain connected to the output node NO, and a source connected to the second stage 62. Figure 6 As shown in FIG. 1 , the source of the fifth transistor M25 may be connected to the drain of the tenth transistor M30 (ie, the third node N3), and the tenth transistor M30 receives the inverted reset signal RB at the second stage 62. Figure 5B Compared with the control circuit 50b of FIG. 5, the control circuit 61 may include a reduced number of transistors. Here, the signal generated by the second stage 62 at the third node N3 may be referred to as an internal signal. For example, the second stage 62 may generate the internal signal based on at least one of the inverted reset signal RB and the inverted set signal SB. The control circuit 61 may generate the bridge signal CB based on the internal signal of the second stage 62 and the data input D, the inverted data input DB, the inverted reset signal RB, and the inverted set signal SB.

[0055] The second stage 62 can receive the data input D, the clock signal CK, the inverted reset signal RB and the inverted set signal SB, and generate the data output Q. Figure 6 As shown in , the second stage 62 includes a sixth transistor M26 to an eleventh transistor M31, a first inverter INV1 and a second inverter INV2. Each of the first inverter INV1 and the second inverter INV2 may include a PFET and an NFET connected in series with each other between a first power supply node and a second power supply node. The sixth transistor M26 and the seventh transistor M27 may be PFETs, and the eighth transistor M28 to the eleventh transistor M31 may be NFETs.

[0056] The sixth transistor M26 may be connected between the first power supply node and the first node N1, and may include a gate that receives an inverted reset signal RB, the first node N1 corresponds to the inverted data output. The eighth transistor M28 may receive a clock signal CK, the ninth transistor M29 may receive a data input D, and the tenth transistor M30 may receive an inverted reset signal RB. The eighth transistor M28 to the tenth transistor M30 may be connected in series between the first node N1 and the second power supply node. The source of the ninth transistor M29 and the drain of the tenth transistor M30 may be connected at the third node N3, and as described above, the third node N3 may be connected to the source of the fifth transistor M25. In some embodiments, the eighth transistor M28 and the ninth transistor M29 may be connected in series with the third node N3. Figure 6 The nodes of the embodiment shown in FIG. 1 are connected in series to each other between the first node N1 and the third node N3 in different orders.

[0057] The first inverter INV1 may have an input connected to the first node N1 and an output connected to the second node N2. The seventh transistor M27 and the eleventh transistor M31 may constitute an inverter and have an input connected to the second node N2 and an output connected to the first node N1. That is, the inverter including the seventh transistor M27 and the eleventh transistor M31 may be cross-coupled with the first inverter INV1. Figure 6 As shown in , the seventh transistor M27 may include a source receiving the inverted set signal SB, and the eleventh transistor M31 may include a source connected to the third node N3. The second inverter INV2 may have an input connected to the first node N1, and may generate a data output Q.

[0058] Figure 7 is a circuit diagram showing a flip-flop 70 according to some embodiments. For example, Figure 7 The circuit diagram of FIG. 1 shows a control circuit 71 included in the first stage and a second stage 72 in the flip-flop 70 as a differential type. In some embodiments, the control circuit 71 may share at least one transistor with the second stage 72, and thus, the flip-flop 70 may include a reduced number of transistors. Note that Figure 1 The control circuit 11_2 and the second stage 12 are not limited to Figure 7 The control circuit 71 and the second stage 72 in.

[0059] Reference Figure 7, the control circuit 71 generating the bridge signal CB at the output node NO includes a first transistor M41 to a fourth transistor M44. The first transistor M41 and the second transistor M42 may be PFETs, and the third transistor M43 and the fourth transistor M44 may be NFETs. Each of the first transistor M41 to the fourth transistor M44 may include a gate receiving one of the data input D, the inverted data input DB, the inverted reset signal RB, and the inverted set signal SB.

[0060] The first transistor M41 may have a gate receiving an inverted reset signal RB, a drain receiving a data input D, and a source connected to the output node NO. The second transistor M42 may have a gate receiving an inverted set signal SB, a drain receiving an inverted data input DB, and a source connected to the output node NO. In some embodiments, the control circuit 71 may also include a control circuit as described above with reference to Figure 5A The two PFETs are between the first power supply node and the output node NO.

[0061] The third transistor M43 may include a gate receiving the inverted data input DB, a drain connected to the output node NO, and a source connected to the second stage 72. Figure 7 As shown in , the source of the third transistor M43 may be connected to the drain of the twelfth transistor M52 (i.e., the fourth node N4), and the twelfth transistor M52 receives the inverted set signal SB at the second stage 72. The fourth transistor M44 may include a gate receiving the data input D, a drain connected to the output node NO, and a source connected to the second stage 72. Figure 7 As shown in FIG. 1 , the source of the fourth transistor M44 can be connected to the drain of the seventeenth transistor M57 (ie, the fifth node N5), and the seventeenth transistor M57 receives the inverted reset signal RB in the second stage 72. Figure 5B Compared with the control circuit 50b of the embodiment of the present invention, the control circuit 71 may include a reduced number of transistors. Here, the signals generated by the second stage 72 at the fourth node N4 and the fifth node N5 may be referred to as internal signals. For example, the second stage 72 may generate the internal signal based on at least one of the inverted reset signal RB and the inverted set signal SB. The control circuit 71 may generate the bridge signal CB based on the internal signal of the second stage 72 and the data input D, the inverted data input DB, the inverted reset signal RB, and the inverted set signal SB.

[0062] The second stage 72 can receive the data input D, the clock signal CK, the inverted reset signal RB and the inverted set signal SB, and generate the data output Q. Figure 7As shown in FIG. 1 , the second stage 72 includes a fifth transistor M45 to a seventeenth transistor M57. The fifth transistor M45 to the ninth transistor M49 may be PFETs, and the tenth transistor M50 to the seventeenth transistor M57 may be NFETs.

[0063] The fifth transistor M45 and the tenth transistor M50 to the twelfth transistor M52 may respectively receive the inverted set signal SB, the clock signal CK, the inverted data input DB and the inverted set signal SB, and may be connected in series between the first power supply node and the second power supply node. Figure 7 As shown in FIG. 1 , the drain of the fifth transistor M45 and the drain of the tenth transistor M50 may be connected to each other at the sixth node N6. In addition, the source of the eleventh transistor M51 and the drain of the twelfth transistor M52 may be connected to each other at the fourth node N4, and as described above, the fourth node N4 may be connected to the source of the third transistor M43 of the control circuit 71. In some embodiments, the tenth transistor M50 and the eleventh transistor M51 may be connected to each other at the sixth node N6. Figure 7 The nodes having different orders from those shown in FIG. 1 are connected in series to each other between the sixth node N6 and the fourth node N4.

[0064] The seventh transistor M47 and the fifteenth to seventeenth transistors M55 to M57 may respectively receive the inverted reset signal RB, the clock signal CK, the data input D, and the inverted reset signal RB, and may be connected in series between the first power supply node and the second power supply node. Figure 7 As shown in FIG. 1 , the drain of the seventh transistor M47 and the drain of the fifteenth transistor M55 may be connected to each other at the seventh node N7. The source of the sixteenth transistor M56 and the drain of the seventeenth transistor M57 may be connected to each other at the fifth node N5, and as described above, the fifth node N5 may be connected to the source of the fourth transistor M44 of the control circuit 71. In some embodiments, the fifteenth transistor M55 and the sixteenth transistor M56 may be connected to each other at the seventh node N7. Figure 7 The nodes of the embodiment shown in FIG. 1 are connected in series to each other between the seventh node N7 and the fifth node N5 in a different order from that shown in FIG.

[0065] The eighth transistor M48, the ninth transistor M49, the thirteenth transistor M53, and the fourteenth transistor M54 may constitute two cross-coupled inverters between the sixth node N6 and the seventh node N7. The data output Q may be generated at the sixth node N6, and the inverted data output QB may be generated at the seventh node N7. The sixth transistor M46 may be connected between the first power supply node and the inverter, and may receive the clock signal CK.

[0066] Figure 8 is a flow chart illustrating the operation of a trigger according to some embodiments. Figure 8The operation of can be referred to as a method of generating a data output Q by latching a data input D based on a clock signal CK. Figure 8 As shown in , the method of generating a data output Q by latching a data input D based on a clock signal CK includes operations S10 and S20. In some embodiments, Figure 8 The method can be Figure 1 The trigger 10 is executed. In the following, reference will be made to Figure 1 right Figure 8 Give a description.

[0067] Reference Figure 8 , a first latch signal L1 and a second latch signal L2 may be generated in response to a rising edge of a clock signal CK in operation S10. For example, the first stage 11 may sample the data input D at a rising edge of the clock signal CK, and may generate a first latch signal L1 and a second latch signal L2 corresponding to the sampling result. As described above with reference to the accompanying drawings, the first stage 11 may generate a first latch signal L1 and a second latch signal L2 by pulling down a first pull-down node or a second pull-down node according to the data input D and the inverted data input DB at a rising edge of the clock signal CK. In addition, the first stage 11 includes a bridge circuit 11_1 and a control circuit 11_2, so that the data output Q is not affected by changes in the data input D during the holding period. The following will refer to Fig. 9 An example of operation S10 is described.

[0068] In operation S20, a data output Q may be generated based on the first latch signal L1 and the second latch signal L2. For example, the second stage 12 may receive the first latch signal L1 and the second latch signal L2 generated in operation S10, and generate a data output Q based on the first latch signal L1 and the second latch signal L2. In some embodiments, as described above with reference to Figure 2 As described, the second stage 12 may include an SR latch, and the first latch signal L1 and the second latch signal L2 may correspond to the inverted reset signal RB and the inverted set signal SB, respectively. Therefore, the second stage 12 may generate a data output Q of 1 in response to the activated first latch signal L1 and the deactivated second latch signal L2. The second stage 12 may generate a data output Q of 0 in response to the deactivated first latch signal L1 and the activated second latch signal L2. In addition, the second stage 12 may maintain the data output Q in response to the activated first latch signal L1 and the activated second latch signal L2.

[0069] Fig. 9 is a flow chart illustrating the operation of a trigger according to some embodiments. For example, Fig. 9 The flowchart in Figure 8 As shown in the above reference Figure 8 As mentioned above, Fig. 9 In operation S10', in response to the rising edge of the clock signal CK, a first latch signal L1 and a second latch signal L2 are generated. Fig. 9 As shown in , operation S10' includes multiple operations S11 to S14. In some embodiments, Fig. 9 The operation S10' can be performed by Figure 3 The control circuit 32 is executed. Figure 3 right Fig. 9 Give a description.

[0070] Reference Fig. 9 , it may be determined in operation S11 whether the clock signal CK is 1. For example, the first stage 30 may generate an inverted reset signal RB and an inverted set signal SB precharged to 1 when the clock signal CK is 0, and complementarily generate the inverted reset signal RB and the inverted set signal SB when the clock signal CK is 1. Therefore, when the inverted reset signal RB and the inverted set signal SB are complementary to each other, the control circuit 32 may recognize that the clock signal CK is 1. Fig. 9 As shown in , when the clock signal CK is 1, operation S12 may be subsequently performed, and when the clock signal CK is not 1, operation S14 may be subsequently performed.

[0071] When the clock signal CK is 1, the new data input D may be determined in operation S12. NEW Whether to enter D with existing data OLD Different. That is, the transition of the data input D can be detected. In one embodiment, when the clock signal CK is 1, the transition of the data input D can be detected based on the data input D, the inverted data input DB, the inverted reset signal RB, and the inverted set signal SB. In one embodiment, when the clock signal CK is 1, the transition of the data input D can be detected based on the data input D, the inverted data input DB, the inverted reset signal RB, the inverted set signal SB, and the internal signal generated by the second stage (e.g., the second stage 62 or the second stage 72). For example, the control circuit 32 may receive the data input D and the inverted data input DB, and when the clock signal CK is 1, the control circuit 32 may detect the transition of the data input D and the inverted data input DB when the clock signal CK is 1. As Fig. 9 As shown in , when the transition of the data input D and the inverted data input DB is detected, operation S13 may be subsequently performed, and when the transition of the data input D and the inverted data input DB is not detected, operation S14 may be subsequently performed.

[0072] When the transition of the data input D and the inverted data input DB occurs "when the clock signal CK is 1", the bridge signal CB may be activated in operation S13. For example, the control circuit 32 may generate a deactivated bridge signal CB of, for example, 0, according to the data input D, the inverted reset signal RB, and the inverted set signal SB, and when the transition of the data input D occurs, the control circuit 32 may generate an activated bridge signal CB of, for example, 1, according to the transitioned data input D, the inverted reset signal RB, and the inverted set signal SB. The bridge circuit 31 may electrically connect the first pull-down node NA1 and the second pull-down node NA2 to each other in response to the activated bridge signal CB, and, as described above with reference to FIG. Figure 4 As described above, the inverted reset signal RB and the inverted set signal SB may be maintained regardless of the transition of the data input D.

[0073] In operation S14, the bridge signal CB may be deactivated. The bridge circuit 31 may electrically disconnect the first pull-down node NA1 and the second pull-down node NA2 from each other in response to the deactivated bridge signal CB. As described above, “when the clock signal CK is 0” or “when the transition of the data input D does not occur when the clock signal CK is 1”, operation S14 may be performed. For example, when the clock signal CK is 0, the control circuit 32 may generate a bridge signal CB of 0 regardless of the data input D according to the inverted reset signal RB and the inverted set signal SB precharged to 1. In addition, “when the clock signal CK is 0”, “when the transition of the data input D does not occur when the clock signal CK is 1”, the control circuit 32 may maintain the deactivated bridge signal CB. Therefore, “when the clock signal CK is 0” or “when the transition of the data input D does not occur when the clock signal CK is 1”, the first pull-down node NA1 and the second pull-down node NA2 may be electrically disconnected from each other.

[0074] Fig.10 is a flow chart illustrating a method of manufacturing an integrated circuit (IC) according to some embodiments. Specifically, Fig.10 The flowchart of FIG. 1 shows an example of a method of manufacturing an IC including a standard cell. A standard cell is a unit of a layout included in an IC and can be designed to perform a predefined function. Fig.10 As shown in , the method of manufacturing an IC includes a plurality of operations S31 to S35.

[0075] The cell library (or standard cell library) D12 may include information about standard cells (such as information about functions, characteristics, layouts, etc.). In some embodiments, the trigger (i.e., SAFF) described above with reference to the accompanying drawings may be included in the IC as a standard cell. For example, the cell library D12 may include information about a cell corresponding to the trigger described above with reference to the accompanying drawings. Therefore, the IC may have high operating speed, reduced power consumption, and high operating reliability.

[0076] Design rule D14 may include requirements that the layout of the IC needs to comply with. For example, design rule D14 may include requirements for the space between patterns in the same layer, the minimum width of the pattern, the routing direction of the routing layer, etc. In some embodiments, design rule D14 may define the minimum spacing distance within the same track of the routing layer.

[0077] In operation S31, a logic synthesis operation may be performed to generate netlist data D13 from RTL (register transfer level) data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform synthesis logic according to RTL data D11 written in VHSIC hardware description language (VHDL) and hardware description language (HDL) (such as Verilog) by referring to a cell library D12, and generate netlist data D13 including a bitstream or a netlist. The netlist data D13 may correspond to an input of a layout and routing to be described below.

[0078] In operation S32, standard cells may be placed. For example, a semiconductor design tool (e.g., a place and route (P&R) tool) may place standard cells used in the netlist data D13 with reference to the cell library D12. In some embodiments, the semiconductor design tool may place the standard cells in rows extending parallel to each other, and the placed standard cells may receive power from power rails extending along the boundaries of the rows.

[0079] In operation S33, the pins of the standard cell may be wired. For example, the semiconductor design tool may generate an interconnect that electrically connects the output pins and input pins of the placed standard cell, and generates layout data D15 defining the placed standard cell and the generated interconnects. The interconnects may include vias of a via layer and / or a pattern of a wiring layer. In some embodiments, the wiring layer may include a front wiring layer located above the gate electrode and a back wiring layer located below the gate electrode. The layout data D15 may have a format such as GDSII, for example, and may include geometric information of the cell and the interconnects. The semiconductor design tool may refer to the design rule D14 when wiring the pins of the cell. The layout data D15 may correspond to the output of the layout and wiring. A separate operation S33 may be referred to as a method for designing an IC, or operations S32 and S33 may be collectively referred to as a method for designing an IC.

[0080] In operation S34, a mask may be manufactured. For example, optical proximity correction (OPC) for correcting distortion (such as refraction) caused by the characteristics of light in photolithography may be applied to the layout data D15. The pattern on the mask may be defined to form a pattern placed on a plurality of layers based on the data to which the OPC is applied, and at least one mask (or photomask) may be manufactured to form a pattern for each of the plurality of layers. In some embodiments, the layout of the IC may be limitedly modified in operation S34, and the step of limitedly modifying the IC in operation S34 may be referred to as design polishing as a post-processing process for optimizing the structure of the IC.

[0081] In operation S35, the IC may be manufactured. For example, the IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S34. The front-end process (FEOL) may include, for example, planarizing and cleaning the wafer, forming a groove, forming a well, forming a gate electrode, and forming a source and a drain. Through the FEOL, independent components (such as transistors, capacitors, resistors, etc.) may be formed on the substrate. In addition, the back-end process (BEOL) may include, for example, silicide the gate, source, and drain regions, add a dielectric, planarize the dielectric, form a hole, add a metal layer, form a via, and form a passivation layer, etc. Through the BEOL, independent components (such as transistors, capacitors, resistors, etc.) may be interconnected. In some embodiments, an intermediate process (MOL) may be performed between the FEOL and the BEOL, and contacts may be formed on independent components. Hereinafter, the IC may be packaged in a semiconductor package and used as a component in various applications.

[0082] Fig.11 1 is a block diagram illustrating a system on chip (SoC) 110 according to some embodiments. SoC 110 may represent an IC that integrates components of a computing system or other electronic system. For example, an application processor (AP) as an example of SoC 110 may include a processor and components for other functions. Fig.11 As shown in FIG. 1 , SoC 110 includes core 111, digital signal processor (DSP) 112, graphics processor (GPU) 113, embedded memory 114, communication interface (I / F) 115, and memory interface 116. The components of SoC 110 may communicate with each other through bus 117.

[0083] The components of the SoC 110 may include the trigger described above with reference to the drawings. Therefore, each of the components may have a high operating speed, reduced power consumption, and high operating reliability, and thus, the performance, efficiency, and reliability of the SoC 110 may be improved.

[0084] The core 111 may process instructions and control the operation of the components included in the SoC 110. For example, the core 111 may drive the operating system by processing a series of instructions and run applications on the operating system. The DSP 112 may generate useful data by processing digital signals (e.g., digital signals provided from the communication interface 115). The GPU 113 may generate data of an image output by a display device according to image data provided from the embedded memory 114 or the memory interface 116, and may encode the image data. The embedded memory 114 may store data required for the core 111, the DSP 112, and the GPU 113 to operate. The communication interface 115 may provide an interface for a communication network or one-to-one communication. The memory interface 116 may provide an interface to an external memory (such as a dynamic random access memory (DRAM) and a flash memory) of the SoC 110.

[0085] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the protection that can be claimed. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in a specific combination, one or more features from the combination may be removed from the combination in some cases, and the combination may involve a sub-combination or a variation of the sub-combination.

[0086] While the disclosure has been particularly shown and described with reference to certain embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A sense amplifier trigger, comprising: The first stage is configured to: generate a first latch signal and a second latch signal by pulling down a first pull-down node or a second pull-down node according to a data input and an inverted data input in response to a rising edge of a clock signal; as well as The second stage is configured to generate a data output based on the first latch signal and the second latch signal, The first level includes: a bridge circuit configured to: electrically connect the first pull-down node and the second pull-down node to each other in response to activation of the bridge signal; and A control circuit is configured to activate the bridge signal when the data input transitions while the clock signal is logic high.

2. The sense amplifier trigger of claim 1, wherein: The control circuit is configured to deactivate the bridge signal based on the data input not transitioning when the first latch signal and the second latch signal are complementary to each other.

3. The sense amplifier trigger of claim 1 , wherein: The control circuit is configured to deactivate the bridge signal when the first latch signal and the second latch signal are precharged.

4. The sense amplifier trigger as claimed in claim 1, wherein: The control circuit is configured to generate a bridge signal based on a data input, an inverted data input, a first latch signal, and a second latch signal.

5. The sense amplifier trigger as claimed in claim 1, wherein: The control circuit includes: a first p-channel field effect transistor and a second p-channel field effect transistor, the first p-channel field effect transistor and the second p-channel field effect transistor being connected in series with each other between a first power supply node to which a positive power supply voltage is applied and an output node to which a bridge signal is generated, wherein the first p-channel field effect transistor is configured to receive an inverted data input and the second p-channel field effect transistor is configured to receive a first latch signal; and a third p-channel field effect transistor and a fourth p-channel field effect transistor, the third p-channel field effect transistor and the fourth p-channel field effect transistor are connected in series with each other between the first power supply node and the output node, wherein the third p-channel field effect transistor is configured to receive a data input, and the fourth p-channel field effect transistor is configured to receive a second latch signal.

6. The sense amplifier trigger as claimed in claim 1, wherein: The control circuit includes: a first p-channel field effect transistor including: a source configured to receive a data input, a drain connected to an output node generating a bridge signal, and a gate configured to receive a first latch signal; and The second p-channel field effect transistor includes a source configured to receive an inverted data input, a drain connected to the output node, and a gate configured to receive a second latch signal.

7. The sense amplifier trigger as claimed in claim 1, wherein: The control circuit includes: a first n-channel field effect transistor and a second n-channel field effect transistor, the first n-channel field effect transistor and the second n-channel field effect transistor being connected in series with each other between an output node generating a bridge signal and a second power supply node to which a negative power supply voltage is applied, wherein the first n-channel field effect transistor is configured to receive an inverted data input, and the second n-channel field effect transistor is configured to receive a second latch signal; and a third n-channel field effect transistor and a fourth n-channel field effect transistor, the third n-channel field effect transistor and the fourth n-channel field effect transistor are connected in series with each other between the output node and the second power supply node, wherein the third n-channel field effect transistor is configured to receive a data input, and the fourth n-channel field effect transistor is configured to receive a first latch signal.

8. The sense amplifier trigger as claimed in claim 1, in, The control circuit includes: a first n-channel field effect transistor and a second n-channel field effect transistor, the first n-channel field effect transistor and the second n-channel field effect transistor being connected in series with each other between an output node generating a bridge signal and a second power supply node to which a negative power supply voltage is applied, wherein the first n-channel field effect transistor is configured to receive an inverted data input, and the second n-channel field effect transistor is configured to receive a second latch signal; and a third n-channel field effect transistor including a drain connected to the output node and a gate configured to receive a data input, and Among them, the second level includes: a fourth n-channel field effect transistor including: a source connected to a second power supply node to which a negative power supply voltage is applied, a gate configured to receive a first latch signal, and a drain connected to the source of the third n-channel field effect transistor; and At least one transistor is connected to the drain of the fourth n-channel field effect transistor.

9. The sense amplifier trigger as claimed in claim 1, wherein: The control circuit includes: a first n-channel field effect transistor including: a drain connected to an output node generating a bridge signal and a gate configured to receive an inverted data input; and a second n-channel field effect transistor including a drain connected to the output node and a gate configured to receive a data input, and The second level includes: a third n-channel field effect transistor comprising: a source connected to a second power supply node to which a negative power supply voltage is applied, a gate configured to receive a second latch signal, and a drain connected to the source of the first n-channel field effect transistor; a fourth n-channel field effect transistor comprising: a source connected to the second power supply node, a gate configured to receive the first latch signal, and a drain connected to the source of the second n-channel field effect transistor; at least one transistor connected to the drain of the third n-channel field effect transistor; and At least one transistor is connected to the drain of the fourth n-channel field effect transistor.

10. The sense amplifier trigger as claimed in claim 1, wherein: The bridge circuit includes a first n-channel field effect transistor including a source connected to a first pull-down node, a drain connected to a second pull-down node, and a gate configured to receive a bridge signal.

11. The sense amplifier trigger according to any one of claims 1 to 10, wherein: The second level is configured as: generating a logic high data output in response to activation of the first latch signal and deactivation of the second latch signal; and In response to the deactivation of the first latch signal and the activation of the second latch signal, a logic low data output is generated.

12. A sense amplifier trigger, comprising: The first stage is configured to: generate a first latch signal and a second latch signal by pulling down a first pull-down node or a second pull-down node according to a data input and an inverted data input in response to a rising edge of a clock signal; as well as The second stage is configured to generate a data output based on the first latch signal and the second latch signal, Wherein the first stage is configured to electrically connect the first pull-down node and the second pull-down node to each other when the data input transitions when the clock signal is logic high.

13. The sense amplifier trigger of claim 12, wherein: The first stage is configured to electrically disconnect the first pull-down node and the second pull-down node from each other based on the data input not transitioning when the clock signal is a logic high.

14. The sense amplifier trigger of claim 12, wherein: The first stage is configured to electrically disconnect the first pull-down node and the second pull-down node from each other when the clock signal is logic low.

15. The sense amplifier trigger of claim 12, wherein: The first stage is configured to detect a transition of the data input based on the data input, the inverted data input, the first latch signal, and the second latch signal when the clock signal is logic high.

16. The sense amplifier trigger as claimed in any one of claims 12 to 15, wherein: The second stage is configured to generate at least one internal signal based on at least one of the first latch signal and the second latch signal, and The first stage is configured to detect a transition of the data input based on the data input, the inverted data input, the first latch signal, the second latch signal, and the at least one internal signal when the clock signal is logic high.

17. A method of generating a data output by latching a data input based on a clock signal, the method comprising: In response to a rising edge of a clock signal, generating a first latch signal and a second latch signal by pulling down a first pull-down node or a second pull-down node according to a data input and an inverted data input; as well as generating a data output based on the first latch signal and the second latch signal, The steps of generating the first latch signal and the second latch signal include: detecting a transition of the data input while the clock signal is logic high; and When a transition of the data input is detected, the first pull-down node and the second pull-down node are electrically connected to each other.

18. The method according to claim 17, further comprising: The first pull-down node and the second pull-down node are electrically disconnected from each other based on the data input not transitioning when the clock signal is a logic high.

19. The method according to claim 17, further comprising: When the clock signal is logic low, the first pull-down node and the second pull-down node are electrically disconnected from each other.

20. The method according to any one of claims 17 to 19, wherein: The step of detecting the transition of the data input includes detecting the transition of the data input based on the data input, the inverted data input, the first latch signal, and the second latch signal.

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