Multi-chip for performing security authentication of

Abstract

A method of manufacturing a multi-chip includes generating a first authentication certificate in a first die using a private key of the first die, verifying the first authentication certificate in a second die using a public key of the first die, generating a second authentication certificate in the second die using a private key of the second die, and verifying the second authentication certificate in the second die using a public key of the second die. And verifying the second authentication certificate in the third die using the public key of the second die.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0112043 filed on August 25, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a multi-chip for performing chiplet security authentication and a method of manufacturing the same. Background Art

[0004] Recently, there have been increasing concerns about the risk of systems including spy chips that are vulnerable to hacking or data leakage. To prevent such risks, authentication of individual devices in a host device has been used. However, using conventional methods, it may be difficult to identify whether a spy die is present among the silicon die in a package during the manufacture of a chiplet. Summary of the invention

[0005] Example embodiments of the present disclosure provide a multi-chip for performing chiplet security authentication and a method for manufacturing the same. In an embodiment of the present disclosure, the multi-chip facilitates chiplet authentication at the package level and at the die level before the die is packaged into a complete semiconductor device.

[0006] According to an example embodiment of the present disclosure, a method for verifying the authentication of a multi-chip including a first die, a second die, and a third die may include generating a first authentication certificate in the first die using a private key of the first die; verifying the first authentication certificate in the second die based on a public key of the first die; generating a second authentication certificate in the second die based on the private key of the second die; and verifying the second authentication certificate in the third die based on the public key of the second die.

[0007] According to an example embodiment of the present disclosure, a method for verifying authentication of multiple chips may include connecting a first chip storing a first private key to a second chip storing a first public key paired with the first private key; performing a first authentication operation between the first chip and the second chip by generating a first authentication certificate by signing with the first private key and verifying the first authentication certificate by using the first public key; testing at least one function of the second chip; connecting the second chip storing a second private key to a third chip storing a second public key paired with the second private key; performing a second authentication operation between the second chip and the third chip by generating a second authentication certificate by signing with the second private key and verifying the second authentication certificate by using the second public key; and testing at least one function of the third chip.

[0008] According to an example embodiment of the present disclosure, a multi-chip includes a first die; a second die, which is disposed on the first die and is configured to communicate with the first die through a first chip-grain interface; and a third die, which is disposed on the second die and is configured to communicate with the second die through a second chip-grain interface, wherein the first die, the second die, and the third die are configured to perform authentication operations using pairs of private keys and public keys stored in different dies among the first die, the second die, and the third die.

[0009] According to an example embodiment of the present disclosure, a storage device may include at least one nonvolatile memory device; and a controller configured to control the at least one nonvolatile memory device, wherein the controller includes a first die configured to communicate with an external host device; and a second die configured to communicate with the first die through a chiplet interface and control the at least one nonvolatile memory device, wherein the first die and the second die perform a mutual authentication operation by generating an authentication certificate using a private key and verifying the authentication certificate using a public key. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a diagram illustrating security authentication of multiple chips according to an example embodiment of the present disclosure;

[0012] Figure 2A and Figure 2B is a diagram illustrating a process of inputting a private key and a public key in a process of manufacturing a multi-chip according to an example embodiment of the present disclosure;

[0013] Figure 3A and Figure 3B is a diagram illustrating an authentication operation when a second die is stacked on a first die according to an example embodiment of the present disclosure;

[0014] Figure 4A and Figure 4B is a diagram illustrating an authentication operation when a third die is stacked on a second die according to an example embodiment of the present disclosure;

[0015] Figure 5 is a diagram illustrating an authentication operation of a first die and a third die according to an example embodiment of the present disclosure;

[0016] Figure 6 is a diagram illustrating a process of performing security authentication on a multi-chip including a number k of dies according to an example embodiment of the present disclosure;

[0017] Fig. 7A , Figure 7B and Figure 7Cis a diagram illustrating a multi-chip according to various example embodiments of the present disclosure;

[0018] Figure 8 is a flow chart illustrating operations of manufacturing multiple chips according to an example embodiment of the present disclosure;

[0019] Fig. 9 is a diagram illustrating a storage device according to an example embodiment of the present disclosure;

[0020] Fig.10 is a diagram illustrating a host system according to an example embodiment of the present disclosure;

[0021] Fig.11 is a diagram illustrating a storage device according to another example embodiment of the present disclosure;

[0022] Fig.12 is a diagram illustrating a controller package according to another example embodiment of the present disclosure; and

[0023] Fig.13 is a diagram illustrating a memory system according to another example embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0025] A multi-chip and a method for manufacturing the same according to an example embodiment can provide die authentication in a core particle. Here, each die in the core particle may include an authentication circuit that is configured to perform a mutual authentication function based on interaction or communication with other dies in the core particle. Using a multi-chip and a method for manufacturing the same example embodiment, it is possible to verify whether the die is fake even if there is no main die representing a baseline or ideal state of the die before any potential tempering or unauthorized modification. The multi-chip and the method for manufacturing the same in the example embodiment can be implemented using an authentication request-response function and an algorithm for verification in the process of manufacturing the core particle. The multi-chip implements authentication by comparing the states between multiple monitored dies, without having to compare between the state of the monitored die and the state of the main die.

[0026] Figure 1 is a diagram illustrating security authentication of a multi-chip MCP according to an example embodiment. Figure 1, a multi-chip MCP may include multiple dies D1, D2, and D3. Each of the dies D1, D2, and D3 may be configured to perform a bidirectional security authentication operation, i.e., a mutual authentication operation. Authentication may occur in two directions between multiple dies within a multi-chip (e.g., from a first die to a second die and from a second die to a third die), thereby establishing mutual or bidirectional trust between the multiple dies. In an example embodiment, each of the dies D1, D2, and D3 may be implemented with a silicon die.

[0027] In an example embodiment, during the chip package assembly process, each of the dies D1, D2 and D3 can perform authentication signatures and verifications on each other. For example, when manufacturing a multi-chip MCP, a mutual authentication operation can be performed as follows. A first authentication certificate can be generated in the first die D1 using the private key of the first die D1. The first authentication certificate can be verified in the second die D2 using the public key of the first die D1. A second authentication certificate can be generated in the second die D2 using the private key of the second die D2. The second authentication certificate can be verified in the third die D3 using the public key of the second die D2. A third authentication certificate can be generated in the third die D3 using the private key of the third die D3. The third authentication certificate can be verified in the first die D1 using the public key of the third die D3.

[0028] During the wafer manufacturing process, a unique private key for each of the dies D1, D2, and D3 and a public key for the other dies included in the die package may be input / embedded. In an example embodiment, the private key and the public key may be stored in a read-only memory (ROM) during the manufacturing of the wafer. In another example embodiment, the private key and the public key may be stored in a one-time programming memory (OTP) in post-processing. In an example embodiment, a key may be selected using a value generated based on the ROM / OTP. Here, the management of the public key and the private key may be performed by a multi-chip manufacturer (server).

[0029] Figure 2A and Figure 2B 1 is a diagram illustrating a process of inputting a private key and a public key in a process of manufacturing a multi-chip (MCP) 1 according to an example embodiment. Figure 2A As shown, the multi-chip 1 may be implemented in a structure in which a first die D1, a second die D2, and a third die D3 are stacked. In an example embodiment, each of the first die D1, the second die D2, and the third die D3 may perform mutual authentication-based interaction among a plurality of dies (e.g., the first die D1, the second die D2, and the third die D3). Figure 2BAs shown, during the process of manufacturing the wafer, each private key and the public keys of other dies included in the die package may be input. Each die may contain its own private key and the public keys of other dies. For example, the first die D1 may store the private key of the first die D1 and the public keys of the second die D2 and the third die D3. The second die D2 may store the private key of the second die D2 and the public keys of the first die D1 and the third die D3. The third die D3 may store the private key of the third die D3 and the public keys of the first die D1 and the second die D2.

[0030] In an example embodiment, each of the first die D1, the second die D2, and the third die D3 may store a private key of the corresponding die and a public key of at least one other die in a read-only memory (ROM). In another example embodiment, each of the first die D1, the second die D2, and the third die D3 may store a private key of the corresponding die and a public key of at least one other die in a one-time programming memory (OTP) in post-processing.

[0031] In the following description, a process will be described in which security authentication is performed when manufacturing the multi-chip 1. For example, the security authentication operation may be performed when stacking dies.

[0032] Figure 3A and Figure 3B is a diagram illustrating an authentication operation when a second die D2 is stacked on a first die D1 according to an example embodiment. Figure 3A As shown, the second die D2 can be stacked on the first die D1. The authentication circuit CAC1 of the first die D1 can use the private key of the first die D1 to generate a signature value, that is, a first authentication certificate. The authentication circuit CAC2 of the second die D2 can use the public key of the first die D1 to verify the first authentication certificate of the first die D1. The above authentication operation can be performed in the opposite manner. The authentication circuit CAC2 of the second die D2 can sign using the private key of the second die D2, and the authentication circuit CAC1 of the first die D1 can verify the signature value of the second die D2 using the public key of the second die D2. At the same time, after the authentication operation, the first die D1 can perform a functional test on the second die D2.

[0033] Figure 4A and Figure 4B is a diagram illustrating an authentication operation when a third die D3 is stacked on a second die D2 according to an example embodiment. Figure 4AAs shown, the third die D3 can be stacked on the second die D2. The authentication circuit CAC2 of the second die D2 can use the private key of the second die D2 to generate a signature value, that is, a second authentication certificate. The authentication circuit CAC3 of the third die D3 can use the public key of the second die D2 to verify the second authentication certificate of the second die D2. The above authentication operation can also be performed in the opposite way. The authentication circuit CAC3 of the third die D3 can sign using the private key of the third die D3, and the authentication circuit CAC2 of the second die D2 can use the public key of the third die D3 to verify the signature value of the third die D3. After this authentication operation, the second die D2 can test the function of the third die D3.

[0034] Each of the authentication circuits CAC1 , CAC2 and CAC3 may store a private key and a public key required to perform authentication operations.

[0035] Figure 5 is a diagram illustrating an authentication operation of a first die D1 and a third die D3 according to an example embodiment. Figure 5 As shown, the authentication circuit CAC3 of the third die D3 can use the private key of the third die D3 to generate a signature value, that is, a third authentication certificate. The authentication circuit CAC1 of the first die D1 can use the public key of the third die D3 to verify the third authentication certificate of the third die D3. The above authentication operation can also be performed in the opposite way. The authentication circuit CAC1 of the first die D1 uses the private key of the first die D1 to sign, and the authentication circuit CAC3 of the third die D3 can use the public key of the first die D1 to verify the signature value of the first die D1. At the same time, after the authentication operation, the third die D3 can test the function of the first die.

[0036] As described above, a multi-chip according to an example embodiment may perform authentication based on interaction between a plurality of dies, each die storing its own private key and a public key of at least one other die. Figures 3A to 5 In the example, the multi-chip 1 includes three dies D1, D2 and D3, so that the authentication process can be performed three times. However, in the example embodiment, the authentication order and the number of times the authentication is performed are not limited thereto. In the example embodiment, the order of generating and verifying the signature value can also be reversed.

[0037] exist Figures 1 to 5 , a multi-chip including three cores is shown, but the number of cores in the exemplary embodiment is not limited thereto. A multi-chip including a number k (an integer equal to or greater than 2) of cores (or dies) can perform a mutual authentication algorithm during manufacturing.

[0038] Figure 6 is a diagram illustrating a process of performing security authentication on a multi-chip including a number k of dies according to an example embodiment. Figure 6, when the second die D2 is mounted on the first die D1, the first die D1 may issue an authentication certificate using a private key. The second die D2 may receive the authentication certificate of the first die D1, and may verify the authentication certificate of the first die D1 using the public key of the first die D1. Thereafter, when the third die D3 is mounted on the second die D2, the second die D2 may issue an authentication certificate using a private key. The third die D3 may receive the authentication certificate of the second die D2, and may verify the authentication certificate of the second die D2 using the public key of the second die D2.

[0039] As described above, the issuance of the authentication certificate and the verification of the authentication certificate may be repeatedly performed. When the kth die Dk is mounted on the k-1th die Dk-1, the k-1th die Dk-1 may issue an authentication certificate using a private key. The kth die Dk may receive the authentication certificate of the k-1th die Dk-1, and may verify the authentication certificate of the k-1th die Dk-1 using the public key of the k-1th die Dk-1. Finally, the kth die Dk may issue an authentication certificate using a private key. The first die D1 may receive the authentication certificate of the kth die Dk, and may verify the authentication certificate of the kth die Dk using the public key of the kth die Dk. Therefore, the mutual authentication operation of the entirety of the dies D1 to Dk included in the multi-chip may be completed.

[0040] The multi-chip according to example embodiments may be implemented as a combination of a logic integrated circuit (IC), an analog IC, a memory, or a non-volatile memory (NVM).

[0041] Fig. 7A , Figure 7B and Figure 7C is a diagram illustrating a multi-chip according to various example embodiments.

[0042] Reference Fig. 7A , the multi-chip 10 may include an analog chip 11 and a digital chip 12. Fig. 7A As shown, the digital chip 12 can be disposed on the analog chip 11, and the analog chip 11 can be combined with analog input and output circuits. Meanwhile, the arrangement of the analog chip 11 and the digital chip 12 is not limited thereto.

[0043] Refer again Fig. 7A , the analog chip 11 can store the private key of the analog chip 11 and the public key of the digital chip 12 to perform mutual authentication. The digital chip 12 can store the private key of the digital chip 12 and the public key of the analog chip 11 to perform mutual authentication. The private key and the public key can be embedded in each chip during the process of manufacturing the tube die.

[0044] Reference Figure 7B , the multi-chip 10a may include an analog chip 11, a digital chip 12, and a memory chip 13. Figure 7BAs shown, the digital chip 12 may be disposed on the analog chip 11, and the memory chip 13 may be disposed on the digital chip 12. Meanwhile, the arrangement of the analog chip 11, the digital chip 12, and the memory chip 13 is not limited thereto.

[0045] Return to reference Figure 7B , the analog chip 11 can store the private key of the analog chip 11, the public key of the digital chip 12, and the public key of the memory chip 13 to perform mutual authentication. The digital chip 12 can store the private key of the digital chip 12, the public key of the analog chip 11, and the public key of the memory chip 13 to perform mutual authentication. The memory chip 13 can store the private key of the memory chip 13, the public key of the analog chip 11, and the public key of the digital chip 12 to perform mutual authentication.

[0046] Reference Figure 7C The multi-chip 10b may include an analog chip 11, a digital chip 12, a volatile memory chip (e.g., a random access memory (RAM)) 13A, and a non-volatile memory chip (e.g., a read-only memory (ROM), a flash memory, and a hard disk drive) 13B. Figure 7C As shown, the digital chip 12 may be disposed on the analog chip 11, the volatile memory chip 13A may be disposed on the digital chip 12, and the nonvolatile memory chip 13B may be disposed on the volatile memory chip 13A. The arrangement of the analog chip 11, the digital chip 12, the volatile memory chip 13A, and the nonvolatile memory chip 13B is not limited thereto.

[0047] Refer again Figure 7C , the analog chip 11 can store the private key of the analog chip 11, the public key of the digital chip 12, the public key of the volatile memory chip 13A, and the public key of the non-volatile memory chip 13B to perform mutual authentication. The digital chip 12 can store the private key of the digital chip 12, the public key of the analog chip 11, the public key of the volatile memory chip 13A, and the public key of the non-volatile memory chip 13B to perform mutual authentication. The volatile memory chip 13A can store the private key of the volatile memory chip 13A, the public key of the analog chip 11, the public key of the digital chip 12, and the public key of the non-volatile memory chip 13B to perform mutual authentication. The non-volatile memory chip 13B can store the private key of the non-volatile memory chip 13B, the public key of the analog chip 11, the public key of the digital chip 12, and the public key of the volatile memory chip 13A to perform mutual authentication.

[0048] Each chip included in the chiplet can perform mutual authentication.

[0049] Figure 8 is a flow chart illustrating an operation of manufacturing a multi-chip according to an example embodiment. Figures 1 to 8, operations for manufacturing multiple chips can be performed.

[0050] The first chip and the second chip may be connected to each other (S110). An authentication operation (S120) may be performed between the first chip and the second chip. Here, the authentication operation may be a mutual authentication operation. When the authentication verification is successful, a first test operation (S130) may be performed on the function of the second chip that may be executed. Here, the first test operation may be performed on the first chip. Thereafter, the third chip may be connected to the second chip (S140). An authentication operation (S150) may be performed between the second chip and the third chip. When the authentication verification is successful, a second test operation (S160) may be performed on the function of the third chip that may be executed. Here, the second test operation may be performed on the first chip or the second chip.

[0051] In an example embodiment, each of the first chip, the second chip, and the third chip may include an authentication circuit configured to perform mutual authentication. In an example embodiment, the first chip may test the functions of the second chip and the third chip. In another example embodiment, the first chip may test at least one function of the second chip, and the second chip may test at least one function of the third chip. In an example embodiment, each of the first chip, the second chip, and the third chip may input a corresponding private key and a public key of at least one other chip during the process of manufacturing a wafer.

[0052] Example embodiments may be applicable to a memory device having a memory controller implemented as a chiplet.

[0053] Fig. 9 2 is a diagram illustrating a storage device 20 according to an example embodiment. Fig. 9 , the storage device 20 may include a plurality of media block circuits 21 - 1 and 21 - 2 and a storage controller 22 configured to control the blocks.

[0054] The memory controller 22 may include a first die SSU1 ( 22 - 1 ) and a second die SSU2 ( 22 - 2 ).

[0055] The first die SSU1 (22-1) may include a host block circuit. The host block circuit may be implemented to communicate with an external host device through a host interface. Here, the host interface may be implemented as an interface of a storage device, such as Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), SCSIe, Serial Advanced Technology Attachment (SATA), SATAe, or Computer Express Link (CXL).

[0056] The second die SSU2 (22-2) may include first and second media block circuits. Each of the first and second media block circuits may be implemented to communicate with the corresponding media block circuits 21-1 and 21-2 via a media interface. Here, the media interface may be an interface of a memory device, such as a NAND interface, a NOR interface, etc.

[0057] In addition, the first die 22-1 and the second die 22-2 may be connected to each other through a core particle interface. In other words, the sub-silicon boards SSU1 and SSU2 of the storage controller 22 may communicate with each other according to the core particle interface. In an example embodiment, the core particle interface may include a universal chip interconnect express (UCIe) interface. In addition, the first die 22-1 and the second die 22-2 may be implemented to perform a mutual authentication operation in the manufacturing process as described above, and to perform a test operation.

[0058] Fig.10 is a diagram illustrating a host system 30 according to an example embodiment. Fig.10 , the host system 30 may include a host device 31 and a storage device 32 .

[0059] The host system 30 may be implemented as a server computer, a personal computer (PC), a desktop computer, a laptop computer, a workstation computer, a network attached storage device (NAS), a data center, an Internet data center (IDC), or a mobile computing device. For example, the mobile computing device may be implemented as a smart phone, a tablet computer, or a mobile Internet device (MID).

[0060] The host device 21 may be implemented to control data processing operations (e.g., write operations or read operations) of the storage device 32. The host device 21 may include at least one of a central processing unit (CPU), a buffer memory, a memory device, a memory controller, and an interface circuit. The host device 21 may be implemented as an integrated circuit, a mainboard, or a system on a chip. In an example embodiment, the host device 21 may be implemented as an application processor or a mobile application processor.

[0061] The CPU can exchange commands or data with the buffer memory, memory controller and interface circuit through the bus architecture. In an example embodiment, the bus architecture can be implemented as an advanced microcontroller bus architecture (AMBA), an AMBA advanced extensible interface (AXI), an AMBA advanced high-performance bus (AHB) or an advanced interface bus (AIB). The buffer memory can store queues. In an example embodiment, the buffer memory can be implemented as a register or a static random access memory (SRAM). The queue may include a submission queue. The queue may store commands (e.g., write commands or read commands). In an example embodiment, the queue may further include a completion queue.

[0062] The memory device may be implemented as a volatile memory device or a non-volatile memory device. Here, the volatile memory may be implemented as a random access memory (RAM), SRAM or dynamic RAM DRAM. The non-volatile memory may also be implemented as NAND flash memory, NOR flash memory, phase change RAM (PRAM), magnetoresistive RAM (MRAM), spin transfer torque magnetic random access memory (STT-MRAM), ferroelectric RAM (FRAM) or resistive RAM (RRAM). The memory controller may write data to the memory device under the control of the CPU, or may read stored data from the memory device. In an example embodiment, the memory controller may include the function of a direct memory access (DMA) controller. The interface circuit may be connected to the host interface circuit 250HIF of the storage device 32 via a predetermined host interface.

[0063] The storage device 32 may include at least one nonvolatile memory device (NVM, 100) and a controller 200. At least one nonvolatile memory device 100 may be implemented to store data. The nonvolatile memory device 100 may be implemented as a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), and a spin transfer torque random access memory (STT-RAM). Hereinafter, for ease of description, the nonvolatile memory device 100 will be referred to as a vertical NAND flash memory device.

[0064] The controller 200 may be connected to at least one nonvolatile memory device 100 through a plurality of control pins that transmit control signals (e.g., a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip activation (CE) signal, a write enable (WE) signal, a read enable (RE) signal, etc.). In addition, the controller 200 may be implemented to control the nonvolatile memory device 100 using the control signals (CLE, ALE, CE, WE, RE, etc.). For example, the nonvolatile memory device 100 may perform a program operation / read operation / erase operation by latching a command (CMD) or an address (ADD) at the edge of a WE signal according to a CLE signal and an ALE signal. For example, during a read operation, the CE signal may be activated, the CLE signal may be activated during a command transmission period, the ALE signal may be activated during an address transmission period, and the RE signal may be switched in a period in which data is transmitted through a data signal line (DQ). The data strobe signal DQS may be switched at a frequency corresponding to a data input / output speed. The read data may be sequentially transmitted in synchronization with a data strobe signal (DQS).

[0065] Furthermore, the controller 200 may be implemented to control overall operations of the storage device 32. The controller 200 may include at least one processor 210, a buffer memory 220, an error correction circuit 230, at least one nonvolatile memory interface circuit (NIF) 240, and a host interface circuit (HIF) 250.

[0066] At least one processor 210 (e.g., a CPU) may be implemented to control the overall operation of the storage device 32. The processor 210 may perform various managements, such as cache / buffer management, firmware management, garbage collection management, wear leveling management, data anti-duplication management, read refresh / reclaim management, bad block management, multi-stream management, mapping management between host data and non-volatile memory, quality of service (QoS) management, system resource allocation management, non-volatile memory queue management, read level management, erase / program management, hot / cold data management, power-off protection management, dynamic thermal management, initialization management, and redundant array of inexpensive disks (RAID). These management operations may be implemented according to hardware / firmware / software.

[0067] The buffer memory 220 may be implemented to temporarily store data required for the operation of the storage device 32. For example, the buffer memory 220 may temporarily store data to be written to the nonvolatile memory device 100 or data read from the nonvolatile memory device 100. In an example embodiment, the buffer memory 220 may be configured to be included in the controller 200. In another example embodiment, the buffer memory 220 may be provided outside the controller 200. In addition, the buffer memory 220 may be implemented as a volatile memory (e.g., a static random access memory (SRAM), a dynamic RAM DRAM, a synchronous RAM (SDRAM), etc.) or a nonvolatile memory (a flash memory, a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), etc.).

[0068] The error correction circuit 230 may be implemented to generate an error correction code ECC during a program operation, and may use the error correction code to recover data during a read operation. That is, the error correction circuit 230 may generate an error correction code ECC for correcting a fail bit or an error bit of data received from the nonvolatile memory device 100. In addition, the error correction circuit 230 may form data to which a parity bit is added by performing error correction encoding on the data provided to the nonvolatile memory device 100. The parity bit may be stored in the nonvolatile memory device 100.

[0069] In addition, the error correction circuit 230 may perform error correction decoding on the data output from the nonvolatile memory device 100. The error correction circuit 230 may use parity check to correct errors. The error correction circuit 230 may use low-density parity check (LDPC) codes, BCH codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), and coded modulation such as trellis coded modulation (TCM) and block coded modulation (BCM) to correct errors. When an error cannot be corrected in the error correction circuit 230, a read retry operation may be performed.

[0070] At least one nonvolatile memory interface circuit (NIF) 240 may exchange data through the above-mentioned plurality of pins in at least one nonvolatile memory device 100. The nonvolatile memory interface circuit 240 may transmit data to be written to the nonvolatile memory 100 to the nonvolatile memory 100, or may receive data read from the nonvolatile memory 100. The memory interface circuit 240 may be implemented to comply with a standard protocol such as JEDEC, Toggle, or ONFI.

[0071] The host interface circuit (HIF) 250 may be implemented to provide an interface function with the host device 21. The host interface circuit 250 may be implemented to send packets to the host and receive packets from the host. The packet sent from the host to the host interface circuit 250 may include a command or data to be written to the non-volatile memory 100. The packet sent from the host interface circuit 250 to the host may include a response to a command or data read from the non-volatile memory 100.

[0072] In an example embodiment, a host interface circuit (HIF) 250 may be formed on a first die Die1, and other components 210, 220, 230, and 240 may be formed on a second die Die2. Here, the first die and the second die may be implemented to communicate with each other through a core particle interface. Each of the other components 210, 220, 230, and 240 may communicate with each other using a core particle interface. For example, the other components 210, 220, 230, and 240 may be connected to a system bus that supports a core particle interface. Here, the system bus may be an advanced interface bus (AIB). The first die and the second die may be implemented as described above to perform mutual authentication during the manufacturing process.

[0073] The controller 200 may further include an encryption device to improve information protection. The encryption device may perform at least one of an encryption operation and a decryption operation on data input to the controller 200 using a symmetric key algorithm. The encryption device may perform encryption and decryption of data using an advanced encryption standard (AES) algorithm. The encryption device may include an encryption module and a decryption module. In an example embodiment, the encryption device may be implemented according to hardware / software / firmware. The encryption device may perform a self-encrypting disk (SED) function or a trusted computing group (TCG) security function. The SED function may store encrypted data in the non-volatile memory device 100 using an encryption algorithm, or may decrypt encrypted data from the non-volatile memory device 100. The encryption / decryption operation may be performed using an internally generated encryption key. The TCG security function may provide a mechanism capable of performing access control on user data of the non-volatile memory device 100. For example, the TCG security function may perform an authentication process between an external device and the non-volatile memory device 100. In an example embodiment, the SED function or the TCG security function may be optionally selected.

[0074] exist Fig.10 In the controller 200 shown, the host interface circuit 250 and other components 210, 220, 230 and 240 may be formed on different dies. However, example embodiments thereof are not limited thereto, and the components in the controller may be formed on a sub-silicon board in various combinations.

[0075] Fig.11 is a diagram illustrating a storage device 1000 according to another example embodiment. Fig.11 , the storage device 1000 may include a controller 1100 in which internal components are arranged in three dies.

[0076] The controller 1100 may include a host interface circuit 1150 located on a first die Die1, a processor 1110 located on a second die Die2, a buffer memory 1120, and a volatile memory controller 1160, and a non-volatile memory interface circuit 1140a located on a third die Die3. Here, the first die Die1, the second die Die2, and the third die Die3 may be implemented as different sub-silicon boards. In an example embodiment, the first die Die1, the second die Die2, and the third die Die3 may communicate with each other through a core particle interface (e.g., UCIe). In addition, each of the first to third dies may be implemented to perform mutual authentication during the manufacturing process.

[0077] exist Fig.11In the embodiment of the present invention, the processor 1110, the buffer memory 1120 and the volatile memory controller 1160 may be arranged on the second die Die2. However, the exemplary embodiments thereof are not limited thereto. For example, the processor, the buffer memory and the volatile memory controller may be arranged only on the first die Die1 or only on the third die Die3. That is, the processor, the buffer memory and the volatile memory controller may be arranged in at least one of the first die Die1, the second die Die2 and the third die Die3 in various combinations.

[0078] Fig.12 2 is a diagram showing a controller package 2000 according to another example embodiment. Fig.12 , the controller package 2000 may include a package substrate 2001 , a first die Die1 2100 , a second die Die2 2200 , and a third die Die3 2300 .

[0079] The first die 2100 may include a host interface circuit. In an example embodiment, the first die 2100 may be configured as a sub-silicon board disposed on the package substrate 2001. The second die 2200 may include a processor. In an example embodiment, the second die 2200 may be configured as a sub-silicon board disposed on the package substrate 2001. The third die 2300 may include a non-volatile memory interface circuit. In an example embodiment, the third die 2300 may be configured as a sub-silicon board disposed on the package substrate 2001.

[0080] In example embodiments, the first die 2100 and the second die 2200 may be connected to each other based on a chiplet interface. In example embodiments, the second die 2200 and the third die 2300 may be connected to each other based on a chiplet interface.

[0081] Example embodiments may be applicable to a process of manufacturing a high bandwidth memory (HBM) that provides a memory interface for a three-dimensional (3D) stacked synchronous dynamic random access memory (SDRAM).

[0082] Fig.13 is a diagram showing a memory system 3000 according to another example embodiment. Fig.13 , the memory system 3000 may include a plurality of memory modules 3300 - 1 , 3300 - 2 , 3300 - 3 , and 3300 - 4 and a controller (CTRL) 3400 . In example embodiments, an interposer 3200 may be further provided on the package substrate 3100 , optionally.

[0083] The memory system 3000 may be implemented to be included in a personal computer (PC) or a mobile electronic device. The mobile electronic device may include a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, and a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a drone.

[0084] Each of the memory modules 3300-1, 3300-2, 3300-3, and 3300-4 may be implemented to be mounted on a package substrate 3100 such as a printed circuit board. In addition, each of the memory modules 3300-1 to 3300-4 may be connected to the controller 3400 through channels CH1 to CH4 and may be implemented with a chip on chip (CoC).

[0085] In addition, each of the memory modules 3300-1 to 3300-4 may include a buffer chip 3310 and at least one memory chip 3320 (MEM). Here, the buffer chip 3310 and the at least one memory chip 3320 may be connected to each other through through silicon vias (TSVs).

[0086] The buffer chip 3310 may be implemented to perform a buffer function on data of the memory chip 3320. In addition, the buffer chip 3310 may be implemented to perform a training operation on the memory chip 3320.

[0087] The memory chip 3320 (MEM) may be implemented as a volatile memory device or a non-volatile memory device. In an example embodiment, the volatile memory device may be implemented as a random access memory (RAM), a dynamic RAM (DRAM), a static RAM (SRAM), or a low power double data rate (LPDDR) DRAM. In an example embodiment, the non-volatile memory device may be implemented as an electrically erasable programmable read-only memory (EPROM), a NOAH flash memory, a NAND flash memory, a magnetoresistive random access memory (MRAM), a spin transfer torque (STT)-MRAM, a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory.

[0088] In example embodiments, each of the memory modules 3300 - 1 , 3300 - 2 , 3300 - 3 , and 3300 - 4 may be implemented as a high bandwidth memory (HBM). Fig.13 The number of the illustrated memory modules 3300-1, 3300-2, 3300-3, and 3300-4 is not limited thereto.

[0089] Controller (CTRL) 3400 may be implemented to control memory modules 3300-1, 3300-2, 3300-3, and 3300-4 connected to the channels, respectively. In an example embodiment, controller 3400 may be implemented as a system on chip (SoC), an application processor (AP), a mobile AP, a chipset, or a chipset. Controller 1400 may include a random access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a modem. In an example embodiment, controller 3400 may perform a modem function and an AP function.

[0090] In addition, the controller 3400 may be implemented to control the memory chip 3320 to read data stored in the memory chip 3320 or write data to the memory chip 3320. The controller 3400 may control the write operation or read operation of the memory chip 3320 by providing a command and an address to the memory chip 3320 in synchronization with a clock signal. In addition, data may be transmitted and received between the controller 3400 and the memory chip 3320 in synchronization with a data transfer clock.

[0091] In an example embodiment, in the process of manufacturing each of the plurality of memory modules 3300-1, 3300-2, 3300-3, and 3300-4 of the memory system 3000, when stacking memory chips, a mutual authentication operation may be performed. In addition, in the process of manufacturing the controller (CTRL) 3400, a mutual authentication operation may be performed by a core particle (i.e., chip) unit. In addition, a mutual authentication operation may be performed in the process of packaging the memory modules 3300-1, 3300-2, 3300-3, and 3300-4 and the controller 3400.

[0092] Example embodiments may be applicable to various memory modules. For example, the memory module may be implemented as a single inline memory module (SIMM), a dual inline memory module (DIMM), a small outline DIMM (SODIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FBDIMM), a rank-buffered DIMM (RBDIMM), a mini DIMM, a micro DIMM, a registered DIMM (RDIMM), or a load-reduced DIMM (RDIMM).

[0093] The above-mentioned device can be implemented with a combination of hardware components, software components and / or hardware components and software components. For example, the devices and components described in the example embodiments can be implemented using one or more general or special computers, such as processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable gate arrays (FPGAs) and programmable logic units (PLUs), microprocessors or any other devices that can execute instructions and responses. The processing device can execute an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device can access, store, manipulate, process and generate data in response to the execution of software. For ease of description, a single processing device can be used, but the processing device can include multiple processing elements or multiple types of processing elements. For example, the processing device can include multiple processors or a processor and a controller. In addition, other processing configurations such as parallel processors are possible.

[0094] Software may include computer programs, codes, instructions, or a combination of one or more thereof, and may configure a processing device to operate as required or to instruct the processing device independently or collectively. Software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device to be interpreted by or to provide instructions or data to the processing device. Software may be distributed on networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0095] According to the above-described exemplary embodiments, a multi-chip and a method for manufacturing the same can ensure die reliability by implementing mutual authentication between dies during the manufacturing process.

[0096] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A method for verifying authentication of a multi-chip including a first die, a second die, and a third die, the method comprising: generating a first authentication certificate in the first die based on the private key of the first die; verifying the first authentication certificate in the second die based on the public key of the first die; generating a second authentication certificate in the second die based on the private key of the second die; as well as The second authentication certificate is verified in the third die based on the public key of the second die.

2. The method according to claim 1, wherein: The first die, the second die and the third die respectively include a first authentication circuit, a second authentication circuit and a third authentication circuit, and the first authentication circuit, the second authentication circuit and the third authentication circuit are configured to perform mutual authentication based on an interaction between the first die, the second die and the third die.

3. The method according to claim 1, further comprising: storing the private key of the first die, the public key of the second die, and the public key of the third die in a wafer of the first die; storing the private key of the second die, the public key of the first die, and the public key of the third die in a wafer of the second die; as well as The private key of the third die, the public key of the first die, and the public key of the second die are stored in a wafer of the third die.

4. The method according to claim 1, wherein: Each of the first die, the second die, and the third die stores a private key of the corresponding die and a public key of at least one other die in a read-only memory ROM.

5. The method according to claim 1, wherein: Each of the first die, the second die and the third die stores a private key of the corresponding die and a public key of at least one other die in a one-time programming memory OTP in a post-process.

6. The method according to claim 1, further comprising: generating a third authentication certificate in the third die using the private key of the third die; as well as The third authentication certificate is verified in the first die using the public key of the third die.

7. The method according to claim 1, further comprising: Before generating the first authentication certificate, stacking the second die on the first die; The third die is stacked on the second die before generating the second authentication certificate.

8. The method according to claim 1, wherein: The first die, the second die, and the third die include at least one of an analog chip, a digital chip, and a memory chip.

9. The method according to claim 1, further comprising: After performing mutual authentication between at least one of the first die, the second die, and the third die and at least another one, a function of the at least one of the first die, the second die, and the third die is tested.

10. The method according to claim 1, wherein: The first die, the second die, and the third die communicate with each other via a die-grain interface.

11. A method for verifying the authentication of multiple chips, the method comprising: connecting a first chip storing a first private key to a second chip storing a first public key paired with the first private key; performing a first authentication operation between the first chip and the second chip by generating a first authentication certificate by signing with the first private key and verifying the first authentication certificate with the first public key; testing at least one function of the second chip; connecting the second chip storing a second private key to a third chip storing a second public key paired with the second private key; performing a second authentication operation between the second chip and the third chip by generating a second authentication certificate by signing with the second private key and verifying the second authentication certificate using the second public key; and At least one function of the third chip is tested.

12. The method according to claim 11, wherein: The first chip, the second chip and the third chip respectively include a first authentication circuit, a second authentication circuit and a third authentication circuit, and the first authentication circuit, the second authentication circuit and the third authentication circuit are configured to perform mutual authentication based on interaction between the first chip, the second chip and the third chip.

13. The method according to claim 11, wherein: The test on the at least one function of the second chip and the test on the at least one function of the third chip are performed by the first chip.

14. The method according to claim 11, in, The testing of the at least one function of the second chip is performed by the first chip, and The test on the at least one function of the third chip is performed by the second chip.

15. The method according to claim 11, further comprising: During manufacturing of the first chip, storing the first private key in the first chip; storing the first public key and the second private key in the second chip during manufacturing of the second chip; as well as The second public key is stored in the third chip during manufacturing of the third chip.

16. A multi-chip comprising: a first tube core; a second die disposed on the first die and configured to communicate with the first die via a first die-grain interface; a third die disposed on the second die and configured to communicate with the second die via a second die-grain interface, The first die, the second die, and the third die are configured to perform an authentication operation using a pair of a private key and a public key stored in a different die among the first die, the second die, and the third die.

17. The multi-chip according to claim 16, wherein: The first die includes a first authentication circuit configured to perform the authentication operation based on a first pair of a first private key and a first public key, among the pairs of private keys and public keys, stored in the first die and the second die, respectively.

18. The multi-chip according to claim 17, wherein: The second die includes a second authentication circuit configured to perform the authentication operation based on a second pair of a second private key and a second public key, among the pair of private keys and public keys, stored in the second die and the third die, respectively.

19. The multi-chip according to claim 16, wherein: The multi-chip functions as a storage device controller or a high bandwidth memory HBM.

20. The multi-chip according to claim 16, wherein: The authentication operation is a mutual authentication operation performed based on an interaction between the first die, the second die, and the third die.

Images