Semiconductor device, method of fabrication, and memory system

Abstract

This application discloses a semiconductor device, fabrication method, and memory system, comprising: a semiconductor pillar extending along a first direction Y; a gate dielectric layer surrounding the side of the semiconductor pillar; a gate electrode connected to the gate dielectric layer; a first insulating layer surrounding the gate electrode and the semiconductor pillar; a second insulating layer located above the first insulating layer; a connection portion located above and connected to the semiconductor pillar, wherein at least a portion of the connection portion is located above the first insulating layer; and a conductive portion located on the side of the connection portion away from the semiconductor pillar, connected to the connection portion. The semiconductor device provided by this application extends the structure of the semiconductor pillar through the connection portion, thereby allowing the conductive portion to be fully retained, thus improving the connection stability between the conductive portion and other components, and greatly improving the yield of the semiconductor device.

Description

Technical Field

[0001] The embodiments of this application relate to the field of electronic device technology, and in particular to a semiconductor device, a fabrication method, and a memory system. Background Technology

[0002] Capacitors are crucial components in semiconductor devices. During capacitor manufacturing, the connection points in transistors are often over-etched and damaged, causing the capacitors to fail to meet production standards and leading to quality problems in subsequent use of the semiconductor device. Summary of the Invention

[0003] Embodiments of this application provide a semiconductor device, a fabrication method, and a memory system to solve the technical problem that connection points in transistors are easily over-etched in the prior art.

[0004] To address the aforementioned technical problems, embodiments of this application disclose the following technical solutions:

[0005] In a first aspect, a semiconductor device is provided, comprising:

[0006] A semiconductor pillar extending along a first direction Y;

[0007] A gate dielectric layer surrounding the side of the semiconductor pillar;

[0008] A gate, wherein the gate is connected to the gate dielectric layer;

[0009] A first insulating layer surrounds the gate and the semiconductor pillar;

[0010] A second insulating layer is located above the first insulating layer;

[0011] A connecting portion, the connecting portion being located above and connected to the semiconductor pillar, wherein at least a portion of the connecting portion is located above the first insulating layer;

[0012] A conductive portion is located on the side of the connecting portion away from the semiconductor pillar, and the conductive portion is connected to the connecting portion.

[0013] In conjunction with the first aspect, it also includes a capacitor structure located on the side of the conductive portion away from the connecting portion and coupled to the conductive portion, wherein the second insulating layer surrounds the peripheral side surface of the capacitor structure.

[0014] In conjunction with the first aspect, it also includes a stop layer located between the first insulating layer and the second insulating layer, the stop layer surrounding the connection portion; or

[0015] The stop layer surrounds the connection portion and the conductive portion.

[0016] In conjunction with the first aspect, the second insulating layer surrounds the conductive portion; or

[0017] The second insulating layer surrounds the connection portion and the conductive portion.

[0018] In conjunction with the first aspect, the conductive part is electrically connected to the connecting part, and the material of the conductive part includes metal silicide.

[0019] In conjunction with the first aspect, the connecting portion includes an epitaxially grown semiconductor, and the connecting portion is made of the same material as the semiconductor pillar.

[0020] In a second aspect, a method for fabricating a semiconductor device is provided, the method comprising:

[0021] A semiconductor pillar is formed, the semiconductor pillar extending along a first direction;

[0022] A gate dielectric layer is formed around the side of the semiconductor pillar;

[0023] A gate is formed around the gate dielectric layer;

[0024] A first insulating layer is formed around the semiconductor pillar and the gate;

[0025] A second insulating layer is formed on the first insulating layer, and the second insulating layer is etched to form a connection trench to expose the semiconductor pillar;

[0026] A connection portion is formed in the connection groove, the connection portion being located above and connected to the semiconductor pillar, wherein at least a portion of the connection portion is located above the first insulating layer;

[0027] A conductive portion connected to the connecting portion is formed in the connecting groove, and the conductive portion is located on the side of the connecting portion away from the semiconductor pillar.

[0028] In conjunction with the second aspect, after the conductive portion is formed, a capacitor structure is formed in the connecting groove, and the capacitor structure is coupled to the conductive portion.

[0029] In conjunction with the second aspect, prior to forming the connecting groove, the preparation method further includes:

[0030] A stop layer is formed on the first insulating layer and the semiconductor pillar;

[0031] A second insulating layer is formed on the stop layer, and the second insulating layer covers the stop layer;

[0032] A mask layer is formed on the second insulating layer, the mask layer covering the second insulating layer;

[0033] The stop layer, the first insulating layer and the mask layer are etched away along the first direction Y to form a connection trench to expose the semiconductor pillar.

[0034] In conjunction with the second aspect, there are multiple semiconductor pillars and multiple connecting slots, with each connecting slot corresponding to one of the semiconductor pillars.

[0035] In conjunction with the second aspect, the method of forming a connection on the semiconductor pillar includes:

[0036] The semiconductor pillar is used to form the connection portion within the connection groove using an epitaxial growth process.

[0037] Both the connecting part and the semiconductor pillar are made of silicon.

[0038] In conjunction with the second aspect, the method for forming a conductive portion on the connecting portion includes:

[0039] The conductive portion is deposited and formed within the connecting groove; and

[0040] Remove the mask layer to expose the second insulating layer;

[0041] The conductive part covers the connecting part, and the conductive part is electrically connected to the connecting part.

[0042] In conjunction with the second aspect, the material of the conductive part includes silicon titanium.

[0043] Thirdly, a memory system is provided, comprising:

[0044] Semiconductor devices as described in any embodiment of the first aspect;

[0045] A controller, which is electrically connected to the semiconductor device, is used to control the semiconductor device.

[0046] One of the above technical solutions has the following advantages or beneficial effects:

[0047] Compared with the prior art, this application provides a semiconductor device, including: a semiconductor pillar extending along a first direction Y; a gate dielectric layer surrounding the side of the semiconductor pillar; a gate electrode connected to the gate dielectric layer; a first insulating layer surrounding the gate electrode and the semiconductor pillar; a second insulating layer located above the first insulating layer; a connection portion located above and connected to the semiconductor pillar, wherein at least a portion of the connection portion is located above the first insulating layer; and a conductive portion located on the side of the connection portion away from the semiconductor pillar, connected to the connection portion. The semiconductor device provided by this application extends the structure of the semiconductor pillar through the connection portion, thereby allowing the conductive portion to be completely retained, thus improving the connection stability between the conductive portion and other components, and greatly improving the yield of the manufactured semiconductor device.

[0048] This application provides a method for fabricating a semiconductor device. The method includes: forming a semiconductor pillar, wherein the semiconductor pillar extends along a first direction and a gate dielectric layer is formed around the side of the semiconductor pillar; forming a gate surrounding the gate dielectric layer; forming a first insulating layer surrounding the semiconductor pillar and the gate; forming a second insulating layer on the first insulating layer; etching the second insulating layer to form a connection trench to expose the semiconductor pillar; forming a connection portion in the connection trench, the connection portion being located above and connected to the semiconductor pillar, wherein at least a portion of the connection portion is located above the first insulating layer; and forming a conductive portion in the connection trench connected to the connection portion, the conductive portion being located on the side of the connection portion away from the semiconductor pillar. This application ensures that the semiconductor pillar and the conductive portion are completely preserved by forming the second insulating layer after forming the semiconductor pillar and then etching to expose the semiconductor pillar, thereby improving the connection stability of the conductive portion with other components and thus increasing the yield of the semiconductor device. Attached Figure Description

[0049] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0050] Figure 1 This is a schematic diagram of the first preparation method provided in the embodiments of this application;

[0051] Figure 2 This is a schematic diagram of the transition etching structure provided in an embodiment of this application;

[0052] Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0053] Figure 4 A schematic cross-sectional view of the semiconductor layer and semiconductor pillars provided in an embodiment of this application;

[0054] Figure 5A top view of the semiconductor layer and semiconductor pillars provided in an embodiment of this application;

[0055] Figure 6 This is a schematic cross-sectional view of the gate structure provided in an embodiment of this application.

[0056] Figure 7 This is a schematic cross-sectional view of the structure after the formation of the first insulating layer, provided in an embodiment of this application.

[0057] Figure 8 This is a schematic diagram of the cross-sectional structure after the deposition of the mask layer provided in an embodiment of this application;

[0058] Figure 9 This is a schematic cross-sectional view of the etching-formed connection groove provided in an embodiment of the present application;

[0059] Figure 10 This is a schematic cross-sectional view of the connecting portion provided in an embodiment of this application;

[0060] Figure 11 This is a cross-sectional structural diagram of the conductive portion provided in an embodiment of this application;

[0061] Figure 12 This is a schematic diagram of the cross-sectional structure after removing the mask layer, provided in an embodiment of this application.

[0062] Figure 13 This is a cross-sectional structural diagram of the capacitor structure provided in an embodiment of this application.

[0063] The attached figures are labeled as follows:

[0064] 100-Semiconductor layer, 101-Substrate, 110-Semiconductor pillar, 111-First trench, 112-Second trench, 113-Third trench, 120-Gate, 130-Gate dielectric layer, 140-First insulating layer, 150-Air gap, 210-Stop layer, 220-Second insulating layer, 230-Mask layer, 240-Connection portion, 250-Conductive portion, 300-Connection trench, 400-Capacitor structure. Detailed Implementation

[0065] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0066] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0067] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0068] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0069] This paper uses a Cartesian coordinate system (X, Y, and Z) to represent the cross-section of the memory in various directions, where the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

[0070] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0071] The memory in this embodiment of the invention can be a wafer or a three-dimensional memory. Three-dimensional memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data, etc. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products, etc.

[0072] Please see Figure 1 and Figure 2 , Figure 1 and Figure 2 This is a semiconductor device fabrication step in some other embodiments of this disclosure, which includes the following steps before this step: depositing a conductive portion 250 on the formed semiconductor pillar 110, then forming a gate dielectric layer 130 and a gate 120, then depositing a first insulating layer 140, the upper surface of the first insulating layer 140 being flush with the top of the conductive portion 250, and then sequentially depositing a stop layer 210, a second insulating layer 220 and a mask layer 230; then obtaining the semiconductor device fabrication step by a first etching method. Figure 1 The structure shown in the left figure is then further processed by a second etching method to remove the stop layer 210 to expose the conductive portion 250, resulting in the structure shown in the left figure. Figure 1 The structure shown in the right figure. However, during the second etching, due to the inability to ensure the etching progress, the conductive part 250 was either completely or partially etched, resulting in the following... Figure 2 The structure shown leads to the semiconductor device becoming unusable, resulting in low yield. This application proposes a new semiconductor structure and fabrication method to avoid over-etching of the semiconductor device during the second etching process.

[0073] Please see Figure 13 , Figure 13This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. An embodiment of this application provides a semiconductor device including a semiconductor pillar 110, a gate dielectric layer 130, a gate 120, a first insulating layer 140, a second insulating layer 220, a connection portion 240, and a conductive portion 250. The semiconductor pillar 110 extends along a first direction Y; the gate dielectric layer 130 surrounds the side of the semiconductor pillar 110; the gate 120 is connected to the gate dielectric layer 130; the first insulating layer 140 surrounds the gate 120 and the semiconductor pillar 110; the second insulating layer 220 is located above the first insulating layer 140; the connection portion 240 is located above and connected to the semiconductor pillar 110, wherein at least a portion of the connection portion 240 is located above the first insulating layer 140; the conductive portion 250 is located on the side of the connection portion 240 away from the semiconductor pillar 110, and the conductive portion 250 is connected to the connection portion 240. It is understood that the semiconductor pillar 110, along with its side gate 120 and gate dielectric layer 130, can constitute a transistor, and the transistor's conduction can be controlled by applying a voltage to the gate 120. In this application, the connection portion 240 extends the semiconductor pillar 110, thereby reducing the impedance between the conductive portion 250 and the semiconductor pillar 110. It should be noted that the connection portion 240 can be grown using an epitaxial process. Generally, the epitaxially grown connection portion 240 is made of the same material as the semiconductor pillar 110, typically Si. In some other cases, the epitaxially grown connection portion 240 may be made of a different material than the semiconductor pillar 110, such as the semiconductor pillar 110 being SiGe or SiC, while the connection portion 240 is made of Si. The connection portion 240, obtained through epitaxial growth, extends the structure of the semiconductor pillar 110, improves the fabrication process, and allows the conductive portion 250 to be completely preserved, thereby improving the connection stability between the conductive portion 250 and other components and greatly increasing the yield of semiconductor device manufacturing.

[0074] In some optional embodiments of this disclosure, please refer to Figure 13 It also includes a capacitor structure 400, which is located on the side of the conductive portion 250 away from the connecting portion 240 and coupled to the conductive portion 250. A second insulating layer 220 surrounds the peripheral side of the capacitor structure 400. It is understood that after the semiconductor pillar 110 is coupled to the capacitor structure 400 via the conductive portion 250, a dynamic random access memory (DRAM) cell is formed. This memory cell stores corresponding data and is used in different scenarios. The capacitor structure 400 can be one or more of a pillar capacitor, a cylindrical capacitor, or a cup-shaped capacitor.

[0075] In some optional embodiments of this disclosure, please refer to Figure 13The system also includes a stop layer 210, which is located between the first insulating layer 140 and the second insulating layer 220, surrounding the connection portion 240; or the stop layer 210 surrounds the connection portion 240 and the conductive portion 250. It is understood that the composition of the stop layer 210 is different from that of the second insulating layer 220, resulting in a higher etching rate for the second insulating layer 220 during the etching process compared to the stop layer 210. This reduces over-etching of the semiconductor pillar 110 after the stop layer 210 penetrates through it, thus preventing damage to the semiconductor pillar 110 and improving the yield of the semiconductor structure. Simultaneously, the stop layer 210 surrounding the connection portion 240 or surrounding the connection portion 240 and the conductive portion 250 not only supports the connection portion 240 and the conductive portion 250 but also insulates adjacent connection portions 240 and the conductive portion 250.

[0076] In some optional embodiments of this disclosure, the second insulating layer 220 surrounds the conductive portion 250; or the second insulating layer 220 surrounds the connecting portion 240 and the conductive portion 250. It is understood that the second insulating layer 220 not only serves to isolate the connecting portion 240 and the conductive portion 250 but also supports the capacitor structure 400, thereby ensuring that the capacitor structure 400 has a certain structure and stability.

[0077] In some optional embodiments of this disclosure, the conductive portion 250 is electrically connected to the connecting portion 240, and the material of the conductive portion 250 includes metal silicides. It is understood that metal silicides include tungsten silicide, titanium silicide, zirconium silicide, tantalum silicide, palladium silicide, cobalt silicide, or platinum silicide, etc. In some optional embodiments of this disclosure, the conductive portion 250 includes a metallic material, such as gold, silver, copper, aluminum, titanium, nickel, or tungsten, etc. The metallic material facilitates coupling with the capacitor structure 400 and provides better support for the capacitor structure 400.

[0078] Figures 3 to 13 This is a schematic diagram illustrating a semiconductor device fabrication method according to an exemplary embodiment. Please refer to [link / reference]. Figures 3 to 13 The manufacturing method includes the following steps:

[0079] S1: A semiconductor pillar 110 is formed, extending along a first direction. (See also...) Figures 3 to 5 The specific steps are as follows:

[0080] A semiconductor layer 100 is formed using monocrystalline silicon or polycrystalline silicon. After field etching of the semiconductor layer 100, a semiconductor pillar 110 protruding along the Y direction and a substrate 101 located at the bottom of the semiconductor pillar 110 are obtained. The semiconductor pillars 110 and 101 together form a first groove 111, a second groove 112, and a third groove 113. Figure 4 and Figure 5The positional structure of the corresponding semiconductor pillar 110 and the first groove 111, the second groove 112, and the third groove 113 is shown. It should be noted that... Figure 4 and Figure 5 The number of semiconductor pillars 110 and the first groove 111, the second groove 112 and the third groove 113 shown are only examples. In actual applications, the number of semiconductor pillars 110 and the first groove 111, the second groove 112 and the third groove 113 may be more or less.

[0081] S2: A gate dielectric layer 130 is formed around the side of the semiconductor pillar 110. (See also...) Figure 6 The specific steps are as follows: a gate dielectric layer 130 is formed on one or more sides of the semiconductor pillar 110. In some other embodiments, the gate dielectric layer 130 may also be arranged around the semiconductor pillar 110.

[0082] S3: Form a gate 120 surrounding the gate dielectric layer 130. (See also...) Figure 6 The specific steps are as follows: after forming a gate dielectric layer 130 on the semiconductor pillar 110, a gate 120 is formed on the surface of the gate dielectric layer 130. The gate 120 may completely cover the gate dielectric layer 130 or partially cover the gate dielectric layer 130. This forms a semiconductor structure connected to the capacitor structure 400.

[0083] S4: Form a first insulating layer 140 surrounding the semiconductor pillar 110 and the gate 120. (See also...) Figure 7 The specific steps are as follows:

[0084] After the gate 120 structure is formed, many gaps still exist between the semiconductor pillars 110. To reduce crosstalk between the semiconductor pillars 110, a first insulating layer 140 is formed between the multiple semiconductor pillars 110, so that the semiconductor pillars 110, the gate dielectric layer 130, and the gate 120 are all surrounded by the first insulating layer 140, and the gaps between the semiconductor pillars 110 are also filled. The first insulating layer 140 provides support for the semiconductor pillars 110, the gate dielectric layer 130, and the gate 120, and provides insulation between adjacent gates 120. The material of the first insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane, polysilazane, and any combination thereof. During the deposition and formation of the first insulating layer 140, air gaps 150 are formed inside the first insulating layer 140. Part of the first insulating layer 140 can be removed by etching or other methods to open the air gaps 150 and then fill them.

[0085] S5: A second insulating layer 220 is formed on the first insulating layer 140, and the second insulating layer 220 is etched to form a connection trench 300 to expose the semiconductor pillar 110. (See also...) Figure 8 and Figure 9The specific steps are as follows:

[0086] A stop layer 210 is formed on the first insulating layer 140 and the semiconductor pillar 110; a second insulating layer 220 is formed on the stop layer 210, covering the stop layer 210; a mask layer 230 is formed on the second insulating layer 220, covering the second insulating layer 220; the first insulating layer 140, the mask layer 230, and the stop layer 210 are sequentially etched along the first direction Y to remove them, forming a connection trench 300 to expose the semiconductor pillar 110. It is understood that to improve the integration density of the capacitor structure 400 and increase the storage capacity of the memory, the aspect ratio of the connection trench 300 can be increased. Since the height of the connection trench 300 is basically fixed, the aspect ratio can only be increased by reducing the diameter of the connection trench 300. To avoid the diameter of the connection trench 300 becoming too large during etching, the etching rate is controlled by the mask layer 230, the second insulating layer 220, and the stop layer 210, and the aperture of the connection trench 300 is controlled by multiple etching operations.

[0087] S6: A connecting portion 240 is formed in the connecting groove 300. The connecting portion 240 is located above and connected to the semiconductor pillar 110, wherein at least a portion of the connecting portion 240 is located above the first insulating layer 140. Please refer to [link / reference]. Figure 10 The specific steps are as follows:

[0088] Epitaxial growth is used to form a connection portion 240 within the connection trench 300 from the semiconductor pillar 110. Both the connection portion 240 and the semiconductor pillar 110 are made of silicon. Generally, the epitaxially grown connection portion 240 and the semiconductor pillar 110 are made of the same material, typically Si. However, in some other cases, the epitaxially grown connection portion 240 may be made of a different material than the semiconductor pillar 110; for example, the semiconductor pillar 110 may be SiGe or SiC, while the connection portion 240 is made of Si. The connection portion 240 obtained through epitaxial growth elongates the structure of the semiconductor pillar 110, improves the fabrication process, and allows the conductive portion 250 to be completely preserved. This improves the connection stability between the conductive portion 250 and other components, significantly increasing the yield of semiconductor device manufacturing.

[0089] S7: A conductive portion 250, which connects to the connecting portion 240, is formed in the connecting groove 300. The conductive portion 250 is located on the side of the connecting portion 240 away from the semiconductor pillar 110. Please refer to [link / reference]. Figure 11 and Figure 12 The specific steps are as follows:

[0090] A conductive portion 250 is deposited within the connection trench 300; and the mask layer 230 is removed to expose the second insulating layer 220; the conductive portion 250 covers the connection portion 240, and the conductive portion 250 is electrically connected to the connection portion 240. The connection portion 240 extends the semiconductor pillar 110, thereby reducing the impedance between the conductive portion 250 and the semiconductor pillar 110. Simultaneously, epitaxial growth allows the semiconductor pillar 110 and the connection portion 240 to form a single unit, enabling the conductive portion 250 to obtain more silicon source. See also... Figure 13 After forming the conductive portion 250, a capacitor structure 400 is formed in the connecting groove 300, and the capacitor structure 400 is coupled to the conductive portion 250. The semiconductor pillar 110, coupled to the capacitor structure 400 via the conductive portion 250, forms a dynamic random access memory (DRAM) cell, which stores corresponding data. The capacitor structure 400 includes a first electrode, a dielectric layer, and a second electrode, with the dielectric layer located between the first and second electrodes. Typically, the second electrode is a pillar-shaped structure, with the dielectric layer and the first electrode surrounding the outside of the second electrode, and the first electrode is coupled to the conductive portion 250. The materials used to form the first and second electrodes can include conductive materials such as gold, silver, copper, aluminum, titanium, nickel, tungsten, monocrystalline silicon, or polycrystalline silicon. The materials used to form the dielectric layer can include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride. The conductive part 250 is made of conductive silicide materials such as silicon titanate and aluminum silicide, or it can be conductive materials such as gold, silver, copper, aluminum, titanium, nickel, tungsten, monocrystalline silicon or polycrystalline silicon.

[0091] In some optional embodiments of this disclosure, there are multiple semiconductor pillars 110 and multiple connection slots 300, with each connection slot 300 corresponding to one semiconductor pillar 110. It is understood that after forming connection portions 240 and conductive portions 250 on the semiconductor pillars 110, a capacitor structure 400 can be formed, thereby forming a memory cell.

[0092] This application also provides a memory system, including: a semiconductor device as provided in any of the above embodiments; and a controller electrically connected to the semiconductor device for controlling the semiconductor device.

[0093] The above provides a detailed description of a semiconductor device and its fabrication method, as well as a memory system, provided by the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. 一 A semiconductor device, characterized in that, include: Semiconductor pillars extending along a first direction (Y); A gate dielectric layer surrounding the side of the semiconductor pillar; A gate, wherein the gate is connected to the gate dielectric layer; A first insulating layer surrounds the gate and the semiconductor pillar; A second insulating layer is located above the first insulating layer; A connecting portion, the connecting portion being located above and connected to the semiconductor pillar, wherein at least a portion of the connecting portion is located above the first insulating layer; A conductive portion is located on the side of the connecting portion away from the semiconductor pillar, and the conductive portion is connected to the connecting portion.

2. The semiconductor device according to claim 1, characterized in that, It also includes a capacitor structure located on the side of the conductive portion away from the connection portion and coupled to the conductive portion, and the second insulating layer surrounds the peripheral side of the capacitor structure.

3. The semiconductor device according to claim 1, characterized in that, It also includes a stop layer located between the first insulating layer and the second insulating layer, the stop layer surrounding the connection portion; or The stop layer surrounds the connection portion and the conductive portion.

4. The semiconductor device according to claim 1, characterized in that, The second insulating layer surrounds the conductive portion; or The second insulating layer surrounds the connection portion and the conductive portion.

5. The semiconductor device according to claim 1, characterized in that, The conductive part is electrically connected to the connecting part, and the material of the conductive part includes metal silicide.

6. The semiconductor device according to claim 1, characterized in that, The connecting portion includes an epitaxially grown semiconductor, and the connecting portion is made of the same material as the semiconductor pillar.

7. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor pillar is formed, the semiconductor pillar extending along a first direction; A gate dielectric layer is formed around the side of the semiconductor pillar; A gate is formed around the gate dielectric layer; A first insulating layer is formed around the semiconductor pillar and the gate; A second insulating layer is formed on the first insulating layer, and the second insulating layer is etched to form a connection trench to expose the semiconductor pillar; A connection portion is formed in the connection groove, the connection portion being located above and connected to the semiconductor pillar, wherein at least a portion of the connection portion is located above the first insulating layer; A conductive portion connected to the connecting portion is formed in the connecting groove, and the conductive portion is located on the side of the connecting portion away from the semiconductor pillar.

8. The semiconductor device fabrication method according to claim 7, characterized in that, After the conductive portion is formed, a capacitor structure is formed in the connecting groove, and the capacitor structure is coupled to the conductive portion.

9. The semiconductor device fabrication method according to claim 7, characterized in that, Before forming the connecting groove, the preparation method further includes: A stop layer is formed on the first insulating layer and the semiconductor pillar; A second insulating layer is formed on the stop layer, and the second insulating layer covers the stop layer; A mask layer is formed on the second insulating layer, the mask layer covering the second insulating layer; The stop layer, the first insulating layer and the mask layer are etched away along the first direction (Y) to form a connection trench to expose the semiconductor pillar.

10. The method for fabricating a semiconductor device according to claim 7, characterized in that, The number of semiconductor pillars is multiple, and the number of connecting slots is multiple, with each connecting slot corresponding to one of the semiconductor pillars.

11. The semiconductor device fabrication method according to claim 7, characterized in that, The method of forming a connection on the semiconductor pillar includes: The semiconductor pillar is used to form the connection portion within the connection groove using an epitaxial growth process; Both the connecting part and the semiconductor pillar are made of silicon.

12. The semiconductor device fabrication method according to claim 9, characterized in that, The method for forming a conductive portion on the connection portion includes: The conductive portion is deposited and formed within the connecting groove; and Remove the mask layer to expose the second insulating layer; The conductive part covers the connecting part, and the conductive part is electrically connected to the connecting part.

13. The semiconductor device fabrication method according to claim 7, characterized in that, The conductive part is made of silicon titanium.

14. A memory system, characterized in that, include: The semiconductor device as described in any one of claims 1-6; A controller, which is electrically connected to the semiconductor device, is used to control the semiconductor device.

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