Light emitting element and display device including the same

Abstract

A light emitting element and a display device including the same are provided. The light emitting element includes: an anode electrode; a cathode electrode facing the anode electrode; and a light emitting structure disposed between the anode electrode and the cathode electrode, and including a first light emitting unit, a charge generation layer, and a second light emitting unit. The second light emitting unit includes: a second hole transport unit disposed on the charge generation layer; a second light emitting layer disposed on the second hole transport unit; an intermediate layer disposed on the second light emitting layer; a third light emitting layer disposed on the intermediate layer; and a second electron transport unit disposed between the third light emitting layer and the cathode electrode.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0110812 filed in the Korean Intellectual Property Office on August 23, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention discloses a light emitting element and a display device including the light emitting element. Background Art

[0003] As information technology develops, the importance of display devices as a connection medium between users and corresponding information has become prominent.

[0004] The display device includes a plurality of light emitting elements. The light emitting elements can emit light, for example, when holes from an anode electrode and electrons injected from a cathode electrode in a light emitting layer recombine to generate excitons, the excitons transition (for example, relax from an excited state to a ground state) to emit light.

[0005] Implementing a light-emitting element into a display device requires (or desires) to improve light efficiency, lifespan, etc. Therefore, it is necessary or desirable to develop a material for enabling a light-emitting element to stably achieve these characteristics or expectations. Summary of the invention

[0006] One or more aspects of the embodiments of the present disclosure relate to a light emitting element having improved efficiency and desired roll-off characteristics and a display device including the light emitting element. Additional aspects will be set forth in part in the description below and in part will be apparent from the description, or can be understood by practicing the disclosed presented embodiments.

[0007] According to some disclosed embodiments, the light-emitting element may include: an anode electrode; a cathode electrode facing the anode electrode; and a light-emitting structure disposed between the anode electrode and the cathode electrode and including a first light-emitting unit, a charge generation layer, and a second light-emitting unit. The second light-emitting unit may include: a second hole transport unit disposed on the charge generation layer; a second light-emitting layer disposed on the second hole transport unit; an intermediate layer disposed on the second light-emitting layer; a third light-emitting layer disposed on the intermediate layer; and a second electron transport unit disposed between the third light-emitting layer and the cathode electrode.

[0008] The first light emitting unit may include: a first hole transport unit disposed on the anode electrode; a first electron transport unit facing the first hole transport unit and adjacent to the charge generation layer; and a first light emitting layer disposed between the first hole transport unit and the first electron transport unit.

[0009] The total thickness of the second light-emitting layer, the intermediate layer and the third light-emitting layer can be to

[0010] The thickness of the middle layer can be to

[0011] The lowest unoccupied molecular orbital (LUMO) energy level of the intermediate layer may be higher than the LUMO energy level of the third light emitting layer.

[0012] The LUMO energy level of the intermediate layer may be less than 1.5 electron volts (eV).

[0013] The intermediate layer may include a compound having at least one of a carbazole group and a triphenylamine group.

[0014] The first light emitting unit may include a first light emitting layer, the first light emitting layer may emit blue light, the second light emitting layer may emit red light, and the third light emitting layer may emit green light.

[0015] The first light emitting layer may include a blue fluorescent host and a blue fluorescent dopant.

[0016] The second light emitting layer may include a red hole transport host, a red electron transport host, and a red phosphorescent dopant, and the third light emitting layer may include a green hole transport host, a green electron transport host, and a green phosphorescent dopant.

[0017] The charge generation layer may include: an n-type (or n-type) charge generation layer adjacent to the first light emitting unit; and a p-type (or p-type) charge generation layer adjacent to the second light emitting unit.

[0018] The light emitting element may further include: a cap layer disposed on the cathode electrode.

[0019] According to some embodiments, the light-emitting element may include: an anode electrode; a cathode electrode facing the anode electrode; and a light-emitting structure disposed between the anode electrode and the cathode electrode and including a first light-emitting unit, a charge generation layer, and a second light-emitting unit. The second light-emitting unit may include: a second hole transport unit disposed on the charge generation layer; a second electron transport unit facing the second hole transport unit and adjacent to the cathode electrode; and a second light-emitting layer and a third light-emitting layer disposed between the second hole transport unit and the second electron transport unit. The second light-emitting layer may include a red bipolar host and a red phosphorescent dopant.

[0020] The second light-emitting layer may be disposed between the second hole transport unit and the third light-emitting layer, and the third light-emitting layer may be disposed between the second light-emitting layer and the second electron transport unit.

[0021] The third light emitting layer may include a green hole transport host, a green electron transport host, and a green phosphorescent dopant.

[0022] The LUMO energy level of the red bipolar host may be higher than the LUMO energy level of the green electron transport host.

[0023] The LUMO energy level of the red bipolar host can be less than 1.9 eV.

[0024] The first light emitting unit may include: a first hole transport unit disposed on the anode electrode; a first electron transport unit facing the first hole transport unit and adjacent to the charge generation layer; and a first light emitting layer disposed between the first hole transport unit and the first electron transport unit.

[0025] According to some embodiments, a display device may include a light emitting element.

[0026] The display device may include at least one selected from a flat panel display, a curved display, a flexible display, a rollable display, a foldable display, a stretchable display, a head-up display, a head-mounted display, a wearable display, a microdisplay, a three-dimensional (3D) display, a virtual reality display, an augmented reality display, a mixed reality display, and one or more combinations thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The foregoing and other features of the disclosure will become more apparent by describing the disclosed embodiments in more detail with reference to the accompanying drawings, which are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0028] Figure 1 is a diagram illustrating a display device according to some embodiments of the present disclosure.

[0029] Figure 2 is a diagram illustrating sub-pixels according to some embodiments of the present disclosure.

[0030] Figure 3 is a diagram illustrating a display panel according to some embodiments of the present disclosure.

[0031] Figure 4 It is shown Figure 3 An exploded perspective view of a portion of a display panel.

[0032] Figure 5 It is shown Figure 4 A diagram of some embodiments of any one of the pixels.

[0033] Figure 6 It is shown Figure 4 A diagram of some embodiments of any one of the pixels.

[0034] Figure 7 It is shown Figure 4A plan view of some embodiments of any one of the pixels.

[0035] Figure 8 It is along Figure 5 A cross-sectional view taken along line II'.

[0036] Fig. 9 is a diagram illustrating a light emitting element according to some embodiments of the present disclosure.

[0037] Fig.10 It is shown Fig. 9 A diagram of the light-emitting principle of a light-emitting element.

[0038] Fig.11 It shows that for each gray level Fig. 9 Diagram of the exciton distribution at the position of the light-emitting element.

[0039] Fig.12 is a diagram illustrating a light emitting element according to some embodiments of the present disclosure.

[0040] Fig.13 It is shown Fig.12 A diagram of the light-emitting principle of a light-emitting element.

[0041] Fig.14 It is shown that for each gray level Fig.12 Diagram of the exciton distribution at the position of the light-emitting element.

[0042] Fig.15 is a graph showing red light efficiency according to current density for each light emitting element according to some embodiments of the present disclosure.

[0043] Fig.16 is a graph showing current density according to driving voltage for each light emitting element according to some embodiments of the present disclosure.

[0044] Fig.17 is a diagram illustrating a light emitting element according to some embodiments of the present disclosure.

[0045] Fig.18 It is shown Fig.17 A diagram of the light-emitting principle of a light-emitting element.

[0046] Fig.19 It is shown that for each gray level Fig.17 Diagram of the exciton distribution at the position of the light-emitting element.

[0047] Fig. 20 is a graph showing red light efficiency according to current density for each light emitting element according to some embodiments of the present disclosure.

[0048] Fig.21is a graph showing current density according to driving voltage for each light emitting element according to some embodiments of the present disclosure.

[0049] Fig. 22 is a diagram illustrating a display system according to some embodiments.

[0050] Fig.23 It is shown Fig. 22 FIG. 1 is a diagram showing an application example of the display system.

[0051] Fig.24 It is shown Fig.23 FIG. 1 is a diagram of a head mounted display device worn by a user. DETAILED DESCRIPTION

[0052] Hereinafter, the preferred embodiments disclosed are described in more detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the disclosed operation are described, and the description of other parts is omitted to avoid blurring the disclosed subject matter. In certain embodiments, the disclosure may be implemented in other forms, and is not limited to the embodiments described herein. However, the embodiments described herein are provided to describe in more detail, which is sufficient to easily realize the disclosed technical spirit for those skilled in the art to disclose.

[0053] Throughout the specification, when a part is "connected" to another part, the situation includes not only the situation that the part is "directly connected" to the other part, but also the situation that the part is "indirectly connected" to the other part and another element is inserted therebetween. The same figure mark always refers to the same element, and its repeated description may not be provided. In some embodiments, in the drawings, in order to effectively describe the technical content, the thickness, proportion and size of the elements are exaggerated. As used herein, the term "and / or" includes any combination and all combinations that can be defined by the relevant construction.

[0054] The term used here is to describe a specific embodiment, and is not intended to limit disclosure. Throughout the specification, in the case of a certain part "including one or more components", unless otherwise specified, the situation refers to that the part can also include another component without excluding another component. "At least any one (kind / person) of X, Y and Z" and "at least any one (kind / person) selected from the group consisting of X, Y and Z" can be interpreted as any combination of two or more of X, Y and Z (for example, XYZ, XYY, YZ and ZZ). Here, "and / or" includes all combinations of one or more corresponding structures. Unless otherwise specified, the term in the singular includes plural forms. For example, unless the context clearly indicates otherwise, "one", "one (kind / person)" and "the (described)" are also intended to include plural forms.

[0055] As used herein, the term "use" and variations thereof may be considered synonymous with the term "utilize" and variations thereof, respectively.

[0056] As used herein, expressions such as “at least one of,” “one of,” “selected from,” and “selected from,” when preceding (following) a list of elements, modify the entire list of elements and do not modify the individual elements in the list. For example, the expressions “at least one of a to c” and “at least one of a, b, and c” may refer to only a, only b, only c, both a and b (e.g., simultaneously), both a and c (e.g., simultaneously), both b and c (e.g., simultaneously), all of a, b, and c, or variations thereof.

[0057] The term "and / or" includes all combinations of one or more of the associated listed elements.

[0058] In the present application, when a layer, film, region or plate is referred to as being "on" another layer, film, region or plate or "on the upper part of" another layer, film, region or plate, the layer, film, region or plate may not only be "directly on" the other layer, film, region or plate, but also there may be intervening layers, films, regions or plates. Similarly, when a layer, film, region or plate is referred to as being "on the lower part of" another layer, film, region or plate, the layer, film, region or plate may not only be directly below the other layer, film, region or plate, but also there may be intervening layers, films, regions or plates. In some embodiments, it will be understood that when a component is referred to as being "on" another component, the component may be disposed above the other component, or may also be disposed below the other component. It will be understood that when the terms "include" and its variations, "comprises" and its variations, "has" and its variations, when used in this specification, indicate the presence of the described features, wholes, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0059] As used herein, the term "may" will be understood to refer to "one or more embodiments of the present disclosure," some of which include the described elements, and some of which exclude the elements and / or include alternative elements. Similarly, alternative language such as "or" refers to "one or more embodiments of the present disclosure," each of which includes the corresponding listed items.

[0060] Unless otherwise defined, all terms used herein (including chemical terms, technical terms and scientific terms) have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0061] As used herein, the phrase "consisting essentially of" means that any additional components will not substantially affect the chemical, physical, optical, or electrical properties of the semiconductor film.

[0062] As used herein, the phrase "on a plane" or "plan view" refers to viewing a target portion from the top, and the phrase "in section" refers to viewing a section formed by vertically cutting the target portion from the side.

[0063] In the present disclosure, "does not include one or any 'component'", "excludes one or any 'component'", "does not contain 'component'" and the like mean that the "component" is not added, selected or used as a component in the composition, but due to other impurities and / or external factors, the "component" may still be included in an appropriate amount less than that.

[0064] Here, terms such as first and second can be used to describe one or more suitable components, but these components are not limited to these terms. These terms are used to distinguish one component from another component. Therefore, without departing from the scope disclosed herein, a first component can refer to a second component within the scope.

[0065] Spatially relative terms such as "below" and / or "on" may be used for descriptive purposes to describe the relationship between one element or feature and another element or feature as shown in the accompanying drawings. In addition to the directions depicted in the accompanying drawings, spatially relative terms are intended to include other directions of the device in use, operation and / or manufacture. For example, if the device shown in the accompanying drawings is inverted (e.g., when the device shown in the accompanying drawings is inverted), the elements depicted as being "below" other elements or features will be located in the direction "on" other elements or features. Therefore, in some embodiments, the term "below" may (e.g., simultaneously) include both directions below and above. In some embodiments, the device may face other directions (e.g., rotated 90 degrees or in other directions), so the spatially relative terms used herein are interpreted accordingly.

[0066] Various embodiments are described with reference to the accompanying drawings that schematically illustrate idealized embodiments. Therefore, it will be expected that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, and should be construed to include changes in shape that occur, for example, as a result of manufacturing. As described herein, the shapes shown in the accompanying drawings may not illustrate the actual shape of an area of ​​the device, and the present embodiments are not limited thereto.

[0067] Hereinafter, disclosed embodiments will be described in more detail with reference to the accompanying drawings.

[0068] Display device

[0069] Figure 1 is a diagram illustrating a display device according to some embodiments.

[0070] Reference Figure 1 , the display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0071] The display panel 110 includes sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The sub-pixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0072] Each of the sub-pixels SP may include at least one light emitting element configured to generate light. Therefore, each of the sub-pixels SP may generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels among the sub-pixels SP may constitute one pixel PXL. For example, Figure 1 As shown in FIG. , three sub-pixels can constitute one pixel PXL.

[0073] The gate driver 120 is connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to the gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame and / or a horizontal synchronization signal for outputting a gate signal in synchronization with the timing of applying a data signal, etc.

[0074] In some embodiments, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction may also be provided. In this case, the gate driver 120 may include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm, and the emission control driver may operate under the control of the controller 150.

[0075] The gate driver 120 may be disposed on one side of the display panel 110. However, the embodiment is not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically divided drivers, and such a driver may be disposed on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side. As described herein, according to the embodiment, the gate driver 120 may be disposed around the display panel 110 in one or more suitable shapes.

[0076] The data driver 130 is connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 receives the image data DATA and the data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock and / or a source output enable signal, etc.

[0077] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using a voltage from the voltage generator 140. If a gate signal is applied to each of the first to m-th gate lines GL1 to GLm (for example, when a gate signal is applied to each of the first to m-th gate lines GL1 to GLm), a data signal corresponding to the image data DATA may be applied to the data lines DL1 to DLm. Therefore, the corresponding sub-pixel SP may emit light corresponding to the data signal. Thus, an image is displayed on the display panel 110.

[0078] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0079] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may be configured to generate a plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and correcting the adjusted voltage.

[0080] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS may be provided to the sub-pixel SP. The first power voltage VDD may have a relatively high voltage level, and the second power voltage VSS may have a voltage level lower than that of the first power voltage VDD. In other embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device 100.

[0081] In some embodiments, the voltage generator 140 may generate one or more suitable voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a set or predetermined reference voltage may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate such a reference voltage.

[0082] The controller 150 controls the overall operation of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling display of an image from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0083] Controller 150 may convert input image data IMG so that it is suitable for display device 100 or display panel 110 and output image data DATA. In an embodiment, controller 150 may output image data DATA by aligning input image data IMG so that it is suitable for sub-pixels SP of a row unit.

[0084] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140 and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140 and the controller 150 may be functionally separated components within one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140 and the controller 150 may be provided as a component separated from the driver integrated circuit DIC.

[0085] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense a temperature near or around the temperature sensor 160 and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0086] The controller 150 may control one or more suitable operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first power voltage VDD and the second power voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0087] In some embodiments, the display device 100 may include any of a flat panel display, a curved display, a flexible display, a rollable display, a foldable display, a stretchable display, a head-up display, a head-mounted display, a wearable display, a microdisplay, a 3D display, a virtual reality display, an augmented reality display, and a mixed reality display.

[0088] Figure 2 is a diagram illustrating sub-pixels according to some embodiments. Figure 2 In the diagram, the sub-pixel SPij arranged in the i-th (i is an integer greater than or equal to 1 and less than or equal to m)-th row and the j-th (j is an integer greater than or equal to 1 and less than or equal to n)-th column is shown as Figure 1 An example among the sub-pixels SP.

[0089] Reference Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0090] The light emitting element LD is connected between the first power voltage node VDDN and the second power voltage node VSSN. At this time, the first power voltage node VDDN is the transmission node. Figure 1 The first power voltage node VDD is the transmission node, and the second power voltage node VSSN is the transmission node Figure 1 A node of a second power voltage VSS is connected to the node.

[0091] The anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light emitting element LD may be connected to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0092] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm, Figure 1 The i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm and Figure 1 The sub-pixel circuit SPC is configured to control the light emitting element LD according to signals received through the signal lines.

[0093] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. Figure 2 As shown in , the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described herein, if the i-th gate line GLi includes two or more sub-gate lines (for example, when the i-th gate line GLi includes two or more sub-gate lines), the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0094] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi may include one or more sub-emission control lines. If the i-th emission control line ELi includes two or more sub-emission control lines (for example, when the i-th emission control line ELi includes two or more sub-emission control lines), the sub-pixel circuit SPC may operate in response to an emission control signal received through the corresponding sub-emission control line.

[0095] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC may adjust a current flowing from the first power voltage node VDDN through the light emitting element LD to the second power voltage node VSSN according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Therefore, the light emitting element LD may generate light having a brightness corresponding to the data signal.

[0096] Figure 3 is a diagram illustrating a display panel according to some embodiments.

[0097] Reference Figure 3, in some embodiments, Figure 1 The display panel 110 may be Figure 3 The display panel DP is marked as DP in FIG. 1 and may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is disposed around the display area DA.

[0098] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0099] If the display panel DP is used as a display screen of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and / or an augmented reality (AR) device, etc. (for example, when the display panel DP is used as a display screen of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and / or an augmented reality (AR) device, etc.), the display panel DP can be positioned very close to the user's eyes. In this case, the sub-pixels SP have a relatively high degree of integration. In order to increase the degree of integration of the sub-pixels SP, the substrate SUB can be (for example, set to) a silicon substrate. The sub-pixels SP and / or the display panel DP can be formed on a substrate SUB which is a silicon substrate. A display device 100 (refer to Figure 1 ) can be called an OLED on silicon (OLEDoS) display device.

[0100] The sub-pixels SP are disposed in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix shape along a first direction DR1 and a second direction DR2 crossing the first direction DR1. However, the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0101] Two or more sub-pixels among the plurality of sub-pixels SP may constitute (eg, be constituted as) one pixel PXL.

[0102] Components for controlling the sub-pixel SP may be disposed in the non-display area NDA on the substrate SUB. For example, a line (such as a Figure 1 The first gate lines GL1 to the m-th gate lines GLm and the first data lines DL1 to the n-th data lines DLn) may be disposed in the non-display area NDA.

[0103] Figure 1At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 of the display panel DP may be integrated in the non-display area NDA of the display panel DP. In an embodiment, Figure 1 The gate driver 120 may be mounted on the display panel DP and may be disposed in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separated from the display panel DP. In an embodiment, the temperature sensor 160 may be disposed in the non-display area NDA to sense the temperature of the display panel DP.

[0104] The pad PD is disposed in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0105] The pad PD may connect the display panel DP to the display device 100 (refer to Figure 1 ) other components. In an embodiment, the pad PD can be Figure 1 The driver integrated circuit DIC provides voltages and signals required for the operation of components included in the display panel DP. For example, the first data line DL1 to the nth data line DLn may be connected to the driver integrated circuit DIC through the pad PD. For example, the first power voltage VDD and the second power voltage VSS may be received from the driver integrated circuit DIC through the pad PD. For example, if the gate driver 120 is mounted on the display panel DP (for example, when the gate driver 120 is mounted on the display panel DP), the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0106] In an embodiment, the circuit board may be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. At this time, the circuit board may be a flexible circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pad PD.

[0107] In an embodiment, the display area DA may have one or more suitable shapes. The display area DA may have a closed loop shape including straight edges and / or curved edges. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, and / or an ellipse.

[0108] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In an embodiment, the display panel DP may be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB may include a material having flexibility.

[0109] Figure 4 It is shown Figure 3 An exploded perspective view of a portion of a display panel. Figure 4 In the embodiment, for the sake of clarity and simplicity, the display panel DP is schematically shown. Figure 3 Portions of the display panel DP corresponding to the two pixels PXL1 and PXL2 among the pixels PXL of the display panel DP may be similarly configured.

[0110] Reference Figure 3 and Figure 4 , each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiment is not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0111] exist Figure 4 In the embodiment, if viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2 (for example, when viewed from the third direction DR3 intersecting the first direction DR1 and the second direction DR2), the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 have a quadrilateral shape and have sizes equal to each other. However, the embodiment is not limited thereto. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be modified to have one or more suitable shapes.

[0112] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0113] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer and / or a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0114] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least a portion of a circuit element and / or line, etc. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0115] The circuit element may include a sub-pixel circuit SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (refer to Figure 2 ). The sub-pixel circuit SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, if the substrate SUB is set to a silicon substrate (for example, when the substrate SUB is set to a silicon substrate), the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, if the substrate SUB is set to a glass substrate or a PI substrate (for example, when the substrate SUB is set to a glass substrate or a PI substrate), the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart and / or separated from each other. For example, each capacitor may include electrodes overlapping each other on a plane defined by a first direction DR1 and a second direction DR2 (for example, in a plan view), for example, each capacitor may include an electrode of a first electrode included on a second electrode. For example, each capacitor may include electrodes spaced apart and / or separated from each other in a third direction DR3, and an insulating layer is placed therebetween (for example, between the first electrode and the second electrode of the electrode of the capacitor).

[0116] The lines of the pixel circuit layer PCL may include signal lines connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, such as gate lines, emission control lines, and / or data lines. The lines may further include signals connected to Figure 2 In some embodiments, the line may also include a line connected to the first power voltage node VDDN. Figure 2 A line to the second power voltage node VSSN.

[0117] The light emitting element layer LDL may include an anode electrode (or referred to as an anode) AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode (or referred to as a cathode) CE.

[0118] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may contact a circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0119] The pixel defining layer PDL is disposed on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a portion of each of the anode electrodes AE. The opening OP of the pixel defining layer PDL may be understood as emission regions corresponding to the first to third sub-pixels SP1 to SP3, respectively.

[0120] In an embodiment, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide SiO x (For example, x may be 2 or less) and silicon nitride SiN x (For example, x may be 1 or less.) In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0121] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to emit light, an electron transport layer configured to transport electrons, and / or a hole transport layer configured to transport holes.

[0122] In an embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be entirely disposed on the pixel defining layer PDL. In other words, the light emitting structure EMS may extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least a portion of the layer in the light emitting structure EMS may be disconnected or bent at the boundary between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiment is not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of them may be disposed in the opening OP of the pixel defining layer PDL.

[0123] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first to third subpixels SP1 to SP3. As described herein, the cathode electrode CE may be disposed as a common electrode for the first to third subpixels SP1 to SP3.

[0124] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode electrode CE may include at least one of one or more suitable transparent conductive materials, the transparent conductive material including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and a mixture thereof. However, the material of the cathode electrode CE is not limited thereto.

[0125] It can be understood that any one of the anode electrodes AE, the portion of the light emitting structure EMS overlapping with the anode electrode AE, and the portion of the cathode electrode CE overlapping with the anode electrode AE ​​constitute a light emitting element LD (refer to Figure 2 ). In other words, each of the light emitting elements of the first to third sub-pixels SP1 to SP3 may include an anode electrode, a portion of the light emitting structure EMS overlapping the anode electrode, and a portion of the cathode electrode CE overlapping the anode electrode. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE may be transferred to the light emitting layer of the light emitting structure EMS to form excitons, and if the excitons transition from an excited state to a ground state (for example, when the excitons transition from an excited state to a ground state), light may be generated. The brightness of the light may be determined according to the amount of current flowing through the light emitting layer. According to the configuration of the light emitting layer, the wavelength range of the generated light may be determined.

[0126] The encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent or reduce oxygen and / or moisture from entering the light emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layer may include silicon nitride, silicon oxide, and / or silicon oxynitride (SiO x N y ) etc. For example, the organic layer may include an organic insulating material such as acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0127] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include aluminum oxide (AlO x , for example, x may be 1.5 or less). The thin film including aluminum oxide may be located on an upper surface of the encapsulation layer TFE opposite to the optical function layer OFL and / or a lower surface of the encapsulation layer TFE opposite to the light emitting element layer LDL.

[0128] The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto. The encapsulation layer TFE may also include a thin film formed of at least one of one or more suitable materials suitable for improving encapsulation efficiency.

[0129] The optical function layer OFL is disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0130] The color filter layer CFL is disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to filter the light emitted from the light emitting structure EMS, and selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively, and each of the color filters CF may allow light of a wavelength range corresponding to the corresponding sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 may allow red light to pass through, the color filter corresponding to the second sub-pixel SP2 may allow green light to pass through, and the color filter corresponding to the third sub-pixel SP3 may allow blue light to pass through. Depending on the light emitted from the light emitting structure EMS of each sub-pixel, at least a portion of the color filter CF may not be provided.

[0131] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may improve light output efficiency by outputting light emitted from the light emitting structure EMS to a desired path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylate material. However, the material of the lens LS is not limited thereto.

[0132] In an embodiment, at least a portion of the color filter CF of the color filter layer CFL and at least a portion of the lenses LS of the lens array LA may be shifted in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2 compared to the opening OP of the pixel defining layer PDL. Figure 3), if viewed in the third direction DR3 (for example, when viewed in the third direction DR3), the center of the color filter CF and the center of the lens LS may be aligned with or overlapped with the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the central area of ​​the display area DA, the opening OP of the pixel defining layer PDL may be completely overlapped with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In an area adjacent to the non-display area NDA in the display area DA, if viewed in the third direction DR3 (for example, when viewed in the third direction DR3), the center of the color filter CF and the center of the lens LS may be offset from the center of the opening OP of the corresponding pixel defining layer PDL in the plane direction. For example, in an area adjacent to the non-display area NDA in the display area DA, the opening OP of the pixel defining layer PDL may be partially overlapped with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, light emitted from the light emitting structure EMS may be effectively output in the normal direction of the display surface. In an area adjacent to the non-display area NDA in the display area DA, light emitted from the light emitting structure EMS may be effectively output in a direction inclined at a set or predetermined angle with respect to a normal direction of the display surface.

[0133] The outer coating OC may be disposed on the lens array LA. The outer coating OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS and / or the pixel circuit layer PCL. The outer coating OC may include one or more suitable materials suitable for protecting the layers therebelow from foreign matter (such as dust or moisture). For example, the outer coating OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC may include an epoxy resin, but the embodiment is not limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0134] The cover window CW may be disposed on the outer coating layer OC. The cover window CW is configured to protect the layers thereunder. The cover window CW may have a refractive index higher than that of the outer coating layer OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect components disposed thereunder. In other embodiments, the cover window CW may not be provided.

[0135] Figure 5 It is shown Figure 4 Figure 1 shows some embodiments of any of the pixels of FIG. Figure 5 In order to make the description clear and concise, the schematic diagram is shown. Figure 4 The remaining pixels may be configured similarly to the first pixel PXL1.

[0136] Reference Figure 4 and Figure 5 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0137] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0138] The first emission area EMA1 may be formed from the light emitting structure EMS (refer to Figure 4 ) may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. Figure 4 As described, each emission region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0139] Figure 6 It is shown Figure 4 A diagram of some embodiments of any one of the pixels.

[0140] Reference Figure 6 , the first pixel PXL1 ′ may include first to third sub-pixels SP1 ′ to SP3 ′.

[0141] The first subpixel SP1' may include a first emission area EMA1' and a non-emission area NEA' around the first emission area EMA1'. The second subpixel SP2' may include a second emission area EMA2' and a non-emission area NEA' around the second emission area EMA2'. The third subpixel SP3' may include a third emission area EMA3' and a non-emission area NEA' around the third emission area EMA3'.

[0142] The first subpixel SP1' and the second subpixel SP2' may be arranged in the second direction DR2. The third subpixel SP3' may be arranged in the first direction DR1 with respect to each of the first subpixel SP1' and the second subpixel SP2'.

[0143] The second sub-pixel SP2' may have an area larger than that of the first sub-pixel SP1', and the third sub-pixel SP3' may have an area larger than that of the second sub-pixel SP2'. Therefore, the second emission area EMA2' may have an area larger than that of the first emission area EMA1', and the third emission area EMA3' may have an area larger than that of the second emission area EMA2'. However, the embodiment is not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same area, and the third sub-pixel SP3' may have an area larger than that of each of the first sub-pixel SP1' and the second sub-pixel SP2'. As described herein, the areas of the first to third sub-pixels SP1' to SP3' may be modified differently according to the embodiment.

[0144] Figure 7 It is shown Figure 4 A plan view of some embodiments of any one of the pixels.

[0145] Reference Figure 7 , the first pixel PXL1 ″ may include first to third sub-pixels SP1 ″ to SP3 ″.

[0146] The first subpixel SP1" may include a first emission area EMA1" and a non-emission area NEA" around the first emission area EMA1". The second subpixel SP2" may include a second emission area EMA2" and a non-emission area NEA" around the second emission area EMA2". The third subpixel SP3" may include a third emission area EMA3" and a non-emission area NEA" around the third emission area EMA3".

[0147] If viewed in the third direction DR3 (eg, in a plan view) (eg, when viewed in the third direction DR3 (eg, in a plan view)), the first to third sub-pixels SP1″ to SP3″ may have a polygonal shape. Figure 7 As shown in FIG. 1 , the shapes of the first to third sub-pixels SP1 ″ to SP3 ″ may be hexagonal shapes.

[0148] If viewed in the third direction DR3 (eg, when viewed in the third direction DR3), the first to third emission areas EMA1" to EMA3" may have a circular shape. However, the embodiment is not limited thereto. For example, each of the first to third emission areas EMA1" to EMA3" may have a polygonal shape.

[0149] The first subpixel SP1” and the third subpixel SP3” may be arranged in the first direction DR1. The second subpixel SP2” may be disposed relative to the first subpixel SP1” in a direction inclined at an acute angle in the opposite direction of the second direction DR2 (or in a diagonal direction between the opposite direction of the second direction DR2 and the first direction DR1).

[0150] Figures 5 to 7 The arrangement of the sub-pixels shown in is only an example, and the embodiment is not limited thereto. For example, each pixel may include two or more sub-pixels, the sub-pixels may be arranged in one or more suitable methods, each of the sub-pixels may have one or more suitable shapes, and each of the emission regions of each of the sub-pixels may also have one or more suitable shapes.

[0151] Figure 8 It is along Figure 5 A cross-sectional view taken along line II'.

[0152] Reference Figure 8 A substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB are provided.

[0153] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium and / or silicon-germanium.

[0154] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC (refer to Figure 2 ), the transistor T_SP2 of the second sub-pixel SP2 may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 8 , for clarity and concise description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0155] The transistor T_SP1 of the first subpixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0156] The source region SRA and the drain region DRA may be disposed in the substrate SUB. A well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed to be spaced and / or separated from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0157] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be spaced and / or separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0158] The plurality of layers included in the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers, and such a conductive pattern may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection portion DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection portion SRC passing through one or more insulating layers.

[0159] Since the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to different circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1 may be set to any one of the transistors of the first subpixel SP1.

[0160] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may be configured similarly to the transistor T_SP1 of the first subpixel SP1.

[0161] As described herein, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3 .

[0162] The via layer VIAL is disposed on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and may have a substantially flat surface. The via layer VIAL is configured to flatten the step difference on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x , for example, x may be 2 or less and 0 or more), silicon nitride (SiN x , for example, x may be at least one of 1 or less and 0 or more) and silicon carbonitride (SiCN), but the embodiment is not limited thereto.

[0163] The light emitting element layer LDL is disposed on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3 , a planarization layer PLNL, first to third anode electrodes AE1 to AE3 , a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0164] On the via layer VIAL, first to third reflective electrodes RE1 to RE3 are respectively disposed in the first to third subpixels SP1 to SP3. Each of the first to third reflective electrodes RE1 to RE3 may contact a circuit element disposed in the pixel circuit layer PCL through a via hole passing through the via layer VIAL.

[0165] The first to third reflective electrodes RE1 to RE3 may be used as total reflectors that reflect light emitted from the light emitting structure EMS toward the display surface (or cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected therefrom, but the embodiment is not limited thereto.

[0166] In an embodiment, a connection electrode may be disposed under each of the first to third reflective electrodes RE1 to RE3. The connection electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connection electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN) and / or tantalum nitride (TaN), etc., but the embodiment is not limited thereto. In an embodiment, the corresponding reflective electrode may be located between multiple layers of the connection electrode.

[0167] The buffer pattern BFP may be disposed under at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but the embodiment is not limited thereto. By providing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0168] The first to third reflective electrodes RE1 to RE3 may be used as full reflectors, and the cathode electrode CE may be used as a half reflector. The light emitted from the light emitting layer of the light emitting structure EMS may be at least partially amplified by reciprocating between the corresponding reflective electrodes and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. As described herein, the distance between each reflective electrode and the cathode electrode CE may be understood as the resonance distance of the light emitted from the light emitting layer of the light emitting structure EMS.

[0169] Due to the buffer pattern BFP, the first subpixel SP1 can have a resonance distance shorter than the resonance distances of other subpixels. As described herein, the adjusted resonance distance can allow light of a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first subpixel SP1 can effectively and efficiently output light of the corresponding wavelength range.

[0170] exist Figure 8 In the embodiment, the buffer pattern BFP is set for the first sub-pixel SP1, and the buffer pattern BFP is not set for the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiment is not limited thereto. The buffer pattern BFP may also be set for at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively, and as required, the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0171] The planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3 to planarize the step differences between the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may substantially cover the first to third reflective electrodes RE1 to RE3 and the via layer VIAL and may have a flat surface. In an embodiment, the planarization layer PLNL may not be disposed.

[0172] On the planarization layer PLNL, first to third anode electrodes AE1 to AE3 are disposed to overlap the first to third reflective electrodes RE1 to RE3, respectively. If viewed in the third direction DR3 (eg, when viewed in the third direction DR3), the first to third anode electrodes AE1 to AE3 may have the same Figure 5The first to third emission areas EMA1 to EMA3 are similar in shape. The first to third anode electrodes AE1 to AE3 are respectively connected to the first to third reflective electrodes RE1 to RE3. The first anode electrode AE1 may be connected to the first reflective electrode RE1 through a first via hole VIA1 passing through the planarization layer PLNL. The second anode electrode AE2 may be connected to the second reflective electrode RE2 through a second via hole VIA2 passing through the planarization layer PLNL. The third anode electrode AE3 may be connected to the third reflective electrode RE3 through a third via hole VIA3 passing through the planarization layer PLNL.

[0173] In an embodiment, the first to third anode electrodes AE1 to AE3 may include at least one of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first to third anode electrodes AE1 to AE3 are not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0174] In an embodiment, an insulating layer for adjusting the height of one or more anode electrodes among the first anode electrode AE1 to the third anode electrode AE3 may also be provided. The insulating layer may be provided between one or more of the first anode electrode AE1 to the third anode electrode AE3 and the corresponding reflective electrode. In this case, the planarization layer PLNL and / or the buffer pattern BFP may not be provided. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively, the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE.

[0175] The pixel defining layer PDL is disposed on a portion of the first to third anode electrodes AE1 to AE3 and the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing a portion of each of the first to third anode electrodes AE1 to AE3. The opening OP of the pixel defining layer PDL may define an emission region of each of the first to third sub-pixels SP1 to SP3. As described herein, the pixel defining layer PDL may be disposed on Figure 5 The non-emitting area NEA can be defined as Figure 5 The first emission area EMA1 to the third emission area EMA3.

[0176] In an embodiment, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiOx , for example, x may be 2 or less and 0 or more) and silicon nitride (SiN x , for example, x may be at least one of 1 or less and 0 or greater). For example, the pixel defining layer PDL may include a first inorganic insulating layer to a third inorganic insulating layer stacked sequentially, and the first inorganic insulating layer to the third inorganic insulating layer may include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the embodiment is not limited thereto. The first inorganic insulating layer to the third inorganic insulating layer may have a step-shaped cross-section in a region adjacent to the opening OP.

[0177] The spacer SPR may be disposed in the boundary area BDA between adjacent sub-pixels. In other words, the spacer SPR may be disposed in the boundary area BDA between adjacent sub-pixels. Figure 3 In each of the boundary regions between the sub-pixels SP.

[0178] The spacer SPR may cause discontinuity in the light emitting structure EMS at the boundary area BDA. For example, the light emitting structure EMS may be disconnected or bent at the boundary area BDA by the spacer SPR.

[0179] The spacer SPR may be disposed in or on the pixel defining layer PDL. The pixel defining layer PDL may include one or more trenches TRCH1 and TRCH2 as the spacer SPR in the boundary area BDA. Figure 8 As shown in , one or more trenches TRCH1 and TRCH2 may pass through the pixel defining layer PDL and may partially pass through the planarization layer PLNL. In other embodiments, one or more trenches TRCH1 and TRCH2 may pass through the pixel defining layer PDL and the planarization layer PLNL, and may partially pass through the via layer VIAL. In other embodiments, one or more trenches TRCH1 and TRCH2 may at least partially pass through the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL may be disposed in one or more trenches TRCH1 and TRCH2.

[0180] exist Figure 8 In the embodiment, two grooves TRCH1 and TRCH2 are provided for the boundary area BDA. However, the embodiment is not limited thereto. For example, the pixel defining layer PDL may include one groove in the boundary area BDA. In some embodiments, the pixel defining layer PDL may include three or more grooves in the boundary area BDA.

[0181] Due to the first trench TRCH1 and the second trench TRCH2, in the boundary area BDA, a discontinuous portion such as a first void VD1 and a second void VD2 may be formed in the light emitting structure EMS. A portion of a plurality of layers stacked in the light emitting structure EMS may be disconnected or bent by the first void VD1 and the second void VD2. For example, at least one charge generating layer included in the light emitting structure EMS may be disconnected in the first void VD1 and the second void VD2. As described herein, due to the first trench TRCH1 and the second trench TRCH2, a portion of the light emitting structure EMS included in the first to third sub-pixels SP1 to SP3 may be at least partially separated.

[0182] exist Figure 8 In the boundary area BDA, the first void VD1 and the second void VD2 are formed in the light emitting structure EMS, but this is an example and the embodiment is not limited thereto. For example, in the boundary area BDA, a concave valley may be formed in the light emitting structure EMS. According to the shapes of the first trench TRCH1 and the second trench TRCH2, the discontinuous portion formed in the light emitting structure EMS may be changed differently.

[0183] In embodiments, the light emitting structure EMS may be formed by vacuum deposition and / or inkjet printing, etc. In this case, the same material as the light emitting structure EMS may be positioned on the bottom surfaces of the first and second trenches TRCH1 and TRCH2 adjacent to the via layer VIAL.

[0184] The spacer SPR may be modified and arranged differently so that the light emitting structure EMS may have a discontinuous portion in the boundary area BDA. In an embodiment, an inorganic insulating pattern additionally stacked on the pixel defining layer PDL may be arranged in the boundary area BDA without the first trench TRCH1 and the second trench TRCH2 being arranged in the boundary area BDA. Among the additionally stacked inorganic insulating patterns, the width of the topmost inorganic insulating pattern may be greater than the width of the inorganic insulating pattern arranged directly below it. For example, in the boundary area BDA, the first to third inorganic insulating patterns may be stacked sequentially from the pixel defining layer PDL, and the topmost third inorganic insulating pattern may have a width greater than the width of the second inorganic insulating pattern. For example, the pixel defining layer PDL may have a "T"-shaped or "I"-shaped cross-section in the boundary area BDA. According to the shape of the pixel defining layer PDL, the multiple layers included in the light emitting structure EMS may be at least partially disconnected or bent in the boundary area BDA.

[0185] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be disposed entirely across the first to third sub-pixels SP1 to SP3. As described herein, the light emitting structure EMS may be at least partially disconnected or bent in the boundary area BDA by the spacer SPR. Therefore, during operation of the display panel DP, the current flowing from each of the first to third sub-pixels SP1 to SP3 through the layer included in the light emitting layer to the adjacent sub-pixel may be reduced. Therefore, the first to third light emitting elements LDa to LDc may operate with relatively high reliability.

[0186] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may be commonly disposed for the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0187] The first anode electrode AE1, a portion of the light emitting structure EMS overlapping with the first anode electrode AE1, and a portion of the cathode electrode CE overlapping with the first anode electrode AE1 may constitute a first light emitting element LDa. The second anode electrode AE2, a portion of the light emitting structure EMS overlapping with the second anode electrode AE2, and a portion of the cathode electrode CE overlapping with the second anode electrode AE2 may constitute a second light emitting element LDb. The third anode electrode AE3, a portion of the light emitting structure EMS overlapping with the third anode electrode AE3, and a portion of the cathode electrode CE overlapping with the third anode electrode AE3 may constitute a third light emitting element LDc.

[0188] The encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE can prevent or reduce the penetration of oxygen and / or moisture, etc. into the light emitting element layer LDL.

[0189] The optical function layer OFL is disposed on the encapsulation layer TFE. In an embodiment, the optical function layer OFL may be attached to the encapsulation layer TFE through an adhesive layer APL. For example, the optical function layer OFL may be manufactured separately and attached to the encapsulation layer TFE through an adhesive layer APL. The adhesive layer APL may also perform the function of protecting the lower layer including the encapsulation layer TFE.

[0190] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third subpixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may allow light of different wavelength ranges to pass through. For example, the first to third color filters CF1 to CF3 may allow red, green, and blue light to pass through, respectively.

[0191] In an embodiment, the first to third color filters CF1 to CF3 may be partially overlapped in the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced and / or separated from each other, and a black matrix may be disposed between the first to third color filters CF1 to CF3.

[0192] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third lenses LS1 to LS3 may improve light output efficiency by outputting light emitted from the first to third light emitting elements LDa to LDc to a desired path.

[0193] Fig. 9 is a diagram illustrating a light emitting element according to some embodiments.

[0194] Reference Fig. 9 , the light emitting element LD may have a series structure in which the first light emitting unit EU1 and the second light emitting unit EU2 are stacked. In this case, Figure 8 Each of the first to third light emitting elements LDa to LDc in the embodiment may be configured as a light emitting element LD. The light emitting element LD may include an anode electrode AE, a light emitting structure EMS, and a cathode electrode CE. According to some embodiments, the light emitting element LD may further include a cap layer CPL.

[0195] The light emitting structure EMS may be disposed between the anode electrode AE ​​and the cathode electrode CE. The light emitting structure EMS may include a first light emitting unit EU1, a charge generation layer CGL, and a second light emitting unit EU2. Each of the first light emitting unit EU1 and the second light emitting unit EU2 may emit light according to an applied current. The charge generation layer CGL may provide electrons or holes.

[0196] In an embodiment, the first light emitting unit EU1 and the second light emitting unit EU2 may emit light of different colors. Therefore, the light emitted from each of the first light emitting unit EU1 and the second light emitting unit EU2 may be mixed and regarded as white light. For example, the first light emitting unit EU1 may emit blue light and the second light emitting unit EU2 may emit yellow light.

[0197] The first light emitting unit EU1 may be disposed between the anode electrode AE ​​and the charge generation layer CGL. The first light emitting unit EU1 may include a first hole transport unit HTU1, a first light emitting layer EML1, and a first electron transport unit ETU1. The first light emitting unit EU1 may emit light based on holes from the anode electrode AE ​​and electrons from the charge generation layer CGL.

[0198] The first hole transport unit HTU1 may be disposed between the anode electrode AE ​​and the first light emitting layer EML1. The first hole transport unit HTU1 may include at least one of a hole injection layer and a hole transport layer, and if necessary (e.g., when needed), may further include a hole buffer layer and / or an electron blocking layer, etc. The first hole transport unit HTU1 may transport holes from the anode electrode AE ​​to the first light emitting layer EML1.

[0199] The first light emitting layer EML1 may be disposed between the first hole transport unit HTU1 and the first electron transport unit ETU1. In an embodiment, the first light emitting layer EML1 may emit blue light. In an embodiment, the first light emitting layer EML1 may include a blue fluorescent host and a blue fluorescent dopant, but is not limited thereto. For example, the first light emitting layer EML1 may include a blue phosphorescent host and a blue phosphorescent dopant.

[0200] The first electron transport unit ETU1 may be disposed between the charge generation layer CGL and the first light emitting layer EML1. The first electron transport unit ETU1 may include at least one of an electron injection layer and an electron transport layer, and if necessary (e.g., when needed), may further include an electron buffer layer and / or a hole blocking layer, etc. The first electron transport unit ETU1 may transport electrons from the charge generation layer CGL to the first light emitting layer EML1.

[0201] The charge generation layer CGL may be disposed between the first light emitting unit EU1 and the second light emitting unit EU2. The charge generation layer CGL may include an organic layer. In an embodiment, the charge generation layer CGL may include a p-type (or p-type) charge (e.g., p-charge) generation layer p-CGL and an n-type (or n-type) charge (e.g., n-charge) generation layer n-CGL. The p-type (or p-type) charge generation layer p-CGL may be adjacent to the second light emitting unit EU2 (or the second hole transport unit HTU2). The p-type (or p-type) charge generation layer p-CGL may provide holes to the second light emitting unit EU2. For example, the p-type (or p-type) charge generation layer p-CGL may include a p-type (or p-type) dopant (such as HAT-CN, TCNQ, or NDP-9), but is not limited thereto. The n-type (or n-type) charge generation layer n-CGL may be adjacent to the first light emitting unit EU1 (or the first electron transport unit ETU1). The n-type (or n-type) charge generation layer n-CGL may provide electrons to the first light emitting unit EU1. For example, the n-type (or n-type) charge generation layer n-CGL may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof, but is not limited thereto.

[0202] The second light emitting unit EU2 may be disposed between the cathode electrode CE and the charge generation layer CGL. The second light emitting unit EU2 may include a second hole transport unit HTU2, a second light emitting layer EML2, a third light emitting layer EML3, and a second electron transport unit ETU2. The second light emitting unit EU2 may emit light based on electrons from the cathode electrode CE and holes from the charge generation layer CGL.

[0203] The second hole transport unit HTU2 may be disposed between the charge generation layer CGL (or the p-type (or p-like) charge generation layer p-CGL) and the second light-emitting layer EML2. The second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and if necessary (e.g., when necessary), may further include a hole buffer layer and / or an electron blocking layer, etc. The second hole transport unit HTU2 may transport holes from the p-type (or p-like) charge generation layer p-CGL to the second light-emitting layer EML2 and the third light-emitting layer EML3.

[0204] The second light-emitting layer EML2 may be disposed between the second hole transport unit HTU2 and the third light-emitting layer EML3. In an embodiment, the second light-emitting layer EML2 may emit red light. In an embodiment, the second light-emitting layer EML2 may include a red hole transport host, a red electron transport host, and a red phosphorescent dopant. The red hole transport host may be a compound having strong hole properties, and may include a portion that easily accepts holes (or a hole transport portion). For example, the hole transport portion may include an amine group, a carbazole group, a dibenzofuran group, a dibenzothiophene group, and / or a fluorene group, etc., but is not limited thereto. The red electron transport host may be a compound having strong electronic properties, and may include a portion that easily accepts electrons (or an electron transport portion). For example, the electron transport portion may include -F, a cyano group, a C substituted by -F or a cyano group, or a C substituted by -F or a cyano group. 1 -C 60 Alkyl, C substituted by -F or cyano 6 -C 60 an aromatic group and / or a π-electron deficient nitrogen-containing cyclic group, etc., but not limited thereto. The red hole transport host and the red electron transport host may be mixed in a weight ratio to balance hole transport and electron transport.

[0205] The third light-emitting layer EML3 may be disposed between the second light-emitting layer EML2 and the second electron transport unit ETU2. In an embodiment, the third light-emitting layer EML3 may emit green light. In an embodiment, the third light-emitting layer EML3 may include a green hole transport host, a green electron transport host, and a green phosphorescent dopant. The green hole transport host may be a compound having strong hole characteristics and may include a hole transport portion. The green hole transport host may be composed of a compound that is the same as or different from the compound of the red hole transport host. The green electron transport host may be a compound having strong electron characteristics and may include an electron transport portion. The green electron transport host may be composed of a compound that is the same as or different from the compound of the red electron transport host. The mixing ratio of the green hole transport host and the green electron transport host is not particularly limited, and the green hole transport host and the green electron transport host may be mixed in a weight ratio that balances hole transport and electron transport.

[0206] Since the second light emitting unit EU2 includes the second light emitting layer EML2 and the third light emitting layer EML3, red light emitted from the second light emitting layer EML2 and green light emitted from the third light emitting layer EML3 may be mixed to provide yellow light.

[0207] The second electron transport unit ETU2 may be disposed between the third light emitting layer EML3 and the cathode electrode CE. The second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and if necessary (e.g., when necessary), may further include an electron buffer layer and / or a hole blocking layer, etc. The second electron transport unit ETU2 may transport electrons from the cathode electrode CE to the second light emitting layer EML2 and the third light emitting layer EML3.

[0208] The cap layer CPL may be disposed in the direction of emitting light. For example, the cap layer CPL may be disposed on the cathode electrode CE. The cap layer CPL may improve external light emission efficiency based on the principle of constructive interference. The cap layer CPL may include an organic material, an inorganic material, or a composite material including an organic material and an inorganic material.

[0209] Fig.10 It is shown Fig. 9 The diagram shows the light-emitting principle of the light-emitting element. Fig.10 , components related to light emission of the second light emitting layer EML2 and the third light emitting layer EML3 are illustrated, and remaining components are omitted. Fig.11 It shows that for each gray level Fig. 9 Diagram of the exciton distribution at the position of the light-emitting element.

[0210] Reference Fig. 9 and Fig.10 , if voltage is applied to the light emitting element LD (see Fig. 9) (for example, when voltage is applied to the light emitting element LD), holes move along the highest occupied molecular orbital HOMO energy level. For example, holes from the p-type (or p-like) charge generation layer p-CGL reach the second light emitting layer EML2 and the third light emitting layer EML3 through the second hole transport unit HTU2. In some embodiments, electrons move along the lowest unoccupied molecular orbital LUMO energy level. For example, electrons from the cathode electrode CE reach the second light emitting layer EML2 and the third light emitting layer EML3 through the second electron transport unit ETU2. Therefore, excitons obtained by recombining holes and electrons are formed in each of the second light emitting layer EML2 and the third light emitting layer EML3, and the second light emitting layer EML2 emits red light (R) and the third light emitting layer EML3 emits green light (G).

[0211] At this time, because the LUMO energy level of the second light-emitting layer EML2 is lower (or deeper) than the LUMO energy level of the third light-emitting layer EML3, electrons are easily and quickly injected from the third light-emitting layer EML3 into the second light-emitting layer EML2. In particular, when an excessive amount of electrons is injected into the second light-emitting layer EML2 at a relatively low grayscale, the red light efficiency is excessively increased. As a result, a roll-off phenomenon in which the red light efficiency is rapidly reduced at a relatively high grayscale may occur due to saturation and / or characteristic degradation of the second light-emitting layer EML2, etc.

[0212] Reference Fig.11 , because the electron injection from the third light-emitting layer EML3 to the second light-emitting layer EML2 is easy and fast at a relatively low gray level, the excitons are excessively formed near the second light-emitting layer EML2 adjacent to the second hole transport unit HTU2, and thus the red light efficiency is excessively increased. At a relatively high gray level, the excitons are mainly formed near the third light-emitting layer EML3 adjacent to the second light-emitting layer EML2. For example, from a low gray level (i.e., a low gray value) to a high gray level (i.e., a high gray value), the main position of the exciton distribution moves from the second light-emitting layer EML2 to the third light-emitting layer EML3. At this time, due to the mutual influence between the excitons of the second light-emitting layer EML2 and the excitons of the third light-emitting layer EML3, exciton quenching in which the light efficiency is reduced may occur. In this case, because the difference in red light efficiency between low gray levels and high gray levels is large, the roll-off phenomenon may be aggravated.

[0213] Fig.12 is a diagram showing a light emitting element according to some embodiments. Fig.12 In the Fig. 9 The content duplicates the description of the content.

[0214] Reference Fig.12, the light emitting element LD' may further include an intermediate layer IL. The intermediate layer IL may be included in the second light emitting unit EU2. The intermediate layer IL may be disposed on the second light emitting layer EML2. More specifically, the intermediate layer IL may be disposed between the second light emitting layer EML2 and the third light emitting layer EML3. The intermediate layer IL may block or reduce (or lower) electron injection from the third light emitting layer EML3 to the second light emitting layer EML2, while increasing hole injection from the second light emitting layer EML2 to the third light emitting layer EML3.

[0215] In an embodiment, the entire thickness of the second light emitting layer EML2, the intermediate layer IL, and the third light emitting layer EML3 may be 300 angstroms. to For example, about to

[0216] In an embodiment, the thickness of the intermediate layer IL may be to In some embodiments, the thickness of the intermediate layer IL may be about Within the range described herein, the red light roll-off phenomenon can be reduced by preventing or reducing the red light efficiency from increasing rapidly at low gray levels. In some embodiments, sufficient red light efficiency can be ensured without increasing the driving voltage.

[0217] In an embodiment, the LUMO energy level of the intermediate layer IL may be higher than (or shallower than) the LUMO energy level of the third light-emitting layer EML3. In this case, electron injection from the third light-emitting layer EML3 to the second light-emitting layer EML2 becomes difficult. In particular, since excessive electron injection into the second light-emitting layer EML2 at a low gray level is prevented or reduced, a rapid increase in red light efficiency can be prevented or reduced.

[0218] In an embodiment, the LUMO level of the intermediate layer IL may be less than 1.5 electron volts (eV). If the LUMO level of the intermediate layer IL is 1.5 eV or higher (for example, when the LUMO level of the intermediate layer IL is 1.5 eV or higher), electron injection from the third light-emitting layer EML3 to the second light-emitting layer EML2 may be excessively reduced, and thus the red light efficiency may be excessively reduced. For example, within the range described herein, sufficient red light efficiency can be ensured by preventing or reducing excessive increase and decrease in red light efficiency at low gray levels.

[0219] In an embodiment, the intermediate layer IL may include a compound having at least one of a carbazole group and a triphenylamine group. In this case, electron injection from the third light-emitting layer EML3 to the second light-emitting layer EML2 may be blocked (or reduced), and hole injection from the second light-emitting layer EML2 to the third light-emitting layer EML3 may be smoothly performed. For example, the intermediate layer IL may include at least one compound represented by the following Formulae 1 to 4. Formula 1 is N-[1,1'-biphenyl]-4-yl-N-phenyl-3'-3-phenyl-9H-carbazole-9-yl-[1,1'-biphenyl]-4-amine, Formula 2 is N,N-di[1,1'-biphenyl]-4-yl-4'-9H-carbazole-9-yl-[1,1'-biphenyl]-4-amine, Formula 3 is N,N-di[1,1'-biphenyl]-4-yl-3'-9H-carbazole-9-yl-[1,1'-biphenyl]-4-amine, and Formula 4 is N-[1,1'-biphenyl]-4-yl-3'-9H-carbazole-9-yl-N-phenyl-[1,1'-biphenyl]-4-amine.

[0220] Formula 1

[0221]

[0222] Formula 2

[0223]

[0224] Formula 3

[0225]

[0226] Formula 4

[0227]

[0228] Fig.13 It is shown Fig.12 The diagram shows the light-emitting principle of the light-emitting element. Fig.13 , components related to light emission of the second light emitting layer EML2 and the third light emitting layer EML3 are illustrated, and remaining components are omitted. Fig.14 It shows that for each gray level Fig.12 Diagram of the exciton distribution at the position of the light-emitting element.

[0229] Reference Fig.12 and Fig.13, because the LUMO energy level of the intermediate layer IL is higher (or shallower) than the LUMO energy level of the third light-emitting layer EML3, the electron injection from the third light-emitting layer EML3 to the intermediate layer IL is reduced, and as a result, the electron injection into the second light-emitting layer EML2 is reduced. In particular, since excessive electron injection into the second light-emitting layer EML2 at low gray levels is prevented or reduced, excessive increase in red light efficiency can be prevented or reduced. As a result, since the degree of reduction in red light efficiency at high gray levels is reduced, the roll-off phenomenon can be improved.

[0230] Reference Fig.14 , because the electron injection from the third light-emitting layer EML3 to the second light-emitting layer EML2 at low gray levels is prevented or reduced (or reduced), the excitons are mainly formed in the vicinity of the second light-emitting layer EML2 adjacent to the intermediate layer IL. In some embodiments, the amount of excitons formed in the second light-emitting layer EML2 is reduced, so the red light efficiency is reduced. At high gray levels, the excitons are mainly formed in the vicinity of the third light-emitting layer EML3 adjacent to the intermediate layer IL. For example, from low gray levels to high gray levels, the main position of the exciton distribution moves from the second light-emitting layer EML2 to the third light-emitting layer EML3, but due to the intermediate layer IL, the degree of reduction in red light efficiency caused by exciton quenching is reduced. Therefore, the difference in red light efficiency between low gray levels and high gray levels can be reduced, thereby improving the roll-off phenomenon of red light.

[0231] Fig.15 is a graph showing red light efficiency according to current density for each light emitting element. Fig.16 is a graph showing current density according to driving voltage for each light emitting element.

[0232] Reference Fig.15 ,exist Fig. 9 In the light emitting element LD, electrons are excessively injected into the second light emitting layer EML2 (refer to Fig.10 ), so the red light efficiency increases significantly or rapidly. On the other hand, when the gray level is at a relatively high gray level where the current density is relatively high, the red light efficiency is greatly reduced and a roll-off phenomenon occurs. Fig.12 In the light emitting element LD', at a relatively low gray level where the current density is relatively low, electron injection into the second light emitting layer EML2 (refer to Fig.13 ), so the red light efficiency does not increase significantly or rapidly. In addition, even if the gray level is a relatively high gray level in which the current density is relatively high, the roll-off phenomenon can be reduced or improved because the degree of reduction in the red light efficiency is relatively small.

[0233] Reference Fig.16 ,according to Fig. 9 The light emitting element LD and Fig.12The current density of the driving voltage of the light emitting element LD' is presented at a similar level. For example, if the intermediate layer IL (refer to Fig.12 ) of the light emitting element LD' (for example, when using the light emitting element LD' comprising the intermediate layer IL (refer to Fig.12 ) when the light-emitting element LD' is provided, the roll-off phenomenon described here can be reduced or improved, and sufficient current density can be ensured without increasing the driving voltage.

[0234] Fig.17 is a diagram showing a light emitting element according to some embodiments. Fig.17 In the Fig. 9 The content duplicates the description of the content.

[0235] Reference Fig.17 ,and Fig.12 Unlike the light emitting element LD', the light emitting element LD" does not include the intermediate layer IL, and includes Fig. 9 The light emitting element LD is different from the second light emitting layer EML2.

[0236] In an embodiment, the second light-emitting layer EML2 may include a red bipolar host and a red phosphorescent dopant. The red bipolar host may include at least one hole transport portion and at least one electron transport portion. For example, the red bipolar host may be an amphiphilic host having both hole properties and electron properties (e.g., simultaneously). For example, the hole transport portion may include an amine group, a carbazole group, a dibenzofuranyl group, a dibenzothiophene group, and / or a fluorene group, and the electron transport portion may include -F, a cyano group, a C substituted by -F or a cyano group, or a C substituted by -F or a cyano group. 1 -C 60 Alkyl, C substituted by -F or cyano 6 -C 60 aromatic group and / or π-electron deficient nitrogen-containing cyclic group, etc., but the disclosure is not limited thereto. In this case, since the second light-emitting layer EML2 includes a red electron transport host (see Fig. 9 ), the electron accepting performance of the second light-emitting layer EML2 is reduced, so the injection of electrons into the second light-emitting layer EML2 can be reduced.

[0237] In an embodiment, the LUMO energy level of the red bipolar host may be higher than (or shallower than) the LUMO energy level of the green electron transport host included in the third light-emitting layer EML3. In this case, the LUMO energy level of the second light-emitting layer EML2 becomes higher than the LUMO energy level of the third light-emitting layer EML3, and thus electron injection from the third light-emitting layer EML3 to the second light-emitting layer EML2 becomes difficult. In particular, since excessive electron injection into the second light-emitting layer EML2 at a relatively low gray level is prevented or reduced, a rapid increase in red light efficiency can be prevented or reduced.

[0238] In an embodiment, the LUMO energy level of the red bipolar host may be less than 1.9 eV. If the LUMO energy level of the red bipolar host is 1.9 eV or higher (for example, when the LUMO energy level of the red bipolar host is 1.9 eV or higher), the LUMO energy level of the second light-emitting layer EML2 may become too high, and the electron injection from the third light-emitting layer EML3 to the second light-emitting layer EML2 may be excessively reduced, so the red light efficiency may become too low. For example, within the range described herein, sufficient red light efficiency can be ensured by preventing or reducing excessive increase and decrease of red light efficiency at low grayscales.

[0239] Fig.18 It is shown Fig.17 The diagram shows the light-emitting principle of the light-emitting element. Fig.18 , components related to light emission of the second light emitting layer EML2 and the third light emitting layer EML3 are illustrated, and remaining components are omitted. Fig.19 It is shown that for each gray level Fig.17 Diagram of the exciton distribution at the position of the light-emitting element.

[0240] Reference Fig.17 and Fig.18 , because the LUMO energy level of the second light-emitting layer EML2 is higher (or shallower) than the LUMO energy level of the third light-emitting layer EML3, the electron injection from the third light-emitting layer EML3 to the second light-emitting layer EML2 is reduced. In particular, since excessive electron injection into the second light-emitting layer EML2 at a relatively low gray level is prevented or reduced, an excessive increase in red light efficiency can be prevented or reduced. As a result, since the degree of reduction in red light efficiency at a relatively high gray level is reduced, the roll-off phenomenon can be reduced or improved.

[0241] Reference Fig.19 , because the electron injection from the third light-emitting layer EML3 to the second light-emitting layer EML2 at a relatively low gray level is blocked (or reduced), the excitons are mainly formed in the vicinity of the second light-emitting layer EML2 adjacent to the third light-emitting layer EML3. In some embodiments, the amount of excitons is reduced, so the red light efficiency is reduced. At a relatively high gray level, the excitons are mainly formed in the vicinity of the third light-emitting layer EML3 adjacent to the second light-emitting layer EML2. For example, from a low gray level to a high gray level, the main position of the exciton distribution moves from the second light-emitting layer EML2 to the third light-emitting layer EML3, and exciton quenching occurs, so the red light efficiency is reduced. In this case, because the red light efficiency is small at a relatively low gray level, the difference in red light efficiency between a relatively low gray level and a relatively high gray level can be reduced, thereby improving the roll-off phenomenon of red light.

[0242] Fig. 20is a graph showing red light efficiency according to current density for each light emitting element. Fig.21 is a graph showing current density according to driving voltage for each light emitting element.

[0243] Reference Fig. 20 ,exist Fig. 9 In the light emitting element LD, electrons are excessively injected into the second light emitting layer EML2 (refer to Fig.10 ), so the red light efficiency increases rapidly. Therefore, when the gray level is at a relatively high gray level with high current density, the red light efficiency is greatly reduced and a roll-off phenomenon occurs. On the contrary, Fig.17 In the light-emitting element LD", at a relatively low gray level where the current density is low, electron injection into the second light-emitting layer EML2 (refer to Fig.18 ), so the red light efficiency does not increase rapidly. Therefore, even if the grayscale is at a relatively high grayscale level where the current density is high, the roll-off phenomenon can be reduced or improved because the degree of reduction in the red light efficiency is small.

[0244] Reference Fig.21 ,according to Fig. 9 The light emitting element LD and Fig.17 The current density of the driving voltage of the light-emitting element LD" is presented at a similar level. For example, if the second light-emitting layer EML2 (refer to Fig.17 )" (for example, when using a second light-emitting layer EML2 (refer to Fig.17 ) when the light-emitting element LD is "light-emitting", the roll-off phenomenon described here can be reduced or improved, and sufficient current density can be ensured without increasing the driving voltage.

[0245] Fig. 22 is a diagram illustrating a display system according to some embodiments.

[0246] Reference Fig. 22 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0247] The processor 1100 may perform one or more suitable tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor and / or a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system and control the other components.

[0248] exist Fig. 22, the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and may be connected to the second display device 1220 through a second channel CH2.

[0249] Through the first channel CH1, the processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 The display device 100 described above is similarly constructed. In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0250] Through the second channel CH2, the processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The display device 100 described above is similarly constructed. In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0251] The display system 1000 may include at least one selected from among computing systems that provide an image display function (such as a portable computer, a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a portable multimedia player (PMP), a navigation device, an ultra mobile personal computer (UMPC), and one or more combinations thereof). In some embodiments, the display system 1000 may include at least one of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0252] Fig.23 It is shown Fig. 22 FIG. 1 is a diagram showing an application example of the display system.

[0253] Reference Fig.23 , Fig. 22 The display system 1000 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that may be worn on a user's head.

[0254] The head-mounted display device 2000 may include a head-mounted band 2100 and a display device storage case 2200. The head-mounted band 2100 may be connected to the display device storage case 2200. The head-mounted band 2100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper part of the user's head. However, the embodiment is not limited thereto. For example, the head-mounted band 2100 may be implemented in the form of a glasses frame and / or a helmet, etc.

[0255] The display device storage housing 2200 can accommodate Fig. 22 The display device storage housing 2200 can also accommodate the first display device 1210 and the second display device 1220. Fig. 22 Processor 1100.

[0256] Fig.24 It is shown Fig.23 FIG. 1 is a diagram of a head mounted display device worn by a user.

[0257] Reference Fig.24 , the first display device 1210 (see Fig. 22 ) of the first display panel DP1 and the second display device 1220 (see Fig. 22 ) is provided in the head mounted display device 2000. The head mounted display device 2000 may further include one or more lenses LLNS and RLNS.

[0258] The right-eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user in the display device storage case 2200. The left-eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user in the display device storage case 2200.

[0259] The image output from the first display panel DP1 may be displayed to the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract light from the first display panel DP1 to guide it toward the right eye of the user. The right eye lens RLNS may perform an optical function for adjusting the viewing distance between the first display panel DP1 and the right eye of the user.

[0260] The image output from the second display panel DP2 may be displayed to the left eye of the user through the left eye lens LLNS. The left eye lens LLNS may refract the light from the second display panel DP2 to guide it toward the left eye of the user. The left eye lens LLNS may perform an optical function for adjusting the viewing distance between the second display panel DP2 and the left eye of the user.

[0261] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In this case, each display panel may output images corresponding to the sub-regions of the multi-channel lens, respectively, and the output images may pass through the corresponding sub-regions and may be viewed by a user.

[0262] Example

[0263] Comparative Example 1

[0264] The light emitting element LD1 of Comparative Example 1 does not include the intermediate layer IL. In some embodiments, the second light emitting layer EML2 includes a red hole transport host, a red electron transport host, and a red phosphorescent dopant, and the thickness of the second light emitting layer EML2 is 50 angstroms. In some embodiments, the third light-emitting layer EML3 includes a green hole transport host, a green electron transport host, and a green phosphorescent dopant, and the thickness of the third light-emitting layer EML3 is

[0265] Comparative Example 2

[0266] The light emitting element LD2 of Comparative Example 2 is the same as the light emitting element LD1 of Comparative Example 1, except that the second light emitting layer EML2 includes a red fluorescent dopant and the third light emitting layer EML3 includes a green fluorescent dopant.

[0267] Example 1

[0268] In addition to the light emitting element LD1′ of Example 1 including the intermediate layer IL, the intermediate layer IL includes the compound F1 represented by Formula 1 herein and the thickness of the intermediate layer IL is Otherwise, the light emitting element LD1 ′ of Example 1 is the same as the light emitting element LD1 of Comparative Example 1.

[0269] Example 2

[0270] The light emitting element LD2 ′ of Example 2 is the same as the light emitting element LD1 ′ of Example 1, except that the intermediate layer IL includes the compound F2 represented by Formula 2 herein.

[0271] Example 3

[0272] The light emitting element LD3 ′ of Example 3 is the same as the light emitting element LD1 ′ of Example 1, except that the intermediate layer IL includes the compound F3 represented by Formula 3 herein.

[0273] Example 4

[0274] In addition to the thickness of the intermediate layer IL Otherwise, the light emitting element LD4' of the fourth embodiment is the same as the light emitting element LD3' of the third embodiment.

[0275] Example 5

[0276] In addition to the thickness of the intermediate layer IL Otherwise, the light emitting element LD5' of the fifth embodiment is the same as the light emitting element LD3' of the third embodiment.

[0277] Example 6

[0278] In addition to the thickness of the second light emitting layer EML2 The thickness of the third light emitting layer EML3 is Otherwise, the light emitting element LD6' of the sixth embodiment is the same as the light emitting element LD5' of the fifth embodiment.

[0279] Example 7

[0280] In addition to the thickness of the second light emitting layer EML2 The thickness of the third light emitting layer EML3 is Otherwise, the light emitting element LD7' of the seventh embodiment is the same as the light emitting element LD5' of the fifth embodiment.

[0281] Example 8

[0282] In addition to the second light-emitting layer EML2 including a red bipolar host, the second light-emitting layer EML2 has a thickness of The thickness of the third light emitting layer EML3 is Except for this, the light emitting element LD″ of Example 8 is the same as the light emitting element LD1 of Comparative Example 1.

[0283] Evaluation Example

[0284] Table 1 shows the driving voltage, efficiency, and roll-off of the light emitting elements of Comparative Examples 1 to 2 and Examples 1 to 8 at a low gray scale.

[0285] Table 1

[0286]

[0287]

[0288] Referring to Table 1, it can be seen that the light-emitting element LD2 of Comparative Example 2 has an improved roll-off phenomenon of red light compared to the light-emitting element LD1 of Comparative Example 1, but exhibits a very high driving voltage and a very low red light efficiency (e.g., 70%). It can be seen that the roll-off phenomenon of red light in the light-emitting elements of Examples 1 to 8 is improved compared to the light-emitting element LD1 of Comparative Example 1, while the driving voltage and the red light efficiency do not change significantly. In particular, it can be seen that under the same driving voltage, the roll-off phenomenon of red light is improved while the same red light efficiency and high green light efficiency are maintained in the light-emitting element LD5' of Example 5 at the same time (e.g., in parallel) compared to the light-emitting element LD1 of Comparative Example 1.

[0289] Although the disclosure has been described according to the embodiments described herein, it should be noted that the embodiments described herein are used to describe the disclosure rather than to limit the scope of the disclosure. A person skilled in the art will appreciate that one or more suitable modifications are possible within the scope of the disclosed technical spirit.

[0290] The scope of the disclosure is not limited to the details described in the detailed description of the specification, but should also be defined by the claims and their equivalents. It will be understood that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the disclosure.

Claims

1. A light-emitting element, comprising: anode; a cathode facing the anode; as well as a light emitting structure between the anode and the cathode and including a first light emitting unit, a charge generating layer and a second light emitting unit, Wherein, the second light-emitting unit includes: a second hole transport unit on the charge generating layer; a second light-emitting layer on the second hole transport unit; an intermediate layer on the second light-emitting layer; a third light-emitting layer on the intermediate layer; and a second electron transport unit between the third light-emitting layer and the cathode.

2. The light-emitting element according to claim 1, wherein The first light emitting unit comprises: a first hole transport unit, on the anode; a first electron transport unit facing the first hole transport unit and adjacent to the charge generation layer; and The first light-emitting layer is between the first hole transport unit and the first electron transport unit.

3. The light-emitting element according to claim 1, wherein The total thickness of the second light-emitting layer, the intermediate layer and the third light-emitting layer is to 4. The light-emitting element according to claim 1, wherein The thickness of the intermediate layer is to 5. The light emitting element according to claim 1, wherein The LUMO energy level of the intermediate layer is higher than the LUMO energy level of the third light-emitting layer.

6. The light-emitting element according to claim 5, wherein The LUMO energy level of the intermediate layer is less than 1.5 eV.

7. The light-emitting element according to claim 1, wherein The intermediate layer includes a compound having at least one of a carbazole group and a triphenylamine group.

8. The light-emitting element according to claim 1, wherein The first light-emitting unit includes a first light-emitting layer, The first light-emitting layer is configured to emit blue light, The second light emitting layer is configured to emit red light, and The third light-emitting layer is configured to emit green light.

9. The light-emitting element according to claim 8, wherein The first light emitting layer includes a blue fluorescent host and a blue fluorescent dopant.

10. The light emitting element according to claim 8, wherein The second light emitting layer includes a red hole transport host, a red electron transport host and a red phosphorescent dopant, and The third light-emitting layer includes a green hole transport host, a green electron transport host and a green phosphorescent dopant.

11. The light emitting element according to claim 1, wherein The charge generation layer comprises: An n-type charge generation layer adjacent to the first light emitting unit; and The p-type charge generation layer is adjacent to the second light emitting unit.

12. The light-emitting element according to claim 1, further comprising: A capping layer is on the cathode.

13. A light-emitting element, comprising: anode; a cathode facing the anode; as well as a light emitting structure between the anode and the cathode and including a first light emitting unit, a charge generating layer and a second light emitting unit, The second light-emitting unit includes: a second hole transport unit on the charge generation layer; a second electron transport unit facing the second hole transport unit and adjacent to the cathode; and a second light-emitting layer and a third light-emitting layer between the second hole transport unit and the second electron transport unit, and The second light-emitting layer includes a red bipolar host and a red phosphorescent dopant.

14. The light emitting element according to claim 13, wherein The second light-emitting layer is between the second hole transport unit and the third light-emitting layer, and the third light-emitting layer is between the second light-emitting layer and the second electron transport unit.

15. The light emitting element according to claim 13, wherein The third light-emitting layer includes a green hole transport host, a green electron transport host and a green phosphorescent dopant.

16. The light emitting element according to claim 15, wherein The LUMO energy level of the red bipolar host is higher than the LUMO energy level of the green electron transport host.

17. The light emitting element according to claim 16, wherein The LUMO energy level of the red bipolar host is less than 1.9 eV.

18. The light emitting element according to claim 13, wherein The first light emitting unit comprises: a first hole transport unit, on the anode; a first electron transport unit facing the first hole transport unit and adjacent to the charge generation layer; and The first light-emitting layer is between the first hole transport unit and the first electron transport unit.

19. A display device comprising the light-emitting element according to claim 1.

20. The display device according to claim 19, wherein: The display device includes at least one of a flat panel display, a curved display, a flexible display, a rollable display, a foldable display, a stretchable display, a head-up display, a head-mounted display, a wearable display, a microdisplay, a 3D display, a virtual reality display, an augmented reality display, and a mixed reality display.

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