Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a first pixel electrode disposed on a substrate in a first emission area; the insulating layer covers the edge of the first pixel electrode; a first light emitting layer disposed on the first pixel electrode and the insulating layer; the first common electrode is arranged on the first light-emitting layer; a conductive layer disposed on the insulating layer to surround the first emission region, and contacting the first common electrode; a first bank disposed on the conductive layer; a second bank disposed on the first bank and including a tip protruding from a side surface of the first bank toward the first emission region; and a third bank disposed on the second bank and including an inorganic material.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] With the development of information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices, such as smart phones, digital cameras, notebook computers, navigation devices and smart TVs. The display device can be a flat panel display device, such as a liquid crystal display device, a field emission display device and a light-emitting display device (e.g., an organic light-emitting display device). Among these flat panel display devices, the light-emitting display device includes a light-emitting element that enables each pixel of the display panel to emit light by itself. Therefore, the light-emitting display device can display an image without a backlight unit that provides light to the display panel. Summary of the invention

[0003] Aspects of the present disclosure provide a display device capable of improving reliability of a light emitting element by blocking a moisture permeation path and a method of manufacturing the display device.

[0004] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0005] According to an embodiment, a display device includes: a first pixel electrode, which is arranged on a substrate in a first emission area; an insulating layer, which covers an edge of the first pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode and the insulating layer; a first common electrode, which is arranged on the first light-emitting layer; a conductive layer, which is arranged on the insulating layer to surround the first emission area and contact the first common electrode; a first dam, which is arranged on the conductive layer; a second dam, which is arranged on the first dam, and the second dam includes a tip protruding from a side surface of the first dam toward the first emission area; and a third dam, which is arranged on the second dam, and the third dam includes an inorganic material.

[0006] The display device may further include a fourth bank disposed on the third bank and including a metal material.

[0007] The thickness of the first bank may be greater than the sum of the thicknesses of the second bank, the third bank, and the fourth bank, and the thickness of the third bank may be greater than the thickness of each of the second bank and the fourth bank.

[0008] The display device may also include: a first organic pattern, which includes the same material as the first light-emitting layer and is arranged on the fourth embankment in an area adjacent to the first emission area; and a first electrode pattern, which includes the same material as the first common electrode and is arranged on the first organic pattern on the fourth embankment.

[0009] The display device may further include: a cladding layer disposed on the first common electrode; and a first cladding pattern including the same material as the cladding layer, and the first cladding pattern is disposed on the first electrode pattern.

[0010] The display device may also include a first inorganic layer, which covers the side surface of the first embankment, the lower surface and side surface of the tip of the second embankment, the side surface of the third embankment and the side surface of the fourth embankment, the side surface of the first organic pattern, the side surface of the first electrode pattern, and the upper surface and side surface of the first coating pattern.

[0011] The display device may further include: a second pixel electrode disposed on the substrate in the second emission region; a second light emitting layer disposed on the second pixel electrode; and a second common electrode disposed on the second light emitting layer to contact the conductive layer.

[0012] The first common electrode and the second common electrode may be electrically connected through the conductive layer.

[0013] The display device may further include: a coating layer disposed on the second common electrode; a second organic pattern comprising the same material as the second light-emitting layer, and the second organic pattern being disposed on the fourth embankment in an area adjacent to the second emission region; a second electrode pattern comprising the same material as the second common electrode, and the second electrode pattern being disposed on the second organic pattern on the fourth embankment; and a second coating pattern comprising the same material as the coating layer, and the second coating pattern being disposed on the second electrode pattern.

[0014] The display device may also include a second inorganic layer, which covers the side surface of the first embankment, the lower surface and side surface of the tip of the second embankment, the side surface of the third embankment and the side surface of the fourth embankment, the side surface of the second organic pattern, the side surface of the second electrode pattern, and the upper surface and side surface of the second coating pattern.

[0015] The display device may also include: a coating layer disposed on the first common electrode; a first organic pattern comprising the same material as the first light-emitting layer, and the first organic pattern being disposed on the third embankment in an area adjacent to the first emission area; a first electrode pattern comprising the same material as the first common electrode, and the first electrode pattern being disposed on the first organic pattern on the third embankment; and a first coating pattern comprising the same material as the coating layer, and the first coating pattern being disposed on the first electrode pattern.

[0016] The display device may further include a fourth bank disposed on the third bank, and the fourth bank and the third bank may include a different inorganic material.

[0017] The display device may further include: a fourth bank disposed on the third bank; and a fifth bank disposed on the fourth bank, and the fifth bank protrudes from a side surface of the fourth bank toward the first emission region.

[0018] According to an embodiment, a display device includes: a first pixel electrode, which is arranged on a substrate in a first emission area; a second pixel electrode, which is arranged on the same layer as the first pixel electrode in the second emission area; an insulating layer, which covers the edge of each of the first pixel electrode and the second pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode and the insulating layer; a first common electrode, which is arranged on the first light-emitting layer; a second light-emitting layer, which is arranged on the second pixel electrode and the insulating layer; a second common electrode, which is arranged on the second light-emitting layer; a conductive layer, which is arranged on the insulating layer to surround each of the first emission area and the second emission area and electrically connect the first common electrode and the second common electrode; a first dam, which is arranged on the conductive layer; a second dam, which is arranged on the first dam, and the second dam includes a tip protruding from the side surface of the first dam toward each of the first emission area and the second emission area; a third dam, which is arranged on the second dam; and a fourth dam, which is arranged on the third dam, and the fourth dam includes a tip protruding from the side surface of the third dam toward each of the first emission area and the second emission area.

[0019] The display device may also include: a coating layer disposed on the first common electrode; a first organic pattern comprising the same material as the first light-emitting layer, and the first organic pattern is disposed on the fourth embankment in an area adjacent to the first emission area; a first electrode pattern comprising the same material as the first common electrode, and the first electrode pattern is disposed on the first organic pattern on the fourth embankment; a first coating pattern comprising the same material as the coating layer, and the first coating pattern is disposed on the first electrode pattern; and a first inorganic layer covering the side surface of the first embankment, the lower surface and side surface of the tip of the second embankment, the side surface of the third embankment, the lower surface and side surface of the tip of the fourth embankment, the side surface of the first organic pattern, the side surface of the first electrode pattern, and the upper surface and side surface of the first coating pattern.

[0020] The display device may also include: a coating layer disposed on the second common electrode; a second organic pattern comprising the same material as the second light-emitting layer, and the second organic pattern is disposed on the fourth embankment in an area adjacent to the second emission area; a second electrode pattern comprising the same material as the second common electrode, and the second electrode pattern is disposed on the second organic pattern on the fourth embankment; a second coating pattern comprising the same material as the coating layer, and the second coating pattern is disposed on the second electrode pattern; and a second inorganic layer covering the side surface of the first embankment, the lower surface and the side surface of the tip of the second embankment, the side surface of the third embankment, the lower surface and the side surface of the tip of the fourth embankment, the side surface of the second organic pattern, the side surface of the second electrode pattern, and the upper surface and side surface of the second coating pattern.

[0021] According to an embodiment, a method for manufacturing a display device includes: forming a pixel electrode and a sacrificial layer on a substrate, the pixel electrode including a first pixel electrode overlapping a first emission region and a second pixel electrode overlapping a second emission region; sequentially stacking an insulating layer, a conductive layer, a first dam, a second dam, a third dam and a fourth dam on the pixel electrode; forming a tip of the second dam protruding from a side surface of the first dam by etching the fourth dam, the third dam, the second dam, the first dam and the conductive layer; exposing the first pixel electrode and the second pixel electrode by etching the insulating layer and the sacrificial layer; forming a first light-emitting layer on the first pixel electrode, and A first organic pattern is formed on the fourth embankment; a first common electrode is formed on the first light-emitting layer, and a first electrode pattern is formed on the first organic pattern on the fourth embankment; a coating layer is formed on the first common electrode, and a first coating pattern is formed on the first electrode pattern on the fourth embankment; and a first inorganic layer is formed, the first inorganic layer covering the upper surface of the coating layer, the side surface of the first embankment, the lower surface and side surface of the tip of the second embankment, the side surface of the third embankment and the side surface of the fourth embankment, the side surface of the first organic pattern, the side surface of the first electrode pattern, and the upper surface and side surface of the first coating pattern.

[0022] Each of the third bank and the first inorganic layer may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0023] The method may further include etching the first inorganic layer, the first cladding pattern, the first electrode pattern, and the first organic pattern overlapping the second emission region and the fourth bank disposed adjacent to the second emission region.

[0024] The method may also include: forming a second light-emitting layer on the second pixel electrode, and forming a second organic pattern on the fourth embankment; forming a second common electrode on the second light-emitting layer, and forming a second electrode pattern on the second organic pattern on the fourth embankment; forming a coating layer on the second common electrode, and forming a second coating pattern on the second electrode pattern on the fourth embankment; and forming a second inorganic layer, the second inorganic layer covering the upper surface of the coating layer, the side surface of the first embankment, the lower surface and the side surface of the tip of the second embankment, the side surface of the third embankment and the side surface of the fourth embankment, the side surface of the second organic pattern, the side surface of the second electrode pattern, and the upper surface and side surface of the second coating pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a perspective view of a display device according to an embodiment;

[0027] Figure 2 is a cross-sectional view of a display device according to an embodiment;

[0028] Figure 3 is a plan view of a display unit of a display device according to an embodiment;

[0029] Figure 4 is a cross-sectional view showing a pixel of a display device according to an embodiment;

[0030] Figure 5 yes Figure 4 An enlarged view of area A1;

[0031] Figure 6 is a cross-sectional view showing a pixel of a display device according to an embodiment;

[0032] Figure 7 yes Figure 6 An enlarged view of area A2;

[0033] Figure 8 is a cross-sectional view showing a pixel of a display device according to an embodiment;

[0034] Fig. 9 yes Figure 8 An enlarged view of area A3;

[0035] Fig.10 is a cross-sectional view showing a pixel of a display device according to an embodiment;

[0036] Fig.11 yes Fig.10 An enlarged view of area A4;

[0037] Fig.12 is a cross-sectional view showing a pixel of a display device according to an embodiment;

[0038] Fig.13 yes Fig.12 An enlarged view of area A5;

[0039] Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 is a cross-sectional view showing a process of manufacturing a display device according to an embodiment;

[0040] Fig. 22 A virtual reality device including a display device according to an embodiment is shown;

[0041] Fig.23 and Fig.24 A head mounted display including a display device according to an embodiment is shown;

[0042] Fig.25 It is shown Figure 22 to Figure 24 A cross-sectional view of a pixel according to an embodiment in a display device of FIG. 1 ;

[0043] Fig.26 It is shown Figure 22 to Figure 24 A cross-sectional view of a pixel according to an embodiment in a display device of FIG. 1 ;

[0044] Fig. 27 It is shown Figure 22 to Figure 24 A cross-sectional view of a pixel according to an embodiment in a display device of FIG. 1 ;

[0045] Fig.28 It is shown Figure 22 to Figure 24 A cross-sectional view of a pixel according to an embodiment in a display device of FIG. 1 ; and

[0046] Fig.29 It is shown Figure 22 to Figure 24 sectional view of a pixel according to an embodiment in a display device of FIG. DETAILED DESCRIPTION

[0047] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more of the disclosures disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, structures and devices are shown in block diagram form to avoid unnecessarily obscuring various embodiments. In addition, various embodiments may be different, but need not be exclusive, nor need to limit the present disclosure. For example, without departing from the present disclosure, the specific shapes, configurations, and features of the embodiments may be used or implemented in other embodiments.

[0048] Unless otherwise specified, the embodiments shown should be understood as providing features of different details of some ways in which the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged without departing from the present disclosure.

[0049] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. As such, unless otherwise indicated, the presence or absence of cross-hatching or shading does not convey or indicate a preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other features, attributes, characteristics, etc. of the elements.

[0050] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments may be implemented differently, a specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. Moreover, the same reference numerals represent the same elements.

[0051] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, connected to, or coupled to another element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements or layers.

[0052] In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and therefore, are not limited to the X-axis, Y-axis, and Z-axis, and the X-axis, Y-axis, and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0053] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, or ZX, etc. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0054] Although the terms "first" and "second" etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0055] Spatially relative terms (such as "under," "below," "below," "lower," "above," "upper," "above," "higher," and "side" (e.g., in a "sidewall"), etc.) may be used herein for descriptive purposes and to describe the relationship of one element to another (or other) elements shown in the drawings. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, then elements or features described as "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "under" can cover both above and below orientations. In addition, the device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative terms used herein should be interpreted accordingly.

[0056] The terms used herein are for describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "one (kind / person)" and "the (the)" are also intended to include plural forms. In addition, the terms "comprises", "comprising") and / or "includes", "including"), when used in this specification, indicate the presence of stated features, wholes, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms, rather than terms of degree, and as such, are used to illustrate the inherent deviations in measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0057] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments disclosed herein need not be construed as limited to the shapes of the particular zones shown, but will include deviations in shape due to, for example, manufacturing. Thus, the zones shown in the drawings may be schematic in nature, and the shapes of these zones may not reflect the actual shapes of the zones of the device, and as such, it is not necessarily intended to limit the shapes of these zones.

[0058] According to the practice in the art, some embodiments are described and shown in the accompanying drawings with respect to functional blocks, units, components and / or modules. It will be understood by those skilled in the art that these blocks, units, components and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements and wiring connections, etc.), and these blocks, units, components and / or modules can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units, components and / or modules are implemented by microprocessors or other similar hardware, blocks, units, components and / or modules can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also conceivable that each block, unit, component and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and processors that perform other functions (e.g., one or more programmed microprocessors and associated circuit systems). Furthermore, without departing from the scope of the present disclosure, each block, unit, component and / or module of some embodiments can be physically divided into two or more interacting and discrete blocks, units, components and / or modules. In addition, without departing from the scope of the present disclosure, the blocks, units, components and / or modules of some embodiments can be physically combined into more complex blocks, units, components and / or modules.

[0059] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the context of the present disclosure, and should not be interpreted in an idealized or overly formal sense.

[0060] Hereinafter, detailed embodiments of the present disclosure are described with reference to the accompanying drawings.

[0061] Figure 1 is a perspective view of a display device 10 according to the embodiment.

[0062] Reference Figure 1The display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays.

[0063] The display device 10 may have a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral having short sides in the X-axis direction and long sides in the Y-axis direction. Each corner where the short side extending in the X-axis direction intersects the long side extending in the Y-axis direction may be a rounded corner with a predetermined curvature or may be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0064] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0065] The display panel 100 may include a main area MA and a sub area SBA.

[0066] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0067] For example, each of the multiple self-luminous elements may include (but is not limited to) at least one of an organic light-emitting diode including an organic light-emitting layer, a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, and a micro light-emitting diode.

[0068] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) that supplies a gate signal to a gate line and a fan-out line (not shown) that connects the display driver 200 and a signal line provided in the display area DA.

[0069] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, curled, etc. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (Z-axis direction). The sub-region SBA may include a display driver 200 and a pad unit connected to the circuit board 300. Alternatively, the sub-region SBA may be omitted, and the display driver 200 and the pad unit may be disposed in the non-display area NDA.

[0070] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to data lines. The display driver 200 may supply power voltages to power lines and supply gate control signals to gate drivers. The display driver 200 may be formed as an integrated circuit and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in a sub-region SBA and may overlap with the main region MA in a thickness direction (Z-axis direction) by bending the sub-region SBA. For another example, the display driver 200 may be mounted on a circuit board 300.

[0071] The circuit board 300 may be connected to the pad unit of the display panel 100 using an anisotropic conductive film. The leads of the circuit board 300 may be electrically connected to the pad unit of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0072] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit and sense a change in capacitance between the touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may determine whether an input has been made based on a change in capacitance between the touch electrodes and calculate the coordinates of the input. The touch driver 400 may be formed as an integrated circuit.

[0073] Figure 2 is a cross-sectional view of a display device 10 according to an embodiment.

[0074] Reference Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0075] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the present disclosure is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0076] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 with the data line, and a lead connecting the display driver 200 with the pad unit. Each of the plurality of thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0077] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, gate lines, data lines, and power lines of the pixels of the thin film transistor layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The leads of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0078] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements each including a pixel electrode, a light emitting layer, and a common electrode sequentially stacked to emit light, and a pixel defining layer defining a pixel. The light emitting element of the light emitting element layer EML may be disposed in the display area DA.

[0079] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a predetermined voltage through the thin film transistor of the thin film transistor layer TFTL and the common electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transport layer, and electrons may move to the organic light-emitting layer through the electron transport layer. Then, the holes and electrons may recombine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode, and the common electrode may be a cathode, but the present disclosure is not limited thereto.

[0080] For another example, each of the plurality of light emitting elements may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0081] The encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer to encapsulate the light emitting element layer EML.

[0082] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing the touch of a user in a capacitive manner, and a touch line connecting the touch electrodes with the touch driver 400. For example, the touch sensing unit TSU may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner.

[0083] For another example, the touch sensing unit TSU may be provided on a separate substrate disposed on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be an encapsulation substrate encapsulating the display unit DU.

[0084] The touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor area overlapping the display area DA. The touch lines of the touch sensing unit TSU may be disposed in a touch peripheral area overlapping the non-display area NDA.

[0085] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters respectively disposed in a plurality of regions corresponding to the plurality of emission regions. Each of the plurality of color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb a portion of light from outside the display device 10, thereby reducing reflected light caused by external light. Therefore, the color filter layer CFL can prevent color distortion caused by reflection of external light.

[0086] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively reduced.

[0087] The sub-region SBA of the display panel 100 may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, curled, etc. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (Z-axis direction). The sub-region SBA may include a display driver 200 and a pad unit electrically connected to the circuit board 300.

[0088] The display device 10 may include a bending protection layer BPL protecting the sub-area SBA. The bending protection layer BPL may be disposed on the transistor layer TFTL of the bent sub-area SBA. The bending protection layer BPL may protect the transistor layer TFTL of the bent sub-area SBA and minimize the tension of the sub-area SBA.

[0089] Figure 3 is a display device 10 according to an embodiment (for example, see Figure 1 ) is a plan view of the display unit DU.

[0090] Reference Figure 3 , the display unit DU may include a display area DA and a non-display area NDA.

[0091] The display area DA is an area for displaying an image and may be defined as a central area of ​​the display panel 100. The display area DA may include a plurality of pixels SP, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL. Each of the plurality of pixels SP may be defined as a minimum unit emitting light.

[0092] The gate lines GL may supply gate signals received from the gate driver 210 to the pixels SP. The gate lines GL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction crossing the X-axis direction.

[0093] The data lines DL may supply data voltages received from the display driver 200 to the pixels SP. The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0094] The power lines VL may supply a power voltage received from the display driver 200 to the pixels SP. Here, the power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, a bias voltage, and a low potential voltage. The power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0095] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 210, a fan-out line FOL, and a gate control line GCL. The gate driver 210 may generate a plurality of gate signals based on a gate control signal and sequentially supply the gate signals to the gate lines GL according to a set order.

[0096] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the data line DL.

[0097] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210.

[0098] The sub-area SBA may include a display driver area in which the display driver 200 is disposed, a display pad area DPA, and first and second touch pad areas TPA1 and TPA2.

[0099] The display driver 200 may output a signal and a voltage for driving the display panel 100 to the fan-out line FOL. The display driver 200 may supply a data voltage to the data line DL through the fan-out line FOL. The data voltage may be supplied to the pixel SP and may determine the brightness of the pixel SP. The display driver 200 may supply a gate control signal to the gate driver 210 through the gate control line GCL.

[0100] The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at the edge of the sub-area SBA. The pad units in the display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 (for example, see FIG. 1 ) using a low-resistance, high-reliability material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP). Figure 1 ).

[0101] The display pad area DPA may include a plurality of display pad units DP. The display pad units DP may be electrically connected to a graphics system through the circuit board 300. The display pad units DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0102] The first touch pad area TPA1 may be disposed at one side of the display pad area DPA and may include a plurality of first touch pad units TP1. The first touch pad unit TP1 may be electrically connected to a touch driver 400 (eg, see FIG. 4 ) disposed on the circuit board 300. Figure 1 ). The first touch pad unit TP1 may supply a touch driving signal to a plurality of driving electrodes through a plurality of driving lines, respectively.

[0103] The second touch pad area TPA2 may be disposed at the other side of the display pad area DPA, and may include a plurality of second touch pad units TP2. The second touch pad unit TP2 may be electrically connected to a touch driver 400 disposed on the circuit board 300. The touch driver 400 may receive a touch sensing signal through a plurality of sensing lines connected to the second touch pad unit TP2, and sense a change in mutual capacitance between the driving electrode and the sensing electrode.

[0104] Figure 4 is a cross-sectional view showing a pixel of the display device 10 according to the embodiment. Figure 5 yes Figure 4 An enlarged view of area A1.

[0105] Reference Figure 4 and Figure 5 And combined with Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0106] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the present disclosure is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0107] The thin film transistor layer TFTL may include a first buffer layer BF1, a light blocking layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0108] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked.

[0109] The light blocking layer BML may be disposed on the first buffer layer BF1. For example, each of the plurality of light blocking layers BML may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. For another example, each of the plurality of light blocking layers BML may be an organic layer including a black pigment.

[0110] The second buffer layer BF2 may be disposed on the first buffer layer BF1 and the light blocking layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked.

[0111] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of the pixel. For example, each of the plurality of thin film transistors TFT may be a driving transistor or a switching transistor of the pixel circuit. Each of the plurality of thin film transistors TFT may include a semiconductor region ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0112] The semiconductor region ACT, the source electrode SE, and the drain electrode DE may be disposed on the second buffer layer BF2. The semiconductor region ACT, the source electrode SE, and the drain electrode DE may overlap the light blocking layer BML in the thickness direction (Z-axis direction). The semiconductor region ACT may overlap the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulating layer GI. The source electrode SE and the drain electrode DE may be formed by making the material of the semiconductor region ACT conductive.

[0113] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor region ACT with the gate insulating layer GI interposed therebetween.

[0114] A gate insulating layer GI may be disposed on the semiconductor region ACT, the source electrode SE, the drain electrode DE, and the second buffer layer BF2. The gate insulating layer GI may insulate the semiconductor region ACT from the gate electrode GE.

[0115] A first interlayer insulating layer ILD1 may be disposed on the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may insulate the gate electrode GE from the capacitor electrode CPE.

[0116] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1 , and may overlap the gate electrode GE in a thickness direction, and the capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0117] The second interlayer insulating layer ILD2 may be disposed on the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may insulate the capacitor electrode CPE from the first connection electrode CNE1.

[0118] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be formed in a contact hole provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0119] The first passivation layer PAS1 may be disposed on the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may insulate the first connection electrode CNE1 from the second connection electrode CNE2.

[0120] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first pixel electrode AE1 of the first light emitting element ED1. The second connection electrode CNE2 may be formed in a contact hole provided in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0121] The second passivation layer PAS2 may be disposed on the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may insulate the second connection electrode CNE2 from the first pixel electrode AE1.

[0122] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first to third light emitting elements ED1 to ED3, a residual pattern RP, a first insulating layer IL1, an etching control layer EST, a capping layer CAP, a conductive layer MTL, a bank BNK, first to third organic patterns ELP1 to ELP3, first to third electrode patterns CEP1 to CEP3, first to third capping patterns CLP1 to CLP3, and first to third inorganic layers TL1 to TL3.

[0123] The display device 10 may include a plurality of pixels arranged along a plurality of rows and columns in the display area DA. The plurality of pixels may respectively include first to third emission areas EA1 to EA3 defined by the bank BNK or the pixel defining layer, and the plurality of pixels may emit light having a predetermined peak wavelength through the first to third emission areas EA1 to EA3. Each of the first to third emission areas EA1 to EA3 may be an area through which light generated by a light emitting element of the display device 10 is emitted to the outside of the display device 10.

[0124] Each of the first emission area EA1 to the third emission area EA3 may emit light having a predetermined peak wavelength to the outside of the display device 10. The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. For example, the light of the first color may be red light having a peak wavelength of about 610nm to about 650nm, the light of the second color may be green light having a peak wavelength of about 510nm to about 550nm, and the light of the third color may be blue light having a peak wavelength of about 440nm to about 480nm. However, the present disclosure is not limited thereto.

[0125] For example, the area of ​​the third emission area EA3 may be greater than the area of ​​the first emission area EA1, and the area of ​​the first emission area EA1 may be greater than the area of ​​the second emission area EA2. However, the present disclosure is not limited thereto. For another example, the area of ​​the first emission area EA1, the area of ​​the second emission area EA2, and the area of ​​the third emission area EA3 may be substantially the same.

[0126] The first light emitting element ED1 may be disposed on the thin film transistor layer TFTL in the first emission area EA1. The first light emitting element ED1 may include a first pixel electrode AE1, a first light emitting layer EL1, and a first common electrode CE1. The second light emitting element ED2 may be disposed on the thin film transistor layer TFTL in the second emission area EA2. The second light emitting element ED2 may include a second pixel electrode AE2, a second light emitting layer EL2, and a second common electrode CE2. The third light emitting element ED3 may be disposed on the thin film transistor layer TFTL in the third emission area EA3. The third light emitting element ED3 may include a third pixel electrode AE3, a third light emitting layer EL3, and a third common electrode CE3.

[0127] The first pixel electrode AE1 to the third pixel electrode AE3 may be disposed on the second passivation layer PAS2. Each of the first pixel electrode AE1 to the third pixel electrode AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. The first pixel electrode AE1 to the third pixel electrode AE3 may be insulated from each other by the first insulating layer IL1. For example, each of the first pixel electrode AE1 to the third pixel electrode AE3 may include at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni) and lanthanum (La). For another example, each of the first pixel electrode AE1 to the third pixel electrode AE3 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO) or indium tin zinc oxide (ITZO). For another example, each of the first pixel electrode AE1 to the third pixel electrode AE3 may have a stacked structure of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0128] The residual pattern RP may be disposed on an edge of each of the first to third pixel electrodes AE1 to AE3. Due to the residual pattern RP, the first insulating layer IL1 may not directly contact an upper surface of each of the first to third pixel electrodes AE1 to AE3. In a process of manufacturing the display device 10, the residual pattern RP may be formed by removing the sacrificial layer SFL (see FIG. 1 ) on each of the first to third pixel electrodes AE1 to AE3. Fig.14 ) is formed.

[0129] The first insulating layer IL1 may be disposed on the second passivation layer PAS2 and the remaining pattern RP. The first insulating layer IL1 may be disposed on the edges of the first pixel electrode AE1 to the third pixel electrode AE3 and the remaining pattern RP, and may be patterned to partially expose the upper surface of the first pixel electrode AE1 to the upper surface of the third pixel electrode AE3 in the process of forming the first insulating layer IL1. For example, the first insulating layer IL1 may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include (but is not limited to) at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0130] The etching control layer EST may be disposed on the first insulating layer IL1. The etching control layer EST may be used as an etching stopper. The etching control layer EST may protect the first to third pixel electrodes AE1 to AE3 during a process of etching the bank BNK and the conductive layer MTL. Alternatively, the etching control layer EST may be omitted.

[0131] The first to third light-emitting layers EL1 to EL3 may be organic light-emitting layers made of organic materials, and may be formed on the first to third pixel electrodes AE1 to AE3, respectively, through a deposition process. For example, in the deposition process of the first to third light-emitting layers EL1 to EL3, the organic material may be deposited in a direction inclined from the upper surface of the substrate SUB.

[0132] The first light-emitting layer EL1 may be directly disposed on the first pixel electrode AE1 in the first emission area EA1. A portion of the first light-emitting layer EL1 may fill the space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another portion of the first light-emitting layer EL1 may cover the upper surface of the etching control layer EST and the side surfaces of the first insulating layer IL1 and the etching control layer EST. The second light-emitting layer EL2 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2. A portion of the second light-emitting layer EL2 may fill the space surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1, and another portion of the second light-emitting layer EL2 may cover the upper surface of the etching control layer EST and the side surfaces of the first insulating layer IL1 and the etching control layer EST. The third light-emitting layer EL3 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3. A portion of the third light-emitting layer EL3 may fill the space surrounded by the third pixel electrode AE3, the residual pattern RP and the first insulating layer IL1, and another portion of the third light-emitting layer EL3 may cover the upper surface of the etching control layer EST and the side surfaces of the first insulating layer IL1 and the etching control layer EST.

[0133] The first common electrode CE1 may be disposed on the first light emitting layer EL1, the second common electrode CE2 may be disposed on the second light emitting layer EL2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3. The first to third common electrodes CE1 to CE3 may include a transparent conductive material and transmit light generated from the first to third light emitting layers EL1 to EL3, respectively. Each of the first to third common electrodes CE1 to CE3 may contact a side surface of the conductive layer MTL and an upper surface of the conductive layer MTL. The first to third common electrodes CE1 to CE3 may be electrically connected through the conductive layer MTL. For example, the first common electrode CE1 may receive a common voltage, a cathode voltage, or a low potential voltage.

[0134] The first pixel electrode AE1 may receive a voltage corresponding to the data voltage from the thin film transistor TFT, and the first common electrode CE1 may receive a common voltage, a cathode voltage, or a low potential voltage. In this case, since a potential difference is formed between the first pixel electrode AE1 and the first common electrode CE1, holes may move to the first light emitting layer EL1 through the hole transport layer, and electrons may move to the first light emitting layer EL1 through the electron transport layer. Therefore, the first light emitting layer EL1 may emit light.

[0135] The capping layer CAP may be disposed on the first to third common electrodes CE1 to CE3 in the first to third emission regions EA1 to EA3. The capping layer CAP may include an inorganic insulating material and may cover the first to third light emitting elements ED1 to ED3. The capping layer CAP may prevent the first to third light emitting elements ED1 to ED3 from being damaged by external air. For example, the capping layer CAP may include, but is not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0136] The conductive layer MTL may be disposed on the etching control layer EST to overlap with the bank BNK. In a plan view, the conductive layer MTL may surround the first emission area EA1 to the third emission area EA3. The conductive layer MTL may include a metal material having high electrical conductivity. For example, the conductive layer MTL may include (but is not limited to) aluminum (Al). The first common electrode CE1 to the third common electrode CE3 may be electrically connected to the conductive layer MTL.

[0137] The bank BNK may be disposed on the conductive layer MTL to define the first to third emission areas EA1 to EA3. In a plan view, the bank BNK may surround the first to third emission areas EA1 to EA3. The bank BNK may include first to fourth banks BNK1 to BNK4.

[0138] The first bank BNK1 may be disposed on the conductive layer MTL, the second bank BNK2 may be disposed on the first bank BNK1, the third bank BNK3 may be disposed on the second bank BNK2, and the fourth bank BNK4 may be disposed on the third bank BNK3. The side surface of the first bank BNK1 may be recessed inward from the side surface of the second bank BNK2 to the side surface of the fourth bank BNK4. Since the side surface of the second bank BNK2 protrudes from the side surface of the first bank BNK1 toward the first emission area EA1, the second bank BNK2 may include a protruding tip. Therefore, an undercut structure may be formed under each tip of the second bank BNK2. The thickness of the first bank BNK1 may be greater than the sum of the thickness of the second bank BNK2 to the thickness of the fourth bank BNK4. The thickness of the third bank BNK3 may be greater than the thickness of each of the second bank BNK2 and the fourth bank BNK4.

[0139] The first bank BNK1 and the second bank BNK2 may include different metal materials. The etching rate of the first bank BNK1 and the etching rate of the second bank BNK2 may be different from each other. For example, in a wet etching process, the etching rate of the first bank BNK1 may be higher than the etching rate of the second bank BNK2, and in the process of forming the first emission area EA1 to the third emission area EA3, the first bank BNK1 may be etched more than the second bank BNK2. Therefore, the profile of the first bank BNK1 and the profile of the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK2. The first bank BNK1 may include a metal material having high electrical conductivity, and the second bank BNK2 may include a material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0140] The third bank BNK3 may include an inorganic insulating material. The third bank BNK3 may include (but not limited to) at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon. The fourth bank BNK4 may include a metal material. The fourth bank BNK4 may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0141] Since the display device 10 includes a third bank BNK3 including an inorganic insulating material and a fourth bank BNK4 including a metal material, the contact area between each of the first inorganic layer TL1 to the third inorganic layer TL3 and the bank BNK can be increased. It is difficult to increase the horizontal area of ​​the bank BNK to ensure the contact area between each of the first inorganic layer TL1 to the third inorganic layer TL3 and the bank BNK. By additionally forming the third bank BNK3 and the fourth bank BNK4 on the second bank BNK2, the contact area between each of the first inorganic layer TL1 to the third inorganic layer TL3 and the bank BNK can be increased, thereby effectively blocking the moisture penetration path. As a result, the reliability of the first light-emitting element ED1 to the third light-emitting element ED3 can be improved. In addition, when the third bank BNK3 and the first inorganic layer TL1 to the third inorganic layer TL3 include the same inorganic insulating material, the encapsulation effect of the display device 10 can be maximized.

[0142] The bank BNK may form the first emission area EA1 to the third emission area EA3 through a mask process, and the first emission layer EL1 to the third emission layer EL3 may be formed in the first emission area EA1 to the third emission area EA3, respectively. When the mask process is performed, a structure for supporting the mask may be required, and an excessively wide non-display area NDA may be required to control the dispersion of the mask process. Therefore, if the mask process is minimized, the structure for supporting the mask can be omitted, and the area of ​​the non-display area NDA for dispersion control can be minimized.

[0143] Each of the first to third light emitting elements ED1 to ED3 may be formed by a deposition process and an etching process instead of a mask process. Since the first bank BNK1 and the second bank BNK2 include different metal materials, each inner wall of the bank BNK may have a tip structure. In the display device 10, different layers may be formed separately in the first to third emission areas EA1 to EA3 by a deposition process. For example, the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited using the same organic material in a deposition process without a mask, and may be disconnected due to a tip formed on the inner wall of the bank BNK. The first light emitting layer EL1 may be disposed in the first emission area EA1, and the first organic pattern ELP1 may be disposed on the bank BNK disposed adjacent to the first emission area EA1.

[0144] The organic material for forming the first light-emitting layer EL1 may be deposited on the entire surface of the display device 10, and the organic material of the first light-emitting layer EL1 deposited in the second emission area EA2 and the third emission area EA3 may be removed. The organic material for forming the second light-emitting layer EL2 may be deposited on the entire surface of the display device 10, and the organic material of the second light-emitting layer EL2 deposited in the first emission area EA1 and the third emission area EA3 may be removed. The organic material for forming the third light-emitting layer EL3 may be deposited on the entire surface of the display device 10, and the organic material of the third light-emitting layer EL3 deposited in the first emission area EA1 and the second emission area EA2 may be removed. Therefore, in the display device 10, different organic materials can be formed in the first emission area EA1 to the third emission area EA3 by a deposition process and an etching process (without using a mask process). The display device 10 can reduce manufacturing costs by omitting unnecessary processes, and can minimize the area of ​​the non-display area NDA.

[0145] The first organic pattern ELP1 may include the same organic material as the first light emitting layer EL1. The first organic pattern ELP1 may be disposed on the fourth bank BNK4 disposed adjacent to the first emission region EA1. The first light emitting layer EL1 and the first organic pattern ELP1 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. Therefore, the first organic pattern ELP1 may be disposed on the fourth bank BNK4 in a region disposed adjacent to the first emission region EA1.

[0146] The first electrode pattern CEP1 may include the same metal material as the first common electrode CE1, and the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1. The first common electrode CE1 and the first electrode pattern CEP1 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. Therefore, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in a region disposed adjacent to the first emission area EA1.

[0147] The first cladding pattern CLP1 may include the same inorganic material as the cladding layer CAP, and the first cladding pattern CLP1 may be disposed on the first electrode pattern CEP1. The cladding layer CAP and the first cladding pattern CLP1 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. Therefore, the first cladding pattern CLP1 may be disposed on the first electrode pattern CEP1 in a region disposed adjacent to the first emission area EA1.

[0148] The first inorganic layer TL1 may be disposed on the capping layer CAP and the first capping pattern CLP1 of the first emission area EA1. The first inorganic layer TL1 may cover the upper surface of the capping layer CAP in the first emission area EA1. The first inorganic layer TL1 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3 and the side surface of the fourth bank BNK4, the side surface of the first organic pattern ELP1, the side surface of the first electrode pattern CEP1, and the upper surface and the side surface of the first capping pattern CLP1. The first inorganic layer TL1 may include an inorganic material to prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include (but is not limited to) at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0149] The second organic pattern ELP2 may include the same organic material as the second light emitting layer EL2. The second organic pattern ELP2 may be disposed on a fourth bank BNK4 disposed adjacent to the second emission region EA2. The second light emitting layer EL2 and the second organic pattern ELP2 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. Therefore, the second organic pattern ELP2 may be disposed on the fourth bank BNK4 in an area disposed adjacent to the second emission region EA2.

[0150] The second electrode pattern CEP2 may include the same metal material as the second common electrode CE2, and the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2. The second common electrode CE2 and the second electrode pattern CEP2 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. Therefore, the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in an area disposed adjacent to the second emission area EA2.

[0151] The second cladding pattern CLP2 may include the same inorganic material as the cladding layer CAP, and the second cladding pattern CLP2 may be disposed on the second electrode pattern CEP2. The cladding layer CAP and the second cladding pattern CLP2 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. Therefore, the second cladding pattern CLP2 may be disposed on the second electrode pattern CEP2 in a region disposed adjacent to the second emission area EA2.

[0152] The second inorganic layer TL2 may be disposed on the capping layer CAP and the second capping pattern CLP2 of the second emission area EA2. The second inorganic layer TL2 may cover the upper surface of the capping layer CAP in the second emission area EA2. The second inorganic layer TL2 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3 and the side surface of the fourth bank BNK4, the side surface of the second organic pattern ELP2, the side surface of the second electrode pattern CEP2, and the upper surface and the side surface of the second capping pattern CLP2. The second inorganic layer TL2 may include an inorganic material to prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. For example, the second inorganic layer TL2 may be made of at least one of the multiple materials listed in the description of the first inorganic layer TL1.

[0153] The third organic pattern ELP3 may include the same organic material as the third light emitting layer EL3. The third organic pattern ELP3 may be disposed on a fourth bank BNK4 disposed adjacent to the third emission region EA3. The third light emitting layer EL3 and the third organic pattern ELP3 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. Therefore, the third organic pattern ELP3 may be disposed on the fourth bank BNK4 in an area disposed adjacent to the third emission region EA3.

[0154] The third electrode pattern CEP3 may include the same metal material as the third common electrode CE3, and the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3. The third common electrode CE3 and the third electrode pattern CEP3 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. Therefore, the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 in an area disposed adjacent to the third emission area EA3.

[0155] The third cladding pattern CLP3 may include the same inorganic material as the cladding layer CAP, and the third cladding pattern CLP3 may be disposed on the third electrode pattern CEP3. The cladding layer CAP and the third cladding pattern CLP3 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. Therefore, the third cladding pattern CLP3 may be disposed on the third electrode pattern CEP3 in an area disposed adjacent to the third emission area EA3.

[0156] The third inorganic layer TL3 may be disposed on the capping layer CAP and the third capping pattern CLP3 of the third emission area EA3. The third inorganic layer TL3 may cover the upper surface of the capping layer CAP in the third emission area EA3. The third inorganic layer TL3 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3 and the side surface of the fourth bank BNK4, the side surface of the third organic pattern ELP3, the side surface of the third electrode pattern CEP3, and the upper surface and the side surface of the third capping pattern CLP3. The third inorganic layer TL3 may include an inorganic material to prevent oxygen or moisture from penetrating into the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. For example, the third inorganic layer TL3 may be made of at least one of the multiple materials listed in the description of the first inorganic layer TL1.

[0157] The encapsulation layer TFEL may be disposed on the first to third inorganic layers TL1 to TL3 to cover the light emitting element layer EML. The encapsulation layer TFEL may include first to third encapsulation layers TFE1 to TFE3.

[0158] The first encapsulation layer TFE1 may be disposed on the first to third inorganic layers TL1 to TL3. The first encapsulation layer TFE1 may include an inorganic material to prevent oxygen or moisture from penetrating into the light emitting element layer EML. For example, the first encapsulation layer TFE1 may include, but is not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0159] The second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1 to flatten the top of the light emitting element layer EML. The second encapsulation layer TFE2 may include an organic material to protect the light emitting element layer EML from foreign matter such as dust. For example, the second encapsulation layer TFE2 may include an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The second encapsulation layer TFE2 may be formed by curing a monomer or coating a polymer.

[0160] The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. The third encapsulation layer TFE3 may include an inorganic material to prevent oxygen or moisture from penetrating into the light emitting element layer EML. For example, the third encapsulation layer TFE3 may be made of at least one of the various materials exemplified in the description of the first encapsulation layer TFE1.

[0161] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a third buffer layer BF3, a bridge electrode BRG, a second insulating layer IL2, a touch electrode TE, and a third insulating layer IL3.

[0162] The third buffer layer BF3 may be disposed on the encapsulation layer TFEL. The third buffer layer BF3 may have insulating and optical functions. The third buffer layer BF3 may include at least one inorganic layer. Optionally, the third buffer layer BF3 may be omitted.

[0163] The bridge electrode BRG may be disposed on the third buffer layer BF3. The bridge electrode BRG may be disposed on a different layer from the touch electrodes TE, and may electrically connect adjacent touch electrodes TE.

[0164] The second insulating layer IL2 may be disposed on the bridge electrode BRG and the third buffer layer BF3. The second insulating layer IL2 may have insulating and optical functions. For example, the second insulating layer IL2 may include (but is not limited to) at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0165] The touch electrode TE may be disposed on the second insulating layer IL2. The touch electrode TE may include a drive electrode and a sensing electrode, and senses a change in mutual capacitance between the drive electrode and the sensing electrode. The touch electrode TE may not overlap with the first emission area EA1 to the third emission area EA3. Each of the plurality of touch electrodes TE may be a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or indium tin oxide (ITO), or may have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and indium tin oxide (ITO / APC / ITO).

[0166] The third insulating layer IL3 may be disposed on the touch electrode TE and the second insulating layer IL2. The third insulating layer IL3 may have insulating and optical functions. The third insulating layer IL3 may be made of at least one of the various materials exemplified in the description of the second insulating layer IL2.

[0167] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a light blocking member BM, first to third color filters CF1 to CF3, and a planarization layer OC.

[0168] The light blocking member BM may be disposed on the third insulating layer IL3 to surround the first optical region OPT1, the second optical region OPT2, and the third optical region OPT3. The light blocking member BM may overlap the touch electrode TE. The light blocking member BM may include a light absorbing material to prevent reflection of light. For example, the light blocking member BM may include an inorganic black pigment, an organic black pigment, or an organic blue pigment. The inorganic black pigment may include carbon black or a metal oxide such as titanium black, the organic black pigment may include at least one of lactam black, perylene black, and aniline black, and the organic blue pigment may be CI pigment blue. However, the present disclosure is not limited thereto. The light blocking member BM may prevent color mixing by preventing the intrusion of visible light between the first emission region EA1 to the third emission region EA3, thereby improving the color gamut of the display device 10.

[0169] First to third color filters CF1 to CF3 may be disposed on the third insulating layer IL3 to correspond to the first to third emission areas EA1 to EA3, respectively.

[0170] The first color filter CF1 may be disposed on the third insulating layer IL3 in the first emission region EA1. In a plan view, the first color filter CF1 may be surrounded by the light blocking member BM. The edge of the first color filter CF1 may partially cover the upper surface of the light blocking member BM, but the present disclosure is not limited thereto. The first color filter CF1 may selectively transmit light of a first color (e.g., red light) and block or absorb light of a second color (e.g., green light) and light of a third color (e.g., blue light). For example, the first color filter CF1 may be a red color filter and may include a red colorant.

[0171] The second color filter CF2 may be disposed on the third insulating layer IL3 in the second emission region EA2. In a plan view, the second color filter CF2 may be surrounded by the light blocking member BM. The edge of the second color filter CF2 may partially cover the upper surface of the light blocking member BM, but the present disclosure is not limited thereto. The second color filter CF2 may selectively transmit light of a second color (e.g., green light) and block or absorb light of a first color (e.g., red light) and light of a third color (e.g., blue light). For example, the second color filter CF2 may be a green color filter and may include a green colorant.

[0172] The third color filter CF3 may be disposed on the third insulating layer IL3 in the third emission area EA3. In a plan view, the third color filter CF3 may be surrounded by the light blocking member BM. The edge of the third color filter CF3 may partially cover the upper surface of the light blocking member BM, but the present disclosure is not limited thereto. The third color filter CF3 may selectively transmit light of a third color (e.g., blue light) and block or absorb light of a first color (e.g., red light) and light of a second color (e.g., green light). For example, the third color filter CF3 may be a blue color filter and may include a blue colorant.

[0173] The first to third color filters CF1 to CF3 may absorb a portion of light from outside the display device 10, thereby reducing reflected light caused by the external light. Therefore, the first to third color filters CF1 to CF3 can prevent color distortion caused by reflection of the external light.

[0174] A planarization layer OC may be disposed on the light blocking member BM and the first to third color filters CF1 to CF3. The planarization layer OC may planarize a top surface of the color filter layer CFL. For example, the planarization layer OC may include an organic insulating material.

[0175] Figure 6 is a cross-sectional view showing a pixel of the display device 10 according to the embodiment. Figure 7 yes Figure 6 An enlarged view of area A2. Figure 6 and Figure 7The display device 10 and Figure 4 and Figure 5 The display device 10 of FIG. 1 is different in the configuration of the bank BNK. The same elements as those described above will be briefly described or not described.

[0176] Reference Figure 6 and Figure 7 And combined with Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0177] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first to third light emitting elements ED1 to ED3, a residual pattern RP, a first insulating layer IL1, an etching control layer EST, a capping layer CAP, a conductive layer MTL, a bank BNK, first to third organic patterns ELP1 to ELP3, first to third electrode patterns CEP1 to CEP3, first to third capping patterns CLP1 to CLP3, and first to third inorganic layers TL1 to TL3.

[0178] The bank BNK may be disposed on the conductive layer MTL to define the first to third emission areas EA1 to EA3. In a plan view, the bank BNK may surround the first to third emission areas EA1 to EA3. The bank BNK may include first to third banks BNK1 to BNK3.

[0179] The first bank BNK1 may be disposed on the conductive layer MTL, the second bank BNK2 may be disposed on the first bank BNK1, and the third bank BNK3 may be disposed on the second bank BNK2. A side surface of the first bank BNK1 may be recessed inward from a side surface of the second bank BNK2 and a side surface of the third bank BNK3. Since a side surface of the second bank BNK2 protrudes from a side surface of the first bank BNK1 toward the first emission region EA1, the second bank BNK2 may include a protruding tip. Therefore, an undercut structure may be formed under each tip of the second bank BNK2. The thickness of the first bank BNK1 may be greater than the sum of the thickness of the second bank BNK2 and the thickness of the third bank BNK3, and the thickness of the third bank BNK3 may be greater than the thickness of the second bank BNK2.

[0180] The first bank BNK1 and the second bank BNK2 may include different metal materials. The etching rate of the first bank BNK1 and the etching rate of the second bank BNK2 may be different from each other. For example, in a wet etching process, the etching rate of the first bank BNK1 may be higher than the etching rate of the second bank BNK2, and in the process of forming the first emission area EA1 to the third emission area EA3, the first bank BNK1 may be etched more than the second bank BNK2. Therefore, the profile of the first bank BNK1 and the profile of the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK2. The first bank BNK1 may include a metal material having high electrical conductivity, and the second bank BNK2 may include a material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0181] For example, the third bank BNK3 may include an inorganic insulating material. The third bank BNK3 may include, but is not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0182] For another example, the third bank BNK3 may include a metal material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu).

[0183] Since the display device 10 includes the third bank BNK3 including an inorganic insulating material or a metal material, the encapsulation area of ​​each of the first inorganic layer TL1 to the third inorganic layer TL3 can be ensured. For example, the horizontal area of ​​the bank BNK can be limited to ensure the plane area of ​​each of the first emission area EA1 to the third emission area EA3. Therefore, the third bank BNK3 can increase the thickness of the bank BNK, and each of the first inorganic layer TL1 to the third inorganic layer TL3 can ensure the encapsulation area of ​​the bank BNK, thereby blocking the moisture penetration path. As a result, the reliability of the first light-emitting element ED1 to the third light-emitting element ED3 can be improved. For example, when the third bank BNK3 and the first inorganic layer TL1 to the third inorganic layer TL3 include the same inorganic insulating material, the encapsulation effect of the display device 10 can be maximized.

[0184] Figure 8 is a cross-sectional view showing a pixel of the display device 10 according to the embodiment. Fig. 9 yes Figure 8 An enlarged view of area A3. Figure 8 and Fig. 9 The display device 10 and Figure 4 and Figure 5The display device 10 of FIG. 1 is different in the configuration of the bank BNK. The same elements as those described above will be briefly described or not described.

[0185] Reference Figure 8 and Fig. 9 And combined with Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0186] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first to third light emitting elements ED1 to ED3, a residual pattern RP, a first insulating layer IL1, an etching control layer EST, a capping layer CAP, a conductive layer MTL, a bank BNK, first to third organic patterns ELP1 to ELP3, first to third electrode patterns CEP1 to CEP3, first to third capping patterns CLP1 to CLP3, and first to third inorganic layers TL1 to TL3.

[0187] The bank BNK may be disposed on the conductive layer MTL to define the first to third emission areas EA1 to EA3. In a plan view, the bank BNK may surround the first to third emission areas EA1 to EA3. The bank BNK may include first to fourth banks BNK1 to BNK4.

[0188] The first bank BNK1 may be disposed on the conductive layer MTL, the second bank BNK2 may be disposed on the first bank BNK1, the third bank BNK3 may be disposed on the second bank BNK2, and the fourth bank BNK4 may be disposed on the third bank BNK3. The side surface of the first bank BNK1 may be recessed inward from the side surface of the second bank BNK2 to the side surface of the fourth bank BNK4. Since the side surface of the second bank BNK2 protrudes from the side surface of the first bank BNK1 toward the first emission area EA1, the second bank BNK2 may include a protruding tip. Therefore, an undercut structure may be formed under each tip of the second bank BNK2. The thickness of the first bank BNK1 may be greater than the sum of the thickness of the second bank BNK2 to the thickness of the fourth bank BNK4. The thickness of each of the third bank BNK3 and the fourth bank BNK4 may be greater than the thickness of the second bank BNK2.

[0189] The first bank BNK1 and the second bank BNK2 may include different metal materials. The etching rate of the first bank BNK1 and the etching rate of the second bank BNK2 may be different from each other. For example, in a wet etching process, the etching rate of the first bank BNK1 may be higher than the etching rate of the second bank BNK2, and in the process of forming the first emission area EA1 to the third emission area EA3, the first bank BNK1 may be etched more than the second bank BNK2. Therefore, the profile of the first bank BNK1 and the profile of the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK2. The first bank BNK1 may include a metal material having high electrical conductivity, and the second bank BNK2 may include a material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0190] The third bank BNK3 may include an inorganic insulating material. The third bank BNK3 may include, but is not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0191] The fourth bank BNK4 may include an inorganic insulating material different from that of the third bank BNK3 . The fourth bank BNK4 may include a material different from that of the third bank BNK3 among silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0192] Since the display device 10 includes the third bank BNK3 and the fourth bank BNK4 including different inorganic insulating materials, the encapsulation area of ​​each of the first inorganic layer TL1 to the third inorganic layer TL3 can be ensured. For example, the horizontal area of ​​the bank BNK can be limited to ensure the plane area of ​​each of the first emission area EA1 to the third emission area EA3. Therefore, the third bank BNK3 and the fourth bank BNK4 can increase the thickness of the bank BNK, and each of the first inorganic layer TL1 to the third inorganic layer TL3 can ensure the encapsulation area of ​​the bank BNK, thereby blocking the moisture penetration path. As a result, the reliability of the first light-emitting element ED1 to the third light-emitting element ED3 can be improved. In addition, when at least one of the third bank BNK3 and the fourth bank BNK4 includes the same inorganic insulating material as the first inorganic layer TL1 to the third inorganic layer TL3, the encapsulation effect of the display device 10 can be maximized.

[0193] Fig.10 is a cross-sectional view showing a pixel of the display device 10 according to the embodiment. Fig.11 yes Fig.10 An enlarged view of area A4. Fig.10 and Fig.11 The display device 10 and Figure 4 and Figure 5The display device 10 of FIG. 1 is different in the configuration of the bank BNK. The same elements as those described above will be briefly described or not described.

[0194] Reference Fig.10 and Fig.11 And combined with Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0195] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first to third light emitting elements ED1 to ED3, a residual pattern RP, a first insulating layer IL1, an etching control layer EST, a capping layer CAP, a conductive layer MTL, a bank BNK, first to third organic patterns ELP1 to ELP3, first to third electrode patterns CEP1 to CEP3, first to third capping patterns CLP1 to CLP3, and first to third inorganic layers TL1 to TL3.

[0196] The bank BNK may be disposed on the conductive layer MTL to define the first to third emission areas EA1 to EA3. In a plan view, the bank BNK may surround the first to third emission areas EA1 to EA3. The bank BNK may include first to fourth banks BNK1 to BNK4.

[0197] The first bank BNK1 may be disposed on the conductive layer MTL, the second bank BNK2 may be disposed on the first bank BNK1, the third bank BNK3 may be disposed on the second bank BNK2, and the fourth bank BNK4 may be disposed on the third bank BNK3. A side surface of the first bank BNK1 may be recessed inward from a side surface of the second bank BNK2, and a side surface of the third bank BNK3 may be recessed inward from a side surface of the fourth bank BNK4. Since a side surface of the second bank BNK2 protrudes from a side surface of the first bank BNK1 and a side surface of the third bank BNK3 toward the first emission region EA1, the second bank BNK2 may include a protruding tip. Since a side surface of the fourth bank BNK4 protrudes from a side surface of the third bank BNK3 toward the first emission region EA1, the fourth bank BNK4 may include a protruding tip. Therefore, an undercut structure may be formed under each tip of each of the second bank BNK2 and the fourth bank BNK4. The thickness of the first bank BNK1 may be greater than the sum of the thickness of the second bank BNK2 to the thickness of the fourth bank BNK4. The thickness of the third bank BNK3 may be greater than the thickness of each of the second bank BNK2 and the fourth bank BNK4 .

[0198] The first bank BNK1 and the second bank BNK2 may include different metal materials. The third bank BNK3 and the fourth bank BNK4 may include different metal materials. The etching rate of the first bank BNK1 and the etching rate of the second bank BNK2 may be different from each other. The etching rate of the third bank BNK3 and the etching rate of the fourth bank BNK4 may be different from each other. For example, in a wet etching process, the etching rate of each of the first bank BNK1 and the third bank BNK3 may be higher than the etching rate of each of the second bank BNK2 and the fourth bank BNK4, and in the process of forming the first emission area EA1 to the third emission area EA3, each of the first bank BNK1 and the third bank BNK3 may be etched more than each of the second bank BNK2 and the fourth bank BNK4. Therefore, the profile of the first bank BNK1 to the profile of the fourth bank BNK4 may be determined by the difference in etching rates between the first bank BNK1 to the fourth bank BNK4. The first bank BNK1 and the third bank BNK3 may include a metal material having high conductivity, and the second bank BNK2 and the fourth bank BNK4 may include a material having low reflectivity. For example, the first bank BNK1 and the third bank BNK3 may include aluminum (Al), and the second bank BNK2 and the fourth bank BNK4 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0199] The first inorganic layer TL1 may be disposed on the capping layer CAP and the first capping pattern CLP1 of the first emission area EA1. The first inorganic layer TL1 may cover the upper surface of the capping layer CAP in the first emission area EA1. The first inorganic layer TL1 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3, the lower surface and the side surface of the tip of the fourth bank BNK4, the side surface of the first organic pattern ELP1, the side surface of the first electrode pattern CEP1, and the upper surface and the side surface of the first capping pattern CLP1.

[0200] The second inorganic layer TL2 may be disposed on the capping layer CAP and the second capping pattern CLP2 of the second emission area EA2. The second inorganic layer TL2 may cover the upper surface of the capping layer CAP in the second emission area EA2. The second inorganic layer TL2 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3, the lower surface and the side surface of the tip of the fourth bank BNK4, the side surface of the second organic pattern ELP2, the side surface of the second electrode pattern CEP2, and the upper surface and the side surface of the second capping pattern CLP2.

[0201] The third inorganic layer TL3 may be disposed on the capping layer CAP and the third capping pattern CLP3 of the third emission area EA3. The third inorganic layer TL3 may cover the upper surface of the capping layer CAP in the third emission area EA3. The third inorganic layer TL3 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3, the lower surface and the side surface of the tip of the fourth bank BNK4, the side surface of the third organic pattern ELP3, the side surface of the third electrode pattern CEP3, and the upper surface and the side surface of the third capping pattern CLP3.

[0202] Since the display device 10 includes the third bank BNK3 and the fourth bank BNK4 including different metal materials, it is possible to ensure the encapsulation area of ​​each of the first inorganic layer TL1 to the third inorganic layer TL3. For example, the horizontal area of ​​the bank BNK can be limited to ensure the plane area of ​​each of the first emission area EA1 to the third emission area EA3. Therefore, the third bank BNK3 and the fourth bank BNK4 can increase the thickness of the bank BNK, and each of the first inorganic layer TL1 to the third inorganic layer TL3 can ensure the encapsulation area of ​​the bank BNK, thereby blocking the moisture penetration path. As a result, the reliability of the first light-emitting element ED1 to the third light-emitting element ED3 can be improved.

[0203] Each of the first to third light emitting elements ED1 to ED3 may be formed by a deposition process and an etching process instead of a mask process. Since the first and third dams BNK1 and BNK3 include different metal materials from the second and fourth dams BNK2 and BNK4, each inner wall of the dam BNK may have a double tip structure. In the display device 10, different layers may be separately formed in the first to third emission areas EA1 to EA3 by a deposition process. For example, the island-shaped first light emitting layer EL1 may be deposited in the first emission area EA1 due to the tip formed around the first emission area EA1 in the process of depositing the organic material without using a mask, and the organic material disposed in the area other than the first emission area EA1 may be removed by an etching process.

[0204] In the display device 10 including the first to fourth banks BNK1 to BNK4 , the first to third light emitting elements ED1 to ED3 can be easily formed by a deposition process and an etching process using a dual tip structure, and moisture can be prevented from penetrating into the first to third light emitting elements ED1 to ED3 .

[0205] Fig.12 is a cross-sectional view showing a pixel of the display device 10 according to the embodiment. Fig.13 yes Fig.12 Magnified view of area A5. Fig.12 and Fig.13 The display device 10 and Figure 4 and Figure 5 The display device 10 of FIG. 1 is different in the configuration of the bank BNK. The same elements as those described above will be briefly described or not described.

[0206] Reference Fig.12 and Fig.13 And combined with Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0207] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first to third light emitting elements ED1 to ED3, a residual pattern RP, a first insulating layer IL1, an etching control layer EST, a capping layer CAP, a conductive layer MTL, a bank BNK, first to third organic patterns ELP1 to ELP3, first to third electrode patterns CEP1 to CEP3, first to third capping patterns CLP1 to CLP3, and first to third inorganic layers TL1 to TL3.

[0208] The bank BNK may be disposed on the conductive layer MTL to define the first to third emission areas EA1 to EA3. In a plan view, the bank BNK may surround the first to third emission areas EA1 to EA3. The bank BNK may include first to fifth banks BNK1 to BNK5.

[0209] The first bank BNK1 may be disposed on the conductive layer MTL, the second bank BNK2 may be disposed on the first bank BNK1, the third bank BNK3 may be disposed on the second bank BNK2, the fourth bank BNK4 may be disposed on the third bank BNK3, and the fifth bank BNK5 may be disposed on the fourth bank BNK4. A side surface of the first bank BNK1 may be recessed inward from a side surface of the second bank BNK2 and a side surface of the third bank BNK3, and a side surface of the fourth bank BNK4 may be recessed inward from a side surface of the fifth bank BNK5. Since a side surface of the second bank BNK2 protrudes from a side surface of the first bank BNK1 and a side surface of the fourth bank BNK4 toward the first emission region EA1, the second bank BNK2 may include a protruding tip. Since a side surface of the fifth bank BNK5 protrudes from a side surface of the fourth bank BNK4 toward the first emission region EA1, the fifth bank BNK5 may include a protruding tip. Therefore, an undercut structure may be formed under each tip of each of the second bank BNK2 and the fifth bank BNK5. The thickness of the first bank BNK1 may be greater than the thickness of each of the second to fifth banks BNK2 to BNK5 . The thickness of each of the third and fourth banks BNK3 and BNK4 may be greater than the thickness of each of the second and fifth banks BNK2 and BNK5 .

[0210] The first bank BNK1 and the second bank BNK2 may include different metal materials. The third bank BNK3 may include an inorganic insulating material. The third bank BNK3 may include (but not limited to) at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide and amorphous silicon. The fourth bank BNK4 and the fifth bank BNK5 may include different metal materials. The etching rate of the first bank BNK1 may be different from the etching rate of the second bank BNK2 and the etching rate of the third bank BNK3. The etching rate of the fourth bank BNK4 and the etching rate of the fifth bank BNK5 may be different from each other. For example, in a wet etching process, the etching rate of each of the first bank BNK1 and the fourth bank BNK4 may be higher than the etching rate of each of the second bank BNK2, the third bank BNK3 and the fifth bank BNK5, and in the process of forming the first emission area EA1 to the third emission area EA3, each of the first bank BNK1 and the fourth bank BNK4 may be etched more than each of the second bank BNK2, the third bank BNK3 and the fifth bank BNK5. Therefore, the profile of the first bank BNK1 to the profile of the fifth bank BNK5 can be determined by the difference in etching rate between the first bank BNK1 to the fifth bank BNK5. The first bank BNK1 and the fourth bank BNK4 may include a metal material having high conductivity, and the second bank BNK2 and the fifth bank BNK5 may include a material having low reflectivity. For example, the first bank BNK1 and the fourth bank BNK4 may include aluminum (Al), and the second bank BNK2 and the fifth bank BNK5 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0211] The first inorganic layer TL1 may be disposed on the capping layer CAP and the first capping pattern CLP1 of the first emission area EA1. The first inorganic layer TL1 may cover the upper surface of the capping layer CAP in the first emission area EA1. The first inorganic layer TL1 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3 and the side surface of the fourth bank BNK4, the lower surface and the side surface of the tip of the fifth bank BNK5, the side surface of the first organic pattern ELP1, the side surface of the first electrode pattern CEP1, and the upper surface and the side surface of the first capping pattern CLP1.

[0212] The second inorganic layer TL2 may be disposed on the capping layer CAP and the second capping pattern CLP2 of the second emission area EA2. The second inorganic layer TL2 may cover the upper surface of the capping layer CAP in the second emission area EA2. The second inorganic layer TL2 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3 and the side surface of the fourth bank BNK4, the lower surface and the side surface of the tip of the fifth bank BNK5, the side surface of the second organic pattern ELP2, the side surface of the second electrode pattern CEP2, and the upper surface and the side surface of the second capping pattern CLP2.

[0213] The third inorganic layer TL3 may be disposed on the capping layer CAP and the third capping pattern CLP3 of the third emission area EA3. The third inorganic layer TL3 may cover the upper surface of the capping layer CAP in the third emission area EA3. The third inorganic layer TL3 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3 and the side surface of the fourth bank BNK4, the lower surface and the side surface of the tip of the fifth bank BNK5, the side surface of the third organic pattern ELP3, the side surface of the third electrode pattern CEP3, and the upper surface and the side surface of the third capping pattern CLP3.

[0214] Since the display device 10 includes the third bank BNK3 including an inorganic insulating material, and the fourth bank BNK4 and the fifth bank BNK5 including different metal materials, it is possible to ensure the encapsulation area of ​​each of the first inorganic layer TL1 to the third inorganic layer TL3. For example, the horizontal area of ​​the bank BNK can be limited to ensure the plane area of ​​each of the first emission area EA1 to the third emission area EA3. Therefore, the third bank BNK3 to the fifth bank BNK5 can increase the thickness of the bank BNK, and each of the first inorganic layer TL1 to the third inorganic layer TL3 can ensure the encapsulation area of ​​the bank BNK, thereby blocking the moisture penetration path. As a result, the reliability of the first light-emitting element ED1 to the third light-emitting element ED3 can be improved.

[0215] Each of the first to third light emitting elements ED1 to ED3 may be formed by a deposition process and an etching process instead of a mask process. Since the first and fourth dams BNK1 and BNK4 include different metal materials from the second and fifth dams BNK2 and BNK5, each inner wall of the dam BNK may have a double tip structure. In the display device 10, different layers may be separately formed in the first to third emission areas EA1 to EA3 by a deposition process. For example, the island-shaped first light emitting layer EL1 may be deposited in the first emission area EA1 due to the tip formed to surround the first emission area EA1 in the process of depositing the organic material without using a mask, and the organic material disposed in the area other than the first emission area EA1 may be removed by an etching process.

[0216] In the display device 10 including the first to fifth banks BNK1 to BNK5, the first to third light emitting elements ED1 to ED3 can be easily formed by a deposition process and an etching process using a dual tip structure, and moisture can be prevented from penetrating into the first to third light emitting elements ED1 to ED3. Hereinafter, the first emission area EA1, the second emission area EA2, the third emission area EA3, the display device 10, and the bank BNK may refer to, for example, Figure 4 .

[0217] Figures 14 to 21 is a cross-sectional view illustrating a process of manufacturing the display device 10 according to the embodiment.

[0218] exist Fig.14 In the embodiment, the first pixel electrode AE1 to the third pixel electrode AE3 may be formed to be spaced apart from each other on the thin film transistor layer TFTL. Each of the first pixel electrode AE1 to the third pixel electrode AE3 may include at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and lanthanum (La). For another example, each of the first pixel electrode AE1 to the third pixel electrode AE3 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). For another example, each of the first pixel electrode AE1 to the third pixel electrode AE3 may have a stacked structure of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0219] A sacrificial layer SFL may be disposed on the first to third pixel electrodes AE1 to AE3. The sacrificial layer SFL may be disposed between the upper surfaces of the first to third pixel electrodes AE1 to AE3 and the first insulating layer IL1. The sacrificial layer SFL may include an oxide semiconductor. For example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium zinc oxide (IZO).

[0220] A first insulating layer IL1 may be disposed on the thin film transistor layer TFTL and the sacrificial layer SFL. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include, but is not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0221] An etching control layer EST may be disposed on the first insulating layer IL1. The etching control layer EST may be used as an etching stopper. Alternatively, the etching control layer EST may be omitted.

[0222] A conductive layer MTL may be disposed on the etching control layer EST. The conductive layer MTL may include a metal material having high electrical conductivity. For example, the conductive layer MTL may include (but is not limited to) aluminum (Al). In the case where the conductive layer MTL is disposed on the etching control layer EST, the etching control layer EST may have good etching selectivity for an etchant that etches the conductive layer MTL.

[0223] A first bank BNK1 may be disposed on the conductive layer MTL, a second bank BNK2 may be disposed on the first bank BNK1, a third bank BNK3 may be disposed on the second bank BNK2, and a fourth bank BNK4 may be disposed on the third bank BNK3. The thickness of the first bank BNK1 may be greater than the sum of the thickness of the second bank BNK2 to the thickness of the fourth bank BNK4, and the thickness of the third bank BNK3 may be greater than the thickness of each of the second bank BNK2 and the fourth bank BNK4. The first bank BNK1 may include a metal material having high electrical conductivity, and the second bank BNK2 may include a material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0224] The third bank BNK3 may include an inorganic insulating material. The third bank BNK3 may include (but not limited to) at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon. The fourth bank BNK4 may include a metal material. The fourth bank BNK4 may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0225] exist Fig.15In the embodiment, the fourth bank BNK4, the third bank BNK3, the second bank BNK2, the first bank BNK1 and the conductive layer MTL may be sequentially etched to form a plurality of holes. These holes may be provided in the regions corresponding to the first emission region EA1 to the third emission region EA3. The conductive layer MTL and the first bank BNK1 to the fourth bank BNK4 may be etched by performing at least one of a dry etching process and a wet etching process. The etching control layer EST may protect the first pixel electrode AE1 to the third pixel electrode AE3 in the process of etching the bank BNK and the conductive layer MTL. The first bank BNK1 and the second bank BNK2 may include different metal materials, and the etching rate of the first bank BNK1 and the etching rate of the second bank BNK2 may be different from each other. The etching rate of the first bank BNK1 may be higher than the etching rate of the second bank BNK2, and the first bank BNK1 may be etched more than the second bank BNK2. Therefore, the profile of the first bank BNK1 and the profile of the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK2. The second bank BNK2 may include a tip protruding from the first bank BNK1 toward the hole. A side surface of the first bank BNK1 may be recessed inward from a side surface of the second bank BNK2. An undercut structure may be formed under each tip of the second bank BNK2.

[0226] The etching control layer EST, the first insulating layer IL1, and the sacrificial layer SFL (see FIG. 1 ) may be etched by performing at least one of a dry etching process and a wet etching process. Fig.14 ) is etched. Since the etching control layer EST, the first insulating layer IL1, and the sacrificial layer SFL are etched, at least a portion of the upper surface of each of the first pixel electrode AE1 to the third pixel electrode AE3 may be exposed. In a plan view, the sacrificial layer SFL may be etched more than the first insulating layer IL1. When the sacrificial layer SFL is etched, the residual pattern RP may remain between the first insulating layer IL1 and the first pixel electrode AE1. Therefore, the side surface of the residual pattern RP may be recessed inward from the side surface of the first insulating layer IL1.

[0227] exist Fig.16 In the embodiment, the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1 in the first emission area EA1. A portion of the first light emitting layer EL1 may fill a space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another portion of the first light emitting layer EL1 may cover an upper surface of an edge of the etching control layer EST and a side surface of the first insulating layer IL1.

[0228] An organic material for forming the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited on the entire surface of the display device 10. The first light emitting layer EL1 and the first organic pattern ELP1 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. A portion of the first organic pattern ELP1 may be disposed on the fourth bank BNK4, another portion of the first organic pattern ELP1 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2, and another portion of the first organic pattern ELP1 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3.

[0229] A first common electrode CE1 may be disposed directly on the first light emitting layer EL1 in the first emission region EA1. The first common electrode CE1 may contact the side surface of the conductive layer MTL and the upper surface of the edge of the conductive layer MTL. The first common electrode CE1 may include a transparent conductive material and transmit light generated from the first light emitting layer EL1. Therefore, the first light emitting element ED1 may be disposed in a hole formed by the bank BNK and may emit light through the first emission region EA1.

[0230] A metal material for forming the first common electrode CE1 and the first electrode pattern CEP1 may be deposited on the entire surface of the display device 10. The first common electrode CE1 and the first electrode pattern CEP1 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. A portion of the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 on the fourth bank BNK4, and another portion of the first electrode pattern CEP1 may be directly disposed on the first organic pattern ELP1 in each of the second emission area EA2 and the third emission area EA3. Therefore, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in an area other than the first emission area EA1.

[0231] A capping layer CAP may be disposed on the first common electrode CE1 in the first emission area EA1. The capping layer CAP may include an inorganic insulating material and may cover the first light emitting element ED1. The capping layer CAP may prevent the first light emitting element ED1 from being damaged by external air. For example, the capping layer CAP may include (but is not limited to) at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0232] An inorganic material for forming the cladding layer CAP and the first cladding pattern CLP1 may be deposited on the entire surface of the display device 10. The cladding layer CAP and the first cladding pattern CLP1 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. A portion of the first cladding pattern CLP1 may be disposed on the first electrode pattern CEP1 on the fourth bank BNK4, and the other portion of the first cladding pattern CLP1 may be disposed on the first electrode pattern CEP1 in each of the second emission area EA2 and the third emission area EA3. Therefore, the first cladding pattern CLP1 may be disposed on the first electrode pattern CEP1 in an area other than the first emission area EA1.

[0233] An inorganic material for forming the first inorganic layer TL1 may be deposited on the entire surface of the display device 10. The first inorganic layer TL1 may cover the upper surface of the capping layer CAP in the first emission area EA1, and may cover the upper surface of the first capping pattern CLP1 in the second emission area EA2 and the third emission area EA3. The first inorganic layer TL1 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3 and the side surface of the fourth bank BNK4, the side surface of the first organic pattern ELP1, the side surface of the first electrode pattern CEP1, and the upper surface and the side surface of the first capping pattern CLP1. The first inorganic layer TL1 may include an inorganic material to prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include (but is not limited to) at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0234] exist Fig.17 In the embodiment, the first inorganic layer TL1, the first cladding pattern CLP1, the first electrode pattern CEP1, and the first organic pattern ELP1 that are not disposed in the first emission area EA1 and the area adjacent to the first emission area EA1 may be etched by an etching process. For example, the first inorganic layer TL1, the first cladding pattern CLP1, the first electrode pattern CEP1, and the first organic pattern ELP1 may be etched by performing at least one of a dry etching process and a wet etching process. Therefore, the second pixel electrode AE2 may be exposed in the second emission area EA2, and the third pixel electrode AE3 may be exposed in the third emission area EA3.

[0235] exist Fig.18In the second emission area EA2, the second light emitting layer EL2 may be directly disposed on the second pixel electrode AE2. A portion of the second light emitting layer EL2 may fill a space surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1, and another portion of the second light emitting layer EL2 may cover an upper surface of an edge of the etching control layer EST and a side surface of the first insulating layer IL1.

[0236] An organic material for forming the second light emitting layer EL2 and the second organic pattern ELP2 may be deposited on the entire surface of the display device 10. The second light emitting layer EL2 and the second organic pattern ELP2 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. A portion of the second organic pattern ELP2 may be disposed on a fourth bank BNK4 disposed adjacent to the second emission area EA2, another portion of the second organic pattern ELP2 may be disposed directly on the third pixel electrode AE3 in the third emission area EA3, and another portion of the second organic pattern ELP2 may be disposed on the first inorganic layer TL1 in the first emission area EA1.

[0237] The second common electrode CE2 may be directly disposed on the second light emitting layer EL2 in the second emission region EA2. The second common electrode CE2 may contact the side surface of the conductive layer MTL and the upper surface of the edge of the conductive layer MTL. The second common electrode CE2 may include a transparent conductive material and transmit light generated from the second light emitting layer EL2. Therefore, the second light emitting element ED2 may be disposed in a hole formed by the bank BNK and may emit light through the second emission region EA2.

[0238] A metal material for forming the second common electrode CE2 and the second electrode pattern CEP2 may be deposited on the entire surface of the display device 10. The second common electrode CE2 and the second electrode pattern CEP2 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. A portion of the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 on the fourth bank BNK4, and another portion of the second electrode pattern CEP2 may be directly disposed on the second organic pattern ELP2 in each of the first emission area EA1 and the third emission area EA3. Therefore, the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in an area other than the second emission area EA2.

[0239] A capping layer CAP may be disposed on the second common electrode CE2 in the second emission area EA2. The capping layer CAP may include an inorganic insulating material and may cover the second light emitting element ED2. The capping layer CAP may prevent the second light emitting element ED2 from being damaged by external air.

[0240] An inorganic material for forming the cladding layer CAP and the second cladding pattern CLP2 may be deposited on the entire surface of the display device 10. The cladding layer CAP and the second cladding pattern CLP2 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. A portion of the second cladding pattern CLP2 may be disposed on the second electrode pattern CEP2 on the fourth bank BNK4, and another portion of the second cladding pattern CLP2 may be disposed on the second electrode pattern CEP2 in each of the first emission area EA1 and the third emission area EA3. Therefore, the second cladding pattern CLP2 may be disposed on the second electrode pattern CEP2 in an area other than the second emission area EA2.

[0241] An inorganic material for forming the second inorganic layer TL2 may be deposited on the entire surface of the display device 10. The second inorganic layer TL2 may cover the upper surface of the capping layer CAP in the second emission area EA2, and may cover the upper surface of the second capping pattern CLP2 in the first emission area EA1 and the third emission area EA3. The second inorganic layer TL2 may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3 and the side surface of the fourth bank BNK4, the side surface of the second organic pattern ELP2, the side surface of the second electrode pattern CEP2, and the upper surface and the side surface of the second capping pattern CLP2. The second inorganic layer TL2 may include an inorganic material to prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. For example, the second inorganic layer TL2 may be made of at least one of the multiple materials listed in the description of the first inorganic layer TL1.

[0242] exist Fig.19 In the embodiment, the second inorganic layer TL2, the second cladding pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2 that are not disposed in the second emission area EA2 and the area adjacent to the second emission area EA2 may be etched by an etching process. For example, the second inorganic layer TL2, the second cladding pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2 may be etched by performing at least one of a dry etching process and a wet etching process. Therefore, the third pixel electrode AE3 may be exposed in the third emission area EA3.

[0243] exist Fig. 20 In the third emission area EA3, the third light emitting layer EL3 may be directly disposed on the third pixel electrode AE3. A portion of the third light emitting layer EL3 may fill a space surrounded by the third pixel electrode AE3, the residual pattern RP, and the first insulating layer IL1, and another portion of the third light emitting layer EL3 may cover an upper surface of an edge of the etching control layer EST and a side surface of the first insulating layer IL1.

[0244] An organic material for forming the third light emitting layer EL3 and the third organic pattern ELP3 may be deposited on the entire surface of the display device 10. The third light emitting layer EL3 and the third organic pattern ELP3 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. A portion of the third organic pattern ELP3 may be disposed on the fourth bank BNK4 adjacent to the third emission area EA3, and another portion of the third organic pattern ELP3 may be disposed on the first inorganic layer TL1 or the second inorganic layer TL2.

[0245] A third common electrode CE3 may be directly disposed on the third light emitting layer EL3 in the third emission region EA3. The third common electrode CE3 may contact the side surface of the conductive layer MTL and the upper surface of the edge of the conductive layer MTL. The third common electrode CE3 may include a transparent conductive material and transmit light generated from the third light emitting layer EL3. Therefore, the third light emitting element ED3 may be disposed in a hole formed by the bank BNK and may emit light through the third emission region EA3.

[0246] A metal material for forming the third common electrode CE3 and the third electrode pattern CEP3 may be deposited on the entire surface of the display device 10. The third common electrode CE3 and the third electrode pattern CEP3 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. A portion of the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 on the fourth bank BNK4, and another portion of the third electrode pattern CEP3 may be directly disposed on the third organic pattern ELP3 in each of the first emission area EA1 and the second emission area EA2. Therefore, the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 in an area other than the third emission area EA3.

[0247] A capping layer CAP may be disposed on the third common electrode CE3 in the third emission area EA3. The capping layer CAP may include an inorganic insulating material and may cover the third light emitting element ED3. The capping layer CAP may prevent the third light emitting element ED3 from being damaged by external air.

[0248] An inorganic material for forming the cladding layer CAP and the third cladding pattern CLP3 may be deposited on the entire surface of the display device 10. The cladding layer CAP and the third cladding pattern CLP3 may be deposited in the same process and may be disconnected due to the tip of the second bank BNK2. A portion of the third cladding pattern CLP3 may be disposed on the third electrode pattern CEP3 on the fourth bank BNK4, and another portion of the third cladding pattern CLP3 may be disposed on the third electrode pattern CEP3 in each of the first emission area EA1 and the second emission area EA2. Therefore, the third cladding pattern CLP3 may be disposed on the third electrode pattern CEP3 in an area other than the third emission area EA3.

[0249] An inorganic material for forming the third inorganic layer TL3 may be deposited on the entire surface of the display device 10. The third inorganic layer TL3 may cover the upper surface of the capping layer CAP in the third emission area EA3, and may cover the side surface of the first bank BNK1, the lower surface and the side surface of the tip of the second bank BNK2, the side surface of the third bank BNK3 and the side surface of the fourth bank BNK4, the side surface of the third organic pattern ELP3, the side surface of the third electrode pattern CEP3, and the upper surface and the side surface of the third capping pattern CLP3. The third inorganic layer TL3 may include an inorganic material to prevent oxygen or moisture from penetrating into the third light-emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. For example, the third inorganic layer TL3 may be made of at least one of the multiple materials listed in the description of the first inorganic layer TL1.

[0250] exist Fig.21 In the embodiment, the third inorganic layer TL3, the third cladding pattern CLP3, the third electrode pattern CEP3, and the third organic pattern ELP3 that are not disposed in the third emission area EA3 and the area adjacent to the third emission area EA3 may be etched by an etching process. For example, the third inorganic layer TL3, the third cladding pattern CLP3, the third electrode pattern CEP3, and the third organic pattern ELP3 may be etched by performing at least one of a dry etching process and a wet etching process.

[0251] Fig. 22 A virtual reality device 1 including a display device 10_1 according to an embodiment is shown. Fig. 22 The display device 10_1 may be according to the above Figures 1 to 13 Any one of the multiple display devices 10 of the embodiments.

[0252] Reference Fig. 22 The virtual reality device 1 may be a glasses-type display. The virtual reality device 1 may include a display device 10_1, a left lens 10a, a right lens 10b, a support frame 20, glasses frame legs 30a and 30b, a reflective member 40, and a display device housing 50.

[0253] Alternatively, the virtual reality device 1 may be applied to a head-mounted display including a head-mounted strap that can be worn on the head instead of the eyeglass frame legs 30a and 30b. Fig. 22 The virtual reality device 1 shown in FIG. 1 can be applied to various other electronic devices in various forms.

[0254] The display device 10_1 and the reflective member 40 may be disposed in a display device housing 50. The image displayed in the display device 10_1 may be reflected by the reflective member 40 and provided to the right eye of the user through the right lens 10b. Therefore, the user can view the virtual reality image displayed in the display device 10_1 through the right eye.

[0255] The display device housing 50 may be disposed at the right end of the support frame 20. However, the position of the display device housing 50 is not limited thereto. For example, the display device housing 50 may also be disposed at the left end of the support frame 20. In this case, the image displayed in the display device 10_1 may be reflected by the reflective member 40 and provided to the left eye of the user through the left lens 10a. Therefore, the user can view the virtual reality image displayed in the display device 10_1 through the left eye.

[0256] As another example, the display device housing 50 may be provided at both the left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed in the display device 10_1 through the left eye and the right eye.

[0257] Fig.23 and Fig.24 A head mounted display including a display device 10_2 according to an embodiment is shown. Fig.23 and Fig.24 The display device 10_2 may be according to the above Figures 1 to 13 Any one of the multiple display devices 10 of the embodiments.

[0258] Reference Fig.23 and Fig.24 , the display device 10_2 may be applied to a head mounted display. The first display device 1100 may provide an image to the right eye of the user, and the second display device 1200 may provide an image to the left eye of the user.

[0259] The first lens array 1310 may be disposed between the first display device 1100 and the housing cover 1700. The first lens array 1310 may include a plurality of lenses 1311. The lenses 1311 may include convex lenses protruding toward the housing cover 1700.

[0260] The second lens array 1410 may be disposed between the second display device 1200 and the housing cover 1700. The second lens array 1410 may include a plurality of lenses 1411. The lenses 1411 may include convex lenses protruding toward the housing cover 1700.

[0261] The display panel housing 1600 may accommodate the first display device 1100, the second display device 1200, the first lens array 1310, and the second lens array 1410. The surface of the display panel housing 1600 may be open to accommodate the first display device 1100, the second display device 1200, the first lens array 1310, and the second lens array 1410.

[0262] The housing cover 1700 may cover the open surface of the display panel housing 1600. The housing cover 1700 may include a first opening 1710 for placing the user's left eye and a second opening 1720 for placing the user's right eye. For example, the first opening 1710 and the second opening 1720 may be formed in a square shape, but the shape of the first opening 1710 and the shape of the second opening 1720 are not limited thereto. For another example, the first opening 1710 and the second opening 1720 may be formed in a circular shape or an elliptical shape. For another example, the first opening 1710 and the second opening 1720 may be integrated to form one opening.

[0263] The second opening 1720 may be aligned with the first display device 1100 and the first lens array 1310, and the first opening 1710 may be aligned with the second display device 1200 and the second lens array 1410. Therefore, the user can view the image of the first display device 1100 magnified as a virtual image by the first lens array 1310 through the second opening 1720, and can view the image of the second display device 1200 magnified as a virtual image by the second lens array 1410 through the first opening 1710.

[0264] The headband 1800 can fix the display panel housing 1600 to the user's head so that the first opening 1710 and the second opening 1720 of the housing cover 1700 are placed on the user's left eye and right eye, respectively. The headband 1800 can be connected to the upper surface, left surface, and right surface of the display panel housing 1600.

[0265] Fig.25 It is shown Figure 22 to Figure 24 sectional view of a pixel according to an embodiment in a display device of FIG. Fig.25 The display device may include Figure 4 The light emitting element layer EML and the encapsulation layer TFEL are the same as those described in . The same elements as those described above will be briefly described or not described.

[0266] Reference Fig.25 , the display panel 100 may include a semiconductor backplane SBP, an emission backplane EBP, a light emitting element layer EML, and an encapsulation layer TFEL.

[0267] The semiconductor back plate SBP may include a semiconductor substrate SSUB, first to third semiconductor insulating layers SIL1 to SIL3 , and contact terminals CTE.

[0268] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be provided in an upper portion of the semiconductor substrate SSUB. The well region WA may be a region doped with a second type of impurity different from the first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. For another example, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0269] Each of the plurality of pixel transistors PTR may include a well region WA, a source region SCA, a drain region DRA, a channel region CH, a first lightly doped impurity region LDD1, a second lightly doped impurity region LDD2, a bottom insulating layer BIL, a gate electrode GE, and a side insulating layer FIL.

[0270] The well area WA may be disposed in an upper portion of the semiconductor substrate SSUB. The source area SCA, the drain area DRA, the channel area CH, the first lightly doped impurity area LDD1, and the second lightly doped impurity area LDD2 may be disposed in the well area WA.

[0271] The source region SCA may correspond to the source electrode of the pixel transistor PTR, and the drain region DRA may correspond to the drain electrode of the pixel transistor PTR. Each of the source region SCA and the drain region DRA may be doped with first type impurities. The source region SCA may be disposed on one side of the gate electrode GE, and the drain region DRA may be disposed on the other side of the gate electrode GE.

[0272] The channel region CH may be disposed between the source region SCA and the drain region DRA. A bottom insulating layer BIL may be disposed on the channel region CH to insulate the channel region CH from the gate electrode GE. The gate electrode GE may be disposed on the bottom insulating layer BIL. The gate electrode GE may overlap the channel region CH and the well region WA in the thickness direction. A side insulating layer FIL (spacer) may be disposed on the side surface of the gate electrode GE and the upper surface of the bottom insulating layer BIL.

[0273] The first lightly doped impurity region LDD1 may be disposed between the channel region CH and the heavily doped impurity region (source region SCA), and the second lightly doped impurity region LDD2 may be disposed between the channel region CH and the heavily doped impurity region (drain region DRA). Due to the side insulating layer FIL (spacer), the first lightly doped impurity region LDD1 may have a lower impurity concentration than the source region SCA. Due to the side insulating layer FIL (spacer), the second lightly doped impurity region LDD2 may have a lower impurity concentration than the drain region DRA. The distance between the source region SCA and the drain region DRA may be increased by the first lightly doped impurity region LDD1 and the second lightly doped impurity region LDD2. Therefore, the length of the channel region CH of the pixel transistor PTR may be increased, thereby preventing a punch-through phenomenon and a hot carrier phenomenon caused by a short channel.

[0274] The first semiconductor insulating layer SIL1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SIL1 may include, but is not limited to, silicon carbonitride (SiCN) or silicon oxide (SiO x ) of the inorganic layer.

[0275] The second semiconductor insulating layer SIL2 may be disposed on the first semiconductor insulating layer SIL1. The second semiconductor insulating layer SIL2 may include, but is not limited to, silicon oxide (SiO x ) of the inorganic layer.

[0276] The contact terminal CTE may be disposed on the second semiconductor insulating layer SIL2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, the source region SCA, and the drain region DRA of the pixel transistor PTR through a contact hole formed through the first semiconductor insulating layer SIL1 and the second semiconductor insulating layer SIL2. The contact terminal CTE may include at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0277] The third semiconductor insulating layer SIL3 may be disposed on a side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SIL3. The third semiconductor insulating layer SIL3 may include, but is not limited to, silicon oxide (SiO x ) of the inorganic layer.

[0278] The emission backplane EBP may include first to eighth metal layers MTL1 to MTL8 , first to eighth vias VIA1 to VIA8 , and first to ninth interlayer insulating layers ILD1 to ILD9 .

[0279] The first metal layer MTL1 to the eighth metal layer MTL8 may be electrically connected to the contact terminal CTE exposed in the semiconductor backplane SBP to form each pixel circuit. For example, the semiconductor backplane SBP may include a plurality of pixel transistors PTR, and the emission backplane EBP may include a connection electrode connecting the pixel transistors PTR and at least one capacitor connected to each of the plurality of pixel transistors PTR. The emission backplane EBP may electrically connect the pixel circuit to the first light emitting element ED1.

[0280] The first interlayer insulating layer ILD1 may be disposed on the semiconductor backplane SBP. The first via hole VIA1 may be formed through the first interlayer insulating layer ILD1 and may be connected to the contact terminal CTE exposed in the semiconductor backplane SBP. The first metal layer MTL1 may be disposed on the first interlayer insulating layer ILD1 and connected to the first via hole VIA1.

[0281] The second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1 and the first metal layer MTL1. The second via hole VIA2 may be formed through the second interlayer insulating layer ILD2 and may be connected to the first metal layer MTL1. The second metal layer MTL2 may be disposed on the second interlayer insulating layer ILD2 and connected to the second via hole VIA2.

[0282] The third interlayer insulating layer ILD3 may be disposed on the second interlayer insulating layer ILD2 and the second metal layer MTL2. The third via hole VIA3 may be formed through the third interlayer insulating layer ILD3 and may be connected to the second metal layer MTL2. The third metal layer MTL3 may be disposed on the third interlayer insulating layer ILD3 and connected to the third via hole VIA3.

[0283] The fourth interlayer insulating layer ILD4 may be disposed on the third interlayer insulating layer ILD3 and the third metal layer MTL3. The fourth via hole VIA4 may be formed through the fourth interlayer insulating layer ILD4 and may be connected to the third metal layer MTL3. The fourth metal layer MTL4 may be disposed on the fourth interlayer insulating layer ILD4 and connected to the fourth via hole VIA4.

[0284] A fifth interlayer insulating layer ILD5 may be disposed on the fourth interlayer insulating layer ILD4 and the fourth metal layer MTL4. A fifth via VIA5 may be formed through the fifth interlayer insulating layer ILD5 and may be connected to the fourth metal layer MTL4. A fifth metal layer MTL5 may be disposed on the fifth interlayer insulating layer ILD5 and connected to the fifth via VIA5.

[0285] The sixth interlayer insulating layer ILD6 may be disposed on the fifth interlayer insulating layer ILD5 and the fifth metal layer MTL5. The sixth via hole VIA6 may be formed through the sixth interlayer insulating layer ILD6 and may be connected to the fifth metal layer MTL5. The sixth metal layer MTL6 may be disposed on the sixth interlayer insulating layer ILD6 and connected to the sixth via hole VIA6.

[0286] The seventh interlayer insulating layer IND7 may be disposed on the sixth interlayer insulating layer ILD6 and the sixth metal layer MTL6. The seventh via hole VIA7 may be formed through the seventh interlayer insulating layer ILD7 and may be connected to the sixth metal layer MTL6. The seventh metal layer MTL7 may be disposed on the seventh interlayer insulating layer ILD7 and connected to the seventh via hole VIA7.

[0287] An eighth interlayer insulating layer IND8 may be disposed on the seventh interlayer insulating layer ILD7 and the seventh metal layer MTL7. An eighth via VIA8 may be formed through the eighth interlayer insulating layer ILD8 and may be connected to the seventh metal layer MTL7. An eighth metal layer MTL8 may be disposed on the eighth interlayer insulating layer ILD8 and connected to the eighth via VIA8. A ninth interlayer insulating layer ILD9 may be disposed on the eighth interlayer insulating layer ILD8 and the eighth metal layer MTL8.

[0288] The first to eighth metal layers MTL1 to MTL8 and the first to eighth vias VIA1 to VIA8 may include substantially the same material. Each of the first to eighth metal layers MTL1 to MTL8 and the first to eighth vias VIA1 to VIA8 may include at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). Each of the first to ninth interlayer insulating layers ILD1 to ILD9 may include, but is not limited to, silicon oxide (SiO x ) of the inorganic layer.

[0289] The thickness of the first metal layer MTL1, the thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may each be greater than the thickness of the first via VIA1, the thickness of the second via VIA2, the thickness of the third via VIA3, the thickness of the fourth via VIA4, the thickness of the fifth via VIA5, and the thickness of the sixth via VIA6. The thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may each be greater than the thickness of the first metal layer MTL1. The thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may be substantially the same. For example, the thickness of the first metal layer MTL1 may be about 1000 Å. The thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may each be about 100 Å. The thickness of the first via hole VIA1, the thickness of the second via hole VIA2, the thickness of the third via hole VIA3, the thickness of the fourth via hole VIA4, the thickness of the fifth via hole VIA5, and the thickness of the sixth via hole VIA6 may each be about 1000 Å.

[0290] The thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may each be greater than the thickness of the first metal layer MTL1, the thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6. The thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may each be greater than the thickness of the seventh via VIA7 and the thickness of the eighth via VIA8. The thickness of the seventh via VIA7 and the thickness of the eighth via VIA8 may each be greater than the thickness of the first via VIA1, the thickness of the second via VIA2, the thickness of the third via VIA3, the thickness of the fourth via VIA4, the thickness of the fifth via VIA5, and the thickness of the sixth via VIA6. The thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may be substantially the same. For example, the thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may each be about The thickness of the seventh via hole VIA7 and the thickness of the eighth via hole VIA8 may each be about 100 Å.

[0291] As its resolution increases, the display device 10 can include a large number of pixels SP in a relatively small area (see Figure 3 ). The emission backplane EBP including the first metal layer MTL1 to the eighth metal layer MTL8 can implement a connection electrode connecting the pixel transistor PTR and at least one capacitor connected to each of the plurality of pixel transistors PTR, thereby implementing a pixel circuit in a relatively small area. Therefore, the light emitting element layer EML can be formed on a silicon wafer (Si wafer) including the semiconductor backplane SBP and the emission backplane EBP, and the display device 10 can achieve ultra-high resolution image quality.

[0292] Fig.26 It is shown Figure 22 to Figure 24 sectional view of a pixel according to an embodiment in a display device of FIG. Fig.26 The display device may include Fig.25 The semiconductor backplane SBP and the transmitting backplane EBP are the same as the semiconductor backplane SBP and the transmitting backplane EBP, and may include Figure 6 The light emitting element layer EML and the encapsulation layer TFEL are the same as the light emitting element layer EML and the encapsulation layer TFEL. Therefore, the Fig.26 Description of the display device.

[0293] Fig. 27 It is shown Figure 22 to Figure 24 sectional view of a pixel according to an embodiment in a display device of FIG. Fig. 27 The display device may include Fig.25 The semiconductor backplane SBP and the transmitting backplane EBP are the same as the semiconductor backplane SBP and the transmitting backplane EBP, and may include Figure 8 The light emitting element layer EML and the encapsulation layer TFEL are the same as the light emitting element layer EML and the encapsulation layer TFEL. Therefore, the Fig. 27 Description of the display device.

[0294] Fig.28 It is shown Figure 22 to Figure 24 sectional view of a pixel according to an embodiment in a display device of FIG. Fig.28 The display device may include Fig.25 The semiconductor backplane SBP and the transmitting backplane EBP are the same as the semiconductor backplane SBP and the transmitting backplane EBP, and may include Fig.10 The light emitting element layer EML and the encapsulation layer TFEL are the same as the light emitting element layer EML and the encapsulation layer TFEL. Therefore, the Fig.28 Description of the display device.

[0295] Fig.29 It is shown Figure 22 to Figure 24 sectional view of a pixel according to an embodiment in a display device of FIG. Fig.29The display device may include Fig.25 The semiconductor backplane SBP and the transmitting backplane EBP are the same as the semiconductor backplane SBP and the transmitting backplane EBP, and may include Fig.12 The light emitting element layer EML and the encapsulation layer TFEL are the same as the light emitting element layer EML and the encapsulation layer TFEL. Therefore, the Fig.29 Description of the display device.

[0296] In the display device and the method for manufacturing the same according to the embodiment, the thickness of the bank is increased to ensure that the inorganic layer encapsulates the area of ​​the bank, thereby blocking the moisture penetration path and improving the reliability of the light emitting element.

[0297] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the claims.

Claims

1. A display device, wherein: The display device comprises: A first pixel electrode is disposed on the substrate in the first emission region; an insulating layer, covering an edge of the first pixel electrode; A first light emitting layer, disposed on the first pixel electrode and the insulating layer; A first common electrode, disposed on the first light-emitting layer; a conductive layer, disposed on the insulating layer to surround the first emission region and contact the first common electrode; A first bank is disposed on the conductive layer; a second bank disposed on the first bank, and including a tip protruding from a side surface of the first bank toward the first emission region; and The third bank is disposed on the second bank, and the third bank includes an inorganic material.

2. The display device according to claim 1, wherein: The display device further includes a fourth bank disposed on the third bank and including a metal material.

3. The display device according to claim 2, wherein: The thickness of the first bank is greater than the sum of the thickness of the second bank, the thickness of the third bank, and the thickness of the fourth bank, and the thickness of the third bank is greater than the thickness of each of the second bank and the fourth bank.

4. The display device according to claim 2, wherein: The display device further includes: a first organic pattern including the same material as the first light emitting layer, and the first organic pattern is disposed on the fourth bank in a region adjacent to the first emission region; and A first electrode pattern includes the same material as the first common electrode, and the first electrode pattern is disposed on the first organic pattern on the fourth bank.

5. The display device according to claim 4, wherein: The display device further includes: a coating layer, disposed on the first common electrode; and The first cladding pattern includes the same material as the cladding layer, and the first cladding pattern is disposed on the first electrode pattern.

6. The display device according to claim 5, wherein: The display device also includes a first inorganic layer, which covers the side surface of the first embankment, the lower surface and side surface of the tip of the second embankment, the side surface of the third embankment and the side surface of the fourth embankment, the side surface of the first organic pattern, the side surface of the first electrode pattern, and the upper surface and side surface of the first coating pattern.

7. The display device according to claim 2, wherein: The display device further includes: a second pixel electrode, disposed on the substrate in the second emission region; A second light emitting layer is disposed on the second pixel electrode; and The second common electrode is disposed on the second light emitting layer to contact the conductive layer.

8. The display device according to claim 7, wherein: The first common electrode and the second common electrode are electrically connected through the conductive layer.

9. The display device according to claim 7, wherein: The display device further includes: A coating layer, disposed on the second common electrode; a second organic pattern including the same material as the second light emitting layer, and the second organic pattern is disposed on the fourth bank in a region adjacent to the second emission region; a second electrode pattern including the same material as the second common electrode, and the second electrode pattern is disposed on the second organic pattern on the fourth bank; and The second cladding pattern includes the same material as the cladding layer, and the second cladding pattern is disposed on the second electrode pattern.

10. The display device according to claim 9, wherein: The display device also includes a second inorganic layer, which covers the side surface of the first embankment, the lower surface and side surface of the tip of the second embankment, the side surface of the third embankment and the side surface of the fourth embankment, the side surface of the second organic pattern, the side surface of the second electrode pattern, and the upper surface and side surface of the second coating pattern.

11. The display device according to claim 1, wherein: The display device further includes: A coating layer, disposed on the first common electrode; a first organic pattern including the same material as the first light emitting layer, and the first organic pattern is disposed on the third bank in a region adjacent to the first emission region; a first electrode pattern including the same material as the first common electrode, and the first electrode pattern is disposed on the first organic pattern on the third bank; and The first cladding pattern includes the same material as the cladding layer, and the first cladding pattern is disposed on the first electrode pattern.

12. The display device according to claim 1, wherein: The display device further includes a fourth bank disposed on the third bank, and the fourth bank and the third bank include a different inorganic material.

13. The display device according to claim 1, wherein: The display device further includes: a fourth bank disposed on the third bank; and A fifth bank is provided on the fourth bank and protrudes from a side surface of the fourth bank toward the first emission region.

14. A display device, wherein: The display device comprises: A first pixel electrode is disposed on the substrate in the first emission region; a second pixel electrode disposed on the same layer as the first pixel electrode in the second emission region; an insulating layer covering an edge of each of the first pixel electrode and the second pixel electrode; A first light emitting layer, disposed on the first pixel electrode and the insulating layer; A first common electrode, disposed on the first light-emitting layer; A second light emitting layer is disposed on the second pixel electrode and the insulating layer; A second common electrode is disposed on the second light emitting layer; a conductive layer disposed on the insulating layer to surround each of the first emission region and the second emission region and to electrically connect the first common electrode and the second common electrode; A first bank is disposed on the conductive layer; a second bank disposed on the first bank, and including a tip protruding from a side surface of the first bank toward each of the first emission region and the second emission region; a third bank disposed on the second bank; and A fourth bank is provided on the third bank, and includes a tip protruding from a side surface of the third bank toward each of the first emission region and the second emission region.

15. The display device according to claim 14, wherein: The display device further includes: A coating layer, disposed on the first common electrode; a first organic pattern including the same material as the first light emitting layer, and the first organic pattern is disposed on the fourth bank in a region adjacent to the first emission region; a first electrode pattern including the same material as the first common electrode, and the first electrode pattern is disposed on the first organic pattern on the fourth bank; a first cladding pattern including the same material as the cladding layer, and the first cladding pattern is disposed on the first electrode pattern; and A first inorganic layer covers the side surface of the first embankment, the lower surface and side surfaces of the tip of the second embankment, the side surface of the third embankment, the lower surface and side surfaces of the tip of the fourth embankment, the side surface of the first organic pattern, the side surface of the first electrode pattern, and the upper surface and side surfaces of the first coating pattern.

16. The display device according to claim 15, wherein: The display device further includes: A coating layer, disposed on the second common electrode; a second organic pattern including the same material as the second light emitting layer, and the second organic pattern is disposed on the fourth bank in a region adjacent to the second emission region; a second electrode pattern including the same material as the second common electrode, and the second electrode pattern is disposed on the second organic pattern on the fourth bank; a second cladding pattern including the same material as the cladding layer, and the second cladding pattern is disposed on the second electrode pattern; and A second inorganic layer covers the side surface of the first embankment, the lower surface and the side surface of the tip of the second embankment, the side surface of the third embankment, the lower surface and the side surface of the tip of the fourth embankment, the side surface of the second organic pattern, the side surface of the second electrode pattern, and the upper surface and side surface of the second coating pattern.

17. A method for manufacturing a display device, wherein: The method comprises: forming a pixel electrode and a sacrificial layer on a substrate, wherein the pixel electrode comprises a first pixel electrode overlapping the first emission region and a second pixel electrode overlapping the second emission region; sequentially stacking an insulating layer, a conductive layer, a first bank, a second bank, a third bank and a fourth bank on the pixel electrode; forming a tip of the second bank protruding from a side surface of the first bank by etching the fourth bank, the third bank, the second bank, the first bank, and the conductive layer; exposing the first pixel electrode and the second pixel electrode by etching the insulating layer and the sacrificial layer; forming a first light emitting layer on the first pixel electrode, and forming a first organic pattern on the fourth bank; forming a first common electrode on the first light emitting layer, and forming a first electrode pattern on the first organic pattern on the fourth bank; forming a capping layer on the first common electrode, and forming a first capping pattern on the first electrode pattern on the fourth bank; and A first inorganic layer is formed, which covers the upper surface of the coating layer, the side surface of the first embankment, the lower surface and side surface of the tip of the second embankment, the side surface of the third embankment and the side surface of the fourth embankment, the side surface of the first organic pattern, the side surface of the first electrode pattern, and the upper surface and side surface of the first coating pattern.

18. The method according to claim 17, wherein: Each of the third bank and the first inorganic layer includes at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

19. The method according to claim 18, wherein: The method further includes etching the first inorganic layer, the first cladding pattern, the first electrode pattern, and the first organic pattern overlapping the second emission region and the fourth bank disposed adjacent to the second emission region.

20. The method according to claim 19, wherein: The method further comprises: forming a second light emitting layer on the second pixel electrode, and forming a second organic pattern on the fourth bank; forming a second common electrode on the second light emitting layer, and forming a second electrode pattern on the second organic pattern on the fourth bank; forming a cladding layer on the second common electrode, and forming a second cladding pattern on the second electrode pattern on the fourth bank; and A second inorganic layer is formed, which covers the upper surface of the coating layer, the side surface of the first embankment, the lower surface and the side surface of the tip of the second embankment, the side surface of the third embankment and the side surface of the fourth embankment, the side surface of the second organic pattern, the side surface of the second electrode pattern, and the upper surface and side surface of the second coating pattern.

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