Method for controlling flash memory module and related flash memory controller and memory device

Abstract

The invention discloses a method for controlling a flash memory module, a related flash memory controller and a memory device. In the method, the flash memory module comprises a plurality of crystal grains, and the method comprises the following steps: if abnormal power failure occurs before the flash memory module is powered on, determining a super block which is written into the flash memory module at the last time before the flash memory module is powered on, and the super block comprises a plurality of blocks which are respectively positioned in the plurality of crystal grains; determining the last written data page of the super block; determining a check range of the super block according to the last written data page of the super block; and reading at least one part of data pages in the checking range to judge that the last data page of each block in the super block can be successfully read.

Description

Technical Field

[0001] The present invention relates to a flash memory. Background Art

[0002] During the process of writing data to a super block of the flash memory module by the flash memory controller, if an abnormal power failure occurs, such as power off recovery (POR) or sudden power off recovery (SPOR), after the flash memory controller is powered on again, the flash memory controller will determine whether an abnormal power failure has occurred, and if it is determined that an abnormal power failure has occurred, determine which data in the super block is still valid, and perform a garbage collection operation on the super block to move the valid data therein to another block. However, since the super block includes multiple blocks, and the data writing progress of each block is different, how to efficiently determine the valid data in the super block is an important issue. Summary of the invention

[0003] Therefore, one of the purposes of the present invention is to provide a control method for a memory device, which can efficiently and accurately determine which data in a super block can continue to be used after the memory device is abnormally powered off and powered on again, and process the super block for continued data writing, so as to solve the problems described in the prior art.

[0004] In one embodiment of the present invention, a method for controlling a flash memory module is disclosed, wherein the flash memory module includes a plurality of dies, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the method includes: after the flash memory module is powered on, determining whether the flash memory module encounters an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters an abnormal power failure before the flash memory module is powered on, determining a super block that is last written to the flash memory module before the power is on, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; determining the last data page written to the super block; determining a check range of the super block according to the last data page written to the super block; reading at least a portion of the data pages within the check range to determine the last successfully readable data page of each first block in the super block; determining a data weak area of ​​the super block according to the last successfully readable data page of each first block in the super block; and moving data in the data weak area to other areas of the super block or to another super block.

[0005] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of dies, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the flash memory controller includes a read-only memory and a microprocessor, and the microprocessor is used to perform the following operations: after the flash memory module is powered on, determine whether the flash memory module encounters an abnormal power failure before powering on; if the flash memory module encounters an abnormal power failure before powering on, determine the last super memory written to the flash memory module before powering on; The invention discloses a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of crystal grains; determining a last data page written in the super block; determining a check range of the super block according to the last data page written in the super block; reading at least a part of the data pages in the check range to determine the last successfully readable data page of each first block in the super block; determining a data weak area of ​​the super block according to the last successfully readable data page of each first block in the super block; and moving the data in the data weak area to other areas of the super block or to another super block.

[0006] In one embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of dies, each of which includes a plurality of blocks, and each of which includes a plurality of data pages. The flash memory controller is used to access the flash memory module, and the flash memory controller performs the following operations: after the flash memory module is powered on, determine whether the flash memory module encounters an abnormal power failure before powering on; if the flash memory module encounters an abnormal power failure before powering on, determine a super block that is last written to the flash memory module before powering on, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; determine a last data page written to the super block; determine a check range of the super block according to the last data page written to the super block; read at least a portion of the data pages within the check range to determine the last data page that can be successfully read of each first block in the super block; determine a data weak area of ​​the super block according to the last data page that can be successfully read of each first block in the super block; and move the data in the data weak area to other areas of the super block or to another super block.

[0007] In one embodiment of the present invention, a method for controlling a flash memory module is disclosed, wherein the flash memory module includes a plurality of dies, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the method includes: selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; configuring a controller buffer, wherein the controller buffer includes a plurality of buffers, and each buffer is used to store data to be written to a single data page; receiving a plurality of read requests from a master device, and sequentially storing the plurality of read requests in a buffer request pool; selecting an earliest write request from the buffer request pool; determining whether the number of buffers occupied by the first block of the dies to be written by the corresponding data of the earliest write request in the controller buffer is higher than a critical value; if the number of buffers occupied by the first block of the dies to be written by the corresponding data of the earliest write request in the controller buffer is higher than the critical value, stopping writing the data corresponding to the earliest write request into the controller buffer.

[0008] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of dies, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the flash memory controller includes a read-only memory and a microprocessor, and the microprocessor is used to perform the following operations: select a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; configure a controller buffer, wherein the controller buffer includes a plurality of buffers, and each buffer is used to store Storing data to be written to a single data page; receiving multiple read requests from a master device and sequentially storing the multiple read requests in a buffer request pool; selecting an earliest write request from the buffer request pool; determining whether the number of buffers occupied by the first block of the grain to be written by the corresponding data of the earliest write request in the controller buffer is higher than a critical value; if the number of buffers occupied by the first block of the grain to be written by the corresponding data of the earliest write request in the controller buffer is higher than the critical value, stopping writing the data corresponding to the earliest write request into the controller buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention.

[0010] Figure 2 FIG. 4 is a schematic diagram of a super block according to an embodiment of the present invention.

[0011] Figure 3 A schematic diagram of multiple data pages contained in a block.

[0012] Figure 4 FIG. 1 is a diagram illustrating writing data from a master device into a super block according to an embodiment of the present invention.

[0013] Figure 5 FIG. 1 is a diagram illustrating writing data from a master device into a super block according to an embodiment of the present invention.

[0014] Figure 6 FIG. 1 is a diagram illustrating writing data from a master device into a super block according to an embodiment of the present invention.

[0015] Figure 7 FIG. 1 is a diagram showing that in the worst case, the difference in the written data pages of two dies / blocks is equal to the number of buffers in the controller buffer.

[0016] Figure 8 FIG. 4 is a flow chart of a control method of a memory device according to an embodiment of the present invention.

[0017] Fig. 9 The flowchart is a method of searching the last data page with data written in a block using a binary search method.

[0018] Fig.10 A schematic diagram for determining the last successfully readable data page of each block in a super block and determining a check range accordingly.

[0019] Fig.11 A schematic diagram for determining weak data areas and invalid areas of a super block.

[0020] Fig.12 FIG. 4 is a flow chart of a control method of a memory device according to an embodiment of the present invention.

[0021] Fig.13 FIG. 4 is a schematic diagram of reducing the inspection range of a super block according to an embodiment of the present invention.

[0022]

Explanation of symbols

[0023] 100: Memory device

[0024] 110: Flash memory controller

[0025] 112: Microprocessor

[0026] 112M: Read-only memory

[0027] 112C: Program code

[0028] 114: Control Logic

[0029] 116: Buffer memory

[0030] 118: Interface Logic

[0031] 120: Flash memory module

[0032] 130: Main device

[0033] 132: Encoder

[0034] 134:Decoder

[0035] 136: Randomizer

[0036] 138:De-Randomizer

[0037] 140: DRAM

[0038] 202,204:Super Block

[0039] 300: Block

[0040] 410: Controller buffer

[0041] 420: Buffer request pool

[0042] 430:Free buffer pool

[0043] 800~814: Steps 900~920: Steps 1200~1212: Steps

[0044] B1~BK: Block

[0045] D1_1~D1_4,D2_1~D2_4,D3_1~D3_4,D4_1~D4_4: data

[0046] D11_1~D19_2: Data

[0047] P1~P448: Data page DETAILED DESCRIPTION

[0048] Figure 11 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a randomizer 136, and a de-randomizer 138, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code, ECC), the decoder 134 is used to decode the data read from the flash memory module 120, the randomizer 136 is used to perform a randomization operation on the data written into the flash memory module 120, and the de-randomizer 138 is used to perform a de-randomization operation on the data read from the flash memory module 120.

[0049] In a typical case, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks. The flash memory controller 110 performs operations such as copying, erasing, and merging data on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of data pages, and the flash memory controller 110 performs operations such as writing data to the flash memory module 120 in units of data pages. In other words, a block is a minimum erase unit in the flash memory module 120, and a data page is a minimum write unit in the flash memory module 120.

[0050] In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform many control operations, such as: using the control logic 114 to control the access operation of the flash memory module 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 and / or a dynamic random access memory (DRAM) 140 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device 130.

[0051] In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the memory device, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage device that complies with Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and is disposed in an electronic device, such as a mobile phone, a watch, a portable medical detection device (e.g., a medical bracelet), a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

[0052] In the present embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Since the 3D NAND-type flash memory architecture is well known to those skilled in the art, it will not be described in detail in the specification.

[0053] Figure 2 FIG. 1 is a schematic diagram of a super block according to an embodiment of the present invention. Figure 2 As shown, it is assumed that the flash memory module 120 includes four dies (die 1 to die 4), and each die includes a plurality of blocks B1 to BK. At this time, the microprocessor 112 can configure the blocks belonging to different data planes or different dies in the flash memory module 120 as a super block to facilitate the management of data access. In this embodiment, it is illustrated that a die has only one data plane, but the present invention is not limited to this. Figure 2As shown, die 1 to die 4 include blocks B1 to BK respectively, and the microprocessor 112 can configure the block B1 of each die as a super block 202, and the block B2 of each die as a super block 204, and so on, and the flash memory controller 110 is similar to a general block when accessing the super blocks 202 and 204. For example, the super block 202 itself is an erase unit, that is, although the four blocks B1 included in the super block 202 can be erased separately, the flash memory controller 110 will definitely erase the four blocks B1 together.

[0054] In addition, reference Figure 3 Schematic diagram of block 300 shown, where block 300 may be Figure 2 Any of the blocks B1 to BK shown, and the block 300 includes multiple data pages, such as 448 data pages shown. When writing data to the super block 202, the data can be written sequentially from the first data page P1 of the block B1 of the die 1, the first data page P1 of the block B1 of the die 2, the first data page P1 of the block B1 of the die 3, and the first data page P1 of the block B1 of the die 4, and then the data is sequentially written to the second data page P2 of the block B1 of the die 1, the second data page P2 of the block B1 of the die 2, ..., and so on. In other words, the flash memory controller 110 will arrange to write data to the first data page P1 of each block B1 in the super block 202, and then arrange to write data to the second data page P2 of each block B1 in the super block 202. The super block is a logically set block, not a physical set block, by the flash memory controller 110 for convenient management of the flash memory module 120. In addition, when performing garbage collection, calculating block valid pages, and calculating the length of block write time, calculations can also be performed using super blocks as units.

[0055] In one embodiment, regarding the operation of the host device 130 writing data into the flash memory module 120, refer to Figure 4, the buffer memory 116 includes a controller buffer 410, which includes a plurality of buffers for temporarily storing data from the master device 130; the interface logic 118 includes a buffer request pool 420 and a free buffer pool 130, wherein the buffer request pool 420 is used to indicate the data requested to be written by the master device 130, and the free buffer pool 130 is used to indicate the buffers in the controller buffer 410 that are in an idle state. In this embodiment, for the convenience of explanation, the controller buffer 410 includes eight buffers, which are numbered #1 to #8 respectively, but the present invention is not limited to this. In other embodiments, the number of buffers included in the controller buffer 410 can vary according to the designer's consideration. In addition, the buffer request pool 420 can be implemented using multiple first-in-first-out (FIFO) buffers.

[0056] Specifically, refer to Figure 4 Initially, the master device 130 transmits one or more write requests to the buffer request pool 420 to request that the data D1_1-D1_4, D2_1-D2_4 be written into the flash memory module 120. Since the eight buffers of the controller buffer 410 are all idle at this time, the flash memory controller 110 can obtain the data D1_1-D1_4, D2_1-D2_4 from the master device 130 according to these write requests, and write the data D1_1-D1_4, D2_1-D2_4 into the buffer #1-buffer #8 respectively. In this embodiment, it is assumed that each of the data D1_1 to D1_4 and D2_1 to D2_4 is written into a data page of the flash memory module 120, that is, the data D1_1 to D1_4 are respectively prepared to be written into the data page P1 of the block B1 of the die 1 to the die 4, and the data D2_1 to D2_4 are respectively prepared to be written into the data page P2 of the block B1 of the die 1 to the die 4. Then, the microprocessor 112 in the flash memory controller 110 transmits the data D1_1 to D1_4 of the buffer zone #1 to the buffer zone #4 to the flash memory module 120 in parallel through a direct memory access (DMA) operation.

[0057] Next, refer to Figure 5 Assuming that the flash memory module 120 successfully receives the data D1_2 first, the hardware components inside the flash memory module 120 will start writing the data D1_2 to the data page P1 of the block B1 of the die 2. At this time, the space of the buffer #2 is released, and the free buffer pool 430 will record that the buffer #2 is currently in an idle state.

[0058] Next, refer to Figure 6 Since the space of buffer #2 is released, the data D3_1 corresponding to the first write request of the buffer request pool 420 will be written to the buffer #2, and at this time, the free buffer pool 430 will not record that any buffer is currently idle.

[0059] As described above, when a buffer in the controller buffer 410 is in an idle state, the corresponding data will be obtained by the autonomous device 130 according to the first write request (i.e., the earliest write request) of the buffer request pool 420, and the obtained data will be written into the buffer in the idle state. However, since each chip in the flash memory module 120 has its own back-end hardware so that the flash memory module 120 can process the data written to multiple chips in parallel, and the processing speed of each chip and the corresponding back-end hardware will be slightly different due to the semiconductor process, therefore, as the amount of data written increases, the slight difference in the write speed of each chip will continue to accumulate, resulting in a larger difference in the data writing of each chip. For example, referring to Figure 7 Assuming that the data writing speed of die 3 is slower than that of other dies, in the worst case, the difference between the data page being written by die 3 and the data page that has been written by die 2 will be equal to the number of buffers in the controller buffer 410 (i.e., eight data pages). Figure 7 As shown, when die 2 has written data D19_2 to data page P19, die 3 is writing data D11_3 to data page P11. In this worst case, the data stored in all buffers #1 to #3 in the controller buffer 410 will be the data to be written to block B1 of die 3, such as D12_3 to D19_3 shown in the figure, thus causing the overall writing speed to be limited by die 3.

[0060] However, if in Figure 7 When the data shown is written to the super block 202, an abnormal power failure occurs, such as a sudden power failure recovery (SPOR) situation. After the memory device 100 is powered on again, the flash memory controller 110 will re-read the content of the super block 202 to determine the status of the super block 202, so as to determine an appropriate processing method. This embodiment proposes a control method after the memory device 100 is powered on again, which can efficiently and accurately determine which data in the super block 202 can continue to be used, and process the super block 202 for continued writing of data, so as to optimize the use of the super block 202.

[0061] Figure 88 is a flow chart of a control method of a memory device 100 according to an embodiment of the present invention. At step 800, the process starts, and the memory device 100 is just powered on and performs an initialization operation. At step 802, the flash memory controller 110 determines whether the memory device 100 has experienced an abnormal power failure before powering on. If so, the process proceeds to step 806; if not, the process proceeds to step 804. In one embodiment, when the memory device 100 is normally shut down / powered off, the flash memory controller 110 stores a plurality of temporary tables and data stored in the buffer memory 116 in the flash memory module 120, and includes a flag for indicating whether the memory device 100 is normally shut down. Therefore, after powering on, the flash memory controller 110 can determine whether the memory device 100 has previously experienced an abnormal power failure by reading the flag stored at a specific address in the flash memory module 120. For example, when the flag is not correctly set, it is determined that an abnormal power failure has previously occurred.

[0062] In step 804, since the memory device 100 does not encounter an abnormal power failure before powering on, the flash memory controller 110 starts to operate normally, such as writing data from the host device 130 to the flash memory module 120, or performing a garbage collection operation on the flash memory module 120, etc., that is, the flash memory controller 110 does not perform Figure 8 Steps 806 to 814.

[0063] In step 806, the flash memory controller 110 determines the last data page written to the flash memory module 120 before power-on. Specifically, step 806 may further include the following operations: first, the flash memory controller 110 determines the last super block written to the flash memory module 120 before power-on, then determines the last data page written to the block of the first die included in the super block, and finally finds the last data page written to the flash memory module 120 before power-on based on the last data page written to the block of the first die. For example, the flash memory controller 110 may search for a super block in an active state recorded in the flash memory module 120 as the last super block written before power-on. In the following embodiments, the super block is selected based on the last data page written to the block of the first die. Figure 7 Next, for the first block in the super block, such as block B1 of die 1 in super block 202, the flash memory controller 110 uses a binary search method or any other suitable search method to search for the last data page with data written in the first block. Figure 7For example, the flash memory controller 110 searches for data page P19 of block B1 of die 1 as the last data page with data written in. Finally, the flash memory controller 110 searches rightward from data page P19 of block B1 of die 1, that is, reads the content of the data page and determines whether there is data written, so as to determine that data page P19 of block B1 of die 2 is the last data page written in the flash memory module 120 before power-on.

[0064] For example, refer to Fig. 9 The flowchart shown is a method of searching the last data page with data written in block B1 of die 1 using a binary search method. The process is described as follows.

[0065] Step 900: The process starts.

[0066] Step 902: Determine the search range (R) and the first data page number to be searched (P=(N / 2)) according to the total number of data pages (N) in block B1, and the search direction is forward (D=2, i.e., the direction of increasing data page numbers).

[0067] Step 904: Read the spare region of the data page (P).

[0068] Step 906: Determine whether the data page (P) is a blank data page based on the content in the spare area. For example, the data page (P) can be determined based on whether the spare area records relevant metadata. If the data page (P) is determined to be a blank data page, the process proceeds to step 608; if the data page (P) is determined to be not a blank data page, the process proceeds to step 610.

[0069] Step 908: Set the data page number to be searched next time to (P=P-(R / 2)), and the search direction at this time is backward (D=1, ie, the direction of decreasing data page numbers).

[0070] Step 910: Set the data page number to be searched next time to (P=P+(R / 2)), and the search direction is forward (D=2).

[0071] Step 912: Determine whether the search range (R) is 1. If not, the process proceeds to step 614; if so, the process proceeds to step 616.

[0072] Step 914 : Reduce the search range by half (R=(R / 2)), and the process returns to step 604 .

[0073] Step 916 : Determine whether the search direction is backward (D=1?), if not, the process proceeds to step 618 ; if yes, the process proceeds to step 620 .

[0074] Step 918: Determine whether the data page (P) is the last data page in block B1 to which data is written.

[0075] Step 920: Determine whether the data page (P-1) is the last data page in block B1 to which data is written.

[0076] It should be noted that Fig. 9 The detailed steps shown are only for illustrative purposes and are not intended to be limiting of the present invention.

[0077] In addition, the detailed operation of step 806 is only used as an example, and is not intended to limit the present invention. In other embodiments, the flash memory controller 110 may perform a binary search on two or more blocks in the super block 202 to search for the last data page with data written in these blocks, and then compare the numbers of the last data page with data written in these blocks to obtain the last data page written in the flash memory module 120 before power-on.

[0078] In step 808, after determining the last data page written to the flash memory module 120 before power-on, the flash memory controller 110 determines a check range of the super block 202. Figure 7 And related content, because in the worst case, the difference between the data page being written in die 3 and the data page that has been written in die 2 will be equal to the number of buffers in the controller buffer 410, therefore, assuming that the number of buffers in the controller buffer 410 is "N", the flash memory controller 110 can back-calculate the "N+1" data page based on the number of the last data page written before the flash memory module 120 is powered on, that is, the number of the last data page written minus "N" to obtain the inspection range. Fig.10 For example, assuming that the last data page written to the flash memory module 120 before power-on is data page P19 of block B1 of die 2, the flash memory controller 110 can first determine that the lower edge of the inspection range is data pages P19, P19, P18, and P18 of the four blocks included in the super block 202 (that is, block B1 of die 1 that is written earlier than die 2 is set to the same data page number P19, and block B1 of die 3 and 4 that is written later than die 2 is set to the data page number minus "1"), and then subtract "N" from these numbers to obtain the upper edge of the inspection range is data pages P11, P11, P10, and P10 of the four blocks included in the super block 202.

[0079] It should be noted that due to Figure 7The worst case is described, therefore, in another embodiment of step 808, the upper edge of the check range may be calculated to be changed according to the quality or operation of the flash memory module 120 so that the check range has fewer data pages. For example, assuming that the number of buffers of the controller buffer 410 is "N", the flash memory controller 110 may subtract "P" from the number of the last data page written by the flash memory module 120 to obtain the upper edge of the check range, wherein "P" may be any suitable value less than "N".

[0080] In step 810, the flash memory controller 110 reads data from the lower edge of the inspection range to the upper edge, or from the upper edge of the inspection range to the lower edge, in the inspection range, until the read data can be successfully decoded by the decoder 134, that is, the decoder 134 can successfully use the error correction code of the read data to complete the decoding operation, so as to determine the last data page that can be successfully read (that is, successfully decoded) in each block of the super block 202. Fig.10 For example, the decoder 134 cannot successfully decode the data of data page P19 of block B1 of die 1, but can successfully decode the data of data page P18 of block B1 of die 1, so the flash memory controller 110 determines that the last data page that can be successfully read in block B1 of die 1 is P18. Similarly, the flash memory controller 110 determines that the last data page that can be successfully read in block B1 of die 2 is P18, the last data page that can be successfully read in block B1 of die 3 is P10, and the last data page that can be successfully read in block B1 of die 4 is P17.

[0081] In step 812, based on the last data page that can be successfully read in each super block 202, the flash memory controller 110 determines the data page with the smallest data page number and a corresponding specific block or a specific die, and accordingly determines the last validly written block and data page in the super block 202. In one embodiment, if the number of the specific block or the die to which the specific block belongs is N, where N is greater than 1, and the number of the data page with the smallest data page number is M, then the number of the die to which the last validly written block belongs is "N-1", and the data page of the last validly written block is "M+1". Fig.10 For example, if the specific die is determined to be die 3, and the data page with the smallest data page number is P10, then the last validly written data page in super block 202 is data page P11 of block B1 of die 2. In addition, if the specific block belongs to die 1, then the die to which the last validly written block belongs is the die with the largest number (e.g. Fig.10 The last validly written data page of the block is “M”.

[0082] In step 814, the flash memory controller 110 determines a weak region and an invalid area of ​​the super block 202 according to the last validly written block and data page in the super block 202 determined in step 812, and moves the data in the weak region to other areas in the super block 202 or to other super blocks. Fig.11 , the flash memory controller 110 may push back the last validly written block and data page in the super block 202 by several data pages (for example, the number of data pages corresponding to one or two word lines) to determine the data weak area. For example, the data weak area may include data pages P5-P10 of block B1 of die 1 to die 4, and data pages P5-P11 of block B11 of die 1 to die 2. In addition, the flash memory controller 110 may push back several data pages (for example, the number of data pages corresponding to one or two word lines) based on the lower edge of the inspection range determined in step 808 to determine the invalid area. For example, the invalid area may include data page P11 of block B1 of die 3 to die 4, and data pages P12-P20 of the block of die 1 to die 2.

[0083] In one embodiment, since the data weak area of ​​the super block 202 can be regarded as an area where data is unstable, if the space after the invalid area in the super block 202 is sufficient, the flash memory controller 110 copies the data in the data weak area to the space after the invalid area in the super block 202, such as the data page P21 and the subsequent data pages of the block B1 of the die 3 to the die 4; and if the space after the invalid area in the super block 202 is insufficient, the flash memory controller 110 copies the data in the data weak area to other super blocks.

[0084] In one embodiment, since the data in the invalid area of ​​the super block 202 is considered as unusable data, the flash memory controller 110 can double program the invalid area of ​​the super block 202, that is, write invalid data or redundant data into the invalid area to stabilize the super block.

[0085] As described in the above embodiments, this embodiment can efficiently and accurately determine which data in the super block 202 can continue to be used, and migrate data in the weak data area of ​​the super block 202 to ensure data reliability.

[0086] In the above embodiments of FIGS. 7 to 10, after the memory device 100 is powered on again, the flash memory controller 110 will need to determine a check range for determining the last data page that can be successfully read for each block in the super block 202, and the upper edge of the check range is determined based on the number of buffers in the controller buffer 410. However, in some designs, the number of buffers in the controller buffer 410 may be very high. Therefore, if the upper edge of the check range is determined based on the number of buffers in the controller buffer 410, the check range will include a large number of data pages, which may cause the flash memory controller 110 to need to read a large number of data pages to determine the last data page that can be successfully read for each block in the super block 202, thereby affecting the execution efficiency of the memory device 100 after power-on. Therefore, in order to solve the above problem, the present embodiment further proposes a method for limiting the number of buffers in the controller buffer 410 that can be occupied by the data of each grain, so as to avoid the following problems: Figure 7 The problem of the written data pages of different blocks of the super block 202 being too different.

[0087] Specifically, Fig.12 1 is a flow chart of a control method of a memory device 100 according to an embodiment of the present invention. In step 1200, the process starts. In step 1202, the flash memory controller 110 receives a plurality of write requests from the master device 130 and stores the write requests in the buffer request pool 420. In step 1204, the flash memory controller 110 determines whether there is an idle buffer in the current controller buffer 410 according to the content of the free buffer pool 430. If so, the process proceeds to step 1206; if not, the process stays at step 1204 to continue the determination.

[0088] In step 1206, the flash memory controller 110 selects an earliest write request in the buffer request pool 420. In step 1208, the flash memory controller 110 determines whether the number of buffers occupied by the die / block to which the corresponding data of the earliest write request is to be written in the controller buffer 410 is higher than a critical value. If so, the process proceeds to step 1212; if not, the process proceeds to step 1210. In this embodiment, the critical value is any suitable value lower than the total number of buffers in the controller buffer 410. For example, assuming that the controller buffer 410 shown in Figures 4 to 7 includes eight buffers, the critical value can be any suitable value lower than "8", such as 2, 3, 4, 5, etc.

[0089] In step 1210 , the flash memory controller 110 writes the data corresponding to the earliest write request into a buffer of the controller buffer 410 for subsequent writing into the flash memory module 120 .

[0090] In step 1210 , the flash memory controller 110 suspends writing the data corresponding to the earliest write request to the controller buffer 410 , even if the controller buffer 410 includes a buffer in an idle state, and the process returns to step 1208 .

[0091] like Fig.12 As described in the process of FIG. 1 , by using the critical value to limit the number of buffers occupied by each chip / block in the controller buffer 410, the following can be avoided: Figure 7 For example, assuming that the critical value is "2", that is, the controller buffer 410 can store at most two data to be written to the same die / block, then refer to Figure 7 , 13 , after the controller buffer 410 has stored the data D12_3 and D13_3 to be written to the block B1 of the die 3, the data D12_4 cannot be written to the controller buffer 410 before the data D12_3 is transmitted and the buffer space is released. Therefore, if an abnormal power failure occurs at this time, after the memory device 100 is powered on again, the number of the last written data page can be subtracted by "T" at the upper edge of the inspection range determined in step 808, where "T" can be the critical value (that is, the controller buffer 410 can store at most T pens of data to be written to the same die / block).

[0092] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for controlling a flash memory module, wherein the flash memory module comprises a plurality of dies, each of which comprises a plurality of blocks, each of which comprises a plurality of data pages, and the method comprises: After the flash memory module is powered on, determining whether the flash memory module encounters an abnormal power failure before being powered on; If the flash memory module encounters an abnormal power failure before powering on, determining a super block to be written last before powering on the flash memory module, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; Determine the last data page written to the super block; Determine a check range of the super block according to the last data page written into the super block; Reading at least a portion of the data pages within the inspection range to determine the last successfully readable data page of each first block in the super block; Determine a data weak area of ​​the super block according to the last successfully readable data page of each first block in the super block; as well as The data in the data weak area is moved to other areas of the super block or to another super block.

2. The method according to claim 1, characterized in that The step of determining the inspection range of the super block according to the last written data page of the super block comprises: Determining the upper edge of the inspection range according to the number of a plurality of buffers included in a controller buffer, wherein each buffer is used to store data to be written to a single data page; and The lower edge of the inspection range is determined according to the last data page written into the super block.

3. The method according to claim 2, characterized in that The step of determining the upper edge of the inspection range according to the number of the plurality of buffers included in the controller buffer comprises: The upper edge of the inspection range is obtained by subtracting the number of the buffers from the number of the last written data page of the super block.

4. The method according to claim 2, characterized in that The step of determining the upper edge of the inspection range according to the number of the plurality of buffers included in the controller buffer comprises: The serial number of the last written data page of the super block is subtracted from a critical value to obtain the upper edge of the inspection range, wherein the critical value is smaller than the number of the plurality of buffers.

5. The method according to claim 1, characterized in that The step of determining the data weak area of ​​the super block according to the last successfully readable data page of each first block in the super block comprises: According to the last successfully readable data page of each first block in the super block, a data page with a minimum data page number and a corresponding specific first block are determined; Determine the last validly written first block and data page in the super block according to the data page with the smallest data page number and the corresponding specific first block; as well as The data weak area is determined according to the first block and the data page that are last effectively written in the super block.

6. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of dies, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the flash memory controller includes: A read-only memory for storing a program code; a microprocessor, used to execute the program code to control access to the flash memory module; The microprocessor is used to perform the following operations: After the flash memory module is powered on, determining whether the flash memory module encounters an abnormal power failure before being powered on; If the flash memory module encounters an abnormal power failure before powering on, determining a super block to be written last before powering on the flash memory module, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; Determine the last data page written to the super block; Determine a check range of the super block according to the last data page written into the super block; Reading at least a portion of the data pages within the inspection range to determine the last successfully readable data page of each first block in the super block; Determine a data weak area of ​​the super block according to the last successfully readable data page of each first block in the super block; as well as The data in the data weak area is moved to other areas of the super block or to another super block.

7. The flash memory controller according to claim 6, wherein: The step of determining the inspection range of the super block according to the last written data page of the super block comprises: Determining the upper edge of the inspection range according to the number of a plurality of buffers included in a controller buffer, wherein each buffer is used to store data to be written to a single data page; and The lower edge of the inspection range is determined according to the last data page written into the super block.

8. The flash memory controller according to claim 7, wherein: The step of determining the upper edge of the inspection range according to the number of the plurality of buffers included in the controller buffer comprises: The upper edge of the inspection range is obtained by subtracting the number of the buffers from the number of the last written data page of the super block.

9. The flash memory controller according to claim 7, wherein: The step of determining the upper edge of the inspection range according to the number of the plurality of buffers included in the controller buffer comprises: The serial number of the last written data page of the super block is subtracted from a critical value to obtain the upper edge of the inspection range, wherein the critical value is smaller than the number of the plurality of buffers.

10. The flash memory controller according to claim 6, wherein: The step of determining the data weak area of ​​the super block according to the last successfully readable data page of each first block in the super block comprises: According to the last successfully readable data page of each first block in the super block, a data page with a minimum data page number and a corresponding specific first block are determined; Determine the last validly written first block and data page in the super block according to the data page with the smallest data page number and the corresponding specific first block; as well as The data weak area is determined according to the first block and the data page that are last effectively written in the super block.

11. A memory device comprising: A flash memory module comprising a plurality of dies, each of which comprises a plurality of blocks, each of which comprises a plurality of data pages; and a flash memory controller for accessing the flash memory module; The flash memory controller performs the following operations: After the flash memory module is powered on, determining whether the flash memory module encounters an abnormal power failure before being powered on; If the flash memory module encounters an abnormal power failure before powering on, determining a super block to be written last before powering on the flash memory module, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; Determine the last data page written to the super block; Determine a check range of the super block according to the last data page written into the super block; Reading at least a portion of the data pages within the inspection range to determine the last successfully readable data page of each first block in the super block; Determine a data weak area of ​​the super block according to the last successfully readable data page of each first block in the super block; as well as The data in the data weak area is moved to other areas of the super block or to another super block.

12. The memory device according to claim 11, characterized in that The step of determining the inspection range of the super block according to the last written data page of the super block comprises: Determining the upper edge of the inspection range according to the number of a plurality of buffers included in a controller buffer, wherein each buffer is used to store data to be written to a single data page; and The lower edge of the inspection range is determined according to the last data page written into the super block.

13. The memory device according to claim 12, characterized in that The step of determining the upper edge of the inspection range according to the number of the plurality of buffers included in the controller buffer comprises: The upper edge of the inspection range is obtained by subtracting the number of the buffers from the number of the last written data page of the super block.

14. The memory device according to claim 12, wherein: The step of determining the upper edge of the inspection range according to the number of the plurality of buffers included in the controller buffer comprises: The serial number of the last written data page of the super block is subtracted from a critical value to obtain the upper edge of the inspection range, wherein the critical value is smaller than the number of the plurality of buffers.

15. The memory device according to claim 11, characterized in that The step of determining the data weak area of ​​the super block according to the last successfully readable data page of each first block in the super block comprises: According to the last successfully readable data page of each first block in the super block, a data page with a minimum data page number and a corresponding specific first block are determined; Determine the last validly written first block and data page in the super block according to the data page with the smallest data page number and the corresponding specific first block; as well as The data weak area is determined according to the first block and the data page that are last effectively written in the super block.

16. A method for controlling a flash memory module, wherein the flash memory module comprises a plurality of dies, each die comprises a plurality of blocks, each block comprises a plurality of data pages, and the method comprises: Selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; configuring a controller buffer, wherein the controller buffer includes a plurality of buffers, and each buffer is used to store data to be written to a single data page; receiving a plurality of read requests from a master device and sequentially storing the plurality of read requests in a buffer request pool; Selecting an earliest write request from the buffer request pool; Determine whether the number of buffers occupied by the first block of the die to be written by the corresponding data of the earliest write request in the controller buffer is higher than a critical value; If the number of buffers occupied by the first block of the die to which the data corresponding to the earliest write request is to be written in the controller buffer is higher than the critical value, the writing of the data corresponding to the earliest write request into the controller buffer is stopped.

17. The method according to claim 16, characterized in that The critical value is less than the number of the plurality of buffers.

18. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprises a plurality of dies, each of the dies comprises a plurality of blocks, each of the blocks comprises a plurality of data pages, and the flash memory controller comprises: A read-only memory for storing a program code; a microprocessor, used to execute the program code to control access to the flash memory module; The microprocessor is used to perform the following operations: Selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; configuring a controller buffer, wherein the controller buffer includes a plurality of buffers, and each buffer is used to store data to be written to a single data page; receiving a plurality of read requests from a master device and sequentially storing the plurality of read requests in a buffer request pool; Selecting an earliest write request from the buffer request pool; Determine whether the number of buffers occupied by the first block of the die to be written by the corresponding data of the earliest write request in the controller buffer is higher than a critical value; If the number of buffers occupied by the first block of the die to which the data corresponding to the earliest write request is to be written in the controller buffer is higher than the critical value, the writing of the data corresponding to the earliest write request into the controller buffer is stopped.

19. The flash memory controller according to claim 18, wherein: The critical value is less than the number of the plurality of buffers.

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