Display panel and display device

Abstract

This application provides a display panel and a display device, solving the problem of large bezel size in existing display panels. The display panel has a display area and a bezel area at least partially surrounding the display area. The bezel area includes a first bezel area, a curved corner bezel area, and a second bezel area connected sequentially. The display panel includes a first gate driving circuit located in the bezel area. The first gate driving circuit includes a plurality of first gate driving units, and the distance between two adjacent first gate driving units in the second bezel area and the curved corner bezel area is greater than the distance between two adjacent first gate driving units in the curved corner bezel area.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a display device. Background Technology

[0002] Currently, displays typically use rounded corners. Due to the circuit layout, the rounded corner bezel area requires a larger area than the straight bezel area, resulting in a wider rounded corner bezel area than the straight bezel area, which is not conducive to achieving narrow bezels. Summary of the Invention

[0003] In view of this, the present application provides a display panel and a display device, which solves the problem of large bezel size of the display panel in the prior art.

[0004] The first aspect of this application provides a display panel having a display area and a border area at least partially surrounding the display area. The border area includes a first border area, an arc-corner border area, and a second border area connected in sequence. The display panel includes a first gate driving circuit located in the border area. The first gate driving circuit includes a plurality of first gate driving units, wherein the distance between two adjacent first gate driving units in the second border area and the arc-corner border area is greater than the distance between two adjacent first gate driving units in the arc-corner border area.

[0005] In conjunction with the first aspect, in some possible implementations, both the first border area and the second border area are straight borders; preferably, the number of first gate driving units in the second border area is less than the number of first gate driving units in the arc-corner border area; preferably, multiple first gate driving units are cascaded sequentially along the circumference of the display area; preferably, the first gate driving circuit includes either a light-emitting driving circuit or a scanning driving circuit.

[0006] In conjunction with the first aspect, in some possible implementations, the display panel further includes a second gate driving circuit located in the bezel area and on the side of the first gate driving circuit that is close to or far from the display area; preferably, the second gate driving circuit includes a plurality of second gate driving units arranged sequentially along the circumference of the display area; preferably, the arc-corner bezel area includes a first sub-area close to the first bezel area and a second sub-area close to the second bezel area; in the circumference of the display area, the second gate driving units of the first sub-area and the second gate driving units of the second sub-area are staggered; preferably, the number of second gate driving units in the second sub-area is equal to the number of first gate driving units in the second bezel area; preferably, the plurality of second gate driving units are cascaded sequentially along the circumference of the display area; preferably, the second gate driving circuit includes either a light-emitting driving circuit or a scanning driving circuit; preferably, the second gate driving circuit includes a first scanning driving circuit.

[0007] In conjunction with the first aspect, in some possible implementations, the display panel further includes a third gate driving circuit located in the bezel area and on the side of the second gate driving circuit away from the first gate driving circuit; preferably, the third gate driving circuit includes a plurality of third gate driving units arranged sequentially along the circumference of the display area; preferably, the arc-corner bezel area includes a first sub-area near the first bezel area and a second sub-area near the second bezel area; in the circumference of the display area, the third gate driving units of the first sub-area and the third gate driving units of the second sub-area are staggered; preferably, the number of third gate driving units in the second sub-area is equal to the number of first gate driving units in the second bezel area; or, the sum of the number of third gate driving units in the second bezel area and the third gate driving units in the second sub-area is equal to the number of first gate driving units in the second bezel area; preferably, the plurality of third gate driving units are cascaded sequentially along the circumference of the display area; preferably, the third gate driving circuit includes either a light-emitting driving circuit or a scanning driving circuit; preferably, the third gate driving circuit includes a second scanning driving circuit.

[0008] In conjunction with the first aspect, in some possible implementations, the first gate driving circuit further includes at least one redundant first gate driving unit; the display panel further includes sub-pixels located in the display area, the first gate driving unit is electrically connected to the sub-pixels, and the redundant first gate driving unit is not electrically connected to the sub-pixels; at least some of the redundant first gate driving units are located in the second border area and are located on at least one side of the first gate driving unit in the circumferential direction of the display area; preferably, some of the redundant first gate driving units are located in the arc corner border area and are located on the side of the first gate driving unit closer to the second border area.

[0009] In conjunction with the first aspect, in some possible implementations, the display panel further includes a second gate driving circuit located on the side of the first gate driving circuit near or away from the display area; the second gate driving circuit includes a plurality of second gate driving units arranged sequentially along the circumference of the display area and at least one redundant second gate driving unit, the second gate driving units being electrically connected to sub-pixels, and the redundant second gate driving units not being electrically connected to sub-pixels; at least one redundant second gate driving unit is located in the arc-corner bezel area and is located on the side of the second gate driving unit near the second bezel area; preferably, the arc-corner bezel area includes a first sub-area near the first bezel area and a second sub-area near the second bezel area; in the circumference of the display area, the second gate driving units of the first sub-area and the second gate driving units of the second sub-area are staggered; preferably, the second bezel area is provided with at least one redundant second gate driving unit; preferably, in the second bezel area, the number of redundant second gate driving units is equal to the sum of the number of first gate driving units and redundant first gate driving units.

[0010] In conjunction with the first aspect, in some possible implementations, the display panel further includes a third gate driving circuit located on the side of the second gate driving circuit close to or far from the first gate driving circuit; the third gate driving circuit includes a plurality of third gate driving units arranged sequentially along the circumference of the display area and at least one redundant third gate driving unit; the redundant third gate driving unit is not electrically connected to the sub-pixel, and the third gate driving unit is electrically connected to the sub-pixel; at least one redundant third gate driving unit is located in the arc-corner bezel area and is located on the side of the third gate driving unit close to the second bezel area; preferably, in the arc-corner bezel area, the second gate driving unit and the third gate driving unit... The number of gate driving units in the arc-corner frame area and the sum of the number of gate driving units in the arc-corner frame area and the number of gate driving units in the arc-corner frame area are equal; preferably, the arc-corner frame area includes a first sub-region near the first frame area and a second sub-region near the second frame area; in the circumferential direction of the display area, the third gate driving units in the first sub-region and the third gate driving units in the second sub-region are staggered; preferably, in the second straight frame area, the sum of the number of first gate driving units and redundant first gate driving units, the sum of the number of second gate driving units and redundant second gate driving units, and the number of redundant third gate driving units are equal.

[0011] In conjunction with the first aspect, in some possible implementations, the display panel further includes a first gate line and a gate connection line; the first gate line is located in the display area, and the gate connection line connects the first gate line and the first gate driving unit in the second bezel area; the gate connection line includes a first sub-connection line, the portion of the first sub-connection line located in the display area extending in the same direction as the first gate line, and the orthographic projection of the first sub-connection line on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the first gate driving unit on the substrate; preferably, the portion of the first sub-connection line located in the bezel area is electrically connected to the first gate line through at least one wire-changing hole; preferably The display panel further includes a second gate line and a third gate line located in the display area. The portion of the first sub-connecting line located in the display area, the second gate line, the first gate line, and the third gate line are arranged sequentially on the substrate by their respective orthogonal projections. Preferably, the first gate line, the second gate line, and the third gate line are disposed in the same layer. Preferably, the first sub-connecting line and the first gate line are disposed in different layers. Preferably, the display panel further includes a second initialization signal line, at least a portion of which is collinear with the first sub-connecting line. Preferably, the first gate line includes a light-emitting line, the second gate line includes a fourth scan line, and the third gate line includes a second scan line.

[0012] In conjunction with the first aspect, in some possible implementations, the display panel further includes a shielding line located on the side of the first sub-connecting line closer to the substrate; the orthographic projection of the first sub-connecting line on the substrate and the orthographic projection of the shielding line on the substrate at least partially overlap; preferably, the shielding line is multiplexed as a first initialization signal line.

[0013] In conjunction with the first aspect, in some possible implementations, the first sub-connection lines of the multiple gate connection lines are located at the first end of the display area corresponding to the sub-pixels, and the orthographic projection of the first end on the substrate overlaps with the orthographic projection of the corresponding sub-pixel on the substrate. The sub-pixels corresponding to the first ends of adjacent first sub-connection lines are located in adjacent rows and adjacent columns; or, the orthographic projection of the first sub-connection lines on the substrate passes through the orthographic projection of at least one sub-pixel on the substrate; the number of orthographic projections of sub-pixels through which the orthographic projections of at least some of the first sub-connection lines pass is equal; preferably, the number of orthographic projections of sub-pixels through which the orthographic projections of at least some of the adjacent odd-numbered and even-numbered first sub-connection lines pass is equal.

[0014] In conjunction with the first aspect, in some possible implementations, the gate connection line further includes a second sub-connection line, which is electrically connected to the end of the first sub-connection line away from the first gate line; the extension directions of the second sub-connection line and the first sub-connection line intersect; preferably, the end of the second sub-connection line away from the first sub-connection line is electrically connected to the first gate driving unit; preferably, the second sub-connection line and the first sub-connection line are disposed on different layers; preferably, the second sub-connection line and the first gate line are disposed on different layers; preferably, the display panel further includes low-voltage power lines, at least some of which are co-linear with the second sub-connection line; preferably, the display panel further includes multiple data lines, with the second sub-connection line located between adjacent data lines; preferably, adjacent odd-numbered and even-numbered second sub-connection lines are connected to the same first gate driving unit.

[0015] In conjunction with the first aspect, in some possible implementations, the second sub-connecting lines of the multiple gate interconnecting lines are located at the second end of the display area corresponding to the sub-pixels, and the orthographic projection of the second end on the substrate overlaps with the orthographic projection of the corresponding sub-pixel on the substrate. The sub-pixels corresponding to adjacent second sub-connecting lines are located in adjacent rows and adjacent columns; or, the orthographic projection of the second sub-connecting lines on the substrate passes through the orthographic projection of at least one sub-pixel on the substrate; the number of orthographic projections of sub-pixels through which the orthographic projections of at least some of the second sub-connecting lines pass is equal; preferably, the number of orthographic projections of sub-pixels through which the orthographic projections of at least some of the adjacent odd-numbered and even-numbered second sub-connecting lines pass is equal.

[0016] In conjunction with the first aspect, in some possible implementations, the arc-corner bezel area includes a first sub-region near the first bezel area and a second sub-region near the second bezel area, and the first gate driving units of the arc-corner bezel area are all located in the first sub-region; preferably, the display panel further includes a second gate driving circuit and a third gate driving circuit, with a portion of the second gate driving circuit and a portion of the third gate driving circuit located in the second sub-region; the first gate driving circuit further includes multiple signal lines, which are connected to the first gate driving units; the orthographic projection of the signal lines on the substrate and the orthographic projections of the second and third gate driving circuits in the second sub-region on the substrate do not overlap; preferably, the multiple signal lines include multiple clock signal lines; the display panel further includes low-voltage power supply traces, which are located on the side of the clock signal lines away from the substrate; the low-voltage power supply traces include multiple vias, and the overlap area of ​​the orthographic projections of different clock signal lines on the substrate and the orthographic projections of the vias on the substrate is the same.

[0017] In conjunction with the first aspect, in some possible implementations, the display panel further includes a bonding area located on the side of the bezel area away from the display area; the first gate driving circuit further includes multiple signal lines, including input signal lines, which include a first sub-input line, a second sub-input line, and a third sub-input line; the first sub-input line extends from the bonding area to the second sub-area, the second sub-input line connects one end of the first sub-input line located in the second sub-area to the first gate driving unit of the first sub-area, and the third sub-input line connects one end of the first sub-input line located in the second sub-area to the first gate driving unit of the first bezel area; preferably, the orthographic projection of the third sub-input line on the substrate and the orthographic projection of the first sub-input line on the substrate do not overlap at least partially.

[0018] In conjunction with the first aspect, in some possible implementations, the width of the border area is equal in different positions.

[0019] A second aspect of this application provides another display panel having a display area and a border area surrounding the display area. The border area includes a first border area and a second border area, which are spaced apart. The display panel includes: a first gate driving circuit located in the border area; the first gate driving circuit includes a plurality of first gate driving units and at least one redundant first gate driving unit; at least some of the redundant first gate driving units are disposed on at least one side of the first gate driving unit in the first border area; and sub-pixels located in the display area; the redundant first gate driving units are not electrically connected to the sub-pixels, and all the first gate driving units are electrically connected to the sub-pixels.

[0020] In conjunction with the second aspect, in some possible implementations, a redundant first gate driving unit is provided on at least one side of the first gate driving unit of the second frame region; preferably, the first frame region and the second frame region are connected through an arc-corner frame region; preferably, a redundant first gate driving unit is provided on at least one side of the first gate driving unit of the arc-corner frame region.

[0021] A third aspect of this application provides a display device, including the display panel provided in any of the above embodiments.

[0022] According to the display panel and display device provided in the embodiments of this application, a portion of the first gate driving unit in the arc-corner bezel area is externalized to the second bezel area. This reduces the area occupied by the arc-corner bezel area, thereby facilitating a smaller arc-corner bezel size and ultimately enabling the implementation of a narrow bezel. Furthermore, the display panel provided in this embodiment only externalizes a portion of the first gate driving circuit in the arc-corner bezel area to the second bezel area, rather than externalizing all of the first gate driving circuit in the arc-corner bezel area. Comparatively, the former can ensure more optimized space utilization in the bezel area while maintaining a consistent width throughout, avoiding space waste. Attached Figure Description

[0023] Figure 1 This is a top view of a display panel provided in an embodiment of this application.

[0024] Figure 2 Provided for the first embodiment Figure 1 An enlarged view of the first partial area of ​​the display panel shown.

[0025] Figure 3 The circuit diagram of the first gate drive circuit in the display panel shown in Figure 1 is shown.

[0026] Figure 4 A circuit diagram of a sub-pixel provided in an embodiment of this application.

[0027] Figure 5 Provided for the second embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0028] Figure 6 Provided for the third embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0029] Figure 7 Provided for the fourth embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0030] Figure 8 Provided for the fifth embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0031] Figure 9 Provided for the sixth embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0032] Figure 10 Provided for the seventh embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0033] Figure 11 A circuit diagram of a first gate drive circuit provided for another embodiment.

[0034] Figure 12 Provided for the eighth embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0035] Figure 13 Provided for the ninth embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0036] Figure 14 Provided for the tenth embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0037] Figure 15 Provided for the eleventh embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0038] Figure 16 Provided for the twelfth embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0039] Figure 17 Provided for the thirteenth embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0040] Figure 18 Provided for the fourteenth embodiment Figure 1 A magnified view of a portion of the display panel shown.

[0041] Figure 19 Provided for the fifteenth embodiment of this application Figure 1 The diagram shows the wiring layout of a partial area of ​​the display panel.

[0042] Figure 20 for Figure 19 An enlarged view of the first partial area of ​​the display panel shown.

[0043] Figure 21 for Figure 19 An enlarged view of the second partial area of ​​the display panel shown.

[0044] Figure 22 for Figure 19 An enlarged view of the third partial area of ​​the display panel shown.

[0045] Figure 23 Provided for the sixteenth embodiment of this application Figure 1 The diagram shows the wiring layout of a partial area of ​​the display panel.

[0046] Figure 24 Provided for the seventeenth embodiment of this application Figure 1 The diagram shows the wiring layout of a partial area of ​​the display panel.

[0047] Figure 25 Provided for the eighteenth embodiment of this application Figure 1 The diagram shows the wiring layout of a partial area of ​​the display panel.

[0048] Figure 26 for Figure 1 An enlarged view of the second partial area of ​​the display panel shown.

[0049] Figure 27 for Figure 26 An enlarged view of the first partial area of ​​the display panel shown.

[0050] Figure 28 for Figure 26 An enlarged view of the second partial area of ​​the display panel shown.

[0051] Figure 29 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a structure is referred to as being "on" or "below" another structure, the structure may be directly on or below the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. Structures referred to herein include any of the following: membrane, element, device, component, assembly.

[0054] When a structure is referred to as being “connected” to another structure, it can be directly connected to the other structure or indirectly connected to the other structure by means of one or more intermediate structures placed between them.

[0055] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0056] In this specification, the term "same-layer arrangement" refers to a structure formed by two (or more) structures through the same patterning process, and their materials may be the same or different.

[0057] With the development of OLED display technology, the demand for narrow bezels is increasing. The display area boundary includes the curved boundary, and the bezel area includes the arc-shaped bezel area located outside the curved boundary. The circuit structure within the arc-shaped bezel area is arranged in an arc shape, occupying a large space, which makes it impossible to achieve narrow bezels in display products.

[0058] To further achieve a narrow bezel, embodiments of this application provide a display panel and a display device. By transferring a portion of the gate driving units in the arc-corner bezel area to the straight bezel area, the area occupied by the arc-corner bezel area is reduced, which is beneficial for achieving a narrow bezel.

[0059] Figure 1 This is a top view of a display panel provided in an embodiment of this application. Figure 2 Provided for the first embodiment Figure 1 An enlarged view of the first partial area of ​​the display panel shown. Figure 2 It shows Figure 1 A magnified view of the first local region P1. Combined with... Figure 1 and Figure 2 As shown, the display panel has a display area AA and a bezel area NA surrounding the display area AA. The bezel area NA includes a first bezel area L1A, a curved bezel area SA, and a second bezel area L2A connected in sequence. For example, both the first bezel area L1A and the second bezel area L2A are straight bezels, and the display area AA includes a first straight boundary L1, a curved boundary S, and a second straight boundary L2 connected in sequence. The first bezel area L1A is located outside the first straight boundary L1, the curved bezel area SA is located outside the curved boundary S, and the second bezel area L2A is located outside the second straight boundary L2.

[0060] The display panel includes a first gate driving circuit G1. The first gate driving circuit G1 is located in the bezel area NA. The first gate driving circuit G1 includes a plurality of first gate driving units G1i, i = 1, 2, 3...n, where n is any positive integer. The distance between two adjacent first gate driving units G1i between the second bezel area L2A and the arc-corner bezel area SA is greater than the distance between two adjacent first gate driving units G1i within the arc-corner bezel area SA.

[0061] For example, a plurality of first gate driving units G1i in the first gate driving circuit G1 are arranged sequentially along the circumference of the display area AA. The arc-corner bezel area SA includes a first sub-area SA1 near the first bezel area L1A and a second sub-area SA2 near the second bezel area L2A. A first portion of the first gate driving units G1i is located in the first sub-area SA1, and a second portion of the first gate driving units G1i is located in the second bezel area L2A. The length of the second sub-area SA2 in the circumferential direction of the display area AA is greater than the spacing between adjacent first gate driving units G1i in the second bezel area L2A and the spacing between adjacent first gate driving units G1i in the first sub-area SA1. This is equivalent to externalizing the last few stages of the first gate driving units G1i of the first gate driving circuit G1 corresponding to the second sub-area SA2 in the second bezel area L2A.

[0062] This reduces the area occupied by the second sub-region SA2, thereby facilitating the reduction of the size of the curved corner bezel region SA and thus enabling the realization of a narrow bezel. Meanwhile, the display panel provided in this embodiment only externalizes a portion of the first gate driving circuit G1 of the curved corner bezel region SA to the second bezel region L2A, rather than externalizing all of the first gate driving circuit G1 of the curved corner bezel region SA. Comparatively, the former can ensure more optimized space utilization in the bezel region NA while maintaining a consistent width throughout the bezel region NA, thus avoiding space waste.

[0063] In one embodiment, such as Figure 2 As shown, the number of first gate driving units G1i in the second border region L2A is less than the number of first gate driving units G1i in the arc-corner border region SA.

[0064] In one embodiment, such as Figure 2 As shown, the third part, the first gate drive circuit G1, is located in the first border area L1A.

[0065] Figure 3 This is a circuit diagram of the first gate drive circuit in the display panel shown in Figure 1. Figure 3As shown, multiple first gate driving units G1i in the first gate driving circuit G1 are cascaded sequentially in the circumferential direction of the display area AA. The first gate driving circuit G1 can generate scan signals and / or light emission signals by receiving clock signals (e.g., a first clock signal transmitted through a first clock signal line CLK1 and a second clock signal transmitted through a second clock signal line CLK2), a start signal SSP, etc., from a timing controller, and can generate scan signals and / or light emission signals by sequentially transmitting the start signal to the next stage circuit under the control of the clock signal. For example, the first gate driving unit G1i includes a shift register.

[0066] like Figure 2 As shown, the display panel also includes a sub-pixel 20 located in the display area AA. A first gate driving circuit G1 is electrically connected to the sub-pixel 20 and is used to provide the generated scanning signal and / or light emission signal to the sub-pixel 20.

[0067] Figure 4 This is a circuit diagram of a sub-pixel provided in one embodiment of this application. (In conjunction with...) Figure 2 and Figure 4 As shown, sub-pixel 20 includes an electrically connected pixel circuit 21 and a light-emitting device 22. The pixel circuit may be, for example, a 7T1C or 8T1C. The light-emitting device 22 may be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot light-emitting diode (QLED), or the like. The light-emitting device 22 may be a light-emitting device of various colors, such as a red light-emitting device R, a green light-emitting device G, and a blue light-emitting device B.

[0068] Taking the 8T1C pixel circuit as an example, such as Figure 4As shown, the pixel circuit 21 includes eight transistors and one capacitor C. The first terminal of the first transistor T1 is connected to the second terminal of the fifth transistor T5, the second terminal of the first transistor T1 is connected to the first terminal of the sixth transistor T6, and the control terminal of the first transistor T1 is connected to the first terminal of the capacitor C. The first terminal of the second transistor T2 is connected to the data line Data, the second terminal of the second transistor T2 is connected to the first terminal of the first transistor T1, and the control terminal of the second transistor T2 is connected to the second scan line S2. The first terminal of the third transistor T3 is connected to the control terminal of the first transistor T1, the second terminal of the third transistor T3 is connected to the second terminal of the first transistor T1, and the control terminal of the third transistor T3 is connected to the third scan line S3. The first terminal of the fourth transistor T4 is connected to the second terminal of the first transistor T1, the second terminal of the fourth transistor T4 is connected to the first initialization signal line Vref1, and the control terminal of the fourth transistor T4 is connected to the first scan line S1. The first terminal of the fifth transistor T5 is connected to the high-voltage power supply line Elvdd, the second terminal of the fifth transistor T5 is connected to the first terminal of the first transistor T1, and the control terminal of the fifth transistor T5 is connected to the light-emitting line Em. The first terminal of the sixth transistor T6 is connected to the second terminal of the first transistor T1. The second terminal of the sixth transistor T6 is connected to the first terminal of the light-emitting device 22. The control terminal of the sixth transistor T6 is connected to the light-emitting line Em. The first terminal of the seventh transistor T7 is connected to the first terminal of the light-emitting device 22. The second terminal of the seventh transistor T7 is connected to the second initialization signal line Vref2. The control terminal of the seventh transistor T7 is connected to the fourth scan line S4. The first terminal of the eighth transistor T8 is connected to the second terminal of the first transistor T1. The second terminal of the eighth transistor T8 is connected to the third initialization signal line Vref3. The control terminal of the eighth transistor T8 is connected to the fourth scan line S4. The second terminal of capacitor C is connected to the high-voltage power supply line Elvdd. The second terminal of the light-emitting device 22 is connected to the low-voltage power supply line Elvss.

[0069] For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors. The third transistor T3 and the fourth transistor T4 are N-type transistors.

[0070] The first gate driving circuit G1 includes either a light-emitting driving circuit or a scanning driving circuit.

[0071] In one embodiment, the first gate driving circuit G1 can be a light-emitting driving circuit. In this case, the first gate driving circuit G1 is connected to the light-emitting line Em to generate a light-emitting signal and provide it to the sub-pixel.

[0072] In one embodiment, the first gate drive circuit G1 may be a first scan drive circuit. The first scan drive circuit is used to provide a scan signal to the N-type transistor. For example, for... Figure 4In the pixel circuit shown, the first gate driving circuit G1 is connected to the first scan line S1 and the third scan line S3.

[0073] In one embodiment, the first gate drive circuit G1 can be a second scan drive circuit. The second scan drive circuit is used to provide a scan signal to the P-type transistor. For example, for... Figure 4 In the pixel circuit shown, the first gate drive circuit G1 is connected to the second scan line S2 and the fourth scan line S4.

[0074] Substrate 10 is a substrate. In some embodiments, the substrate may include an organic resin material such as epoxy resin, triazine, silicone resin, or polyimide. For example, the substrate may be an FR4 type printed circuit board (PCB), or a flexible PCB that is easily deformable. In some embodiments, the substrate may include a ceramic material such as silicon nitride, aluminum nitride, or aluminum oxide, or include a metal or metal compound. For example, the substrate may be a metal core PCB (MCPCB) or a metal-base copper-clad laminate (MCCL).

[0075] Figure 5 Provided for the second embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 5 As shown, the display panel and provided in this embodiment Figure 2 The difference in the display panel shown is that, in this embodiment, the display panel further includes a second gate driving circuit G2, which is located in the bezel area NA and on the side of the first gate driving circuit G1 that is close to or far from the display area AA.

[0076] In one embodiment, the second gate driving circuit G2 includes a plurality of second gate driving units G2j arranged sequentially along the circumference of the display area AA. A first portion of the second gate driving units G2j is located in the second sub-area SA2.

[0077] In one embodiment, the second gate driving unit G2j of the second part is located in the first sub-region SA1.

[0078] In one embodiment, the third part, the second gate driving unit G2j, is located in the first border region L1A.

[0079] In one embodiment, the number of second gate driving units G2j in the second sub-region SA2 is equal to the number of first gate driving units G1i in the second border region L2A.

[0080] In one embodiment, multiple second gate driving units G2j are cascaded together along the circumference of the display area AA.

[0081] In one embodiment, the second gate driving circuit includes either a light-emitting driving circuit or a scan driving circuit. For example, the first gate driving circuit G1 includes a light-emitting driving circuit connected to the light-emitting line Em. The second gate driving circuit G2 includes a first scan driving circuit connected to the first scan line S1 and the third scan line S3.

[0082] Figure 6 Provided for the third embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 5 As shown, the display panel and provided in this embodiment Figure 5 The difference in the display panel shown is that, in this embodiment, the second gate driving unit G2j of the first sub-region SA1 and the second gate driving unit G2j of the second sub-region SA2 are staggered in the circumferential direction of the display area AA.

[0083] For example, multiple virtual concentric rings are centered on the centroid of the display area AA, and these virtual concentric rings are located in the bezel area NA. The second gate driving unit G2j of the second bezel area L2A is located on one concentric ring, and the second gate driving unit G2j of the second sub-area SA2 is located on another concentric ring. It should be noted that the shape of the virtual concentric rings mentioned here is adapted to the edge shape of the display area AA, for example, it is a rounded rectangle.

[0084] In one embodiment, the plurality of virtual concentric rings include a first concentric ring, a second concentric ring, and a third concentric ring arranged sequentially along a direction away from the display area AA. The second gate driving unit G2j of the first sub-region SA1 is arranged along the first concentric ring, the second gate driving unit G2j of the second sub-region SA2 is arranged along the second concentric ring, and the first gate driving unit G1i of the first sub-region SA1 is arranged along the third concentric ring.

[0085] According to the display panel provided in this embodiment, by setting the second gate driving unit G2j of the first sub-region SA1 and the second gate driving unit G2j of the second sub-region SA2 in the circumferential direction of the display area AA, it is beneficial to improve the uniformity of the circuit structure.

[0086] Figure 7 Provided for the fourth embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 7 The display panel shown and Figure 6The difference in the display panel shown is that, in this embodiment, the display panel further includes a third gate driving circuit G3. The third gate driving circuit G3 is located in the bezel area NA and is located on the side of the second gate driving circuit G2 that is close to or far from the first gate driving circuit G1. For example, in the direction close to the display area AA, the first gate driving circuit G1, the second gate driving circuit G2, and the third gate driving circuit G3 are arranged sequentially.

[0087] In one embodiment, the third gate driving circuit G3 includes a plurality of third gate driving units G3m arranged sequentially along the circumference of the display area AA, and the first portion of the third gate driving units G3m is located in the second sub-area SA2.

[0088] In one embodiment, the second part of the third gate driving unit G3m is located in the first sub-region SA1.

[0089] In one embodiment, the third gate driving unit G3m of the third part is located in the first border region L1A.

[0090] In one embodiment, the number of third gate driving units G3m in the second sub-region SA2 is equal to the number of first gate driving units G1i in the second border region L2A.

[0091] In one embodiment, the third gate driving circuit G3 includes either a light-emitting driving circuit or a scanning driving circuit. Exemplarily, the first gate driving circuit G1 includes a light-emitting driving circuit connected to a light-emitting line Em. The second gate driving circuit G2 includes a first scanning driving circuit connected to a first scan line S1 and a third scan line S3. The third gate driving circuit G3 includes a second scanning driving circuit connected to a second scan line S2 and a fourth scan line S4.

[0092] Figure 8 Provided for the fifth embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 8 The display panel shown and Figure 7 The difference in the display panel shown is that, in this embodiment, the third gate driving unit G3m of the first sub-region SA1 and the third gate driving unit G3m of the second sub-region SA2 are staggered in the circumferential direction of the display area AA.

[0093] In one embodiment, a plurality of virtual concentric rings are centered on the centroid of the display area AA, and these virtual concentric rings are located in the bezel area NA. The plurality of virtual concentric rings include a fifth concentric ring, a fourth concentric ring, a first concentric ring, a second concentric ring, and a third concentric ring arranged sequentially along a direction away from the display area AA. The second gate driving unit G2j of the second bezel area L2A is arranged along the fifth concentric ring, and the second gate driving unit G2j of the second sub-area SA2 is arranged along the fourth concentric ring. The second gate driving unit G2j of the first sub-area SA1 is arranged along the first concentric ring, the second gate driving unit G2j of the second sub-area SA2 is arranged along the second concentric ring, and the first gate driving unit G1i of the first sub-area SA1 is arranged along the third concentric ring.

[0094] Figure 9 Provided for the sixth embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 9 The display panel shown and Figure 7 , Figure 8 The difference in the display panel shown is that, in this embodiment, it uses... Figure 8 Taking the display panel shown as an example, the third gate driving unit G3m in the fourth part is located in the second bezel area L2A. The sum of the number of third gate driving units G3m in the second bezel area L2A and the number of third gate driving units G3m in the second sub-area SA2 is equal to the number of first gate driving units G1i in the second bezel area L2A. In this case, the number of circuit structures gradually decreases in the direction from the second sub-area SA2 to the second bezel area L2A, thereby better adapting to the transition from the curved corner bezel area SA to the second bezel area L2A and further improving the space utilization of the curved corner bezel area SA.

[0095] Figure 10 Provided for the seventh embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 10 The display panel shown and Figure 2 The difference in the display panel shown is that, in this embodiment, the first gate driving circuit G1 further includes at least one redundant first gate driving unit G10. The difference between the first gate driving unit G1i and the redundant first gate driving unit G10 is that the first gate driving unit G1i is electrically connected to the sub-pixel 20, while the redundant first gate driving unit G10 is not electrically connected to the sub-pixel 20. At least a portion of the redundant first gate driving unit G10 is located in the second border region L2A, and is located on at least one side of the first gate driving unit G1i in the circumferential direction of the display area AA.

[0096] For example, the second frame region L2A is provided with a plurality of first gate driving units G1i, and at least one redundant first gate driving unit G10 is provided on the side of the plurality of first gate driving units G1i close to the arc corner frame region SA; and / or, at least one redundant first gate driving unit G10 is provided on the side of the plurality of first gate driving units G1i away from the arc corner frame region SA.

[0097] In one embodiment, a partially redundant first gate driving unit G10 is located in the arc-corner border region SA and on the side of the first gate driving unit G1i close to the second border region L2A.

[0098] According to the display panel provided in this embodiment, by setting redundant first gate driving units G10, the circuit structure on both sides of any first gate driving unit G1i is consistent, avoiding the difference in circuit structure caused by inconsistent etching degree in the process due to inconsistent circuit structure, thereby improving the structural uniformity of the first gate driving unit G1i and thus improving the display effect.

[0099] Figure 11 A circuit diagram of a first gate drive circuit provided for another embodiment. (See diagram below.) Figure 11 As shown, among the multiple first gate driving units G1i arranged sequentially along the circumference of the display area AA, the preceding and following first gate driving units G1i of the redundant first gate driving unit G10 are cascaded. The redundant first gate driving unit G10 is not connected to any input signal lines, such as the first clock signal line CLK1, the second clock signal line CLK2, or the output terminal of the previous stage. The redundant first gate driving unit G10 is also not connected to any output signal lines, such as scan lines, and therefore is not electrically connected to the sub-pixel 20.

[0100] Figure 12 Provided for the eighth embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 12 The display panel shown and Figure 10 The difference in the display panel shown is that, in this embodiment, the display panel further includes a second gate driving circuit G2. The second gate driving circuit G2 is located on the side of the first gate driving circuit G1 that is closer to or farther from the display area AA. The second gate driving circuit G2 includes a plurality of second gate driving units G2j arranged sequentially along the circumference of the display area AA and at least one redundant second gate driving unit G20. The difference between the redundant second gate driving unit G20 and the second gate driving unit G2j is that the redundant second gate driving unit G20 is not electrically connected to the sub-pixel 20, while the second gate driving unit G2j is electrically connected to the sub-pixel 20. At least one redundant second gate driving unit G20 is located in the arc-corner bezel area SA and is located on the side of the second gate driving unit G2j that is closer to the second bezel area L2A.

[0101] According to the display panel provided in this embodiment, by setting redundant second gate driving units G20, the circuit structure on both sides of any second gate driving unit G2j is consistent, avoiding the difference in circuit structure caused by inconsistent etching degree in the process due to inconsistent circuit structure, thereby improving the structural uniformity of the second gate driving unit G2j and thus improving the display effect.

[0102] Figure 13 Provided for the ninth embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 13 The display panel shown and Figure 12 The difference in the display panel shown is that, in this embodiment, the first gate driving unit G1i of the first sub-region SA1 and the first gate driving unit G1i of the second sub-region SA2 are staggered in the circumferential direction of the display area AA.

[0103] Figure 14 Provided for the tenth embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 14 The display panel shown and Figure 12 , Figure 13 The difference in the display panel shown is that, in this embodiment, it uses... Figure 13 Taking the display panel shown as an example, the second bezel area L2A is provided with at least one redundant second gate driving unit G20.

[0104] In one embodiment, in the second border region L2A, the number of redundant second gate drive units G20 is equal to the sum of the number of first gate drive units G1i and redundant first gate drive units G10.

[0105] Figure 15 Provided for the eleventh embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 15 The display panel shown and Figure 12 The difference in the display panel shown is that, in this embodiment, the display panel further includes a third gate driving circuit G3. The third gate driving circuit G3 includes a plurality of third gate driving units G3m arranged sequentially along the circumference of the display area AA, and at least one redundant third gate driving unit G30. The difference between the third gate driving unit G3m and the redundant third gate driving unit G30 is that the third gate driving unit G3m is electrically connected to the sub-pixel 20, while the redundant third gate driving unit G30 is not electrically connected to the sub-pixel 20. At least one redundant third gate driving unit G30 is located in the arc-corner bezel area SA, and is located on the side of the third gate driving unit G3m closest to the second bezel area L2A.

[0106] In one embodiment, in the arc-corner border region SA, the number of second gate driving units G2j and third gate driving units G3m are equal, and the number of redundant second gate driving units G20 and redundant third gate driving units G30 are equal.

[0107] Figure 16 Provided for the twelfth embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 16 The display panel shown and Figure 15 The difference in the display panel shown is that, in this embodiment, the sum of the number of the second gate driving units G2j in the arc-corner bezel area SA and the second gate driving units G2j in the second bezel area L2A is equal to the number of the third gate driving units G3m in the arc-corner bezel area SA.

[0108] Figure 17 Provided for the thirteenth embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 17 The display panel shown and Figure 15 , Figure 16 The difference in the display panel shown is that, in this embodiment, it uses... Figure 16 Taking the display panel shown as an example, in the circumferential direction of the display area AA, the third gate driving unit G3m of the first sub-area SA1 and the third gate driving unit G3m of the second sub-area SA2 are arranged in a staggered manner.

[0109] Figure 18 Provided for the fourteenth embodiment Figure 1 This is a magnified view of a portion of the display panel. (See attached image.) Figure 18 The display panel shown and Figures 15-17 The difference between the display panels shown in any of the embodiments is that, in this embodiment, a... Figure 17 Taking the display panel shown as an example, in the second bezel area L2A, the sum of the number of the first gate driving unit G1i and the number of the redundant first gate driving unit G10, the sum of the number of the second gate driving unit G2j and the number of the redundant second gate driving unit G20, and the number of the redundant third gate driving unit G30 are equal.

[0110] Figure 19 Provided for the fifteenth embodiment of this application Figure 1 The diagram shows the wiring layout of a partial area of ​​the display panel. (See attached image.) Figure 19As shown, the display panel also includes a first gate line 31 and a gate connection line 40. The first gate line 31 is located in the display area AA, and the gate connection line 40 connects the first gate line 31 and the first gate driving unit G1i in the second bezel area L2A. The gate connection line 40 includes a first sub-connection line 41. The portion of the first sub-connection line 41 located in the display area AA extends in the same direction as the first gate line 31, and the orthographic projection of the first sub-connection line 41 on the substrate 10 lies between the orthographic projection of the first gate line 30 on the substrate 10 and the orthographic projection of the first gate driving unit G1i on the substrate 10. The portion of the first sub-connection line 41 located in the bezel area NA is electrically connected to the first gate line 31 through at least one wire exchange hole O.

[0111] In one embodiment, the gate connection line 40 further includes a second sub-connection line 42, which is electrically connected to the end of the first sub-connection line 41 away from the first gate line 31; the extension directions of the second sub-connection line 42 and the first sub-connection line 41 intersect. For example, the extension directions of the second sub-connection line 42 and the first sub-connection line 41 are perpendicular.

[0112] Figure 20 for Figure 19 An enlarged view of the first sub-region of the display panel shown. Figure 21 for Figure 19 An enlarged view of the second sub-region of the display panel shown. Figure 20 An enlarged view of the first sub-local region P11 is shown. Figure 21 An enlarged view of the second sub-local region P12 is shown. Combined with... Figure 19 , Figure 20 and Figure 21 As shown, the display panel also includes a second gate line 32 and a third gate line 33 located in the display area AA. The portion of the first sub-connection line 41 located in the display area AA, the second gate line 32, the first gate line 31 and the third gate line 33 are respectively arranged in orthographic projection on the substrate 10.

[0113] In one embodiment, the first gate line 31 includes a light-emitting signal line Em, the second gate line 32 includes a fourth scan line S4, and the third gate line 33 includes a second scan line S2.

[0114] In one embodiment, the first gate line 31, the second gate line 32, and the third gate line 33 are disposed in the same layer. For example, the display panel includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer stacked sequentially along a direction away from the substrate 10. The first gate line 31, the second gate line 32, and the third gate line 33 are all located in the first metal layer.

[0115] In one embodiment, the first sub-connection line 41 and the first gate line 31 are disposed on different layers. Continuing with the previous example, the first sub-connection line 41 is located on the fourth metal layer.

[0116] In one embodiment, the display panel further includes a second initialization signal line Vref2, at least a portion of which is collinear with the first sub-connection line 41. Collinearity of the second initialization signal line Vref2 and the first sub-connection line 41 means that they are located on the same metal layer and on the same straight line. Continuing the previous example, if the first sub-connection line 41 is located on a fourth metal layer, at least a portion of the second initialization signal line Vref2 is also located on the fourth metal layer.

[0117] In one embodiment, the display panel further includes a shielding line located on the side of the first sub-connection line 41 near the substrate 10. The orthographic projection of the first sub-connection line 41 on the substrate 10 and the orthographic projection of the shielding line on the substrate 10 at least partially overlap. Exemplarily, the shielding line includes a portion of the first initialization signal line Vref1, i.e., a portion of the first initialization signal line Vref1 serves as the shielding line. Continuing the previous example, the shielding line is located in the third metal layer. Another portion of the first initialization signal line Vref1 is located in the first metal layer, and the first initialization signal line Vref1 of the first metal layer and the multiplexed first initialization signal line Vref1 of the third metal layer intersect in a mesh pattern. The shielding line can shield the first sub-connection line 41 from interference between the signal lines in the first and second metal layers.

[0118] In one embodiment, the second sub-connection line 42 is disposed on a different layer than the first gate line 31. Continuing with the previous example, the second sub-connection line 42 is located on the fifth metal layer.

[0119] In one embodiment, the display panel further includes low-voltage power lines Elvss, at least a portion of which are collinear with the second sub-connection line 42. Collinearity of the low-voltage power lines Elvss and the second sub-connection line 42 means that the low-voltage power lines Elvss and the second sub-connection line 42 are located on the same metal layer and are on the same straight line. Continuing the previous example, if the second sub-connection line 42 is located on the fifth metal layer, at least a portion of the low-voltage power lines Elvss are also located on the fifth metal layer.

[0120] In one embodiment, the display panel further includes multiple data lines Data, with a second sub-connection line 42 located between adjacent data lines Data. Continuing the previous example, the data lines Data are also located on the fifth metal layer.

[0121] In one embodiment, the display panel further includes high-voltage power lines Elvdd, at least a portion of which are located between adjacent data lines. These high-voltage power lines Elvdd are alternately arranged with the second sub-connection line 42. Continuing with the previous example, at least a portion of the high-voltage power lines Elvdd are located in the fifth metal layer. In another embodiment, a portion of the high-voltage power lines Elvdd are located in the fourth metal layer, and the high-voltage power lines Elvdd in the fourth and fifth metal layers intersect in a mesh pattern.

[0122] In one embodiment, the second sub-connection lines of adjacent odd-numbered and even-numbered bits are connected to the same first gate driving unit G1i.

[0123] In one embodiment, such as Figure 21 As shown, the first sub-connection line 41 is connected to the first gate line 31 through three conductive vias O. For example, the first gate line 31 is located in the first metal layer, and the first sub-connection line 41 is located in the fourth metal layer. The three conductive vias O include a first conductive via O1, a second conductive via O2, and a third conductive via O3. The first sub-connection line 41 is routed through the first conductive via O1 to the third metal layer, then through the second conductive via O2 to the second metal layer, and then through the third conductive via O3 to the first metal layer, where it is electrically connected to the first gate line 31.

[0124] Figure 22 for Figure 19 An enlarged view of the third sub-region of the display panel shown. Figure 22 An enlarged view of the third sub-local region P13 is shown. Combined with... Figure 19 and Figure 22 As shown, the first gate driving circuit G1 further includes multiple signal lines 50, which are connected to the first gate driving unit G1i. These multiple signal lines include external input signal lines and cascaded signal lines between adjacent first gate driving units G1i. The orthographic projections of the multiple signal lines on the substrate 10 and the orthographic projections of the second gate driving unit G2j and / or the third gate driving unit G3m of the second sub-region SA2 on the substrate 10 do not overlap. That is, the signal lines 50 avoid the circuit structure of the second sub-region SA2.

[0125] In one embodiment, the multiple signal lines 50 include multiple clock signal lines CLK. The display panel also includes low-voltage power traces 60 located on the side of the clock signal lines CLK facing away from the substrate 10. The low-voltage power traces 60 are electrically connected to the low-voltage power lines Elvss of the display area AA. The low-voltage power traces 60 include multiple vias H, and the overlap area of ​​the orthographic projections of different clock signal lines CLK on the substrate 10 and the orthographic projections of the vias H on the substrate 10 is the same.

[0126] An organic layer is provided between the clock signal line CLK and the low-voltage power supply trace 60. Moisture in the organic layer can be released by providing via H. At the same time, by setting the overlap area of ​​the orthographic projection of different clock signal lines CLK on the substrate 10 to be the same as the orthographic projection of via H on the substrate 10, the load on different clock signal lines CLK can be kept consistent.

[0127] Figure 23 Provided for the sixteenth embodiment of this application Figure 1 The diagram shows the wiring layout of a partial area of ​​the display panel. (See attached image.) Figure 23 As shown, in this embodiment, the first sub-connecting line 41 is located at the first end D1 of the display area AA, corresponding to the sub-pixel 20. The orthographic projection of the first end D1 on the substrate overlaps with the orthographic projection of the corresponding sub-pixel 20 on the substrate. The sub-pixels 20 corresponding to the first ends D1 of adjacent first sub-connecting lines 41 are located in adjacent rows and adjacent columns. And / or, the second sub-connecting line 42 is located at the second end D2 of the display area AA, corresponding to the sub-pixel 20. The orthographic projection of the second end D2 on the substrate overlaps with the orthographic projection of the corresponding sub-pixel 20 on the substrate. The sub-pixels 20 corresponding to the second ends D2 of adjacent second sub-connecting lines 42 are located in adjacent rows and adjacent columns.

[0128] In one embodiment, the first gate driving unit G1i is connected to two adjacent second sub-connection lines 42.

[0129] Figure 24 Provided for the seventeenth embodiment of this application Figure 1 The diagram shows the wiring layout of a partial area of ​​the display panel. (See attached image.) Figure 24 As shown, in this embodiment, the orthographic projection of the first sub-connection line 41 onto the substrate passes through the orthographic projection of at least one sub-pixel 20 onto the substrate. At least a portion of the orthographic projections of the first sub-connection line 41 pass through an equal number of sub-pixels 20.

[0130] In one embodiment, the number of orthogonal projections of at least some of the adjacent odd-numbered and even-numbered first sub-connection lines 41 passing through the sub-pixel 20 is equal. For example, the number of orthogonal projections of adjacent odd-numbered and even-numbered first sub-connection lines 41 connected to the same first gate driving unit G1i passing through the sub-pixel 20 is equal.

[0131] According to the display panel provided in this embodiment, by setting the number of sub-pixels 20 through which the orthographic projection of at least some of the first sub-connecting lines 41 passes to be equal, the effect of balancing capacitance can be achieved, so that the load on different first sub-connecting lines 41 remains consistent, thereby improving the display effect.

[0132] Figure 25 Provided for the eighteenth embodiment of this application Figure 1The diagram shows the wiring layout of a partial area of ​​the display panel. (See attached image.) Figure 25 In the display panel shown, in this embodiment, the orthographic projection of the second sub-connecting line 42 onto the substrate passes through the orthographic projection of at least one sub-pixel 20 onto the substrate. At least a portion of the orthographic projections of the second sub-connecting line 42 pass through an equal number of sub-pixels 20.

[0133] In one embodiment, the number of orthogonal projections of at least some of the adjacent odd-numbered and even-numbered second sub-connection lines 42 passing through the sub-pixel 20 is equal. For example, the number of orthogonal projections of adjacent odd-numbered and even-numbered second sub-connection lines 42 connected to the same first gate driving unit G1i passing through the sub-pixel 20 is equal.

[0134] According to the display panel provided in this embodiment, by setting the number of sub-pixels 20 through which the orthographic projection of at least some of the second sub-connecting lines 42 passes to be equal, the effect of balancing capacitance can be achieved, so that the load on different second sub-connecting lines 42 remains consistent, thereby improving the display effect.

[0135] The arc-corner bezel area SA mentioned in any of the above embodiments is applicable to any arc-corner bezel area SA of the display panel. For example, for a rounded rectangular display panel, the structure of the arc-corner bezel area SA is applicable to any one of the four arc-corner bezel areas. For the lower arc-corner bezel area SA, due to its proximity to the pad area, it has a different circuit structure design. The unique structure of the arc-corner bezel area SA adjacent to the pad area is described in detail below.

[0136] Figure 26 for Figure 1 An enlarged view of the second partial area of ​​the display panel shown. Figure 26 It shows Figure 1 A magnified view of the second local region P2 in the middle. Figure 27 for Figure 26 An enlarged view of the fourth sub-region of the display panel shown. Figure 28 for Figure 26 An enlarged view of the fifth sub-region of the display panel shown. Figure 27 An enlarged view of the fourth sub-local region P21 is shown. Figure 28 An enlarged view of the fifth sub-local region P22 is shown.

[0137] Combination Figure 1 , Figures 26-28As shown, the display panel also has a bonding area BA, which is located on the side of the bezel area NA away from the display area AA. The first gate drive circuit G1 also includes multiple signal lines 50, which are connected to the first gate drive unit G1i. These multiple signal lines include input signal lines IL and cascaded signal lines between adjacent first gate drive units G1i. At least a portion of the input signal lines IL include a first sub-input line IL1, a second sub-input line IL2, and a third sub-input line IL3. The first sub-input line IL1 extends from the bonding area BA to the second sub-area SA2, the second sub-input line IL2 connects one end of the first sub-input line IL1 located in the second sub-area SA2 to the first gate drive unit G1i in the first sub-area SA1, and the third sub-input line IL3 connects one end of the first sub-input line IL1 located in the second sub-area SA2 to the first gate drive unit G1i in the first bezel area L1A.

[0138] In one embodiment, the orthographic projection of the third sub-input line IL3 on the substrate 10 and the orthographic projection of the first sub-input line IL1 on the substrate 10 do not overlap at least partially. This avoids signal interference.

[0139] In one embodiment, the width of the curved corner border area SA is greater than or equal to 700 micrometers and less than or equal to 1000 micrometers. For example, the width of the curved corner border area SA is 800 micrometers, 850 micrometers, 900 micrometers, 950 micrometers, etc.

[0140] In one embodiment, the width of the border area NA is equal at different locations. For example, the width of the first border area L1A is consistent everywhere, the width of the curved corner border area SA is consistent everywhere, the width of the second border area L2A is consistent everywhere, and the widths of the first border area L1A, the curved corner border area SA, and the second border area L2A are equal.

[0141] This application also provides another display panel. See [link / reference] Figure 1 ,as well as Figures 10-28 The display panel shown in any embodiment. The display panel has a display area AA and a border area NA surrounding the display area AA. The border area NA includes a first border area and a second border area, which are spaced apart.

[0142] For example, the first border area includes Figures 10-28 The second border area L2A shown includes... Figures 1-25 The curved border area SA is shown. It should be noted that the first border area and the second border area can also be two areas set at any interval within the border area NA.

[0143] The display panel includes a first gate driving circuit G1. The first gate driving circuit G1 is located in the bezel area NA. The first gate driving circuit G1 includes a plurality of first gate driving units G1i and at least one redundant first gate driving unit G10. At least some of the redundant first gate driving units G10 are disposed on at least one side of the first gate driving units G1i in the first bezel area. Similarly, this design can also be used in the second bezel area and the rounded corner bezel area.

[0144] This application also provides a display device. Figure 29 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 29 As shown, the display device includes the display panel 100 provided in any of the above embodiments.

[0145] A display device is a product with image display capabilities. For example, a display device can be used to display static images, such as pictures or photographs. A display device can also be used to display dynamic images, such as videos.

[0146] Display devices can be laptops, mobile phones, handheld or portable computers, cameras, camcorders, in-vehicle smart central control screens, calculators, smartwatches, GPS navigators, electronic photographs, electronic billboards or signs, projectors, etc.

[0147] In addition, the display device can also perform functions such as taking photos, recording videos, fingerprint recognition, and facial recognition. Accordingly, the display device also includes at least one functional module for implementing the above functions, such as an under-display camera or an under-display fingerprint recognition sensor.

[0148] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0149] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a border area at least partially surrounding the display area, the border area comprising a first border area, a curved corner border area, and a second border area connected in sequence. Substrate; A first gate driving circuit is located on one side of the substrate and within the border region. The first gate driving circuit includes a plurality of first gate driving units, which are cascaded sequentially along the circumference of the display area. The distance between two adjacent first gate driving units within the second border region and the arc-corner border region is greater than the distance between two adjacent first gate driving units within the arc-corner border region. The second gate driving circuit is located in the bezel area and on the side of the first gate driving circuit that is close to or far from the display area. The second gate driving circuit includes a plurality of second gate driving units arranged sequentially along the circumference of the display area, and the plurality of second gate driving units are cascaded sequentially along the circumference of the display area. The arc-corner bezel area includes a first sub-area close to the first bezel area and a second sub-area close to the second bezel area. In the circumference of the display area, the second gate driving units of the first sub-area and the second gate driving units of the second sub-area are arranged in a staggered manner.

2. The display panel according to claim 1, characterized in that, Both the first border area and the second border area include straight borders; The number of first gate driving units in the second frame region is less than the number of first gate driving units in the arc-corner frame region; The first gate driving circuit includes either a light-emitting driving circuit or a scanning driving circuit.

3. The display panel according to claim 1 or 2, characterized in that, The number of second gate driving units in the second sub-region is equal to the number of first gate driving units in the second border region; The second gate driving circuit includes either a light-emitting driving circuit or a scanning driving circuit; The second gate driving circuit includes a first scan driving circuit.

4. The display panel according to claim 1, characterized in that, It also includes a third gate driving circuit, which is located in the frame region and on the side of the second gate driving circuit away from the first gate driving circuit. The third gate driving circuit includes a plurality of third gate driving units arranged sequentially along the circumference of the display area; The arc-shaped frame area includes a first sub-area near the first frame area and a second sub-area near the second frame area; in the circumferential direction of the display area, the third gate driving unit of the first sub-area and the third gate driving unit of the second sub-area are staggered. The number of the third gate driving units in the second sub-region is equal to the number of the first gate driving units in the second border region; or, the sum of the number of the third gate driving units in the second border region and the number of the third gate driving units in the second sub-region is equal to the number of the first gate driving units in the second border region. Along the circumference of the display area, a plurality of the third gate driving units are cascaded in sequence; The third gate driving circuit includes either a light-emitting driving circuit or a scanning driving circuit. The third gate driving circuit includes a second scan driving circuit.

5. The display panel according to claim 1, characterized in that, The first gate driving circuit further includes at least one redundant first gate driving unit; the display panel further includes a sub-pixel located in the display area, the first gate driving unit is electrically connected to the sub-pixel, and the redundant first gate driving unit is not electrically connected to the sub-pixel; at least a portion of the redundant first gate driving units are located in the second border area and are located on at least one side of the first gate driving unit in the circumferential direction of the display area; Part of the redundant first gate driving unit is located in the arc-shaped border area, and is located on the side of the first gate driving unit closer to the second border area.

6. The display panel according to claim 5, characterized in that, It also includes a second gate driving circuit, located on the side of the first gate driving circuit that is close to or far from the display area; the second gate driving circuit includes a plurality of second gate driving units arranged sequentially along the circumference of the display area and at least one redundant second gate driving unit, the second gate driving units being electrically connected to the sub-pixel, and the redundant second gate driving unit not being electrically connected to the sub-pixel; at least one of the redundant second gate driving units is located in the arc-corner border area and is located on the side of the second gate driving unit that is close to the second border area; The arc-shaped frame area includes a first sub-region near the first frame area and a second sub-region near the second frame area; in the circumferential direction of the display area, the second gate driving unit of the first sub-region and the second gate driving unit of the second sub-region are staggered. The second border region is provided with at least one of the redundant second gate driving units; In the second border region, the number of redundant second gate driving units is equal to the sum of the number of first gate driving units and the number of redundant first gate driving units.

7. The display panel according to claim 6, characterized in that, It also includes a third gate driving circuit, located on the side of the second gate driving circuit that is close to or far from the first gate driving circuit; the third gate driving circuit includes a plurality of third gate driving units arranged sequentially along the circumference of the display area and at least one redundant third gate driving unit; the redundant third gate driving unit is not electrically connected to the sub-pixel, but is electrically connected to the sub-pixel; at least one of the redundant third gate driving units is located in the arc-corner border area and is located on the side of the third gate driving unit that is close to the second border area; In the arc-corner border region, the number of the second gate driving unit and the number of the third gate driving unit are equal; or, the sum of the number of the second gate driving unit in the arc-corner border region and the number of the second gate driving unit in the second border region is equal to the number of the third gate driving unit in the arc-corner border region. The arc-shaped frame area includes a first sub-area near the first frame area and a second sub-area near the second frame area; in the circumferential direction of the display area, the third gate driving unit of the first sub-area and the third gate driving unit of the second sub-area are staggered. In the second border region, the sum of the number of the first gate driving unit and the number of the redundant first gate driving unit, the sum of the number of the second gate driving unit and the number of the redundant second gate driving unit, and the number of the redundant third gate driving unit are equal.

8. The display panel according to claim 1, characterized in that, It also includes a first gate line and a gate connection line; the first gate line is located in the display area, and the gate connection line connects the first gate line and the first gate driving unit in the second frame area; the gate connection line includes a first sub-connection line, the portion of the first sub-connection line located in the display area extends in the same direction as the first gate line, and the orthographic projection of the first sub-connection line on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the first gate driving unit on the substrate. The portion of the first sub-connection line located in the frame area is electrically connected to the first gate line through at least one wire switching hole; The display panel further includes a second gate line and a third gate line located in the display area, wherein the portion of the first sub-connection line located in the display area, the second gate line, the first gate line, and the third gate line are arranged sequentially on the substrate. The first gate line, the second gate line, and the third gate line are disposed in the same layer; The first sub-connection line and the first gate line are disposed on different layers; The display panel further includes a second initialization signal line, at least a portion of which is collinear with the first sub-connection line; The first gate line includes a light-emitting line, the second gate line includes a fourth scan line, and the third gate line includes a second scan line.

9. The display panel according to claim 8, characterized in that, The display panel further includes a shielding line located on the side of the first sub-connecting line close to the substrate; the orthographic projection of the first sub-connecting line on the substrate and the orthographic projection of the shielding line on the substrate at least partially overlap. The shield line is reused as the first initialization signal line.

10. The display panel according to claim 8 or 9, characterized in that, The first sub-connecting line is located at the first end of the display area and corresponds to the sub-pixel. The orthographic projection of the first end on the substrate overlaps with the orthographic projection of the corresponding sub-pixel on the substrate. The sub-pixels corresponding to the first ends of adjacent first sub-connecting lines are located in adjacent rows and adjacent columns. or, The orthographic projection of the first sub-connecting line on the substrate passes through the orthographic projection of at least one of the sub-pixels on the substrate; at least a portion of the orthographic projections of the first sub-connecting line pass through an equal number of the orthographic projections of the sub-pixels. The number of orthographic projections of the first sub-connecting lines at least partially adjacent odd and even positions passing through the sub-pixels is equal.

11. The display panel according to claim 8, characterized in that, The gate connection line further includes a second sub-connection line, which is electrically connected to the end of the first sub-connection line away from the first gate line; the extension directions of the second sub-connection line and the first sub-connection line intersect. The end of the second sub-connecting line away from the first sub-connecting line is electrically connected to the first gate driving unit; The second sub-connector is disposed on a different layer than the first sub-connector; The second sub-connection line is disposed on a different layer from the first gate line; The display panel also includes a low-voltage power line, at least a portion of which is shared with the second sub-connection line; The display panel also includes multiple data lines, with the second sub-connecting line located between adjacent data lines; The second sub-connection lines of adjacent odd-numbered and even-numbered bits are connected to the same first gate driving unit.

12. The display panel according to claim 11, characterized in that, The second sub-connecting line is located at the second end of the display area and corresponds to the sub-pixel. The orthographic projection of the second end on the substrate overlaps with the orthographic projection of the corresponding sub-pixel on the substrate. The sub-pixels corresponding to adjacent second sub-connecting lines are located in adjacent rows and adjacent columns; or, the orthographic projection of the second sub-connecting line on the substrate passes through the orthographic projection of at least one sub-pixel on the substrate; at least some of the orthographic projections of the second sub-connecting lines pass through an equal number of orthographic projections of the sub-pixels. The number of orthographic projections of the second sub-connecting lines at least partially adjacent odd and even positions passing through the sub-pixels is equal.

13. The display panel according to claim 1, characterized in that, The arc-shaped frame region includes a first sub-region near the first frame region and a second sub-region near the second frame region, and the first gate driving unit of the arc-shaped frame region is located in the first sub-region; The display panel further includes a second gate driving circuit and a third gate driving circuit, with a portion of the second gate driving circuit and a portion of the third gate driving circuit located in the second sub-region; The first gate driving circuit further includes multiple signal lines, which are connected to the first gate driving unit; The orthographic projection of the signal line on the substrate and the orthographic projections of the second gate driving circuit and the third gate driving circuit of the second sub-region on the substrate do not overlap; The signal lines include multiple clock signal lines; the display panel also includes low-voltage power supply traces located on the side of the clock signal lines away from the substrate. The low-voltage power supply trace includes multiple vias, and the overlapping area of ​​the orthographic projections of the different clock signal lines on the substrate and the orthographic projections of the vias on the substrate is the same.

14. The display panel according to claim 1, characterized in that, It also has a bonding area located on the side of the bezel area away from the display area; the first gate driving circuit further includes multiple signal lines, including input signal lines, including a first sub-input line, a second sub-input line, and a third sub-input line; the first sub-input line extends from the bonding area to the second sub-area, the second sub-input line connects one end of the first sub-input line located in the second sub-area to the first gate driving unit of the first sub-area, and the third sub-input line connects one end of the first sub-input line located in the second sub-area to the first gate driving unit of the first bezel area; The orthographic projection of the third sub-input line on the substrate and the orthographic projection of the first sub-input line on the substrate do not overlap at least partially.

15. The display panel according to claim 1, characterized in that, The width of the border area is the same at different positions.

16. A display device, characterized in that, The display panel includes any one of claims 1-15.

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