An array substrate, a display panel including the same, and a display device

Abstract

The application provides an array substrate, a display panel and a display device. The array substrate comprises a scanning circuit, the scanning circuit comprises a shift register unit, the shift register unit comprises a forward and reverse scanning module, the forward and reverse scanning module comprises a first input unit, a second input unit, a third input unit and a fourth input unit; wherein the first input unit comprises a first transistor, the second input unit comprises a second transistor, the third input unit comprises a third transistor, the fourth input unit comprises a fourth transistor, the first electrode of the first transistor and the first electrode of the fourth transistor are connected with a first power supply end, the first power supply end continuously provides a low-level signal, the first electrodes of the second transistor and the third transistor are connected with a second power supply end, the second power supply end continuously provides a high-level signal, the second electrodes of the first transistor, the second transistor, the third transistor and the fourth transistor are connected with a pull-up node, the first transistor and the fourth transistor pull down the potential of the pull-up node, the second transistor and the third transistor pull up the potential of the pull-up node, in the forward and reverse scanning switching process, the functions of the first transistor, the second transistor, the third transistor and the fourth transistor remain unchanged, and the shift register unit can realize normal forward and reverse scanning switching.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] In the related art, a plurality of cascaded shift register units are included in a gate scanning circuit (GOA, Gate Driver On Array), and the driving output ends of each stage of shift register units correspond to a gate line respectively to realize line-by-line scanning of a display panel. With the development of the technology of the gate scanning circuit, it has been generally required that the gate scanning circuit can realize forward and reverse scanning functions.

[0003] However, the shift register unit suitable for forward and reverse scanning will cause threshold drift of some transistors in the shift register unit after long-time forward scanning or reverse scanning, so that the gate scanning circuit cannot work normally when switching the scanning direction. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art, and proposes an array substrate, a display panel and a display device to solve the problem of threshold drift of transistors in a forward and reverse scanning shift register unit.

[0005] In one aspect, the present application provides an array substrate, comprising: a scanning circuit, the scanning circuit comprising a plurality of shift register units, the shift register unit comprising at least a first input unit, a second input unit, a third input unit and a fourth input unit;

[0006] The control end of the first input unit is electrically connected to the first trigger end, the input end of the first input unit is electrically connected to the first power supply end, and the output end of the first input unit is electrically connected to the pull-up node, for responding to the control of the first trigger end and adjusting the potential of the pull-up node according to the first power supply signal provided by the first power supply end;

[0007] The control end of the second input unit is electrically connected to the second trigger end, the input end of the second input unit is electrically connected to the second power supply end, and the output end of the second input unit is electrically connected to the pull-up node, for responding to the control of the second trigger end and adjusting the potential of the pull-up node according to the second power supply signal provided by the second signal end;

[0008] The control end of the third input unit is electrically connected to the third trigger end, the input end of the third input unit is electrically connected to the second power supply end, and the output end of the third input unit is electrically connected to the pull-up node, for responding to the control of the third trigger end and adjusting the potential of the pull-up node according to the second power supply signal provided by the second power supply end;

[0009] The control end of the fourth input unit is electrically connected with the fourth trigger end, the input end of the fourth input unit is electrically connected with the first power supply end, and the output end of the fourth input unit is electrically connected with the pull-up node, for responding to the control of the fourth trigger end and adjusting the potential of the pull-up node according to the first power supply signal provided by the first power supply end.

[0010] The first power supply signal and the second power supply signal are electrically different.

[0011] On the other hand, based on the same inventive concept, the present application provides an array substrate, which comprises X-stage shift register units, each stage of shift register units comprises a forward and reverse scanning module, and the forward and reverse scanning module comprises a first transistor, a second transistor, a third transistor and a fourth transistor.

[0012] The gate of the first transistor of the n-stage shift register unit is connected with the shift output end or trigger line of the n-2i-stage shift register unit, n≤X, i≥1, the first pole of the first transistor is connected with the first power supply end, and the second pole is connected with the pull-up node.

[0013] The gate of the second transistor of the n-stage shift register unit is connected with the shift output end or trigger line of the n-i-stage shift register unit, the first pole of the second transistor is connected with the second power supply end, and the second pole is connected with the pull-up node.

[0014] The gate of the third transistor of the n-stage shift register unit is connected with the shift output end or trigger line of the n+i-stage shift register unit, the first pole of the third transistor is connected with the second power supply end, and the second pole is connected with the pull-up node.

[0015] The gate of the fourth transistor of the n-stage shift register unit is connected with the shift output end or trigger line of the n+2i-stage shift register unit, the first pole of the fourth transistor is connected with the first power supply end, and the second pole is connected with the pull-up node.

[0016] On the other hand, based on the same inventive concept, the present application provides a display panel, which comprises the array substrate as described above.

[0017] On the other hand, based on the same inventive concept, the present application provides a display device, which comprises the display panel as described above.

[0018] In the present application, the input end of the first input unit of each stage shift register unit is electrically connected to the first power supply end, the input end of the second input unit is electrically connected to the second power supply end, the input end of the third input unit is electrically connected to the second power supply end, the input end of the fourth input unit is electrically connected to the first power supply end, and the output ends of the first input unit, the second input unit, the third input unit and the fourth input unit are electrically connected to the pull-up node, that is, each stage shift register unit comprises a forward and reverse scanning module, the forward and reverse scanning module comprises a first transistor, a second transistor, a third transistor and a fourth transistor, the first pole of the first transistor is connected to the first power supply end, the first pole of the second transistor is connected to the second power supply end, the first pole of the third transistor is connected to the second power supply end, the first pole of the fourth transistor is connected to the first power supply end, and the second pole of the first transistor, the second pole of the second transistor, the second pole of the third transistor and the second pole of the fourth transistor are all connected to the pull-up node. In the process of forward and reverse scanning switching, the first power supply end always provides a first power supply signal, and the second power supply end always provides a second power supply signal, so that normal forward and reverse scanning switching can be realized, and the stability and reliability of the shift register unit can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0020] Figure 1 It is a circuit structure schematic diagram of the shift register unit in the related art;

[0021] Figure 2 It is a current-gate source voltage (I-Vgs) characteristic curve schematic diagram of the shift register unit in the related art;

[0022] Figure 3 It is a signal timing schematic diagram of the forward and reverse scanning input transistors received in the shift register unit in the related art;

[0023] Figure 4 It is a schematic diagram of an array substrate provided by an embodiment of the present application;

[0024] Figure 5 It is a schematic diagram of a shift register unit provided by an embodiment of the present application;

[0025] Figure 6 It is another schematic diagram of a shift register unit provided by an embodiment of the present application;

[0026] Figure 7 It is Figure 6Timing diagram of the shift register unit shown when performing forward scanning;

[0027] Figure 8 is Figure 6 Timing diagram of the shift register unit shown when performing reverse scanning;

[0028] Figure 9 is a schematic diagram of a scan circuit provided by an embodiment of the application;

[0029] Figure 10 is Figure 9 Schematic diagram of clock signals and trigger signals of the scan circuit in a forward scanning mode shown;

[0030] Figure 11 is Figure 9 Schematic diagram of clock signals and trigger signals of the scan circuit in a reverse scanning mode shown;

[0031] Figure 12 is a schematic diagram of another scan circuit provided by an embodiment of the application;

[0032] Figure 13 is a schematic diagram of yet another scan circuit provided by an embodiment of the application;

[0033] Figure 14 is Figure 12 Schematic diagram of clock signals and trigger signals of the scan circuit in a forward scanning mode shown;

[0034] Figure 15 is Figure 12 Schematic diagram of clock signals and trigger signals of the scan circuit in a reverse scanning mode shown;

[0035] Figure 16 is Figure 13 Schematic diagram of clock signals and trigger signals of the scan circuit in a forward scanning mode shown;

[0036] Figure 17 is Figure 13 Schematic diagram of clock signals and trigger signals of the scan circuit in a reverse scanning mode shown;

[0037] Figure 18 is a schematic diagram of still another scan circuit provided by an embodiment of the application;

[0038] Figure 19 is Figure 18 Schematic diagram of clock signals and trigger signals of the scan circuit in a forward scanning mode shown;

[0039] Figure 20 is Figure 18 Schematic diagram of clock signals and trigger signals of the scan circuit in a reverse scanning mode shown;

[0040] Figure 21 is another schematic diagram of a scan circuit provided by an embodiment of the present application;

[0041] Figure 22 is Figure 21 is a schematic diagram of clock signals and trigger signals in a forward scan mode of the scan circuit shown in

[0042] Figure 23 is Figure 21 is a schematic diagram of clock signals and trigger signals in a reverse scan mode of the scan circuit shown in

[0043] Figure 24 is a schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0045] The transistors used in all the embodiments of the present application can be thin film transistors, field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain are not distinguished. In the embodiments of the present application, one of the two poles except the gate of the transistor is called the first pole, and the other is called the second pole. The first pole and the second pole are only distinguished in name, and are not essentially distinguished. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are described by taking the N-type transistor as an example. It is conceivable that the P-type transistor is used to implement, which is easily conceived by those of ordinary skill in the art without creative work, and thus is also within the protection scope of the embodiments of the present application.

[0046] Figure 1 is a schematic diagram of a circuit structure of a shift register unit suitable for forward and reverse scanning in the related art, as shown in Figure 1The shift register unit comprises a forward scanning input transistor T1, a backward scanning input transistor T2 and a first node N1. Taking the example that the forward scanning input transistor T1 and the backward scanning input transistor T2 are both N-type transistors, when forward scanning is performed, the input end FW of the forward scanning input transistor T1 continuously provides a high-level signal, the input end BW of the backward scanning input transistor T2 continuously provides a low-level signal, INPUT1 and INPUT2 are connected to the gate of the forward scanning input transistor T1 and the gate of the backward scanning input transistor T2 respectively, and the opening of the forward scanning input transistor T1 and the backward scanning input transistor T2 is intermittently and continuously controlled. In the long-time forward scanning process, the forward scanning input transistor T1 pulls up the potential of the first node N1, and the backward scanning input transistor T2 pulls down the potential of the first node N1. Since the gate-source voltage Vgs of the backward scanning input transistor T2 is greater than the threshold voltage of the backward scanning input transistor T2 for a long time, the current-gate-source voltage (I-Vgs) characteristic curve of the backward scanning input transistor T2 produces a forward drift as shown in Figure 2 Therefore, the threshold voltage of the backward scanning input transistor T2 increases and the driving capability decreases. When the scanning direction is switched from forward scanning to backward scanning, as shown in Figure 3 The input end FW of the forward scanning input transistor T1 changes to provide a low potential, the input end BW of the backward scanning input transistor T2 changes to provide a high potential, and the level signals provided by the input end FW of the forward scanning input transistor T1 and the input end BW of the backward scanning input transistor T2 are switched with each other. Since the threshold voltage of the backward scanning input transistor T2 is large and the driving capability is low, the potential written to the first node N1 decreases, and thus the shift register unit cannot work normally.

[0047] Figure 4 is a schematic diagram of an array substrate provided by an embodiment of the present application, Figure 5 is a schematic diagram of a shift register unit provided by an embodiment of the present application. As Figure 4 and Figure 5As shown, the array substrate comprises a scanning circuit 100, which comprises an X-stage shift register unit 101, and the shift register unit comprises at least a first input unit 111, a second input unit 112, a third input unit 113 and a fourth input unit 114. The control end of the first input unit 111 is electrically connected with a first trigger end IN1, the input end of the first input unit 111 is electrically connected with a first power supply end PW1, and the output end of the first input unit 111 is electrically connected with a pull-up node PU, for adjusting the potential of the pull-up node PU according to a first power supply signal VGL provided by the first power supply end PW1 in response to the control of the first trigger end IN1. The control end of the second input unit 112 is electrically connected with a second trigger end IN2, the input end of the second input unit 112 is electrically connected with a second power supply end PW2, and the output end of the second input unit 112 is electrically connected with the pull-up node PU, for adjusting the potential of the pull-up node PU according to a second power supply signal VGH provided by the second power supply end PW2 in response to the control of the second trigger end IN2. The control end of the third input unit 113 is electrically connected with a third trigger end IN3, the input end of the third input unit 113 is electrically connected with the second power supply end PW2, and the output end of the third input unit 113 is electrically connected with the pull-up node PU, for adjusting the potential of the pull-up node PU according to the second power supply signal VGH provided by the second power supply end PW2 in response to the control of the third trigger end IN3. The control end of the fourth input unit 114 is electrically connected with a fourth trigger end IN4, the input end of the fourth input unit 114 is electrically connected with the first power supply end PW1, and the output end of the fourth input unit 114 is electrically connected with the pull-up node PU, for adjusting the potential of the pull-up node PU according to the first power supply signal VGL provided by the first power supply end PW1 in response to the control of the fourth trigger end IN4. The first power supply signal VGL and the second power supply signal VGH are different in electrical property, and in this embodiment, the first power supply signal VGL can make the N-type transistor turn off, and the second power supply signal VGH can make the N-type transistor turn on.

[0048] In the embodiment, the array substrate includes a display area 201 and a non-display area 202. The display area 201 includes a plurality of sub-pixels 203 arranged in an array, the plurality of sub-pixels 203 are arranged along a first direction F1 to form a row of sub-pixels 203, and the plurality of sub-pixels 203 are arranged along a second direction F2 to form a column of sub-pixels 203, the first direction F1 and the second direction F2 intersect; wherein the arrangement mode of the pixels in the display area 201 can also be other arrangement modes, and is not limited to the array arrangement. The non-display area 202 includes a driving structure for the sub-pixels 203 in the display area 201 to display, specifically, the non-display area 202 at least includes a scan circuit 100, the scan circuit 100 is used to drive the sub-pixels 203 in the display area to display. Optionally, the sub-pixels in the display area 201 can be liquid crystal display units, can also be organic light-emitting display units, and can also be micro light-emitting diode display units, and are not specifically limited. The scan circuit 100 in the non-display area 202 is a gate scan circuit, and is used to control the sub-pixels 203 in the display area 201 to perform line-by-line scanning.

[0049] The scan circuit 100 includes a plurality of stages of shift register units 101. The shift register unit 101 includes a driving output end Gout, and one stage of shift register units 101 is electrically connected with one or more rows of sub-pixels 203 through the driving output end Gout. The shift register unit 101 provides a gate driving signal for the electrically connected sub-pixels 203 through the driving output end Gout, and is used to drive the sub-pixels 203 to work. Figure 4 In the embodiment, the shift register unit 101 is electrically connected with one row of sub-pixels 203, and the shift register unit 101 provides a gate driving signal for the corresponding one row of sub-pixels 203; but in other embodiments, one stage of shift register units can be electrically connected with multiple rows of sub-pixels, and the one stage of shift register units simultaneously or time-divisionally provides a gate driving signal for the multiple rows of sub-pixels.

[0050] In the embodiment, the shift register unit 101 comprises a first input unit 111, a control end of the first input unit 111 is electrically connected with the first trigger end IN1, an input end of the first input unit 111 is connected with the first signal end PW1, and an output end of the first input unit is connected with the pull-up node PU. Specifically, the electrical signal provided by the first trigger end IN1 is a signal jumping between high level and low level, thereby the on-off state of the first input unit 111 can be controlled. It can be understood that the transistor in the shift register unit 101 is taken as an N-type transistor for illustration, therefore, the high level signal can make the first input unit 111 turn on, and the low level signal can make the first input unit 111 turn off; if the high level signal is provided by the first trigger end IN1, the first power signal VGL provided by the first signal end PW1 is written into the pull-up node PU, if the low level signal is provided by the first trigger end IN1, the first input unit 111 is switched to the off state, and the transmission path between the first signal end PW1 and the pull-up node PU is disconnected. Therefore, the first input unit 111 responds to the control of the first trigger end IN1, and adjusts the potential of the pull-up node PU according to the first power signal VGL provided by the first power end PW1.

[0051] The shift register unit 101 comprises a second input unit 112, a control end of the second input unit 112 is electrically connected with the second trigger end IN2, an input end of the second input unit 112 is connected with the second signal end PW2, and an output end of the second input unit is connected with the pull-up node PU. Specifically, the electrical signal provided by the second trigger end IN2 is a signal jumping between high level and low level, thereby the on-off state of the second input unit 112 can be controlled. It can be understood that the transistor in the shift register unit 101 is taken as an N-type transistor for illustration, therefore, the high level signal can make the second input unit 112 turn on, and the low level signal can make the second input unit 112 turn off, if the high level signal is provided by the second trigger end IN2, the second power signal VGH provided by the second signal end PW2 is written into the pull-up node PU; if the low level signal is provided by the second trigger end IN2, the second input unit 112 is switched to the off state, and the transmission path between the second signal end PW2 and the pull-up node PU is disconnected. Therefore, the second input unit 112 responds to the control of the second trigger end IN2, and adjusts the potential of the pull-up node PU according to the second power signal VGH provided by the second power end PW2.

[0052] The shift register unit 101 comprises a third input unit 113, a control end of the third input unit 113 being electrically connected to the third trigger end IN3, an input end of the third input unit 113 being connected to the second signal end PW2, and an output end of the third input unit being connected to the pull-up node PU. Specifically, the third trigger end IN3 provides an electrical signal that jumps between high and low levels, thereby controlling the on-off state of the third input unit 113. It can be understood that the present application takes the transistor in the shift register unit 101 as an N-type transistor for illustration, and thus the high-level signal can make the third input unit 113 conduct, and the low-level signal can make the third input unit 113 turn off. If the third trigger end IN3 provides a high-level signal, then the second power signal VGH provided by the second signal end PW2 is written to the pull-up node PU; if the third trigger end IN3 provides a low-level signal, then the third input unit 113 is switched to the off state, and the transmission path between the second signal end PW2 and the pull-up node PU is disconnected. Therefore, the third input unit 113 responds to the control of the third trigger end IN3 and adjusts the potential of the pull-up node PU according to the second power signal VGH provided by the second power end PW2.

[0053] The shift register unit 101 comprises a fourth input unit 114, a control end of the fourth input unit 114 being electrically connected to the fourth trigger end IN4, an input end of the fourth input unit 114 being connected to the first signal end PW1, and an output end of the fourth input unit 114 being connected to the pull-up node PU. Specifically, the fourth trigger end IN4 provides an electrical signal that jumps between high and low levels, thereby controlling the on-off state of the fourth input unit 114. It can be understood that the present application takes the transistor in the shift register unit 101 as an N-type transistor for illustration, and thus the high-level signal can make the fourth input unit 114 conduct, and the low-level signal can make the fourth input unit 114 turn off. If the fourth trigger end IN1 provides a high-level signal, then the first power signal VGL provided by the first signal end PW1 is written to the pull-up node PU; if the fourth trigger end IN4 provides a low-level signal, then the fourth input unit 114 is switched to the off state, and the transmission path between the first signal end PW1 and the pull-up node PU is disconnected. Therefore, the fourth input unit 114 responds to the control of the fourth trigger end IN4 and adjusts the potential of the pull-up node PU according to the first power signal VGL provided by the first power end PW1.

[0054] In the embodiment, the input end of the first input unit 111 of the shift register unit 101 is electrically connected to the first power supply end PW1, the input end of the second input unit 112 is electrically connected to the second power supply end PW2, the input end of the third input unit 113 is electrically connected to the second power supply end PW2, the input end of the fourth input unit 114 is electrically connected to the first power supply end PW1, and the output ends of the first input unit 111, the second input unit 112, the third input unit 113 and the fourth input unit 114 are electrically connected to the pull-up node PU; in either the forward scanning mode or the reverse scanning mode, the first input unit 111 and the fourth input unit 114 pull down the potential of the pull-up node PU, and the second input unit 112 and the third input unit 113 pull up the potential of the pull-up node PU, so that the potential of the input end of the first input unit 111 to the fourth input unit 114 does not jump between high and low as in the prior art during the switching between the forward scanning mode and the reverse scanning mode, and thus the reverse scanning mode can be normally switched after a long time of the forward scanning mode or the forward scanning mode can be normally switched after a long time of the reverse scanning mode.

[0055] The optional shift register unit 101 further comprises an output unit 115, the control end of the output unit 115 is electrically connected to the pull-up node PU, the input end of the output unit 115 is electrically connected to the first signal end SG1, and the output end of the output unit 115 is electrically connected to the driving output end Gout; specifically, the potential of the pull-up node PU is controlled to jump between high and low by the first input unit 111, the second input unit 112, the third input unit 113 and the fourth input unit 114, so as to control the on-off state of the output unit 115. In the embodiment, the first signal provided by the first signal end SG1 can be a clock signal, which is marked as the first clock signal CK1; it can be understood that if the potential of the pull-up node PU is a high potential, the first output unit 115 is controlled to switch to the on state, the first clock signal CK1 provided by the first signal end SG1 is written to the driving output end Gout, and if the potential of the pull-up node PU is a low potential, the first output unit 115 is controlled to switch to the off state, and the transmission path between the first signal end SG1 and the driving output end Gout is disconnected. Therefore, the output unit 115 is used to respond to the control of the pull-up node PU, and adjust the signal of the driving output end Gout according to the first signal provided by the first signal end SG1.

[0056] The optional shift register unit further comprises a first reset unit 116, a control end of the first reset unit 116 is electrically connected to the second signal end SG2, an input end of the first reset unit 116 is electrically connected to the first power supply end PW1, and an output end of the first reset unit 116 is electrically connected to the driving output end Gout, for adjusting the signal of the driving output end Gout according to the first power supply signal VGL provided by the first power supply end PW1 in response to the control of the second signal provided by the second signal end SG2. Specifically, the second signal provided by the second signal end SG2 can be a clock signal, which is marked as a second clock signal CK2, and the second clock signal CK2 can control the on-off state of the first reset unit 116. It can be understood that if the potential of the second clock signal CK2 is a high potential, the first reset unit 116 is controlled to switch to the on state, and the first power supply signal VGL provided by the first power supply end PW1 is written to the driving output end Gout, and if the potential of the second clock signal CK2 is a low potential, the first reset unit 116 is controlled to switch to the off state, and the transmission path between the first power supply end PW1 and the driving output end Gout is disconnected. Therefore, the first reset unit 116 is used for adjusting the signal of the driving output end Gout according to the first power supply signal VGL provided by the first power supply end PW1 in response to the control of the second signal end SG2.

[0057] The optional shift register unit further comprises a second reset unit 117, a third reset unit 118 and a node control unit 119.

[0058] The control end of the second reset unit 117 is electrically connected to the third signal end Reset, the input end of the second reset unit 117 is electrically connected to the first power supply end PW1, and the output end of the second reset unit 117 is electrically connected to the pull-up node PU, for adjusting the potential of the pull-up node PU according to the first power supply signal VGL provided by the first power supply end PW1 in response to the control of the third signal end Reset. Specifically, the electrical signal provided by the third signal end Reset is a high-low level jump signal, thereby the on-off state of the second reset unit 117 can be controlled. It can be understood that if the potential of the electrical signal provided by the third signal end Reset is a high potential, the second reset unit 117 is controlled to switch to the on state, and the first power supply signal VGL provided by the first power supply end PW1 is written to the pull-up node PU, and if the potential of the electrical signal provided by the third signal end Reset is a low potential, the second reset unit 117 is controlled to switch to the off state, and the transmission path between the first power supply end PW1 and the pull-up node PU is disconnected. Therefore, the second reset unit 117 is used for adjusting the potential of the pull-up node PU according to the first power supply signal VGL provided by the first power supply end PW1 in response to the control of the third signal end Reset.

[0059] The control end of the third reset unit 118 is electrically connected with the fourth signal end Goff, the input end of the third reset unit 118 is connected with the first power supply end PW1, and the output end of the third reset unit 118 is electrically connected with the driving output end Gout, for adjusting the signal of the driving output end Gout according to the first power signal VGL provided by the first power supply end PW1 in response to the control of the fourth signal end Goff. Specifically, the electrical signal provided by the fourth signal end Goff is a signal of high-low level transition, so as to control the on-off state of the third reset unit 118. It can be understood that if the level signal potential provided by the fourth signal end Reset is a high level potential, the third reset unit 118 is controlled to switch to the on state, and the first power signal VGL provided by the first power supply end PW1 is written to the driving output end Gout. If the level signal potential provided by the fourth signal end Goff is a low level potential, the third reset unit 118 is controlled to switch to the off state, and the transmission path between the first power supply end PW1 and the driving output end Gout is disconnected. Therefore, the third reset unit 118 is used for adjusting the signal of the driving output end Gout according to the first power signal VGL provided by the first power supply end PW1 in response to the control of the fourth signal end Goff.

[0060] The control end of the node control unit 119 is electrically connected with the pull-up node PU and the pull-down node PD, the input end of the node control unit 119 is electrically connected with the first power supply end PW1, and the output end of the node control unit 119 is electrically connected with the pull-up node PU, the pull-down node PD and the driving output end Gout, for adjusting the signals of the pull-up node PU, the pull-down node PD and the driving output end in response to the control of the pull-up node PU or the pull-down node PD according to the first power signal VGL provided by the first power supply end PW1. Specifically, at least one control end of the node control unit 119 is electrically connected with the pull-up node PU, and at least one control end is electrically connected with the pull-down node PD. The signals of the pull-up node PU and the pull-down node PD will have high-low level transition. If the potential of the pull-up node PU is a high level potential, the first power signal VGL provided by the first power supply end PW1 is written to the pull-down node PD. If the potential of the pull-up node PU is a low level potential, the transmission path between the first power supply end PW1 and the pull-down node PD is disconnected. If the potential of the pull-down node PD is a high level potential, the first power signal VGL provided by the first power supply end PW1 is written to the pull-up node PU and the driving output end Gout. If the potential of the pull-down node PD is a low level potential, the transmission paths between the first power supply end PW1 and the pull-up node PU, and the first power supply end PW1 and the driving output end Gout are disconnected. Therefore, the node control unit 119 is used for adjusting the signals of the pull-up node PU, the pull-down node PD and the driving output end Gout according to the first power signal VGL provided by the first power supply end PW1 in response to the control of the pull-up node PU or the pull-down node PD.

[0061] In the embodiment, the scanning circuit 100 can realize the forward and reverse scanning function. In the forward scanning mode or the reverse scanning mode, the input end of the first input unit 111 provides the first power signal VGL, the input end of the second input unit 112 provides the second power signal VGH, the input end of the third input unit 113 provides the second power signal VGH, and the input end of the fourth input unit 114 provides the first power signal VGL. The first input unit 111 and the fourth input unit 114 pull down the potential of the pull-up node PU, and the second input unit 112 and the third input unit 113 pull up the potential of the pull-up node PU. Compared with the prior art, after the scanning direction is switched, the functions of the first input unit 111, the second input unit 112, the third input unit 113 and the fourth input unit 114 do not change, that is, the power signals provided by the input ends of the first input unit 111, the second input unit 112, the third input unit 113 and the fourth input unit 114 do not change. Even if the threshold voltage of the transistor in the first input unit 111 and the fourth input unit 114 becomes larger, the driving capability will not decrease because the pull-up action does not need to be switched, the potential written to the pull-up node PU will not decrease, and the shift register unit 101 can work normally.

[0062] Figure 6 Another shift register unit provided by the embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, the optional shift register unit 101 includes a forward and reverse scanning module S, and the forward and reverse scanning module S includes a first input unit 111, a second input unit 112, a third input unit 113 and a fourth input unit 114.

[0063] The first input unit 111 includes a first transistor M1, a gate of the first transistor M1 is connected with the first trigger end IN1, the first transistor M1 is connected between the first power supply end PW1 and the pull-up node PU, a first electrode of the first transistor M1 is connected with the first power supply end PW1, and a second electrode of the first transistor M1 is connected with the pull-up node PU; the second input unit 112 includes a second transistor M2, a gate of the second transistor M2 is connected with the second trigger end IN2, the second transistor M2 is connected between the second power supply end PW2 and the pull-up node PU, a first electrode of the second transistor M2 is connected with the second power supply end PW2, and a second electrode of the second transistor M2 is connected with the pull-up node PU; the third input unit 113 includes a third transistor M3, a gate of the third transistor M3 is connected with the third trigger end IN3, the third transistor M3 is connected between the second power supply end PW2 and the pull-up node PU, a first electrode of the third transistor M3 is connected with the second power supply end PW2, and a second electrode of the third transistor M3 is connected with the pull-up node PU; the fourth input unit 114 includes a fourth transistor M4, a gate of the fourth transistor M4 is connected with the fourth trigger end IN4, the fourth transistor M4 is connected between the first power supply end PW1 and the pull-up node PU, a first electrode of the fourth transistor M4 is connected with the first power supply end PW1, and a second electrode of the fourth transistor M4 is connected with the pull-up node PU.

[0064] The optional output unit 115 includes a fifth transistor M5, a gate of the fifth transistor M5 is connected with the pull-up node PU, the fifth transistor M5 is connected between the first signal end SG1 and the driving output end Gout, a first electrode of the fifth transistor M5 is connected with the first signal end SG1, and a second electrode of the fifth transistor M5 is connected with the driving output end Gout; specifically, when the potential of the pull-up node PU is high, the fifth transistor M5 is turned on, and the first clock signal CK1 provided by the first signal end SG1 is written into the driving output end Gout; otherwise, when the potential of the pull-up node PU is low, the fifth transistor M5 is turned off.

[0065] The optional first reset unit 116 includes a sixth transistor M6, a gate of the sixth transistor M6 is connected with the second signal end SG2, the sixth transistor M6 is connected between the first power supply end PW1 and the driving output end Gout, a first electrode of the sixth transistor M6 is connected with the first power supply end PW1, and a second electrode of the sixth transistor M6 is connected with the driving output end Gout; when the second clock signal CK2 provided by the second signal end SG2 is high, the sixth transistor M6 is turned on, and the first power supply signal VGL provided by the first power supply end PW1 is written into the driving output end Gout; otherwise, when the second clock signal CK2 provided by the second signal end SG2 is low, the sixth transistor is turned off.

[0066] Optionally, the second reset unit 117 includes a seventh transistor M7, a gate of the seventh transistor M7 is connected to the third signal terminal Reset, the seventh transistor M7 is connected between the first power terminal PW1 and the pull-up node PU, a first pole of the seventh transistor M7 is connected to the first power terminal PW1, and a second pole of the seventh transistor M7 is connected to the pull-up node PU.

[0067] Optionally, the third reset unit 118 includes an eighth transistor M8, a gate of the eighth transistor M8 is connected to the fourth signal terminal Goff, the eighth transistor M8 is connected between the first power terminal PW1 and the driving output terminal Gout, a first pole of the eighth transistor M8 is connected to the first power terminal PW1, and a second pole of the eighth transistor M8 is connected to the driving output terminal Gout. For any one of the seventh transistor M7 and the eighth transistor M8, when the potential of the gate of the transistor is high, the transistor is turned on, and otherwise, for any one of the seventh transistor M7 and the eighth transistor M8, when the potential of the gate of the transistor is low, the transistor is turned off.

[0068] Optionally, the node control unit 119 includes a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11, a gate of the ninth transistor M9 is connected to the pull-up node PU, the ninth transistor M9 is connected between the first power terminal PW1 and the first node PD, a first pole of the ninth transistor M9 is connected to the first power terminal PW1, and a second pole of the ninth transistor M9 is connected to the pull-down node PD; a gate of the tenth transistor M10 and the eleventh transistor M11 is connected to the pull-down node PD, the tenth transistor M10 is connected between the first power terminal PW1 and the pull-up node PU, a first pole of the tenth transistor M10 is connected to the first power terminal PW1, and a second pole of the tenth transistor M10 is connected to the pull-up node PU; the eleventh transistor M11 is connected between the first power terminal PW1 and the driving output terminal Gout, a first pole of the eleventh transistor M11 is connected to the first power terminal PW1, and a second pole of the eleventh transistor M11 is connected to the driving output terminal Gout. For any one of the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11, when the potential of the gate of the transistor is high, the transistor is turned on, and otherwise, for any one of the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11, when the potential of the gate of the transistor is low, the transistor is turned off.

[0069] Optionally, the shift register unit further includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is coupled between the driving output terminal Gout and the pull-up node PU, a first pole of the first capacitor C1 is connected to the driving output terminal Gout, and a second pole of the first capacitor C1 is connected to the pull-up node PU; the second capacitor C2 is coupled between the first signal terminal SG1 and the pull-down node PD, a first pole of the second capacitor C2 is connected to the first signal terminal SG1, and a second pole of the second capacitor C2 is connected to the pull-down node PD.

[0070] In the embodiment, the first capacitor C1 is coupled between the pull-up node PU and the driving output terminal Gout, when the pull-up node PU is in a floating state, the potential change of the driving output terminal Gout affects the potential change of the pull-up node PU. Specifically, when the potential of the driving output terminal Gout jumps from high level to low level, the potential of the pull-up node PU is pulled down; or when the potential of the driving output terminal Gout jumps from low level to high level, the potential of the pull-up node PU is self-boosted.

[0071] The second capacitor C2 is coupled between the pull-down node PD and the first signal terminal SG1, when the pull-down node PD is in a floating state, the potential change of the first clock signal CK1 provided by the first signal terminal SG1 affects the potential change of the pull-down node PD. Specifically, when the first clock signal CK1 jumps from high level to low level, the potential of the pull-down node PD is pulled down; or when the first clock signal CK1 jumps from low level to high level, the potential of the pull-down node PD is self-boosted.

[0072] It can be understood that the structure of the shift register unit of the present application includes but is not limited to Figure 6 The structure of the 11T2C shown in the figure, the relevant practitioners can reasonably design the structure of the shift register unit according to the product required and the application scene of the shift register unit. The present application does not elaborate on other shift register unit structures.

[0073] In the embodiment, the shift register unit 101 shown in the figure is taken as an example to describe its working process Figure 6 The first power supply signal VGL provided by the first power supply terminal PW1 is a low level signal, the second power supply signal VGH provided by the second power supply terminal PW2 is a high level signal, VGL can make the N-type transistor off, VGH can make the N-type transistor conduct, and the scan circuit 100 can perform forward scanning and reverse scanning.

[0074] Figure 7 The timing diagram of the shift register unit shown in the figure is taken as an example to describe its working process Figure 6 The timing diagram of the shift register unit shown in the figure is taken as an example to describe its working process Figure 8 The timing diagram of the shift register unit shown in the figure is taken as an example to describe its working process Figure 6 The timing diagram of the shift register unit shown in the figure is taken as an example to describe its working process Figure 7 The timing diagram of the shift register unit shown in the figure is taken as an example to describe its working process

[0075] In combination with Figure 6 and Figure 7As shown, the forward scanning process of the shift register unit 101 includes at least the following stages: in the first stage t11, the first trigger end IN1 of the shift register unit 101 receives a high-level signal, so that the first transistor M1 is turned on, and the first power supply signal VGL provided by the first power supply end PW1 is written to the pull-up node PU, the potential of the pull-up node PU is pulled down, the fifth transistor M5 is turned off, the potential of the first clock CK1 provided by the first signal end SG1 jumps from low level to high level, after being coupled through the second capacitor C2, the potential of the pull-down node PD is lifted based on the bootstrap action of the second capacitor C2, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the first power supply signal VGL provided by the first power supply end PW1 is written to the pull-up node PU and the driving output end Gout.

[0076] In the second stage t12, the first trigger end IN1 of the shift register unit 101 receives a low-level signal, so that the first transistor M1 is turned off, the first power supply signal VGL stops being written to the pull-up node PU, the second trigger end IN2 receives a high-level signal, so that the second transistor M2 is turned on, the second power supply signal VGH provided by the second power supply end PW2 is written to the pull-up node PU, the potential of the pull-up node PU jumps from low level to high level, so that the fifth transistor M5 is turned on, the potential of the first clock signal CK1 provided by the first signal end SG1 jumps from high level to low level, and the driving output end Gout outputs a low-level signal. At the same time, the ninth transistor M9 is turned on, the first power supply signal VGL provided by the first power supply end PW1 is written to the pull-down node PD, the potential of the pull-down node PD is pulled down, and the tenth transistor M10 and the eleventh transistor M11 are turned off.

[0077] In the third stage t13, the second trigger end IN2 of the shift register unit 101 receives a low-level signal, so that the second transistor M2 is turned off, and the pull-up node PU is in a floating state, the potential of the pull-up node PU maintains the high level in the second stage t12, the fifth transistor M5 remains turned on, the potential of the first clock signal CK1 provided by the first signal end SG1 jumps from low level to high level, the driving output end Gout outputs a high-level signal to drive the corresponding row of sub-pixels, the low-level of the driving output end Gout jumps to a high-level signal, after being coupled through the first capacitor C1, the potential of the pull-up node PU is lifted based on the bootstrap action of the first capacitor C1.

[0078] In the fourth stage t14, the electrical signal received by the third trigger terminal IN3 of the shift register unit 101 is a high-level signal, which turns on the third transistor M3. The second power signal VGH provided by the second power supply terminal PW2 is written into the pull-up node PU, keeping the pull-up node PU at a high level. The fifth transistor M5 remains on. The first clock signal CK1 provided by the first signal terminal SG1 changes from a high level to a low level. The low level of the first clock signal CK1 is written into the drive output terminal Gout.

[0079] In the fifth stage t15, the electrical signal received by the fourth trigger terminal IN4 of the shift register unit 101 is a high-level signal, which turns on the fourth transistor M4. The first power signal VGL provided by the first power supply terminal PW1 is written into the pull-up node PU, and the potential of the pull-up node PU is pulled down. The fifth transistor M5 switches from being turned on to being turned off. The potential of the first clock CK1 provided by the first signal terminal SG1 jumps from a low level to a high level. After being coupled through the second capacitor C2, the potential of the pull-down node PD is raised based on the bootstrap effect of the second capacitor C2. The tenth transistor M10 and the eleventh transistor M11 are turned on, and the first power signal VGL provided by the first power supply terminal PW1 is written into the pull-up node PU and the drive output terminal Gout.

[0080] As described above, the drive output terminal of the shift register unit 101 outputs a high-level signal in the third stage t13. This high-level signal is a valid pulse signal used to scan and drive the corresponding row sub-pixel. After the fifth stage t15, the shift register unit 101 maintains a low-level signal output until the first trigger terminal IN1 receives a high-level signal again.

[0081] Combination Figure 6 and Figure 8 As shown, the reverse scanning operation of the shift register unit 101 includes at least the following stages: In the first stage t21, the electrical signal received by the fourth trigger terminal IN4 of the shift register unit 101 is a high-level signal, the fourth transistor M4 is turned on, the first power supply signal VGL provided by the first power supply terminal PW1 is written into the pull-up node PU, the potential of the pull-up node PU is pulled low, the fifth transistor M5 is turned off, the potential of the first clock signal CK1 provided by the first signal terminal SG1 jumps from low level to high level, and after coupling through the second capacitor C2, the potential of the pull-down node PD is raised based on the bootstrap effect of the second capacitor C2, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the first power supply signal VGL provided by the first power supply terminal PW1 is written into the pull-up node PU and the drive output terminal Gout.

[0082] In the second stage t22, the fourth trigger end IN4 of the shift register unit 101 receives a low-level signal, so that the fourth transistor M4 is turned off, the first power supply signal VGL stops writing the pull-up node PU, the third trigger end IN3 receives a high-level signal, so that the third transistor M3 is turned on, the second power supply end PW2 provides the second power supply signal VGH to write the pull-up node PU, the potential of the pull-up node PU jumps from low level to high level, so that the fifth transistor M5 is turned on, the potential of the first clock signal CK1 provided by the first signal end SG1 jumps from high level to low level, and the driving output end Gout outputs a low-level signal. At the same time, the ninth transistor M9 is turned on, the first power supply end PW1 provides the first power supply signal VGL to write the pull-down node PD, the potential of the pull-down node PD is pulled low, and the tenth transistor M10 and the eleventh transistor M11 are turned off.

[0083] In the third stage t23, the third trigger end IN3 of the shift register unit 101 receives a low-level signal, so that the third transistor M3 is turned off, the pull-up node PU is in a floating state, the potential of the pull-up node PU is maintained at the high level in the second stage t22, the fifth transistor M5 remains turned on, the potential of the first clock signal CK1 provided by the first signal end SG1 jumps from low level to high level, the driving output end Gout outputs a high-level signal to drive the corresponding row of sub-pixels, the low level of the driving output end Gout jumps to a high-level signal, and after being coupled through the first capacitor C1, the potential of the pull-up node PU is lifted based on the bootstrap action of the first capacitor C1.

[0084] In the fourth stage t24, the second trigger end IN2 of the shift register unit 101 receives a high-level signal, so that the second transistor M2 is turned on, the second power supply end PW2 provides the second power supply signal VGH to write the pull-up node PU, maintains the high level of the pull-up node PU, the fifth transistor M5 remains in the turned-on state, the first clock signal CK1 provided by the first signal end SG1 jumps from high level to low level, and the low level of the first clock signal CK1 writes the driving output end Gout.

[0085] In the fifth stage t25, the first trigger end IN1 of the shift register unit 101 receives a high level signal, so that the first transistor M1 is turned on, and the first power supply signal VGL provided by the first power supply end PW1 is written into the pull-up node PU. Then, the potential of the pull-up node PU is lowered by the pull-down, so that the fifth transistor M5 is switched from the on state to the off state. The potential of the first clock CK1 provided by the first signal end SG1 jumps from the low level to the high level, and is coupled through the second capacitor C2. Then, the potential of the pull-down node PD is lifted based on the bootstrap function of the second capacitor C2, so that the tenth transistor M10 and the eleventh transistor M11 are turned on, and the first power supply signal VGL provided by the first power supply end PW1 is written into the pull-up node PU and the driving output end Gout.

[0086] As described above, the driving output end Gout of the shift register unit 101 outputs a high level signal in the third stage t23, and the high level signal is an effective pulse signal used to scan and drive the corresponding row of sub-pixels. The shift register unit 101 keeps outputting a low level signal after the fifth stage t25 until the fourth trigger end IN4 receives a high level signal again.

[0087] It should be noted that the first electrode of the fifth transistor M5 is connected to the first signal end SG1, and the gate of the sixth transistor M6 is connected to the second signal end SG2. The first signal end SG1 receives the first clock signal CK1, and the second signal end SG2 receives the second clock signal CK2. The first clock signal CK1 is different from the second clock signal CK2, so that the clock signal line connected to the first signal end SG1 is different from the clock signal line connected to the second signal end SG2.

[0088] In the embodiment, the first signal end SG1 is connected to the first electrode of the fifth transistor M5, and the second signal end SG2 is connected to the gate of the sixth transistor M6. The first signal end SG1 receives the first clock signal CK1, and the second signal end SG2 receives the second clock signal CK2. The first clock signal CK1 is different from the second clock signal CK2, so that the clock signal line connected to the first signal end SG1 is different from the clock signal line connected to the second signal end SG2. Figure 6As shown, the shift register unit 101 includes a forward and reverse scanning module S, which includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The first transistor M1 and the fourth transistor M4 pull down the potential of a pull-up node PU, and the second transistor M1 and the third transistor M3 pull up the potential of the pull-up node PU. The first electrode of the first transistor M1 is connected to a first power supply end PW1, the first electrode of the second transistor M2 is connected to a second power supply end PW2, the first electrode of the third transistor M3 is connected to the second power supply end PW2, the first electrode of the fourth transistor M4 is connected to the first power supply end PW1, and the second electrodes of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all connected to the pull-up node PU. In the forward scanning process, the first transistor M1 and the fourth transistor M4 pull down the potential of the pull-up node PU, and the second transistor M2 and the third transistor M3 pull up the potential of the pull-up node PU. In the reverse scanning process, the first transistor M1 and the fourth transistor M4 still pull down the potential of the pull-up node PU, and the second transistor M2 and the third transistor M3 pull up the potential of the pull-up node PU. Therefore, after the forward and reverse scanning modes are switched, the functions of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 do not change, and it is not necessary to switch the first power supply signal VGL and the second power supply signal VGH according to the scanning direction. The first transistor M1 and the second transistor M4, which have a forward threshold voltage drift, do not need to pull up the pull-up node PU after the scanning mode is switched. Therefore, the shift register unit 101 can normally switch to the reverse scanning mode after a long time of forward scanning, or can normally switch to the forward scanning mode after a long time of reverse scanning. On this basis, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning, thereby solving the problems in the prior art.

[0089] The optional scanning circuit 100 includes X-stage shift register units 101 connected in cascade. Each stage of the shift register units includes at least one shift output end Gx. The shift output ends Gx of the shift register units are connected in cascade. The signals output by the shift output ends Gx and the driving output end Gout are the same. In some embodiments, the shift output ends Gx and the driving output end Gout are separated. In this embodiment, the shift output ends Gx are multiplexed with the driving output end Gout. As shown, on one hand, the shift register unit 101 outputs a signal through the driving output end Gout to drive the corresponding sub-pixel, and on the other hand, the shift register unit 101 is connected in cascade through the driving output end Gout. Figure 6

[0090] The optional scanning circuit 100 further includes Y clock signal lines and k*Y trigger lines, where k≥1 and Y≥2. In the Y clock signal lines, the clock signals provided by the optional 2 clock signal lines have the same frequency and different phases. Optionally, as shown in the figure, the clock signals provided by the 2 clock signal lines have the same frequency and different phases. Figure 6 ​As shown, the first trigger end IN1 of the nth stage shift register unit is connected with the shift output end Gx or trigger line of the (n-2i)th stage shift register unit, the second trigger end IN2 of the nth stage shift register unit is connected with the shift output end Gx or trigger line of the (n-i)th stage shift register unit, the third trigger end IN3 of the nth stage shift register unit is connected with the shift output end Gx or trigger line of the (n+i)th stage shift register unit, and the fourth trigger end IN4 of the nth stage shift register unit is connected with the shift output end Gx or trigger line of the (n+2i)th stage shift register unit, n≤X, i≥1.

[0091] The scanning circuit in the embodiment can be double-side driven or single-side driven. It can be understood that the clock signal provided by the same clock signal line in the forward scanning can be different from the clock signal provided by the same clock signal line in the reverse scanning, and the trigger signal provided by the same trigger line in the forward scanning can be different from the trigger signal provided by the same trigger line in the reverse scanning.

[0092] Figure 9 is a schematic diagram of a scanning circuit 100 provided by an embodiment of the application, as Figure 9 shown, the single-side structure of the scanning circuit is a 2-phase GOA structure. The optional scanning circuit 100 includes two clock signal lines including a first clock signal line CKL1 and a second clock signal line CKL2, and four trigger lines including a first trigger line STV1, a second trigger line STV2, a third trigger line STV3 and a fourth trigger line STV4.

[0093] The X-stage shift registers 101 in the scanning circuit 100 are sequentially marked as GOA1, GOA2, GOA3, GOA4…GOA X , and the nth stage shift register 101 is marked as GOA n . 1≤n≤X. Two adjacent shift register units 101 constitute a shift register unit group 111, for example, the shift register unit GOA1 and the shift register unit GOA2 constitute the first-stage shift register unit group 111 / 1, the shift register unit GOA3 and the shift register unit GOA4 constitute the second-stage shift register unit group 111 / 2, and so on. Therefore, the scanning circuit 100 includes X / 2 cascaded shift register unit groups 111, Figure 9 only the first-stage shift register unit group 111 / 1, part of the second-stage shift register unit group 111 / 2, part of the X / 2-1th stage shift register unit group 111 / (X / 2-1), and the X / 2th stage shift register unit group 111 / (X / 2) of the scanning circuit 100 are shown in FIG. 1.

[0094] For each stage shift register unit group 111, the two adjacent shift register units 101 included in the group are marked as the first stage shift register unit GOA-1 and the second stage shift register unit GOA-2 of the shift register unit group 111, for example, the shift register unit GOA1 is the first stage shift register unit GOA-1 of the first stage shift register unit group 111 / 1, and the shift register unit GOA2 is the second stage shift register unit GOA-2 of the first stage shift register unit group 111 / 1; the shift register unit GOA3 is the first stage shift register unit GOA-1 of the second stage shift register unit group 111 / 2, and the shift register unit GOA4 is the second stage shift register unit GOA-2 of the second stage shift register unit group 111 / 2, and so on.

[0095] As shown in Figure 9 , the shift register unit group satisfies the following conditions: the first clock signal CKL1 is connected to the first signal end SG1 of the first stage shift register unit GOA-1 of each stage shift register unit group 111 and the second signal end SG2 of the second stage shift register unit GOA-2 of each stage shift register unit group 111; the second clock signal CKL2 is connected to the second signal end SG2 of the first stage shift register unit GOA-1 of each stage shift register unit group 111 and the first signal end SG1 of the second stage shift register unit GOA-2 of each stage shift register unit group 111; the scan circuit 100 includes a forward scan mode and a reverse scan mode, specifically, the forward scan mode can be scanning in the direction of GOA1 pointing to GOA X , and correspondingly, the reverse scan mode is scanning in the reverse direction of GOA X pointing to GOA1.

[0096] When the scan circuit is performing forward scan or reverse scan, the working timing of the first stage shift register unit GOA-1 of each stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal end SG1 is derived from the first clock signal line CKL1, and the second clock signal CK2 received by the second signal end SG2 is derived from the second clock signal line CKL2. The working timing of the second stage shift register unit GOA-2 of each stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal end SG1 is derived from the second clock signal line CKL2, and the second clock signal CK2 received by the second signal end SG2 is derived from the second clock signal line CKL1. It can be understood that in the present embodiment, the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 have the same frequency and opposite phases, and when the forward scan mode and the reverse scan mode are switched, the timing of the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 can be switched with each other.

[0097] Optionally, as shown in Figure 9As shown, the first trigger end IN1 of the n-th stage shift register unit 101 is connected to the shift output end Gx of the (n-2)-th stage shift register unit 101, the second trigger end IN2 of the n-th stage shift register unit 101 is connected to the shift output end Gx of the (n-1)-th stage shift register unit 101, the third trigger end IN3 of the n-th stage shift register unit 101 is connected to the shift output end Gx of the (n+1)-th stage shift register unit 101, and the fourth trigger end IN4 of the n-th stage shift register unit 101 is connected to the shift output end Gx of the (n+2)-th stage shift register unit 101. For the case where n is less than or equal to 2, i.e. including the first stage shift register unit GOA1 and the second stage shift register GOA2, the signals received by the first trigger end INI1 and the second trigger end IN2 of the optional first stage shift register unit GOA1 and the first trigger end IN1 of the second stage shift register unit GOA2 can directly come from the STV trigger lines, for example, the first trigger line STV1 can directly provide an electrical signal to the first trigger end INI1 of the first stage shift register unit GOA1, and the second trigger line STV2 directly provides an electrical signal to the second trigger end IN2 of the first stage shift register unit GOA1 and the first trigger end IN1 of the second stage shift register unit GOA2; for the last two stage GOA units 101, i.e. the (X-1)-th stage shift register unit GOA X-1 and the X-th stage shift register unit GOA X , the signals received by the fourth trigger end IN4 of the optional (X-1)-th stage shift register unit GOA X-1 , the third trigger end IN3 and the fourth trigger end IN4 of the X-th stage shift register unit GOA X may directly come from the STV trigger lines, for example, the third trigger line STV3 can directly provide an electrical signal to the fourth trigger end IN4 of the (X-1)-th stage shift register unit GOA X-1 and the third trigger end IN3 of the X-th stage shift register unit GOA X , and the fourth trigger line STV4 directly provides an electrical signal to the fourth trigger end IN4 of the X-th stage shift register unit GOA X . But not limited to this, in other embodiments, two dummy shift register units can also be arranged above the first stage shift register unit GOA1, which are marked as dummy-GOA1 and dummy-GOA2 respectively, the dummy-GOA1 can directly provide an electrical signal to the first trigger end INI1 of the first stage shift register unit GOA1, and the dummy-GOA2 provides an electrical signal to the second trigger end IN2 of the first stage shift register unit GOA1 and the first trigger end IN1 of the second stage shift register unit GOA2. Similarly, two dummy shift register units can also be arranged below the X-th stage shift register unit GOA X , which are marked as dummy-GOAX-1 and dummy-GOA X dummy-GOA X-1 The shift register unit GOA of the (X-1)th stage can be directly provided. X-1 The fourth trigger terminal IN4 and the Xth stage shift register GOA X The third trigger terminal IN3 provides an electrical signal, dummy-GOA X Directly to the Xth stage shift register GOA X The fourth trigger terminal IN4 provides an electrical signal.

[0098] The optional scanning circuit 100 includes forward and reverse scanning modes. Figure 10 yes Figure 9 The schematic diagram of the clock signal and trigger signal of the scanning circuit 100 in forward scanning mode is shown below. Figure 10 As shown, in forward scan mode, the clock signal provided by the first clock signal line CKL1 and the clock signal provided by the second clock signal line CKL2 have the same frequency but opposite phase. At the beginning of frame scan, the phase of the trigger signal provided by the first trigger signal line STV1 is earlier than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H. At the end of frame scan, the phase of the trigger signal provided by the third trigger signal line STV3 is earlier than the phase of the trigger signal provided by the fourth trigger signal line STV4, and the phase difference between the two is 2*H.

[0099] Figure 11 yes Figure 9 The schematic diagram of the clock signal and trigger signal of the scanning circuit 100 in reverse scanning mode is shown below. Figure 11 As shown, in reverse scan mode, the clock signal provided by the first clock signal line CKL1 and the clock signal provided by the second clock signal line CKL2 have the same frequency but opposite phase. At the beginning of frame scanning, the phase of the trigger signal provided by the fourth trigger signal line STV4 is earlier than the phase of the trigger signal provided by the third trigger signal line STV3, and the phase difference between the two is 2*H. At the end of frame scanning, the phase of the trigger signal provided by the second trigger signal line STV2 is earlier than the phase of the trigger signal provided by the first trigger signal line STV1, and the phase difference between the two is 2*H.

[0100] In other embodiments, Figure 12 This is a schematic diagram of another scanning circuit provided in an embodiment of the present invention, as shown below. Figure 12 As shown, the scanning circuit 100 may include: two clock signal lines, including a first clock signal line CKL1 and a second clock signal line CKL2; and two trigger lines, including a first trigger line STV1 and a second trigger line STV2. That is, as... Figure 9In the scanning circuit shown, the third trigger line STV3 multiplexes the first trigger line STV1, and the fourth trigger line STV4 multiplexes the second trigger line STV2. For example... Figure 12 As shown, in the scanning circuit 100, the first trigger terminal IN1 of the first-stage shift register unit GOA1 is connected to the first trigger line STV1, and the second trigger terminal IN2 of the first-stage shift register unit GOA1 is connected to the second trigger line; the first trigger terminal IN1 of the second-stage shift register unit GOA2 is connected to the second trigger line STV2, and the second trigger terminal IN2 of the second-stage shift register unit GOA2 is connected to the shift output terminal Gx of the first-stage shift register unit GOA1. The (X-1)th stage shift register unit GOA... X-1 The third trigger terminal IN3 is connected to the Xth stage shift register unit GOA. X The shift output terminal Gx, the (X-1)th stage shift register unit GOA X-1 The fourth trigger terminal IN4 is connected to the first trigger line STV1, and the Xth stage shift register unit GOA X The third trigger terminal IN3 is connected to the first trigger line STV1, and the Xth stage shift register unit GOA X The fourth trigger terminal IN4 is connected to the second trigger line STV2; or as follows Figure 13 As shown, Figure 13 This is a schematic diagram of another scanning circuit 100 provided in an embodiment of the present invention, showing the (X-1)th stage shift register unit GOA. X-1 The third trigger terminal IN3 is connected to the Xth stage shift register unit GOA. X The shift output terminal Gx, the (X-1)th stage shift register unit GOA X-1 The fourth trigger terminal IN4 is connected to the second trigger line STV2, and the Xth stage shift register unit GOA X The third trigger terminal IN2 is connected to the second trigger line ST21, and the Xth stage shift register unit GOA X The fourth trigger terminal IN4 is connected to the first trigger line STV1, i.e. Figure 9 In the scanning circuit shown, the third trigger line STV3 reuses the first trigger line STV1, and the fourth trigger line STV4 reuses the second trigger line STV2. This configuration reduces the number of trigger lines by two, thus reducing the bezel of the array substrate.

[0101] Figure 14 yes Figure 12 The diagram shows a clock signal and trigger signal for a forward scanning mode of the scanning circuit; as shown. Figure 14As shown, in forward scan mode, the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 have the same frequency but opposite phase. At the beginning of frame scanning, the phase of the trigger signal provided by the first trigger signal line STV1 is earlier than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H. At the end of frame scanning, the phase of the trigger signal provided by the first trigger signal line STV1 is earlier than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H.

[0102] Figure 15 yes Figure 12 The diagram shows a reverse scan mode clock signal and trigger signal for the scan circuit shown; as follows: Figure 14 As shown, in reverse scan mode, the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 have the same frequency but opposite phase; and Figure 14 The difference shown is that the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 switch phases, that is, the clock signal provided by the first clock signal line CKL1 and... Figure 14 The second clock signal line CKL2 shown has the same phase as the clock signal provided by the second clock signal line CKL2 and... Figure 14 The clock signals provided by the first clock signal line CKL1 shown have the same phase. At the beginning of frame scanning, the phase of the trigger signal provided by the second trigger signal line STV2 is earlier than the phase of the trigger signal provided by the first trigger signal line STV1, and the phase difference between the two is 2*H. At the end of frame scanning, the phase of the trigger signal provided by the second trigger signal line STV2 is earlier than the phase of the trigger signal provided by the first trigger signal line STV1, and the phase difference between the two is 2*H.

[0103] Figure 16 yes Figure 13 The diagram shows a clock signal and trigger signal for a forward scanning mode of the scanning circuit; as shown. Figure 16 As shown, in forward scan mode, the clock signals provided by the first clock signal CKL1 and the second clock signal line CKL2 have the same frequency but opposite timing. At the beginning of frame scan, the phase of the trigger signal provided by the first trigger signal line STV1 is earlier than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H. At the end of frame scan, the phase of the trigger signal provided by the first trigger signal line STV1 is later than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H.

[0104] Figure 17 yes Figure 13 The diagram shows a reverse scan mode clock signal and trigger signal for the scan circuit shown; as follows:Figure 17 As shown in the figure, in the reverse scanning mode, the first clock signal line CKL1 and the second clock signal line CKL2 provide clock signals with the same frequency and opposite phases. Figure 16 Unlike the figure, the phases of the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 are switched with each other, that is, the phase of the clock signal provided by the first clock signal line CKL1 is opposite to the phase of the clock signal provided by the second clock signal line CKL2. Figure 16 As shown in the figure, the phases of the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 are the same, the phase of the clock signal provided by the second clock signal line CKL2 is opposite to the phase of the clock signal provided by the first clock signal line CKL1. Figure 16 As shown in the figure, the phases of the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 are the same, the phase of the clock signal provided by the second clock signal line CKL2 is opposite to the phase of the clock signal provided by the first clock signal line CKL1.

[0105] Figure 18 Another schematic diagram of a scanning circuit provided by an embodiment of the present application is shown in the figure. Figure 18 As shown in the figure, the single-side structure of the scanning circuit 300 is a 4-phase GOA structure, the optional Y clock signal lines include the first clock signal line CKL1, the second clock signal line CKL2, the third clock signal line CKL3 and the fourth clock signal line CKL4, the optional k*Y trigger lines include the first trigger line STV1 to the eighth trigger line STV8, k≥1, Y≥2. The scanning circuit 100 includes X-stage shift register units 101, the X-stage shift register units 101 in the scanning circuit 100 are sequentially marked as GOA1, GOA2, GOA3, GOA4…GOA X , the n-stage shift register unit 101 is marked as GOA n . The adjacent four shift register units 101 constitute a shift register unit group 111, for example, the shift register unit GOA1, the shift register unit GOA2, the shift register unit GOA3 and the shift register unit GOA4 constitute the first-stage shift register unit group 111 / 1, the shift register unit GOA5, the shift register unit GOA6, the shift register unit GOA7 and the shift register unit GOA8 constitute the second-stage shift register unit group 111 / 2, and the like. Therefore, the scanning circuit 100 includes X / 4 cascaded shift register unit groups 111, Figure 18 Only the first-stage shift register unit group 111 / 1 and the X / 4-stage shift register unit group 111 / (X / 4) of the scanning circuit 100 are shown in the figure.

[0106] For any level shift register group 111, the four adjacent shift register units 101 included therein are respectively labeled as the first-level shift register unit GOA-1, the second-level shift register unit GOA-2, the third-level shift register unit GOA-3, and the fourth-level shift register unit GOA-4 of the shift register group 111. For example, shift register unit GOA1 is the first-level shift register unit GOA-1 of the first-level shift register group 111 / 1, shift register unit GOA2 is the second-level shift register unit GOA-2 of the first-level shift register group 111 / 1, and shift register unit GOA3 is the third-level shift register unit GOA-4 of the first-level shift register group 111 / 1. Shift register GOA-3 and shift register GOA-4 are the fourth shift registers in the first-level shift register group 111 / 1; shift register GOA-5 is the first-level shift register GOA-1 in the second-level shift register group 111 / 2; shift register GOA-6 is the second-level shift register GOA-2 in the second-level shift register group 111 / 2; shift register GOA-7 is the third-level shift register GOA-3 in the second-level shift register group 111 / 2; shift register GOA-8 is the fourth-level shift register GOA-4 in the second-level shift register group 111 / 2; and so on.

[0107] like Figure 18 As shown, the shift register unit group satisfies the following condition: the first clock signal CKL1 is connected to the first signal terminal SG1 of the first-level shift register unit GOA-1 of each shift register unit group 111 and the second signal terminal SG2 of the third-level shift register unit GOA-3 of each shift register unit group 111.

[0108] The second clock signal CKL2 connects the first signal terminal SG1 of the second-stage shift register unit GOA-2 of each shift register unit group 111 and the second signal terminal SG2 of the fourth-stage shift register unit GOA-4 of each shift register unit group 111.

[0109] The third clock signal CKL3 connects the first signal terminal SG1 of the third-stage shift register unit GOA-3 of each shift register unit group 111 and the second signal terminal SG2 of the first-stage shift register unit GOA-1 of each shift register unit group 111.

[0110] The fourth clock signal CKL4 connects the first signal terminal SG1 of the fourth-level shift register GOA-4 of each shift register unit group 111 and the second signal terminal SG2 of the second-level shift register GOA-2 of each shift register unit group 111.

[0111] The scan circuit 100 includes a forward scan mode and a reverse scan mode. Specifically, the forward scan mode can be scanning in the direction of GOA1 pointing to GOA X , and correspondingly, the reverse scan mode is scanning in the direction of GOA1 pointing to GOA1 in reverse. X

[0112] When the scan circuit 100 performs forward scanning or reverse scanning, the working timing of the first stage shift register GOA-1 of the stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal end SG1 is derived from the first clock signal line CKL1, and the second clock signal CK2 received by the second signal end SG2 is derived from the third clock signal line CKL3.

[0113] The working timing of the second stage shift register GOA-2 of the stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal end SG1 is derived from the second clock signal line CKL2, and the second clock signal CK2 received by the second signal end SG2 is derived from the fourth clock signal line CKL4.

[0114] The working timing of the third stage shift register GOA-3 of the stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal end SG1 is derived from the third clock signal line CKL3, and the second clock signal CK2 received by the second signal end SG2 is derived from the first clock signal line CKL1.

[0115] The working timing of the fourth stage shift register GOA-4 of the stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal end SG1 is derived from the fourth clock signal line CKL4, and the second clock signal CK2 received by the second signal end SG2 is derived from the second clock signal line CKL2.

[0116] As Figure 18 ​As shown, the first trigger end IN1 of the optional nth-stage shift register unit is connected to the shift output end Gx of the (n-4)th-stage shift register unit 101, the second trigger end IN2 of the nth-stage shift register unit 101 is connected to the shift output end Gx of the (n-2)th-stage shift register unit 101, the third trigger end IN3 of the nth-stage shift register unit 101 is connected to the shift output end Gx of the (n+2)th-stage shift register unit 101, and the fourth trigger end IN4 of the nth-stage shift register unit 101 is connected to the shift output end Gx of the (n+4)th-stage shift register unit 101. For the case where n is less than or equal to 4, i.e., including the shift register units GOA1 to GOA4, the signal received by the first trigger end IN1 of the shift register units GOA1 to GOA4 can be directly from the trigger line STV, and the signal received by the second trigger end IN2 of the shift register units GOA1 and GOA2 can also be directly from the trigger line STV. For example, the first trigger line STV1 can directly provide an electrical signal to the first trigger end IN1 of the first-stage shift register unit GOA1, the second trigger signal line STV2 can provide an electrical signal to the second trigger end IN2 of the first-stage shift register unit GOA1 and the first trigger end IN4 of the third-stage shift register unit GOA3, the third trigger signal line STV3 can directly provide an electrical signal to the first trigger end IN1 of the second-stage shift register unit GOA2, and the fourth trigger signal line STV4 can directly provide an electrical signal to the second trigger end IN2 of the second-stage shift register unit GOA2 and the first trigger end IN1 of the fourth-stage shift register unit GOA4. However, the present application is not limited thereto, and in other embodiments, four dummy shift register units can be arranged above the shift register units GOA1, which are marked as dummy-GOA1, dummy-GOA2, dummy-GOA3 and dummy-GOA4. The dummy-GOA1 can provide an electrical signal to the first trigger end IN1 of the first-stage shift register unit GOA1, the dummy-GOA2 can provide an electrical signal to the second trigger end IN2 of the first-stage shift register unit GOA1 and the first trigger end IN1 of the third-stage shift register unit GOA3, the dummy-GOA3 can directly provide an electrical signal to the first trigger end IN1 of the second-stage shift register unit GOA2, and the dummy-GOA4 can directly provide an electrical signal to the second trigger end IN2 of the second-stage shift register unit GOA2 and the first trigger end IN1 of the fourth-stage shift register unit GOA4. Similarly, for the last four-stage shift register units GOA X-3 to GOA X , the signal received by the fourth trigger end IN4 of the shift register unit GOA X-3 to GOA X can be directly from the trigger line STV, and the signal received by the fourth trigger end IN4 of the shift register unit GOAX-3 and shift register unit GOA X-2 The signal received by the third trigger end IN3 of the third shift register unit GOA X-3 may also directly come from the trigger line STV, for example, the fifth trigger line STV5 can directly provide the electrical signal to the fourth trigger end IN4 of the X-3th shift register unit GOA X-1 and the third trigger end IN3 of the X-1th shift register unit GOA X-2 and the fourth trigger end IN4 of the X-2th shift register unit GOA X and the third trigger end IN3 of the X-1th shift register unit GOA X-1 and the fourth trigger end IN4 of the Xth shift register unit GOA X But not limited to this, in other embodiments, the shift register unit GOA X may also be provided with four dummy shift register units below, which are marked as dummy-GOA5, dummy-GOA6, dummy-GOA7 and dummy-GOA8, the dummy-GOA5 can directly provide the electrical signal to the fourth trigger end IN4 of the X-3th shift register unit GOA X-3 and the third trigger end IN3 of the X-1th shift register unit GOA X-1 and the fourth trigger end IN4 of the X-2th shift register unit GOA X-2 and the third trigger end IN3 of the Xth shift register unit GOA X and the fourth trigger end IN4 of the X-1th shift register unit GOA X-1 and the fourth trigger end IN4 of the Xth shift register unit GOA X .

[0117] Figure 19 is Figure 18 The clock signal and trigger signal schematic diagram of the scanning circuit in the forward scanning mode is shown in FIG. 6. As Figure 19As shown, in the forward scanning mode, the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1*H; the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1*H. In the frame scanning starting stage, the phase of the trigger signal provided by the first trigger line STV1 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the fourth trigger line STV4, and the phase difference between the two is 1*H; in the frame scanning ending stage, the phase of the trigger signal provided by the fifth trigger line STV5 is earlier than the phase of the trigger signal provided by the seventh trigger line STV7, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the seventh trigger line STV7 is earlier than the phase of the trigger signal provided by the sixth trigger line STV6, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the sixth trigger line STV6 is earlier than the phase of the trigger signal provided by the eighth trigger line STV8, and the phase difference between the two is 1*H.

[0118] Figure 20 Figure 18 The clock signal and trigger signal of the scanning circuit in the reverse scanning mode are shown in the schematic diagram. As shown in the figure, Figure 20As shown in the reverse scanning mode, the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL1 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1*H. In the frame scanning starting stage, the phase of the trigger signal provided by the eighth trigger line STV8 is earlier than the phase of the trigger signal provided by the sixth trigger line STV6, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the sixth trigger line STV6 is earlier than the phase of the trigger signal provided by the seventh trigger line STV7, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the seventh trigger line STV7 is earlier than the phase of the trigger signal provided by the fifth trigger line STV5, and the phase difference between the two is 1*H; in the frame scanning ending stage, the phase of the trigger signal provided by the fourth trigger line STV4 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the first trigger line STV1, and the phase difference between the two is 1*H.

[0119] In still other embodiments, Figure 21 is a schematic diagram of still another scanning circuit provided by an embodiment of the present application, as Figure 21 shown, the scanning circuit 100 can include: four clock signal lines including a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3 and a fourth clock signal line CKL4; four trigger lines including a first trigger line STV1, a second trigger line STV2, a third trigger line STV3 and a second trigger line STV4. That is, as shown in the embodiment of the scanning circuit 100, the fifth trigger line STV5 multiplexes the first trigger line STV1, the seventh trigger line STV7 multiplexes the third trigger line STV3, the sixth trigger line STV6 multiplexes the second trigger line STV2, and the eighth trigger line STV8 multiplexes the third trigger line STV1. Figure 18

[0120] In the present embodiment, the first trigger end IN1 of the first-stage shift register unit GOA1 is connected to the first trigger line STV1, and the second trigger end IN2 of the first-stage shift register unit GOA1 is connected to the second trigger line STV2; ​

[0121] The first trigger end IN1 of the second stage shift register unit GOA2 is connected with the third trigger line STV3, and the second trigger end IN4 of the second stage shift register unit GOA2 is connected with the fourth trigger line STV4;

[0122] The first trigger end IN1 of the third stage shift register unit GOA3 is connected with the second trigger line STV2, and the second trigger end IN2 of the third stage shift register unit GOA3 is connected with the shift output end Gx of the first stage shift register unit GOA1;

[0123] The first trigger end IN1 of the fourth stage shift register unit GOA4 is connected with the fourth trigger line STV4, and the second trigger end IN2 of the fourth stage shift register unit GOA4 is connected with the shift output end Gx of the second stage shift register unit GOA2;

[0124] The third trigger end IN3 of the X-3 stage shift register unit GOA X-3 is connected with the shift output end Gx of the X-1 stage shift register unit GOA X-1 , and the fourth trigger end IN4 of the X-3 stage shift register unit GOA X-3 is connected with the first trigger line STV1;

[0125] The third trigger end IN3 of the X-2 stage shift register unit GOA X-2 is connected with the shift output end Gx of the X stage shift register unit GOA X , and the fourth trigger end IN4 of the X-2 stage shift register unit GOA X-2 is connected with the third trigger line STV3;

[0126] The third trigger end IN3 of the X-1 stage shift register unit GOA X-1 is connected with the first trigger line STV1, and the fourth trigger end IN4 of the X-1 stage shift register unit GOA X-1 is connected with the second trigger line STV2;

[0127] The third trigger end IN3 of the X stage shift register unit GOA X is connected with the third trigger line STV3, and the fourth trigger end IN4 of the X stage shift register unit GOA X is connected with the fourth trigger line STV4.

[0128] Figure 22 is Figure 21 a schematic diagram of clock signal and trigger signal in a forward scanning mode of the scanning circuit shown in Fig. Figure 22As shown, in the positive scanning mode, the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1*H; the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1*H. In the frame scanning starting stage, the phase of the trigger signal provided by the first trigger line STV1 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the fourth trigger line STV4, and the phase difference between the two is 1*H; in the frame scanning ending stage, the phase of the trigger signal provided by the first trigger line STV1 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the fourth trigger line STV4, and the phase difference between the two is 1*H.

[0129] Figure 23 is Figure 21 As shown in the scanning circuit, a clock signal and trigger signal schematic diagram of a reverse scanning mode; as Figure 23As shown, the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1*H; the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1*H. In the frame scanning starting stage, the phase of the trigger signal provided by the fourth trigger line STV4 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the first trigger line STV1, and the phase difference between the two is 1*H; in the frame scanning ending stage, the phase of the trigger signal provided by the fourth trigger line STV4 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the first trigger line STV1, and the phase difference between the two is 1*H. In addition, in the embodiment of the present application, the fifth trigger line to the eighth trigger line can multiplex the first to fourth trigger lines in other forms, which will not be described here.

[0130] In the present application, the first electrode of the first transistor M1 is connected to the first power terminal PW1, the first electrode of the second transistor M2 is connected to the second power terminal PW2, the first electrode of the third transistor M3 is connected to the second power terminal PW2, the first electrode of the fourth transistor M4 is connected to the first power terminal PW1, and the second electrode of the first transistor M1, the second electrode of the second transistor M2, the second electrode of the third transistor M3, and the second electrode of the fourth transistor M4 are all connected to the pull-up node PU. In the positive scan switching negative scan process or in the negative scan switching positive scan process, the power supply signals provided by the first power terminal PW1 and the second power terminal PW2 do not change, the first power terminal PW1 always provides the first power supply signal VGL, and the second power terminal PW2 always provides the second power supply signal VGH. Even if the threshold voltage of the first transistor M1 and the fourth transistor M4 increases and the driving capability decreases, the first transistor M1 and the fourth transistor M4 do not need to bear the function of pulling up the pull-up node PU. After a long time of positive scan, the scan circuit 100 can normally switch to the negative scan mode, or after a long time of negative scan, the scan circuit 100 can normally switch to the positive scan mode, so that the output stability, reliability, and reliability of the shift register unit 101 can be improved.

[0131] Based on the same inventive concept, the present application also provides a display panel and a display device, which comprise the array substrate according to any of the above embodiments. Optionally, the display panel is an organic light-emitting display panel, a micro LED display panel, or a liquid crystal display panel, etc., but is not limited thereto. Figure 24 is a schematic diagram of a display device provided by an embodiment of the present application. Optionally, the display device is applied to an electronic device 400 such as a smart phone, a tablet computer, or a vehicle display screen. It can be understood that the above-mentioned embodiments only provide part of the array substrate or partial structures, and the array substrate also includes other structures in actual applications, which will not be described here. The display device provided by the embodiment of the present application has all the functions and advantages of the display panel and the array substrate as described above, and will not be described in detail.

[0132] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An array substrate, characterized by, The application relates to a scan circuit. The scan circuit comprises a multi-stage shift register unit, which comprises at least a first input unit, a second input unit, a third input unit and a fourth input unit. The control end of the first input unit is electrically connected with a first trigger end, the input end of the first input unit is electrically connected with a first power supply end, and the output end of the first input unit is electrically connected with a pull-up node, for adjusting the potential of the pull-up node according to a first power supply signal provided by the first power supply end in response to the control of the first trigger end. The control end of the second input unit is electrically connected with a second trigger end, the input end of the second input unit is electrically connected with a second power supply end, and the output end of the second input unit is electrically connected with the pull-up node, for adjusting the potential of the pull-up node according to a second power supply signal provided by the second power supply end in response to the control of the second trigger end. The control end of the third input unit is electrically connected with a third trigger end, the input end of the third input unit is electrically connected with the second power supply end, and the output end of the third input unit is electrically connected with the pull-up node, for adjusting the potential of the pull-up node according to the second power supply signal provided by the second power supply end in response to the control of the third trigger end. The control end of the fourth input unit is electrically connected with a fourth trigger end, the input end of the fourth input unit is electrically connected with the first power supply end, and the output end of the fourth input unit is electrically connected with the pull-up node, for adjusting the potential of the pull-up node according to the first power supply signal provided by the first power supply end in response to the control of the fourth trigger end. The first power supply signal and the second power supply signal are electrically different. The first input unit comprises a first transistor, the gate of the first transistor is connected with the first trigger end, and the first transistor is connected between the first power supply end and the pull-up node. The second input unit comprises a second transistor, the gate of the second transistor is connected with the second trigger end, and the second transistor is connected between the second power supply end and the pull-up node. The third input unit comprises a third transistor, the gate of the third transistor is connected with the third trigger end, and the third transistor is connected between the second power supply end and the pull-up node. The fourth input unit comprises a fourth transistor, the gate of the fourth transistor is connected with the fourth trigger end, and the fourth transistor is connected between the first power supply end and the pull-up node.

2. The array substrate of claim 1, wherein, The shift register unit further comprises an output unit, the control end of the output unit is electrically connected with the pull-up node, the input end of the output unit is electrically connected with a first signal end, and the output end of the output unit is electrically connected with a driving output end, for adjusting the signal of the driving output end according to a first signal provided by the first signal end in response to the control of the pull-up node.

3. The array substrate of claim 2, wherein, The shift register unit further comprises a first reset unit, a control end of the first reset unit is electrically connected with the second signal end, an input end of the first reset unit is electrically connected with the first power supply end, and an output end of the first reset unit is electrically connected with the driving output end, for adjusting the signal of the driving output end according to the first power supply signal provided by the first power supply end in response to the control of the second signal provided by the second signal end.

4. The array substrate of claim 2, wherein, The output unit comprises a fifth transistor, a gate of the fifth transistor is connected with the pull-up node, and the fifth transistor is connected between the first signal end and the driving output end.

5. The array substrate of claim 3, wherein, The first reset unit comprises a sixth transistor, a gate of the sixth transistor is connected with the second signal end, and the sixth transistor is connected between the first power supply end and the driving output end.

6. The array substrate of claim 2, wherein, The shift register unit further comprises a second reset unit, a third reset unit and a node control unit; A control end of the second reset unit is electrically connected with a third signal end, an input end of the second reset unit is electrically connected with the first power supply end, and an output end of the second reset unit is electrically connected with the pull-up node, for adjusting the potential of the pull-up node according to the first power supply signal provided by the first power supply end in response to the control of the third signal end; A control end of the third reset unit is electrically connected with a fourth signal end, an input end of the third reset unit is electrically connected with the first power supply end, and an output end of the third reset unit is electrically connected with the driving output end, for adjusting the signal of the driving output end according to the first power supply signal provided by the first power supply end in response to the control of the fourth signal end; A control end of the node control unit is electrically connected with the pull-up node and the pull-down node, an input end of the node control unit is electrically connected with the first power supply end, and an output end of the node control unit is electrically connected with the pull-up node, the pull-down node and the driving output end, for adjusting the signals of the pull-up node, the pull-down node and the driving output end according to the first power supply signal provided by the first power supply end in response to the control of the pull-up node or the pull-down node.

7. The array substrate of claim 6, wherein, The second reset unit comprises a seventh transistor, a gate of the seventh transistor is connected with the third signal end, and the seventh transistor is connected between the first power supply end and the pull-up node; The third reset unit comprises an eighth transistor, a gate of the eighth transistor is connected with the fourth signal end, and the eighth transistor is connected between the first power supply end and the driving output end; The node control unit comprises a ninth transistor, a tenth transistor and an eleventh transistor, a gate of the ninth transistor is connected with the pull-up node, the ninth transistor is connected between the first power supply end and the pull-down node, gates of the tenth transistor and the eleventh transistor are both connected with the pull-down node, the tenth transistor is connected between the first power supply end and the pull-up node, and the eleventh transistor is connected between the first power supply end and the driving output end.

8. The array substrate of claim 7, wherein, The shift register unit further comprises a first capacitor and a second capacitor, the first capacitor is coupled between the pull-up node and the driving output terminal, and the second capacitor is coupled between the pull-down node and the first signal terminal.

9. The array substrate of claim 2, wherein, The scan circuit comprises Y clock signal lines and k*Y trigger lines, wherein k≥1, Y≥2 and both are positive integers.

10. The array substrate of claim 9, wherein, The scan circuit comprises a forward scan mode and a reverse scan mode.

11. The array substrate of claim 10, wherein, The scan circuit comprises X-stage shift register units, and each stage of the shift register units comprises at least one shift output terminal.

12. The array substrate of claim 11, wherein, The shift output terminal multiplexes the driving output terminal.

13. The array substrate of claim 11, wherein, The scan circuit comprises two clock signal lines and two trigger lines, the clock signal lines comprise a first clock signal line and a second clock signal line, and the trigger lines comprise a first trigger line and a second trigger line. The first trigger end of the first-stage shift register unit of the scan circuit is connected to the first trigger line, and the second trigger end of the first-stage shift register unit is connected to the second trigger line. The first trigger end of the second-stage shift register unit is connected to the second trigger line, and the second trigger end of the second-stage shift register unit is connected to the shift output terminal of the first-stage shift register unit.

14. The array substrate of claim 13, wherein, The third trigger end of the X-1-stage shift register unit of the scan circuit is connected to the shift output terminal of the X-stage shift register unit, and the fourth trigger end of the X-1-stage shift register unit is connected to the second trigger line; the third trigger end of the X-stage shift register unit is connected to the second trigger line, and the fourth trigger end of the X-stage shift register unit is connected to the first trigger line. Or, The third trigger end of the X-1-stage shift register unit is connected to the shift output terminal of the X-stage shift register unit, the fourth trigger end of the X-1-stage shift register unit is connected to the first trigger line, the third trigger end of the X-stage shift register unit is connected to the first trigger line, and the fourth trigger end of the X-stage shift register unit is connected to the second trigger line.

15. The array substrate of claim 11, wherein, The scan circuit comprises two clock signal lines and four trigger lines, the clock signal lines comprise a first clock signal line and a second clock signal line, and the trigger lines comprise a first trigger line, a second trigger line, a third trigger line and a fourth trigger line. The first trigger end of the first-stage shift register unit of the scan circuit is connected to the first trigger line, and the second trigger end of the first-stage shift register unit is connected to the second trigger line. The first trigger end of the second-stage shift register unit is connected to the second trigger line, and the second trigger end of the second-stage shift register unit is connected to the shift output terminal of the first-stage shift register unit. The third trigger end of the X-1-stage shift register unit is connected to the shift output terminal of the X-stage shift register unit, and the fourth trigger end of the X-1-stage shift register unit is connected to the third trigger line. The third trigger end of the X-stage shift register unit is connected to the third trigger line, and the fourth trigger end of the X-stage shift register unit is connected to the fourth trigger line.

16. The array substrate of claim 11, wherein, The scan circuit comprises four clock signal lines and four trigger lines, the clock signal lines comprise a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, and the trigger lines comprise a first trigger line, a second trigger line, a third trigger line and a fourth trigger line; The first trigger end of the first stage shift register unit is connected with the first trigger line, and the second trigger end of the first stage shift register unit is connected with the second trigger line; The first trigger end of the second stage shift register unit is connected with the third trigger line, and the second trigger end of the second stage shift register unit is connected with the fourth trigger line; The first trigger end of the third stage shift register unit is connected with the second trigger line, and the second trigger end of the third stage shift register unit is connected with the shift output end of the first stage shift register unit; The first trigger end of the fourth stage shift register unit is connected with the fourth trigger line, and the second trigger end of the fourth stage shift register unit is connected with the shift output end of the second stage shift register unit.

17. The array substrate of claim 16, wherein, The third trigger end of the X-3 stage shift register unit of the scan circuit is connected with the shift output end of the X-1 stage shift register unit, and the fourth trigger end of the X-3 stage shift register unit is connected with the first trigger line; The third trigger end of the X-2 stage shift register unit is connected with the shift output end of the X stage shift register unit, and the fourth trigger end of the X-2 stage shift register unit is connected with the third trigger line; The third trigger end of the X-1 stage shift register unit is connected with the first trigger line, and the fourth trigger end of the X-1 stage shift register unit is connected with the second trigger line; The third trigger end of the X stage shift register unit is connected with the third trigger line, and the fourth trigger end of the X stage shift register unit is connected with the fourth trigger line.

18. The array substrate of claim 11, wherein, The scan circuit comprises four clock signal lines and eight trigger lines, the clock signal lines comprise a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, and the trigger lines comprise a first trigger line, a second trigger line, a third trigger line, a fourth trigger line, a fifth trigger line, a sixth trigger line, a seventh trigger line and an eighth trigger line; The first trigger end of the first stage shift register unit is connected with the first trigger line, and the second trigger end of the first stage shift register unit is connected with the second trigger line; The first trigger end of the second stage shift register unit is connected with the third trigger line, and the second trigger end of the second stage shift register unit is connected with the fourth trigger line; The first trigger end of the third stage shift register unit is connected with the second trigger line, and the second trigger end of the third stage shift register unit is connected with the shift output end of the first stage shift register unit; The first trigger end of the fourth stage shift register unit is connected with the fourth trigger line, and the second trigger end of the fourth stage shift register unit is connected with the shift output end of the second stage shift register unit. The third trigger end of the X-3 stage shift register unit is connected with the shift output end of the X-1 stage shift register unit, and the fourth trigger end of the X-3 stage shift register unit is connected with the fifth trigger line; The third trigger end of the X-2th shift register unit is connected with the shift output end of the Xth shift register unit, and the fourth trigger end of the X-2th shift register unit is connected with the seventh trigger line; The third trigger end of the X-1th shift register unit is connected with the fifth trigger line, and the fourth trigger end of the X-1th shift register unit is connected with the sixth trigger line; The third trigger end of the Xth shift register unit is connected with the seventh trigger line, and the fourth trigger end of the Xth shift register unit is connected with the eighth trigger line.

19. An array substrate, comprising: The array substrate comprises Xth shift register units, and each shift register unit comprises a forward and backward scanning module, and the forward and backward scanning module comprises a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor of the nth shift register unit is connected with the shift output end or the trigger line of the n-2ith shift register unit, n≤X, i≥1, the first pole of the first transistor is connected with a first power supply end, and the second pole is connected with a pull-up node; the first power supply end is used for providing a first power supply signal; The gate of the second transistor of the nth shift register unit is connected with the shift output end or the trigger line of the n-ith shift register unit, the first pole of the second transistor is connected with a second power supply end, and the second pole is connected with the pull-up node; the second power supply end is used for providing a second power supply signal; The gate of the third transistor of the nth shift register unit is connected with the shift output end or the trigger line of the n+i th shift register unit, the first pole of the third transistor is connected with the second power supply end, and the second pole is connected with the pull-up node; The gate of the fourth transistor of the nth shift register unit is connected with the shift output end or the trigger line of the n+2ith shift register unit, the first pole of the fourth transistor is connected with the first power supply end, and the second pole is connected with the pull-up node; The first power supply signal and the second power supply signal are electrically different.

20. The array substrate of claim 19, wherein, The shift register unit further comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor and a first capacitor; The gate of the fifth transistor is connected with the pull-up node, the first pole of the fifth transistor is connected with a first signal end, and the second pole of the fifth transistor is connected with a driving output end; The gate of the sixth transistor is connected with a second signal end, the first pole of the sixth transistor is connected with the first power supply end, and the second pole of the sixth transistor is connected with the driving output end; The gate of the seventh transistor is connected with a third signal end, the first pole of the seventh transistor is connected with the first power supply end, and the second pole of the seventh transistor is connected with the pull-up node; The gate of the eighth transistor is connected with a fourth signal end, the first pole of the eighth transistor is connected with the first power supply end, and the second pole of the eighth transistor is connected with the driving output end; The gate of the ninth transistor is connected with the pull-up node, the first pole of the ninth transistor is connected with the first power supply end, and the second pole of the ninth transistor is connected with a pull-down node; The gate of the tenth transistor and the eleventh transistor is connected with the pull-down node, the first pole of the tenth transistor and the eleventh transistor is connected with the first power supply end, the second pole of the tenth transistor is connected with the pull-up node, and the second pole of the eleventh transistor is connected with the driving output end. The first pole of the first capacitor is connected with the driving output end, and the second pole of the first capacitor is connected with the pull-up node.

21. The array substrate of claim 20, wherein, The shift register unit further comprises a second capacitor, the first pole of the second capacitor is connected with the first signal end, and the second pole of the second capacitor is connected with the pull-down node.

22. A display panel, characterized in that, The display panel comprises: The array substrate of any one of claims 1-21.

23. A display device, characterized in that, The display panel of claim 22. ​

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