Array substrate, display driver, display screen module, terminal

Abstract

Embodiments of the present application provide an array substrate, a display driver, a display screen module and a terminal, and relate to the technical field of electronics, and are used for providing a terminal capable of improving display effect or reducing power consumption. The array substrate comprises two groups of parallel light-emitting driving array circuits, and the two groups of parallel light-emitting driving array circuits respectively output an anti-creeping control signal and a light-emitting duty cycle control signal. However, the two groups of light-emitting driving array circuits are controlled by clock signals of different frequencies, so that the frequencies of the anti-creeping control signal and the light-emitting duty cycle control signal are decoupled, thereby realizing decoupling of display effect and power consumption. Adjusting the controlled clock frequency of the light-emitting duty cycle control signal to be less than the controlled clock frequency of the anti-creeping control signal can improve the display effect without increasing the power consumption, or can reduce the power consumption while ensuring the display effect.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to an array substrate, a display driver, a display module, and a terminal. Background Technology

[0002] Currently, in the process of displaying images on a self-emissive display screen, a scan driving circuit located in the non-display area is required to provide scan signals and emission control signals, in conjunction with a data driving circuit to provide image data signals, to drive the pixel circuit located in the effective display area to perform image display. In recent years, in order to improve the integration of the display screen, the gate scan driving circuit, the emission scan driving circuit, and the pixel array are fabricated together on the array substrate, which is commonly referred to in the art as the gate on array (GOA) circuit and the emission on array (EOA) circuit.

[0003] The image display of a screen is affected by the GOA (Graphical Object Array) and EOA (Graphical Object Array) circuits. Therefore, the display effect and power consumption of the screen are also affected by these circuits, with the EOA circuit having a more significant impact. How to improve the display effect without increasing power consumption, or how to reduce power consumption while maintaining display effect, is a technical challenge that those skilled in the art are currently working to solve. Summary of the Invention

[0004] This application provides an array substrate, a display driver, a display module, and a terminal, which can improve the display effect without increasing power consumption, or reduce power consumption while ensuring the display effect.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, this application provides an array substrate, which may or may not have light-emitting units. The array substrate includes a first light-emitting driving array circuit, a second light-emitting driving array circuit, and a pixel circuit. The first light-emitting driving array circuit includes a first clock signal terminal, a second clock signal terminal, a start-leakage protection control signal terminal, and a first output terminal, used to generate a leakage protection control signal based on a first clock signal received by the first clock signal terminal, a second clock signal received by the second clock signal terminal, and a start-leakage protection control signal received by the start-leakage protection control signal terminal. The second light-emitting driving array circuit includes a third clock signal terminal, a fourth clock signal terminal, a start-light-emitting duty cycle control signal terminal, and a second output terminal, used to generate a light-emitting duty cycle control signal based on a third clock signal received by the third clock signal terminal, a fourth clock signal received by the fourth clock signal terminal, and a start-light-emitting duty cycle control signal received by the start-light-emitting duty cycle control signal terminal. The pixel circuit includes a light-emitting control signal terminal; the light-emitting control signal terminal is used to receive the leakage protection control signal to prevent data voltage leakage. The light-emitting control signal terminal is also used to receive the light-emitting duty cycle control signal to drive the light-emitting units to emit light. Where f1 is the frequency of the first clock signal and the second clock signal, and f2 is the frequency of the third clock signal and the fourth clock signal. <f1。

[0007] The array substrate provided in this application embodiment controls a first light-emitting drive array circuit with a first frequency clock signal and a second light-emitting drive array circuit with a second frequency clock signal. This decouples the frequency of the leakage protection control signal and the frequency of the light-emitting duty cycle control signal, allowing for independent adjustment of the frequency of the light-emitting duty cycle control signal while matching the screen refresh rate of the leakage protection control signal. This achieves decoupling between display effect and power consumption. By setting the second frequency to be lower than the first frequency, the frequency (propagation speed) of the light-emitting duty cycle control signal can be reduced, increasing the brightness-dark space cycle of the display screen using this array substrate. This improves the display effect without increasing power consumption and reduces power consumption while maintaining the display effect.

[0008] In addition, by reducing the frequency of the light emission duty cycle control signal, the requirements on the switching frequency that the pixel circuit in the array substrate can withstand can be reduced, making some array substrates that cannot meet the high-frequency switching requirements acceptable and reducing array substrate yield loss.

[0009] In one possible implementation, the array substrate further includes a logic operation circuit; the input terminal of the logic operation circuit is coupled to the first output terminal and the second output terminal, and the output terminal is coupled to the light emission control signal terminal, for performing logic operations on the leakage protection control signal and the light emission duty cycle control signal, and outputting the operation result as the light emission control signal to the light emission control signal terminal.

[0010] By performing logical operations on the leakage protection control signal and the light emission duty cycle control signal before outputting them to the light emission control signal terminal, the light emission control signal terminal only receives one final light emission control signal. Therefore, the structure of the pixel circuit in the array substrate does not need to be modified, and pixel circuits in related technologies are applicable to the embodiments of this application, reducing the workload of modifications. Furthermore, since only one light emission control signal is output, only one output switch is needed, without increasing the width of the bezel.

[0011] In one possible implementation, f2 / f1 takes values ​​from 1 / 5 to 3 / 4. This is a range of values ​​applicable to a given range of light.

[0012] In one possible implementation, the value of f2 / f1 is between 1 / 3 and 1 / 2. If the second frequency is too low, the user will see the black bar moving, affecting the display effect. If the second frequency is too high, it will increase power consumption. Therefore, setting the second frequency within the range of 1 / 3 to 1 / 2 of the first frequency can ensure display effect with lower power consumption.

[0013] In one possible implementation, the logic operation circuit includes an OR operation circuit. This is a structurally simple implementation.

[0014] In one possible implementation, the logic operation circuit includes an AND operation circuit. This is a structurally simple implementation.

[0015] In one possible implementation, the first light-emitting drive array circuit includes multiple cascaded first light-emitting drive units. The first-stage first light-emitting drive unit is coupled to a start-up leakage protection control signal terminal, and each stage of the first light-emitting drive unit is coupled to both a first clock signal terminal and a second clock signal terminal. The second light-emitting drive array circuit includes multiple cascaded second light-emitting drive units. The first-stage second light-emitting drive unit is coupled to a start-up light emission duty cycle control signal terminal, and each stage of the second light-emitting drive unit is coupled to both a third clock signal terminal and a fourth clock signal terminal. This is a structurally simple implementation.

[0016] In one possible implementation, the array substrate includes multiple pixel circuits arranged in an array; the logic operation circuit includes multiple logic operation units, the input terminals of which are correspondingly coupled to the first output terminals of the first light-emitting driving unit and the second output terminals of the second light-emitting driving unit located in the same level, and the light-emitting control signal terminals of the pixel circuits located in the same row are coupled to the output terminals of the same logic operation unit. This is a structurally simple implementation.

[0017] In a possible implementation, the light-emitting control signal terminals of pixel circuits located in multiple rows are coupled to the output terminals of the same logic operation unit. In this way, the pixel circuits in multiple rows share the same set of logic operation units, first light-emitting drive units, and second light-emitting drive units, which can reduce the number of devices in the non-display area, save costs, and facilitate the realization of narrow borders.

[0018] In a second aspect of the embodiments of the present application, a display driver is provided, including: a timing circuit and a starting light-emitting control signal generation circuit; the timing circuit is configured to generate a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, f1 is the frequency of the first clock signal and the second clock signal, f2 is the frequency of the third clock signal and the fourth clock signal, and f2 < f1; the starting light-emitting control signal generation circuit is configured to generate a starting anti-leakage control signal and a starting light-emitting duty ratio control signal. The beneficial effects of the display driver provided in the second aspect of the embodiments of the present application are the same as those of the array substrate provided in the first aspect, and will not be elaborated here.

[0019] In a possible implementation, the value of f2 / f1 is from 1 / 5 to 3 / 4.

[0020] In a possible implementation, the value of f2 / f1 is from 1 / 3 to 1 / 2.

[0021] In a third aspect of the embodiments of the present application, a display screen module is provided, including an array substrate and a display driver, and the display driver is bonded to the array substrate; the array substrate includes the array substrate according to any one of the first aspect; and / or, the display driver includes the display driver according to any one of the second aspect.

[0022] In a fourth aspect of the embodiments of the present application, a terminal is provided, including a housing and a display screen module, and the display screen module is disposed in the housing; the display screen module includes the display screen module according to the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A It is an architecture diagram of an electronic device provided by the embodiments of the present application;

[0024] Figure 1B It is a schematic diagram of a display screen module provided by the embodiments of the present application;

[0025] Figure 2 It is a circuit schematic diagram of a sub-pixel provided by the embodiments of the present application;

[0026] Figure 3 It is a driving timing diagram of a pixel circuit provided by the embodiments of the present application;

[0027] Figures 4A-4CA schematic diagram illustrating the on / off state of a transistor during pixel circuit driving, provided in an embodiment of this application;

[0028] Figure 5 A waveform diagram of a light emission control signal provided in an embodiment of this application;

[0029] Figure 6 This is a brightness distribution map of the display screen at a certain moment in a frame;

[0030] Figure 7 A schematic diagram of the layout of an array substrate provided in an embodiment of this application;

[0031] Figure 8 Waveform diagrams of a leakage current prevention control signal and a light emission duty cycle control signal provided in an embodiment of this application;

[0032] Figure 9 Waveform diagrams of the first timing signal, the second timing signal, the third timing signal, and the fourth timing signal are provided for embodiments of this application;

[0033] Figure 10 This is a brightness distribution map of the display screen at a certain moment in a frame;

[0034] Figures 11A-12 A schematic diagram of the layout of an array substrate provided in an embodiment of this application;

[0035] Figure 13 This is a schematic diagram of the structure of a display module provided in an embodiment of this application. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0037] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0038] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0039] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0040] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0041] This application provides a terminal. The terminal can be, for example, a consumer electronics product with a display function, a home electronics product, an in-vehicle electronics product, or a financial terminal product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminals, augmented reality (AR) terminals, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. This application does not impose any special limitations on the specific form of the above-mentioned terminal.

[0042] Figure 1A This is an architecture diagram of a terminal 1 provided in an embodiment of this application. Figure 1B This is a schematic diagram of a display module 3 provided in an embodiment of this application.

[0043] Taking a mobile phone as an example, such as Figure 1AAs shown, terminal 1 mainly includes a cover plate 2, a display module 3, a middle frame 4, and a back cover 5. The back cover 5 and the display module 3 are located on both sides of the middle frame 4, and the middle frame 4 and the display module 3 are disposed inside the back cover 5. The cover plate 2 is disposed on the side of the display module 3 away from the middle frame 4, and the display surface of the display module 3 faces the cover plate 2. Figure 1A The example shown uses a flat-screen mobile phone as terminal 1. However, terminal 1 in this embodiment can also be a foldable-screen mobile phone. Figure 1A This is just an illustration.

[0044] In some embodiments, such as Figure 1B As shown, the display module 3 includes a display screen and a display driver 20. The display screen can be an organic light-emitting diode (OLED) display screen, which is capable of self-illumination. The display screen can also be a micro OLED display screen. The display screen includes an active display area (AA) and a non-display area BB located around the active display area AA. The active display area AA is used to display images. The display screen may include one active display area AA, or it may include multiple active display areas AA.

[0045] The display screen includes an array substrate 10, and the effective display area AA of the display screen is the effective display area of ​​the array substrate 10. The array substrate 10 includes multiple sub-pixels (SPs), and each sub-pixel is provided with a pixel circuit 11 and a light-emitting unit 12. The pixel circuit 11 is used to drive the light-emitting unit 12 to emit light, and the light-emitting unit 12 can be, for example, an OLED.

[0046] In this application, the description uses a subpixel SP array arrangement as an example. Subpixel SPs arranged in a row along the horizontal direction X are called the same row of subpixel SPs, and the pixel circuits 11 in the same row of subpixel SPs are called a row of pixel circuits 11. Subpixel SPs arranged in a row along the vertical direction Y are called the same column of subpixel SPs, and the pixel circuits 11 in the same column are called a column of pixel circuits 11.

[0047] The display driver 20 can be a display driver integrated circuit (DDIC). In this case, the display driver 20 can be bonded to the array substrate 10 via pads provided on the non-display area BB of the array substrate 10.

[0048] The display driver 20 can be coupled to a system-on-chip (SOC) via a mobile industry processor interface (MIPI). Alternatively, the display driver 20 can also be coupled to the SOC via other high-speed serial / deserial (SerDes) interfaces, with the SOC providing image data to the display driver 20.

[0049] The display driver 20 is used to provide the array substrate 10 with the scanning start signal, timing signal and data signal required for the display screen to emit light. The signals sent by the display driver 20 will be explained in detail later in conjunction with the structure of the pixel circuit 11, and will not be explained here.

[0050] In some embodiments, the pixel circuit 11 typically includes multiple transistors, and the pixel circuit 11 generates a driving current to drive the light-emitting unit 12 to emit light, thereby realizing the emission of the sub-pixel SP.

[0051] In some embodiments, the array substrate 10 includes a light-emitting unit 12, and the array substrate 10 may be equivalent to the display screen of the terminal 1.

[0052] In some other embodiments, the array substrate 10 does not include the light-emitting unit 12. After the array substrate 10 and the light-emitting unit 12 are assembled, they form the display screen of the terminal 1.

[0053] Figure 2 This is a circuit schematic diagram of a subpixel provided in an embodiment of this application.

[0054] In some embodiments, such as Figure 2 As shown, the pixel circuit 11 includes an anode reset circuit 111, a first node initialization circuit 112, a write and threshold compensation circuit 113, and an emissive control circuit 114. Figure 2 The pixel circuit 11 shown is merely an illustration and is not intended to be limiting.

[0055] The anode reset circuit 111 is coupled to the first initialization voltage terminal Vinit1, the first scan signal terminal S1, and the output terminal of the pixel circuit 11 (the anode of the light-emitting unit 12). Under the control of the first scan signal s1 of the first scan signal terminal S1, it transmits the first initialization voltage of the first initialization voltage terminal Vinit1 to the anode of the light-emitting unit 12 to initialize the anode of the light-emitting unit 12.

[0056] The first node initialization circuit 112 is coupled to the second initialization voltage terminal Vinit2, the second scan signal terminal S2, the third scan signal terminal S3, the first node N1, and the second node N2. Under the control of the second scan signal s2 of the second scan signal terminal S2 and the third scan signal s3 of the third scan signal terminal S3, it transmits the second initialization voltage of the second initialization voltage terminal Vinit2 to the first node N1 and the second node N2 to initialize the first node N1 and the second node N2.

[0057] The write and threshold compensation circuit 113 is coupled to the fourth scan signal terminal S4, the third scan signal terminal S3, the second node N2, the first power supply voltage terminal ELVDD, and the data voltage terminal Vdata. Under the control of the fourth scan signal s4 of the fourth scan signal terminal S4 and the third scan signal s3 of the third scan signal terminal S3, the data voltage of the data voltage terminal Vdata is transmitted to the write and threshold compensation circuit 113 to perform data writing and threshold compensation.

[0058] The light-emitting control circuit 114 is coupled to the light-emitting control signal terminal EM, the first power supply voltage terminal ELVDD, the write and threshold compensation circuit 113, and the light-emitting unit 12, and is used to provide driving current to the light-emitting unit 12 under the control of the light-emitting control signal provided by the light-emitting control signal terminal EM.

[0059] The light-emitting unit 12 is coupled to the second power supply voltage terminal ELVSS and is used to emit light under the drive of the driving current.

[0060] In this embodiment, the first power supply voltage terminal ELVDD is used as a high-level power supply voltage terminal and the second power supply voltage terminal ELVSS is used as a low-level power supply voltage terminal for illustration, but it is not limited to this.

[0061] In some embodiments, reference Figure 2 The pixel circuit 11 includes seven transistors and one storage capacitor, commonly referred to in the art as a 7T1C pixel circuit. The anode reset circuit 111 includes a seventh transistor T7, the first node initialization circuit 112 includes a fourth transistor T4 and a third transistor T3, the write and threshold compensation circuit 113 includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst, and the light emission control circuit 114 includes a fifth transistor T5 and a sixth transistor T6. The first transistor T1 is a driving transistor, and the remaining transistors are switching transistors. The first node initialization circuit 112 and the write and threshold compensation circuit 113 share the third transistor T3.

[0062] In the following description, the control electrode of a transistor can be, for example, the gate electrode, and the first electrode and the second electrode can be the source and drain electrode, respectively. This is explained here and will not be further explained below.

[0063] The control terminal of the fourth transistor T4 is coupled to the second scan signal terminal S2, the first terminal of the fourth transistor T4 is coupled to the second initialization voltage terminal Vinit2, and the second terminal of the fourth transistor T4 is coupled to the fourth node N4.

[0064] The control electrode of the third transistor T3 is coupled to the third scan signal terminal S3, the first electrode of the third transistor T3 is coupled to the fourth node N4, and the second electrode of the third transistor T3 is coupled to the first node N1.

[0065] The control terminal of the second transistor T2 is coupled to the fourth scan signal terminal S4, the first terminal of the second transistor T2 is coupled to the data voltage terminal Vdata, and the second terminal of the second transistor T2 is coupled to the third node N3.

[0066] The control electrode of the first transistor T1 is coupled to the first node N1, the first electrode of the first transistor T1 is coupled to the third node N3, and the second electrode of the first transistor T1 is coupled to the second node N2. The second node N2 is also coupled to the fourth node N4.

[0067] One end of the storage capacitor Cst is coupled to the first node N1, and the other end of the storage capacitor Cst is coupled to the first power supply voltage terminal ELVDD.

[0068] The control electrode of the fifth transistor T5 is coupled to the light-emitting control signal terminal EM, the first electrode of the fifth transistor T5 is coupled to the first power supply voltage terminal ELVDD, and the second electrode of the fifth transistor T5 is coupled to the third node N3.

[0069] The control electrode of the sixth transistor T6 is coupled to the light-emitting control signal terminal EM, the first electrode of the sixth transistor T6 is coupled to the second node N2, and the second electrode of the sixth transistor T6 is coupled to the anode of the light-emitting unit 12.

[0070] The control electrode of the seventh transistor T7 is coupled to the first scan signal terminal S1, the first electrode of the seventh transistor T7 is coupled to the first initialization voltage terminal Vinit1, and the second electrode of the seventh transistor T7 is coupled to the anode of the light-emitting unit 12.

[0071] The control terminal of the eighth transistor T8 is coupled to the first scan signal terminal S1, the first terminal of the eighth transistor T8 is coupled to the second initialization voltage terminal Vinit2, and the second terminal of the eighth transistor T8 is coupled to the second node N2.

[0072] For example, in pixel circuit 11, the third transistor T3 and the fourth transistor T4 are Oxide TFTs, which are N-type transistors and are turned on under the control of a high-level signal. The third transistor T3 and the fourth transistor T4 can also be other types of transistors, which is not limited in this embodiment. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are LTPS TFTs, which are P-type transistors and are turned on under the control of a low-level signal. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can also be other types of transistors, which is not limited in this embodiment.

[0073] Figure 3 This application provides a driving timing diagram for a pixel circuit according to an embodiment. Figures 4A-4C This is a schematic diagram illustrating the on / off state of a transistor during the pixel circuit driving process, provided in an embodiment of this application.

[0074] Combination Figure 3 and Figures 4A-4C As shown, the light emission process of the pixel circuit 11 in one frame can be divided into an initialization stage t1, a writing and compensation stage t2, and a light emission stage t3.

[0075] During initialization phase t1:

[0076] like Figure 3 and Figure 4A As shown, the second scan signal s2 at the second scan signal terminal S2 and the third scan signal s3 at the third scan signal terminal S3 change from high level to low level, and then from low level to high level. Consequently, the fourth transistor T4 and the third transistor T3 change from off to on, and then from on to off.

[0077] The first scan signal s1 of the first scan signal terminal S1, the fourth scan signal s4 of the fourth scan signal terminal S4, and the light emission control signal em of the light emission control signal terminal EM are all kept at a high level. Therefore, the seventh transistor T7, the eighth transistor T8, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are all kept in the off state.

[0078] During initialization phase t1, the first transistor T1, the third transistor T3, and the fourth transistor T4 are turned on, realizing voltage control of the fourth node N4, the second node N2, and the first node N1. Since the third transistor T3 and the fourth transistor T4 act as switches, the first node N1 is electrically connected to the control electrode of the first transistor T1, and the second node N2 is electrically connected to the fourth node N4. Therefore, during initialization phase t1, the control electrode voltage of the first transistor T1, the voltage of node N1, the voltage of the second node N2, and the voltage of the fourth node N4 are all controlled. This makes the control electrode voltage of the first transistor T1, the voltage of the first node N1, the voltage of the second node N2, and the voltage of the fourth node N4 the second initialization voltage of the second initialization voltage terminal Vinit2. In other words, the voltages of the control electrode voltage of the first transistor T1, the voltage of the first node N1, the voltage of the second node N2, and the voltage of the fourth node N4 are reset.

[0079] During the write and compensation phase t2:

[0080] like Figure 3 and Figure 4B As shown, the fourth scan signal s4 at the fourth scan signal terminal S4 changes from high level to low level, and then from low level to high level. Consequently, the second transistor T2 changes from off to on, and then from on to off. Similarly, the third scan signal s3 at the third scan signal terminal S3 changes from low level to high level, and then from high level to low level. Consequently, the third transistor T3 changes from off to on, and then from on to off.

[0081] During the write and compensation phase t2, the second transistor T2, the third transistor T3, and the first transistor T1 are turned on, storing the data voltage Vdata at the data voltage terminal in the storage capacitor Cst, thus completing the data voltage write. This also compensates for the threshold voltage of the first transistor T1. The compensation process for the threshold voltage of the first transistor T1 can be considered as the process of the first transistor T1 changing from the on state to the off state.

[0082] During the writing and compensation phase t2, the light emission control signal em at the light emission control signal terminal EM and the second scan signal s2 at the second scan signal terminal S2 are both kept at a high level. Therefore, the fifth transistor T5, the sixth transistor T6, and the fourth transistor T4 are all kept off.

[0083] In some embodiments, the anode of the light-emitting unit 12 is initialized simultaneously during the writing and compensation phase t2. Of course, the anode of the light-emitting unit 12 may be initialized once or multiple times at any time before the light-emitting phase t3.

[0084] For example, the first scan signal s1 at the first scan signal terminal S1 changes from high level to low level, and then from low level to high level. As a result, the seventh transistor T7 changes from off to on, and then from on to off.

[0085] The seventh transistor T7 is turned on, which realizes the control of the anode voltage of the light-emitting unit 12, so that the voltage of the anode of the light-emitting unit 12 is the first initialization voltage of the first initialization voltage terminal Vinit1, thus realizing the reset of the anode voltage of the light-emitting unit 12.

[0086] During the luminescence stage t3:

[0087] like Figure 3 and Figure 4C As shown, the light emission control signal em changes from high level to low level, and then from low level to high level. Consequently, the sixth transistor T6 and the fifth transistor T5 change from off to on, and then from on to off.

[0088] The first scan signal s1 of the first scan signal terminal S1, the second scan signal s2 of the second scan signal terminal S2, the third scan signal s3 of the third scan signal terminal S3, and the fourth scan signal s4 of the fourth scan signal terminal S4 are all kept at high levels, while the seventh transistor T7, the fourth transistor T4, the third transistor T3, and the second transistor T2 are all kept in the off state.

[0089] During the light-emitting stage t3, the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are turned on respectively, transmitting driving current to the light-emitting unit 12, and the light-emitting unit 12 emits light under the drive of the driving current.

[0090] As described above, the timing of the light emission control signal em at the light emission control signal terminal EM within a frame is as follows: during the initialization phase t1 and the write and compensation phase t2, the transistors in the light emission control circuit 114 remain off. In the write and compensation phase t2, the off-state of the light emission control circuit 114 by the light emission control signal em at the light emission control signal terminal EM prevents data voltage leakage from the data voltage terminal Vdata to the first power supply voltage terminal ELVDD and / or the second power supply voltage terminal ELVSS. In the light emission phase t3, the on-state of the light emission control circuit 114 by the light emission control signal em at the light emission control signal terminal EM, allowing adjustment of the display screen's brightness via the duty cycle. The duty cycle of the light emission control signal em can be adjusted using pulse-width modulation (PWM) technology.

[0091] The origin of the scanning signals received by the first scanning signal terminal S1, the second scanning signal terminal S2, the third scanning signal terminal S3, the fourth scanning signal terminal S4, and the light emission control signal terminal EM in the pixel circuit 11 will be illustrated below.

[0092] like Figure 1B As shown, in some embodiments, the array substrate 10 further includes a light-emitting drive array circuit EOA, which is used to transmit light-emitting control signals em to the light-emitting control signal terminals EM of the plurality of pixel circuits 11 in the array substrate 10.

[0093] In some embodiments, such as Figure 1B As shown, the light-emitting drive array circuit EOA includes multiple cascaded light-emitting drive units eoa, each of which is used to provide a light-emitting control signal em to a row of pixel circuits 11.

[0094] Of course, two or more light-emitting drive array circuits EOA can also be provided in the array substrate 10. Each light-emitting drive array circuit EOA is used to provide light-emitting control signal em for a portion of the pixel circuits 11 in a row.

[0095] Each stage of the light-emitting driver unit (EOA) receives a first clock signal clk1 and a second clock signal clk2. The first clock signal clk1 and the second clock signal clk2 are used to control the propagation speed of the light-emitting control signal em. The first-stage light-emitting driver unit (EOA) receives the initial light-emitting control signal STV-em and outputs the light-emitting control signal em. Starting from the second stage, each stage of the light-emitting driver unit (EOA) receives the light-emitting control signal em output by the previous stage's EOA and outputs the corresponding light-emitting control signal em for its current stage. Taking an effective display area AA comprising 10 rows of pixel circuits 11 as an example, the light-emitting driver array circuit EOA comprises 10 cascaded light-emitting driver units (EOA), and the generated light-emitting control signal em includes the first-stage light-emitting control signal em1 to the tenth-stage light-emitting control signal em10.

[0096] In some embodiments, the start-up control signal STV-em, the first clock signal clk1, and the second clock signal clk2 are provided by the display driver 20. The light-emitting drive array circuit EOA is used to receive the start-up control signal STV-em, the first clock signal clk1, and the second clock signal clk2 sent by the display driver 20, and to generate the light-emitting control signal em required by the pixel circuit 11.

[0097] Of course, one light-emitting driving unit eoa can provide a light-emitting control signal em for one row of pixel circuits 11, and one light-emitting unit eoa can also provide light-emitting control signals em for multiple rows of pixel circuits 11 simultaneously. Figure 1B The image is for illustrative purposes only and is not intended to be limiting.

[0098] like Figure 1BAs shown, in some embodiments, the array substrate 10 further includes a first scanning array circuit 13, which is similar in structure to the light-emitting drive array circuit EOA, and is used to transmit a first scanning signal s1 for each row of pixel circuits 11. The first scanning signal s1 generated by the first scanning array circuit 13 includes a first-level first scanning signal s1(1) to an nth-level first scanning signal s1(n), where n is the row number of pixel circuits 11 in the effective display area AA. The initial first scanning signal STV-s1 required by the first scanning array circuit 13 is provided by the display driver 20.

[0099] For example, such as Figure 1B As shown, the first scan signal s1 required by the row pixel circuit 11 is provided by the first scan array circuit 13 located on one side of the effective display area AA.

[0100] Alternatively, for example, the first scan signal s1 required by a row pixel circuit 11 is provided by a first scan array circuit 13 located on both sides of the effective display area AA, each of the first scan array circuits 13 providing the first scan signal s1, for example, to half a row pixel circuit 11.

[0101] The array substrate 10 also includes a second scanning array circuit 14, which is similar in structure to the light-emitting drive array circuit EOA, and is used to transmit a second scanning signal s2 for each row of pixel circuits 11. The second scanning signal s2 generated by the second scanning array circuit 14 includes a first-level second scanning signal s2(1) to an nth-level second scanning signal s2(n), and the initial second scanning signal STV-s2 required by the second scanning array circuit 14 is provided by the display driver 20.

[0102] The array substrate 10 also includes a third scanning array circuit 15, which is similar in structure to the light-emitting drive array circuit EOA, and is used to transmit a third scanning signal s3 for each row of pixel circuits 11. The third scanning signal s3 generated by the third scanning array circuit 15 includes a first-level third scanning signal s33(1) to an nth-level third scanning signal s3(n), and the initial third scanning signal STV-s3 required by the third scanning array circuit 15 is provided by the display driver 20.

[0103] The array substrate 10 also includes a fourth scan array circuit 16, which is similar in structure to the light-emitting drive array circuit EOA, and is used to transmit a fourth scan signal s4 for each row of pixel circuits 11. The fourth scan signal s4 generated by the fourth scan array circuit 16 includes a first-level fourth scan signal s4(1) to an nth-level fourth scan signal s4(n), and the initial fourth scan signal STV-s4 required by the fourth scan array circuit 16 is provided by the display driver 20.

[0104] Each pixel circuit 11 cycles through three stages: initialization stage t1, writing and compensation stage t2, and light emission stage t3. It is controlled by the light emission driving array circuit EOA, the first scanning array circuit 13, the second scanning array circuit 14, the third scanning array circuit 15, and the fourth scanning array circuit 16 located in the non-display area BB, and performs frame-by-frame and line-by-line scanning.

[0105] In some embodiments, the clock signals required by the first scan array circuit 13, the second scan array circuit 14, the third scan array circuit 15, and the fourth scan array circuit 16 are also provided by the display driver 20. Figure 1B The required clock signal is not shown in the diagram.

[0106] Figure 1B The structure of the light-emitting drive array circuit EOA, the first scanning array circuit 13, the second scanning array circuit 14, the third scanning array circuit 15, and the fourth scanning array circuit 16 shown, as well as their positions in the array substrate 10, are merely illustrative and are not intended to limit anything.

[0107] Figure 5 A waveform diagram of a light emission control signal provided in an embodiment of this application. Figure 6 This is a brightness distribution map of the display screen at a certain moment in a frame.

[0108] In some embodiments, the light emission control signal em output by each level of the light emission driving unit eoa is as follows: Figure 5 As shown, in each frame, the light emission control signal em will have a first high-level pulse A1. The first high-level pulse A1 is used to control the light emission control circuit 114 to turn off, so as to prevent the data voltage at the data voltage terminal Vdata from leaking to the first power supply voltage terminal ELVDD and / or the second power supply voltage terminal ELVSS. The toggle between the first high-level pulse A1 and the second high-level pulse A2 is used to adjust the brightness of the light emission by adjusting the duty cycle. For example... Figure 5 The brightness of the light source is adjusted using a 4-pulse PWM.

[0109] For example, if the screen refresh rate of the display is 120 Hz, then the frequency of the light emission control signal em is 480 (4 * 120) Hz, and the frequency of the arbitrary pixel circuit 11 in the light emission stage t3 is 480 Hz. Figure 5 As shown, at any given moment, the display screen always exhibits four cycles of alternating brightness, meaning the light-emitting control signal em alternates between on and off four cycles. For example, Figure 5 The vertical line in the image represents the selected time line. Four of the multiple lines of illumination control signals 'em' on the display intersect the time line, and these four intersecting lines are marked with black stripes. Therefore, as shown... Figure 6As shown, at any given time, the entire display screen has 4 rows of black stripes. The period of the bright and dark space of the display screen is 1 / 4 * screen height. The screen height is the size of the effective display area AA of the display screen in the direction of the 11 columns of the pixel circuit.

[0110] Because eye protection requires minimal fluctuations in luminous flux within the user's viewing area, the display's brightness-dark space cycle must be as small as possible. At a given frame rate and propagation speed (with a constant clock signal frequency), a higher frequency for the light-emitting control signal em is required. In particular, the light-emitting control signal em not only controls whether the light-emitting unit 12 emits light but also prevents pixel leakage during writing. However, since the light-emitting control signal em is an input to an RC model, a higher switching frequency of em results in higher heat dissipation and power consumption, leading to a higher overall power consumption for the terminal 1.

[0111] For example, to achieve better eye protection, it is desirable for the display's brightness-dark space cycle to be 1 / 12 * screen height, and the screen refresh rate to be 120 Hz. This would require the light-emitting control signal em to have a frequency of 12 * 120 Hz = 1440 Hz. This would increase the power consumption of terminal 1. Furthermore, because the light-emitting material in the light-emitting unit 12 includes parasitic capacitance, the light-emitting control signal em during the switching of the light-emitting unit 12 will exhibit both upward and downward fluctuations due to the influence of these capacitances. If the switching frequency is too high, the proportion of these upward and downward fluctuations will be too large, affecting the display effect.

[0112] To reduce power consumption, it is desirable to set the frequency of the light emission control signal em to 480Hz. This results in a brightness interval of 1 / 4 * screen height, leading to poor eye protection.

[0113] Based on this, this application provides a terminal 1 that can reduce power consumption while achieving the same eye protection effect. It improves the eye protection effect while maintaining the same power consumption.

[0114] Figure 7 This is a schematic diagram of the layout of an array substrate provided in an embodiment of this application.

[0115] This application provides an array substrate 10, such as Figure 7 As shown, the array substrate 10 includes a pixel circuit 11, a first light-emitting drive array circuit EOA1, and a second light-emitting drive array circuit EOA2.

[0116] The first light-emitting drive array circuit EOA1 is disposed in the non-display area BB of the array substrate 10. For example, the first light-emitting drive array circuit EOA1 is disposed on one or both sides of the pixel circuit 11 array along the row direction of the pixel circuit 11.

[0117] The second light-emitting drive array circuit EOA2 is disposed in the non-display area BB of the array substrate 10. For example, the second light-emitting drive array circuit EOA2 is disposed on one or both sides of the pixel circuit 11 array along the row direction of the pixel circuit 11.

[0118] In some embodiments, the first light-emitting drive array circuit EOA1 and the second light-emitting drive array circuit EOA2 are located on the same side of the pixel circuit 11 array. This simplifies the wiring layout on the array substrate 10.

[0119] The first light-emitting drive array circuit EOA1 includes a first clock signal terminal CLK1, a second clock signal terminal CLK2, a start leakage protection control signal terminal STV-EM1, and a first output terminal OT1. The first clock signal terminal CLK1 is used to receive the first clock signal clk1, the second clock signal terminal CLK2 is used to receive the second clock signal clk2, and the start leakage protection control signal terminal STV-EM1 is used to receive the start leakage protection control signal STV-em1. The first light-emitting drive array circuit EOA1 is used to generate the leakage protection control signal em1 based on the first clock signal clk1 received by the first clock signal terminal CLK1, the second clock signal clk2 received by the second clock signal terminal CLK2, and the start leakage protection control signal STV-em1 received by the start leakage protection control signal terminal STV-EM1.

[0120] The leakage protection control signal em1 is used to transmit a cutoff signal to the light emission control signal terminal EM during the writing and compensation phase t2. The light emission control circuit 114 is turned off under the control of the leakage protection control signal em1 to prevent the data voltage at the data voltage terminal Vdata from leaking to the first power supply voltage terminal ELVDD and / or the second power supply voltage terminal ELVSS.

[0121] Figure 8 The waveform diagram shows a leakage current prevention control signal and a light emission duty cycle control signal provided in the embodiments of this application.

[0122] In some embodiments, the structure of the first light-emitting drive array circuit EOA1 is similar to... Figure 1B The structure of the light-emitting drive array circuit EOA in terminal 1 shown is the same. The first light-emitting drive array circuit EOA1 receives the first clock signal clk1 and the second clock signal clk2 and... Figure 1BThe first clock signal clk1 and the second clock signal clk2 received by the light-emitting drive array circuit EOA shown are the same. However, the initial leakage protection control signal STV-em1 received by the first light-emitting drive array circuit EOA1 is only a partial waveform of the initial light-emitting control signal STV-em received by the light-emitting drive array circuit EOA, including only the waveform of the initial light-emitting control signal STV-em corresponding to the writing and compensation stage t2. Therefore, the leakage protection control signal em1 only includes the waveform of the light-emitting control signal em corresponding to the writing and compensation stage t2.

[0123] The structure of the first light-emitting drive array circuit EOA1 is not limited in the embodiments of this application, and the light-emitting drive array circuits EOA in related technologies are all applicable to the embodiments of this application.

[0124] For example, the first light-emitting drive array circuit EOA1 includes multiple cascaded first light-emitting drive units eoa1, each of which includes a first output terminal OT1. Each stage of the first light-emitting drive unit eoa1 is also coupled to a first clock signal terminal CLK1 and a second clock signal terminal CLK2. The first clock signal CLK1 and the second clock signal CLK2 are used to control the propagation speed of the leakage protection control signal em1 output from the first output terminal OT1. The first stage of the first light-emitting drive unit eoa1 is coupled to the initial leakage protection control signal terminal STV-EM1, and the remaining stages of the first light-emitting drive unit eoa1 are coupled to the first output terminal OT1 of the previous stage of the first light-emitting drive unit eoa1. The first stage of the first light-emitting drive unit eoa1 receives the initial leakage protection control signal STV-em1 and outputs the leakage protection control signal em1 from its own first output terminal OT1. The remaining stages of the first light-emitting drive unit eoa1 receive the leakage protection control signal em1 output from the previous stage of the first light-emitting drive unit eoa1 and output the leakage protection control signal em1 from its own first output terminal OT1.

[0125] The topology of each first light-emitting driving unit eoa1 can be the same or different. This application does not limit the structure of the first light-emitting driving unit eoa1, and the structures of light-emitting driving units eoa in related technologies are applicable to this application.

[0126] The second light-emitting drive array circuit EOA2 includes a third clock signal terminal CLK3, a fourth clock signal terminal CLK4, a start-up duty cycle control signal terminal STV-EM2, and a second output terminal OT2. The third clock signal terminal CLK3 receives the third clock signal clk3, the fourth clock signal terminal CLK4 receives the fourth clock signal clk4, and the start-up duty cycle control signal terminal STV-EM2 receives the start-up duty cycle control signal STV-em2. The second light-emitting drive array circuit EOA2 generates the light-emitting duty cycle control signal em2 based on the third clock signal clk3 received by the third clock signal terminal CLK3, the fourth clock signal clk4 received by the fourth clock signal terminal CLK4, and the start-up duty cycle control signal STV-em2 received by the start-up duty cycle control signal terminal STV-EM2.

[0127] The light emission duty cycle control signal em2 is used to transmit an on-state control signal to the light emission control signal terminal EM during the light emission stage t3. The light emission control circuit 114 is turned on under the control of the light emission duty cycle control signal em2, so that the driving current generated by the pixel circuit 11 is transmitted to the light emission unit 12, driving the light emission unit 12 to emit light.

[0128] In some embodiments, the structure of the second light-emitting array circuit EOA2 is the same as that of the first light-emitting array circuit EOA1. However, the third clock signal clk3 and the fourth clock signal clk4 received by the second light-emitting array circuit EOA2 are different from the first clock signal clk1 and the second clock signal clk2 received by the first light-emitting array circuit EOA1. Furthermore, the initial emission duty cycle control signal STV-em2 received by the second light-emitting array circuit EOA2 is only... Figure 1B The waveform of the initial emission control signal STV-em received by the light-emitting drive array circuit EOA in terminal 1 shown only includes the waveform of the initial emission control signal STV-em corresponding to the emission stage t3. Therefore, the emission duty cycle control signal em2 only includes the waveform of the emission control signal em corresponding to the emission stage t3.

[0129] The structure of the second light-emitting drive array circuit EOA2 is not limited in this application embodiment, and the light-emitting drive array circuit EOA in related technologies is applicable to the embodiments of this application.

[0130] For example, the second light-emitting drive array circuit EOA2 includes multiple cascaded second light-emitting drive units eoa2, each of which includes a second output terminal OT2. Each stage of the second light-emitting drive unit eoa2 is also coupled to a third clock signal terminal CLK3 and a fourth clock signal terminal CLK4. The third clock signal CLK3 and the fourth clock signal CLK4 are used to control the propagation speed of the light emission duty cycle control signal em2 output from the second output terminal OT2. The first stage of the second light-emitting drive unit eoa2 is coupled to the initial light emission duty cycle control signal terminal STV-EM2, and the remaining stages of the second light-emitting drive unit eoa2 are coupled to the second output terminal OT2 of the previous stage of the second light-emitting drive unit eoa2. The first stage of the second light-emitting drive unit eoa2 receives the initial light emission duty cycle control signal STV-em2 and outputs the light emission duty cycle control signal em2 from its own stage's second output terminal OT2. The remaining stage second light-emitting driving unit eoa2 receives the light-emitting duty cycle control signal em2 output by the previous stage second light-emitting driving unit eoa2, and outputs the light-emitting duty cycle control signal em2 from its own stage second output terminal OT2.

[0131] The topology of each stage of the second light-emitting driving unit eoa2 can be the same or different. This application does not limit the structure of the second light-emitting driving unit eoa2; the structures of light-emitting driving units eoa in related technologies are applicable to this application.

[0132] The array substrate 10 includes, for example, a plurality of pixel circuits 11 arranged in an array, which are disposed in the effective display area AA of the array substrate 10. Each pixel circuit 11 includes a light-emitting control circuit 114, which is coupled to a light-emitting control signal terminal EM. The light-emitting control signal terminal EM receives a leakage protection control signal em1 and a light-emitting duty cycle control signal em2. The light-emitting control circuit 114 is turned off under the control of the leakage protection control signal em1 received by the light-emitting control signal terminal EM to prevent pixel leakage during writing. The light-emitting control circuit 114 is also turned on under the control of the light-emitting duty cycle control signal em2 received by the light-emitting control signal terminal EM to drive the light-emitting unit 12 to emit light.

[0133] In some embodiments, the frequencies of the first clock signal clk1 and the second clock signal clk2 are the first frequency f1, and the frequencies of the third clock signal clk3 and the fourth clock signal clk4 are the second frequency f2, wherein the first frequency f1 and the second frequency f2 are different.

[0134] In this embodiment, the frequency (or propagation speed) of the leakage current prevention control signal em1 is controlled by a first frequency f1, and the frequency of the light emission duty cycle control signal em2 is controlled by a second frequency f2. This decouples the frequencies of the leakage current prevention control signal em1 and the light emission duty cycle control signal em2, thus decoupling the refresh logic and the dimming logic. They can be independently controlled without the need for synchronous control. This improves the flexibility of signal control in the array substrate 10, thereby broadening the applicable scenarios of the array substrate 10.

[0135] In some embodiments, the first frequency f1 is different from the second frequency f2.

[0136] By setting the first frequency f1 and the second frequency f2 to be different, the first frequency f1 is set to the comprehensive optimization frequency, and the second frequency f2 is also set to the comprehensive optimization frequency, so as to optimize the performance of the terminal 1 including the array substrate 10.

[0137] Figure 9 The present application provides waveform diagrams of the first timing signal, the second timing signal, the third timing signal, and the fourth timing signal in the embodiments.

[0138] In some embodiments, such as Figure 9 As shown, the waveforms of the first timing signal clk1 and the third timing signal clk3 are the same, but their frequencies are different. The second frequency f2 of the third timing signal clk3 is less than the first frequency f1 of the first timing signal clk1. Similarly, the waveforms of the second timing signal clk2 and the fourth timing signal clk4 are the same, but their frequencies are different. The second frequency f2 of the fourth timing signal clk4 is less than the first frequency f1 of the second timing signal clk2.

[0139] This allows the PWM dimming enable signal to be generated at a lower frequency, reducing power consumption.

[0140] In some embodiments, the first frequency f1 is equal to the screen refresh rate of terminal 1. The screen refresh rate of terminal 1 may include, for example, 10Hz, 20Hz, 30Hz, 60Hz, 120Hz, 144Hz, etc.

[0141] By setting the first frequency f1 to be equal to the screen refresh rate of terminal 1, it can be ensured that the refresh rate of terminal 1 is not affected, so as to adapt to the current mainstream terminal 1 products.

[0142] In some embodiments, the ratio of the second frequency f2 to the first frequency f1 is between 1 / 5 and 3 / 4. For example, the ratio of the second frequency f2 to the first frequency f1 is 1 / 4, 1 / 3, 2 / 5, 7 / 15, 1 / 2, 8 / 15, 3 / 5, 2 / 3, 11 / 15, etc.

[0143] For example, the ratio of the second frequency f2 to the first frequency f1 can be between 1 / 3 and 1 / 2. For instance, the ratio of the second frequency f2 to the first frequency f1 can be 5 / 12, 11 / 24, 11 / 30, 2 / 5, 13 / 30, 7 / 15, 23 / 49, etc.

[0144] For example, the second frequency f2 is greater than 40 Hz and less than 60 Hz.

[0145] If the second frequency f2 is too small, the user will see the black bar moving, affecting the display effect. If the second frequency f2 is too large, it will increase power consumption. Therefore, setting the second frequency f2 within the range of 1 / 3 to 1 / 2 of the first frequency f1 can ensure display effect with lower power consumption.

[0146] For example, such as Figure 8 As shown, the first frequency f1 is 120 Hz, the second frequency f2 is 1 / 3 of the first frequency f1, and the value of the second frequency f2 is 40 Hz. In one frame, the leakage protection control signal em1 is a single pulse signal, and the light emission duty cycle control signal em2 is a 4-pulse signal.

[0147] Therefore, the refresh rate of pixel circuit 11 is 120Hz, and the switching frequency of pixel circuit 11 is 4 * 120Hz = 480Hz. However, since the second frequency f2 is 1 / 3 of the first frequency f1, the propagation speed of the light emission duty cycle control signal em2 will decrease. The brightness-dark space period of the display screen = propagation speed * initial signal period. With the initial signal period remaining constant, a decrease in propagation speed will lead to a decrease in the brightness-dark space period of the display screen. That is, the brightness-dark space period of the display screen is directly proportional to the frequency of the clock signal; a decrease in the frequency of the clock signal (a decrease in the second frequency f2) will also decrease the brightness-dark space period of the display screen. Figure 8 As shown, after the propagation speed of the light emission duty cycle control signal em2 is reduced by 1 / 3, at any given time, there are always 12 (3*4) cycles of alternating brightness on and off on the display screen, that is, 12 cycles of alternating on and off of the light emission duty cycle control signal em2. For example, Figure 8 The vertical line in the image represents the selected time line. Of the multiple lines of illumination duty cycle control signals em2 on the display screen, 12 lines intersect with the time line, and these intersecting lines are marked with black stripes. Therefore, as shown... Figure 10As shown, at any given time, the display screen has 12 rows of black stripes, and the brightness-dark space period of the display screen is 1 / 12 * screen height. Compared with the above-mentioned scheme that includes a light-emitting drive array circuit EOA in the array substrate 10 (hereinafter referred to as the above scheme), when the switching frequency of the pixel circuit 11 in the above scheme is 480 Hz, the brightness-dark space period of the display screen is only 1 / 4 * screen height. Therefore, under the same power consumption, the display and eye protection effects can be improved. If the array substrate 10 includes a light-emitting drive array circuit EOA, the switching frequency of the pixel circuit 11 needs to reach 12 * 120 Hz = 1440 Hz to achieve a brightness-dark space period of 1 / 12 * screen height. However, in the embodiment of this application, the switching frequency of the pixel circuit 11 only needs to be 480 Hz to achieve the same eye protection effect. Therefore, under the same display and eye protection effects, the embodiment of this application can reduce power consumption.

[0148] Alternatively, for example, the first frequency f1 is 120 Hz, and the second frequency f2 is 40 Hz. In one frame, the leakage protection control signal em1 is a single-pulse signal, and the light emission duty cycle control signal em2 is a 32-pulse signal.

[0149] Therefore, the refresh rate of pixel circuit 11 is 120 Hz, and the switching frequency of pixel circuit 11 is 32 * 120 Hz = 3840 Hz. In the above scheme, when the switching frequency of pixel circuit 11 is 3840 Hz, the brightness-dark space cycle of the display screen is only 1 / 32 * screen height. In the scheme of this application, when the switching frequency of pixel circuit 11 is 3840 Hz, the brightness-dark space cycle of the display screen is only 1 / 3 * 1 / 32 * screen height = 1 / 96 * screen height. Therefore, under the same power consumption, the display and eye protection effects can be improved. If the brightness-dark space cycle of the display screen in the scheme of this application reaches 1 / 32 * screen height, the switching frequency of pixel circuit 11 only needs to be 1280 Hz. Therefore, under the same display and eye protection effects, the embodiment of this application can reduce power consumption.

[0150] Based on this, the array substrate 10 provided in this application embodiment controls the first light-emitting drive array circuit EOA1 with a clock signal of the first frequency f1 and controls the second light-emitting drive array circuit EOA2 with a clock signal of the second frequency f2. This decouples the frequency of the leakage protection control signal em1 and the frequency of the light-emitting duty cycle control signal em2, so that while the leakage protection control signal em1 matches the screen refresh rate, the frequency of the light-emitting duty cycle control signal em2 can be independently adjusted. By setting the second frequency f2 to be less than the first frequency f1, the spatial propagation speed of the light-emitting duty cycle control signal em2 can be reduced. With the frequency of the light-emitting duty cycle control signal em2 fixed, the number of bright and dark space cycles of the display screen using this array substrate 10 can be increased, and the number of bright and dark space cycles of the display screen can be reduced to meet the requirements of high display effect and high eye protection effect. By setting the second frequency f2 to be less than the first frequency f1, the frequency of the light emission duty cycle control signal em2 can be reduced while keeping the number of bright and dark space cycles of the display screen using the array substrate 10 fixed. This reduces power consumption and lowers the requirements on the switching frequency that the pixel circuit 11 in the array substrate 10 can withstand, making some array substrates 10 that cannot meet the high-frequency switching requirements meet the requirements and reducing the yield loss of the array substrate 10.

[0151] Figures 11A-12 This is a schematic diagram of the layout of an array substrate provided in an embodiment of this application.

[0152] In some embodiments, such as Figure 11A As shown, the array substrate 10 also includes a logic operation circuit 17, which is disposed at the output terminals of the first light-emitting drive array circuit EOA1 and the second light-emitting drive array circuit EOA2.

[0153] The logic operation circuit 17 includes an input terminal and an output terminal. The input terminal of the logic operation circuit 17 is coupled to the first output terminal OT1 and the second output terminal OT2, and the output terminal is coupled to the light-emitting control signal terminal EM. It is used to perform logic operations on the leakage protection control signal em1 and the light-emitting duty cycle control signal em2, and output the operation result as the light-emitting control signal em to the light-emitting control signal terminal EM.

[0154] The logic operation circuit 17 is used to perform logic operations on the leakage protection control signal em1 and the light emission duty cycle control signal em2. When both the leakage protection control signal em1 and the light emission duty cycle control signal em2 are on signals, the light emission control signal em output after the logic operation is an on signal; when one of the leakage protection control signal em1 and the light emission duty cycle control signal em2 is an off signal, the light emission control signal em output after the logic operation is an off signal.

[0155] For example, the logic operation circuit 17 includes multiple logic operation units 171. The input terminal of the logic operation unit 171 is coupled to the first output terminal OT1 of the first light-emitting driving unit eoa1 and the second output terminal OT2 of the second light-emitting driving unit eoa2 located at the same level. The light-emitting control signal terminal EM of the pixel circuit 11 located in the same row is coupled to the output terminal of the same logic operation unit 171.

[0156] Optional, such as Figure 11A As shown, the output of a logic operation unit 171 is coupled to the light emission control signal EM of a row pixel circuit 11, providing the light emission control signal em to the row pixel circuit 11.

[0157] Alternatively, as... Figure 11B As shown, the output of a logic operation unit 171 is coupled to the light emission control signal EM of the multi-row pixel circuit 11, providing the light emission control signal em to the multi-row pixel circuit 11.

[0158] For example, the light emission control signal terminal EM of the pixel circuit 11 located in multiple rows is coupled to the output terminal of the same logic operation unit 171. Figure 11B The diagram illustrates the coupling of the light emission control signal terminal EM of the pixel circuit 11 located in two adjacent rows with the output terminal of the same logic operation unit 171.

[0159] In this way, the pixel circuits 11 in multiple rows share the same set of logic operation units 171, first light-emitting driving unit eoa1 and second light-emitting driving unit eoa2, which can reduce the number of devices in the non-display area BB, save costs and facilitate the realization of narrow bezels.

[0160] In some embodiments, the pixel circuit 11 may be, for example, a pixel circuit with a 7T1C structure commonly used in the art. This application does not limit the structure of the pixel circuit 11, and pixel circuits in related technologies are applicable to the embodiments of this application.

[0161] In some embodiments, such as Figure 11A As shown, if the logic operation circuit 17 includes an OR operation circuit, then the logic operation unit 171 includes an OR gate.

[0162] For example, in the leakage current prevention control signal em1 and the light emission duty cycle control signal em2, the high-level signal is "1" and the low-level signal is "0". When both the leakage current prevention control signal em1 and the light emission duty cycle control signal em2 are "0", the light emission control signal em is "0", which is a low-level signal. When either the leakage current prevention control signal em1 or the light emission duty cycle control signal em2 is "1", the light emission control signal em is "1", which is a high-level signal.

[0163] For example, such as Figure 2As shown, the transistor in the light-emitting control circuit 114 is a P-type transistor, which turns on under the control of a low-level signal and turns off under the control of a high-level signal. That is, the light-emitting control circuit 114 conducts when the light-emitting control signal em is "0" and turns off when the light-emitting control signal em is "1". Therefore, as long as the leakage protection control signal em1 is "1" or the light-emitting control signal em is "1", the light-emitting control circuit 114 can be turned off. Only when both the leakage protection control signal em1 and the light-emitting duty cycle control signal em2 are "0" can the light-emitting control circuit 114 be turned on.

[0164] Of course, the embodiments of this application do not limit the logic operation unit 171 to include an OR gate. Any logic circuit that can achieve the same effect as an OR gate is applicable to the embodiments of this application. For example, the logic operation unit 171 includes an AND gate plus a NOT gate, etc.

[0165] In other embodiments, such as Figure 12 As shown, the logic operation circuit 17 includes an AND operation circuit, and the logic operation unit 171 includes an AND gate.

[0166] For example, in the leakage current prevention control signal em1 and the light emission duty cycle control signal em2, the high-level signal is "1" and the low-level signal is "0". When both the leakage current prevention control signal em1 and the light emission duty cycle control signal em2 are "1", the light emission control signal em is "1", which is a high-level signal. When either the leakage current prevention control signal em1 or the light emission duty cycle control signal em2 is "0", the light emission control signal em is "0", which is a low-level signal.

[0167] For example, the transistor in the light-emitting control circuit 114 is an N-type transistor, which turns on under the control of a high-level signal and turns off under the control of a low-level signal. That is, the light-emitting control circuit 114 conducts when the light-emitting control signal em is "1" and turns off when the light-emitting control signal em is "0". Therefore, the light-emitting control circuit 114 can only be turned on when both the leakage current prevention control signal em1 and the light-emitting duty cycle control signal em2 are "1". The light-emitting control circuit 114 can be turned off when either the leakage current prevention control signal em1 is "0" or the light-emitting control signal em is "0".

[0168] Of course, the embodiments of this application do not limit the logic operation unit 171 to include an AND gate. Any logic circuit that can achieve the same effect as an AND gate is applicable to the embodiments of this application. For example, the logic operation unit 171 includes an OR gate plus a NOT gate, etc.

[0169] By performing logical operations on the leakage protection control signal em1 and the light emission duty cycle control signal em2, the signals are then output to the light emission control signal terminal EM. The light emission control signal terminal EM only receives one final light emission control signal em. Therefore, the structure of the pixel circuit 11 in the array substrate 10 does not need to be modified. Pixel circuits 11 in related technologies are applicable to the embodiments of this application, reducing the workload of modifications. Moreover, since only one light emission control signal em is output, only one output switch needs to be set up, without increasing the width of the bezel.

[0170] In some embodiments, such as Figure 12 As shown, the array substrate 10 also includes circuit structures such as a first scanning array circuit 13, a second scanning array circuit 14, a third scanning array circuit 15, and a fourth scanning array circuit 16. The specific structure and arrangement position of the first scanning array circuit 13, the second scanning array circuit 14, the third scanning array circuit 15, and the fourth scanning array circuit 16 are not limited in the embodiments of this application. The structures in related technologies are applicable to the embodiments of this application.

[0171] Figure 13 This is a schematic diagram of the structure of a display module provided in an embodiment of this application.

[0172] This application provides a display driver 20, which can be mounted on an array substrate 10. For example... Figure 13 As shown, the display driver 20 includes a timing circuit 21 and a start-up control signal generation circuit 22.

[0173] The timing circuit 21 is used to generate the first clock signal clk1, the second clock signal clk2, the third clock signal clk3 and the fourth clock signal clk4, transmit the first clock signal clk1 and the second clock signal clk2 to the first light-emitting drive array circuit EOA1, and transmit the third clock signal clk3 and the fourth clock signal clk4 to the second light-emitting drive array circuit EOA2.

[0174] The timing circuit 21 can be, for example, a timing control unit (TCON).

[0175] The start-up light emission control signal generation circuit 22 is used to generate the start-up leakage protection control signal STV-em1 and the start-up light emission duty cycle control signal STV-em1, transmit the start-up leakage protection control signal STV-em1 to the first light emission driving array circuit EOA1, and transmit the start-up light emission duty cycle control signal STV-em1 to the second light emission driving array circuit EOA2.

[0176] This application also provides a display module, such as... Figure 13As shown, the display module 3 includes any of the above-described array substrate 10 and / or any of the above-described display drivers 20, with the display driver 20 bonded to the non-display area BB of the array substrate 10. For example, the display driver module is bonded to one side of the pixel circuit 11 array along the column direction of the pixel circuit 11 array.

[0177] The display module 3 provided in this application embodiment can be applied to the terminal 1 provided in this application embodiment. The terminal 1 includes a housing, and the display module 3 is disposed inside the housing. The housing includes, for example, the aforementioned rear shell 5.

[0178] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: The first light-emitting driving array circuit includes a first clock signal terminal, a second clock signal terminal, a start leakage protection control signal terminal, and a first output terminal, and is used to generate a leakage protection control signal according to the first clock signal received by the first clock signal terminal, the second clock signal received by the second clock signal terminal, and the start leakage protection control signal received by the start leakage protection control signal terminal. The second light-emitting driving array circuit includes a third clock signal terminal, a fourth clock signal terminal, a start-emitting duty cycle control signal terminal, and a second output terminal, which is used to generate a light-emitting duty cycle control signal based on the third clock signal received by the third clock signal terminal, the fourth clock signal received by the fourth clock signal terminal, and the start-emitting duty cycle control signal received by the start-emitting duty cycle control signal terminal. The pixel circuit includes a light-emitting control signal terminal; the light-emitting control signal terminal is used to receive the leakage protection control signal and the light-emitting duty cycle control signal. Where f1 is the frequency of the first clock signal and the second clock signal, and f2 is the frequency of the third clock signal and the fourth clock signal. <f1。 2. The array substrate according to claim 1, characterized in that, The array substrate also includes logic operation circuitry; The input terminal of the logic operation circuit is coupled to the first output terminal and the second output terminal, and the output terminal is coupled to the light-emitting control signal terminal. It is used to perform logic operations on the leakage protection control signal and the light-emitting duty cycle control signal, and output the operation result as the light-emitting control signal to the light-emitting control signal terminal.

3. The array substrate according to claim 1 or 2, characterized in that, The value of f2 / f1 ranges from 1 / 5 to 3 / 4.

4. The array substrate according to claim 1 or 2, characterized in that, The value of f2 / f1 ranges from 1 / 3 to 1 / 2.

5. The array substrate according to claim 2, characterized in that, The logic operation circuit includes an OR operation circuit.

6. The array substrate according to claim 2, characterized in that, The logic operation circuit includes an AND operation circuit.

7. The array substrate according to claim 1 or 2, characterized in that, The first light-emitting driving array circuit includes multiple cascaded first light-emitting driving units. The first stage of the first light-emitting driving unit is coupled to the initial leakage protection control signal terminal. Each stage of the first light-emitting driving unit is coupled to both the first clock signal terminal and the second clock signal terminal. The second light-emitting driving array circuit includes multiple cascaded second light-emitting driving units. The first stage of the second light-emitting driving unit is coupled to the starting light emission duty cycle control signal terminal, and each stage of the second light-emitting driving unit is coupled to both the third clock signal terminal and the fourth clock signal terminal.

8. The array substrate according to claim 7, characterized in that, The array substrate includes a plurality of pixel circuits arranged in an array; if the array substrate further includes a logic operation circuit, the logic operation circuit includes a plurality of logic operation units. The input terminal of the logic operation unit is coupled to the first output terminal of the first light-emitting driving unit and the second output terminal of the second light-emitting driving unit, which are located at the same level. The light emission control signal terminal of the pixel circuit located in the same row is coupled to the output terminal of the same logic operation unit.

9. The array substrate according to claim 8, characterized in that, The light emission control signal terminal of the pixel circuit located in multiple rows is coupled to the output terminal of the same logic operation unit.

10. A display driver, characterized in that, For driving the array substrate according to any one of claims 1-9; The display driver includes: a timing circuit and a start-light control signal generation circuit; The timing circuit is used to output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal to the array substrate, where f1 is the frequency of the first clock signal and the second clock signal, and f2 is the frequency of the third clock signal and the fourth clock signal. <f1; The start-up light emission control signal generation circuit is used to output a start-up leakage protection control signal and a start-up light emission duty cycle control signal to the array substrate.

11. The display driver according to claim 10, characterized in that, The value of f2 / f1 ranges from 1 / 5 to 3 / 4.

12. The display driver according to claim 11, characterized in that, The value of f2 / f1 ranges from 1 / 3 to 1 / 2.

13. A display module, characterized in that, It includes an array substrate and a display driver, wherein the display driver is bonded to the array substrate; The array substrate includes the array substrate according to any one of claims 1-9; And / or, The display driver includes the display driver according to any one of claims 10-12.

14. A terminal, characterized in that, It includes a housing and a display module, wherein the display module is disposed within the housing; the display module includes the display module as described in claim 13.

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