An operating method of a memory device, a memory device, and a memory system

Abstract

Embodiments of the present application provide an operating method of a memory device, a memory device and a memory system. The memory device includes a first memory cell and a second memory cell belonging to the same memory string and being adjacent. The method includes: performing a first programming operation so that the first memory cell is programmed to a first data state; performing a second programming operation. The second programming operation includes: programming the second memory cell; and verifying the second memory cell according to first reference verification information determined according to the first data state.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to an operating method of a memory device, a memory device, and a memory system. Background Technology

[0002] As the storage density of memory devices increases, the number of bits per memory cell gradually increases. To achieve multi-bit storage per memory cell, and with a page divided into multiple data states, the threshold voltage distribution width of each data state needs to be compressed to improve the read window margin (RWM) in order to correctly read the data stored in the memory cell. However, the threshold voltage Vt corresponding to the highest data state is usually relatively high, which leads to rapid charge loss and poor memory device retention. Summary of the Invention

[0003] This application provides an operation method for a memory device, a memory device, and a memory system.

[0004] On one hand, embodiments of this application provide an operation method for a memory device, the memory device including a first memory cell and a second memory cell belonging to the same memory string and being adjacent to each other; the method includes:

[0005] Perform a first programming operation to program the first storage unit into a first data state;

[0006] Perform a second programming operation; the second programming operation includes: programming the second storage unit; and verifying the second storage unit according to the first reference verification information determined by the first data state.

[0007] In the above scheme, the memory unit of the memory device can be programmed to any one of a plurality of data states containing the first data state; the method further includes:

[0008] Obtain a first mapping relationship between the plurality of data states and reference verification information used to verify the programming results of the storage unit;

[0009] The first reference verification information is determined based on the first data state and the first mapping relationship.

[0010] In the above scheme, the reference verification information includes a reference verification voltage or a reference sensing time; obtaining the first mapping relationship between the plurality of data states and the reference verification information used to verify the programming results of the memory cell includes:

[0011] The multiple data states are divided into multiple data groups;

[0012] Obtain a first sub-mapping relationship between the plurality of data groups and the reference verification voltage; or, obtain a second sub-mapping relationship between the plurality of data groups and the reference sensing time;

[0013] The first mapping relationship includes: a first sub-mapping relationship and / or a second sub-mapping relationship.

[0014] In the above scheme, the division of the multiple data states into multiple data groups includes:

[0015] The multiple data states are divided into a first data group and a second data group, wherein the threshold voltage corresponding to the data state in the first data group is less than the threshold voltage corresponding to the data state in the second data group.

[0016] In the above scheme, the first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or, a second sub-mapping relationship between the first data group, the second data and the reference sensing time;

[0017] The first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, and the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, and the correspondence between the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

[0018] In the above scheme, the memory string further includes a third memory cell adjacent to the second memory cell; the method further includes:

[0019] Perform a third programming operation to program the first storage unit to the first target programming state;

[0020] Perform a fourth programming operation to program the third storage unit into a second data state;

[0021] In the second programming operation, the second storage unit is not programmed to the second target data state; the second data state is not the target data state.

[0022] In the above scheme, the memory string further includes: a fourth memory cell adjacent to the first memory cell; before performing the first programming operation, the method further includes:

[0023] Perform the fifth programming operation to program the fourth storage unit to the third data state;

[0024] Perform the sixth programming operation to program the second memory cell to the fourth data state;

[0025] Perform the seventh programming operation to program the fourth storage unit to the third target data state;

[0026] Wherein, the first data state, the third data state, and the fourth data state are not target data states; under the second programming operation, the storage unit is programmed into the second target data state.

[0027] In the above scheme, the first data group and the second data group among the plurality of data groups contain the same number of data states.

[0028] In the above scheme, the multiple data states include 16 data states from L0 to L15; the first data group includes data states from L0 to L7; and the second data group includes data states from L8 to L15.

[0029] In the above scheme, determining the first reference verification information based on the first data state and the first mapping relationship includes:

[0030] The data group to which the first data state belongs is determined according to a preset second mapping relationship, wherein the second mapping relationship includes the correspondence between the plurality of data groups and the plurality of data states;

[0031] The first reference verification information is determined based on the data group to which it belongs and the first sub-mapping relationship, or the first reference verification information is determined based on the data group to which it belongs and the second sub-mapping relationship;

[0032] Specifically, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

[0033] On the other hand, embodiments of this application also provide a memory device, including:

[0034] A memory array includes: a first memory cell and a second memory cell that belong to the same memory string and are adjacent to each other;

[0035] The peripheral circuitry, coupled to the memory array, is configured as follows:

[0036] Perform a first programming operation to program the first storage unit into a first data state;

[0037] Perform a second programming operation; the second programming operation includes: programming the second storage unit; and verifying the second storage unit according to the first reference verification information determined by the first data state.

[0038] In the above scheme, the memory cell of the memory device can be programmed to any one of a plurality of data states including the first data state; the peripheral circuit is further configured to: obtain a first mapping relationship between the plurality of data states and reference verification information for verifying the programming result of the memory cell; and determine the first reference verification information based on the first data state and the first mapping relationship.

[0039] In the above scheme, the reference verification information includes a reference verification voltage or a reference sensing time; the peripheral circuit is further configured to: divide the plurality of data states to form a plurality of data groups; obtain a first sub-mapping relationship between the plurality of data groups and the reference verification voltage; or, obtain a second sub-mapping relationship between the plurality of data groups and the reference sensing time; wherein, the first mapping relationship includes: the first sub-mapping relationship and / or the second sub-mapping relationship.

[0040] In the above scheme, the peripheral circuit is further configured to divide the plurality of data states into a first data group and a second data group, wherein the threshold voltage corresponding to the data state in the first data group is less than the threshold voltage corresponding to the data state in the second data group.

[0041] In the above scheme, the first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or, a second sub-mapping relationship between the first data group, the second data and the reference sensing time;

[0042] The first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, and the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, and the correspondence between the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

[0043] In the above scheme, the memory string further includes a third memory cell adjacent to the second memory cell; the peripheral circuit is further configured to: perform a third programming operation, such that the first memory cell is programmed to a first target programming state; perform a fourth programming operation, such that the third memory cell is programmed to a second data state; wherein, under the second programming operation, the second memory cell is not programmed to a second target data state; the second data state is not a target data state.

[0044] In the above scheme, the memory string further includes: a fourth memory cell adjacent to the first memory cell; the peripheral circuit is further configured to: before performing the first programming operation,

[0045] Perform the fifth programming operation to program the fourth storage unit to the third data state;

[0046] Perform the sixth programming operation to program the second memory cell to the fourth data state;

[0047] Perform the seventh programming operation to program the fourth storage unit to the third target data state;

[0048] Wherein, the first data state, the third data state, and the fourth data state are not target data states; under the second programming operation, the storage unit is programmed into the second target data state.

[0049] In the above scheme, the peripheral circuit is further configured to: determine the data group to which the first data state belongs according to a preset second mapping relationship, wherein the second mapping relationship includes the correspondence between the plurality of data groups and the plurality of data states;

[0050] The first reference verification information is determined based on the data group to which it belongs and the first sub-mapping relationship, or the first reference verification information is determined based on the data group to which it belongs and the second sub-mapping relationship;

[0051] Specifically, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

[0052] In another aspect, embodiments of this application also provide a memory system including one or more memory devices according to any of the foregoing.

[0053] In the above scheme, the memory system is contained in a solid-state drive (SSD) or a memory card.

[0054] This application provides an operation method for a memory device, a memory device, and a memory system. The memory device includes a first memory cell and a second memory cell belonging to the same memory string and being adjacent to each other. The method includes: performing a first programming operation to program the first memory cell into a first data state; performing a second programming operation; the second programming operation includes: programming the second memory cell; and verifying the second memory cell based on first reference verification information determined according to the first data state. The operation method provided in this application allows the verification operation of the later-programmed memory cell in the same memory string to use reference verification information obtained from the data state programmed into the previous-programmed memory cell. This guides the later-programmed memory cell to obtain appropriate reference verification information based on the programming state of the previous memory cell, thereby improving the memory's retention characteristics. Attached Figure Description

[0055] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0056] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to some aspects of embodiments of this application;

[0057] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to some aspects of embodiments of this application;

[0058] Figure 2b A schematic diagram of an exemplary solid-state drive with a memory system provided according to some aspects of embodiments of this application;

[0059] Figure 3 This is a schematic diagram of an exemplary memory device including peripheral circuitry provided according to some aspects of embodiments of this application;

[0060] Figure 4 This is a schematic diagram of the structure of memory strings, word lines, and bit lines in a memory device according to some aspects of embodiments of this application;

[0061] Figure 5This is a schematic cross-sectional view of a memory array provided according to some aspects of embodiments of this application;

[0062] Figure 6 This is a schematic diagram of an exemplary memory device including a memory array and peripheral circuitry, provided according to some aspects of embodiments of this application;

[0063] Figure 7 This is a voltage threshold distribution diagram for TCL type memory cells;

[0064] Figure 8 This is a voltage threshold distribution diagram for QLC type memory cells;

[0065] Figure 9 Schematic diagrams illustrating the definition of RWM for some aspects of embodiments of this application.

[0066] Figure 10 This is a flowchart illustrating an operation method of a memory device provided according to some aspects of embodiments of this application;

[0067] Figure 11 A schematic diagram illustrating a 4BL BIAS programming method for some aspects of embodiments of this application;

[0068] Figure 12 A schematic diagram illustrating the relationship between the potential of a sensing node and the discharge duration, provided for some aspects of embodiments of this application;

[0069] Figure 13 and Figure 14 A schematic diagram illustrating some reasons for charge loss in memory cells, provided for some aspects of embodiments of this application;

[0070] Figure 15 A schematic diagram of a two-sided programming algorithm provided for some aspects of embodiments of this application;

[0071] Figures 16 to 19 An exemplary flowchart illustrating the operation method of an embodiment of this application, providing some aspects of the embodiments;

[0072] Figure 20 and Figure 21 Provided for some aspects of embodiments of this application regarding Figures 16 to 19 A schematic diagram illustrating the effect of the process;

[0073] Figure 22 A schematic diagram of the structure of a memory device provided for some aspects of embodiments of this application. Detailed Implementation

[0074] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0075] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described: that is, not all features of the actual embodiments described herein, nor well-known functions and structures are described in detail.

[0076] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0077] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," "coupled to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intermediate elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intermediate elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. When discussing a second element, component, region, layer, or portion, it does not imply that the application necessarily contains a first element, component, region, layer, or portion.

[0078] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0079] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0080] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0081] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific examples.

[0082] Figure 1 A block diagram of an exemplary system with a memory system is shown. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory system therein. For example... Figure 1As shown, system 100 may include host 108 and memory system 102. Host 108 may include a processor, such as a central processing unit (CPU) or a system-on-chip (SoC), where the SoC may be, for example, an application processor (AP). Host 108 also includes at least one operating system (OS) that can typically manage and control the functions and operations performed in host 108. The OS enables interoperability between host 108 coupled to memory system 102 and users who need and use memory system 102. The OS may support functions and operations corresponding to user requests. For example, and not limited to, depending on whether host 102 is a removable host, OS may be classified as a general-purpose operating system and a mobile operating system. The general-purpose operating system may include personal operating systems and enterprise operating systems. The personal operating system may be an operating system, including Windows and Chrome, used for general purposes to support services; the enterprise operating system may be an operating system, including Windows Server, Linux, Unix, etc., dedicated to ensuring and supporting higher performance. The mobile operating system can refer to an operating system for mobility services or functions (such as power-saving functions). Generally, a mobile operating system can be an operating system such as Android, iOS, or Windows Mobile. In some embodiments, the host 108 may include multiple OSes; correspondingly, the host 108 may run multiple operating systems associated with the memory system 102. In other embodiments, the host 108 translates a user's request into one or more commands and transmits the one or more commands to the memory system 102 so that the memory system 102 performs operations related to the one or more commands.

[0083] The memory system 102 is capable of responding to requests from the host 108, performing specific functions, or performing various internal operations. In some embodiments, the memory system 102 is capable of storing data accessed by the host 108. The memory system 102 can be used as the main memory system or auxiliary memory system of the host 108. The memory system 102 and the host 108 can be electrically connected and communicate with each other according to appropriate protocols. The memory system 102 can be implemented and packaged into different types of terminal electronic products, such as, and not limited to, solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RSMMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, and memory sticks, etc.

[0084] In some embodiments, the memory system 102 may also be configured as part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0085] Return as Figure 1 As shown, the memory system 102 may have one or more memory devices 104 and a memory controller 106. The memory controller 106 can respond to requests from the host 108 and control the memory devices 104. For example, the memory controller 106 can read data from the memory devices 104 and transfer the read data to the host 108; it can also receive data to be stored from the host 108 and store the data to be stored in the memory devices 104. In other words, the memory controller 106 can control the write (or programming) operations, read operations, erase operations, and background operations of the memory devices 104, etc. Furthermore, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0086] Among them, such as Figure 3 As shown, the memory controller 106 may include a host I / F (or front-end interface) 301, a memory I / F (or back-end interface) 302, a processor 303, and memory 304. The aforementioned components 301, 302, 303, and 304 within the memory controller 106 can share internal transmission signals via an internal bus. In some embodiments, the host I / F 301 may interface with the memory system 102 in response to a protocol of the host 108, and the host I / F 301 may exchange transmission commands and data operations between the host 108 and the memory system 102. The host I / F 301 may process commands and data sent by the host 108 and may include at least one of the following: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE). In some embodiments, the host I / F301 is a component of the memory system 102 used to exchange data with the host 108, and can be implemented through firmware known as the host interface layer (HIL).

[0087] Memory I / F 302 can serve as an interface for transmitting commands and data between memory controller 106 and memory device 104, allowing memory controller 106 to control memory device 104 in response to requests transmitted from host 108. Memory I / F 302 can generate control signals for controlling memory device 104. In some embodiments, if memory device 104 is NAND flash memory, memory I / F 302 can write data to or read data from memory device 104 under the control of processor 303. Memory I / F 302 can process commands and data between memory controller 106 and memory device 104, such as operations of the NAND flash interface, particularly operations between memory controller 106 and memory device 104. According to embodiments, memory I / F 302 can be implemented as a component for exchanging data with memory device 104 via firmware referred to as the Flash Interface Layer (FIL).

[0088] Processor 303 may be implemented as a microprocessor or a central processing unit (CPU). Memory system 102 may include one or more processors 303. Processor 303 may control all operations of memory system 102. By way of example and not limitation, processor 303 may control programming or reading operations of memory device 104 in response to write or read requests from host 108. According to embodiments, processor 303 may use or run firmware to control all operations of memory system 102. In this application, firmware may be referred to as a flash translation layer (FTL). FTL may act as an interface between host 108 and memory device 104. Host 108 may transmit requests related to write and read operations to memory device 104 via FTL. For example, memory controller 106 uses processor 303 when performing an operation requested from host 108 in memory device 104. Processor 303 coupled to memory device 104 may process instructions or commands related to commands from host 108. The memory controller 106 can perform foreground operations such as command operations corresponding to commands input from the host 108, such as programming operations corresponding to write commands, reading operations corresponding to read commands, erasing / discarding operations corresponding to erase / discard commands, and parameter setting operations corresponding to setting parameter commands or setting feature commands with setting commands.

[0089] In another example, memory controller 106 may perform background operations on memory device 104 via processor 303. By way of example and not limitation, these background operations may include garbage collection (GC) operations, wear leveling (WL) operations, map sweeping operations, and bad block management operations that check or search for bad blocks. Garbage collection operations may include copying and processing data stored in one memory block of memory device 104 to another memory block. Wear leveling operations may include exchanging and processing stored data between memory blocks of memory device 104. Map sweeping operations may include storing mapped data stored in memory controller 106 in memory blocks of memory device 104. Bad block management operations may include checking and processing bad blocks in memory blocks of memory device 104. Memory controller 106 may respond to operations that access memory blocks of memory device 104, wherein accessing memory blocks of memory device 104 may include foreground or background operations performed on memory blocks of memory device 104.

[0090] Memory 304 may be the working memory of memory controller 106, configured to store data used to drive memory controller 106. More specifically, memory 304 may store firmware driven by processor 303 and data (e.g., metadata) required to drive the firmware when memory controller 106 controls memory device 104 in response to a request from host 108. Memory 304 may also be a buffer memory of memory controller 106, configured to temporarily store write data transferred from host 108 to memory device 104 and read data transferred from memory device 104 to host 108. Memory 304 may include program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, and mapped buffer / cache for storing write and read data. Memory 304 may be implemented using volatile memory. Memory 304 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both.

[0091] Although Figure 3 The illustration shows that memory 304 is included in memory controller 106, but this application is not limited thereto. In embodiments, memory 304 may be included outside of memory controller 106, and memory controller 106 may input and output data to memory 304 via a separate memory interface (not shown).

[0092] See back Figure 1 The memory device 104 may include non-volatile memory, which retains stored data even when no power is supplied. The memory device 104 may also include volatile memory. The memory device 104 can store data provided from the host 108 via write operations; the memory device 104 can also provide the stored data to the host 108 via read operations. In embodiments of this application, the memory device 104 may include any publicly disclosed memory, such as volatile memory devices like Dynamic Random Access Memory (DRAM) and Static RAM (SRAM), or non-volatile memory devices such as Read-Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Ferroelectric RAM (FRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Resistive RAM (RRAM or ReRAM), and flash memory (e.g., 3D NAND flash memory).

[0093] To illustrate a memory device using three-dimensional NAND flash memory, see [link to documentation]. Figure 4It shows a schematic circuit diagram of an exemplary memory device 400 including peripheral circuitry according to some aspects of this application. The memory device 400 may be... Figure 1 An example of memory device 104 is provided. Memory device 400 may include memory array 401 and peripheral circuitry 402 coupled to memory array 401. Taking memory array 401 as an example of a three-dimensional NAND-type memory array, memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0094] In some implementations, each memory cell 406 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 406 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-bit cell (TLC), a four-bit cell (QLC), or five bits per cell (also known as a five-bit cell (PLC)). Each MLC may be programmed to take a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value available for the erase state. In some embodiments, the memory state is also referred to as the data state, and the data state includes the erase state and the programming state, wherein the erase state is the aforementioned erase state; and the programming state is the process of programming from the erase state to one of the other data states.

[0095] like Figure 4As shown, each NAND memory string 408 may include a lower select gate (BSG) 410 at its source end and an upper select gate (TSG) 412 at its drain end. BSG 410 and TSG 412 can be configured to activate the selected NAND memory string 408 during read and program operations. In some embodiments, the sources of the NAND memory strings 408 in the same memory block 404 are coupled via a common source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the TSG 412 of each NAND memory string 408 is coupled to a corresponding bit line (BL) 416, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 412) or a deselection voltage (e.g., 0V) to the corresponding TSG 412 via one or more TSG lines 413 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 410) or a deselection voltage (e.g., 0V) to the corresponding BSG 410 via one or more BSG lines 415.

[0096] like Figure 4As shown, NAND memory strings 408 can be organized into multiple memory blocks 404, each of which may have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is the basic data unit for an erase operation, i.e., all memory cells 406 on the same memory block 404 are erased simultaneously. To erase memory cells 406 in a selected memory block 404, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 414 of the selected memory block 404 and the unselected memory blocks 404 on the same plane as the selected memory block 404. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 is affected by read and program operations. In some implementations, each word line 418 is coupled to a page 420 of a memory cell 406, where the page 420 can be a basic data unit for programming operations. The size of a page 420, measured in bits, can be related to the number of NAND memory strings 408 coupled by word lines 418 in a memory block 404. Each word line 418 may include multiple control gates (gate electrodes) at each memory cell 406 in the corresponding page 420, as well as gate lines coupling the control gates. It should be noted that, with the development of control technology, the smallest unit of programming may also be smaller than a page 420, and the operation methods provided in the embodiments of this application may still be applicable. The description of pages in the embodiments of this application is merely exemplary, and the embodiments of this application are not limited to other definitions.

[0097] Figure 5 A cross-sectional schematic diagram of an exemplary memory array 401 including NAND memory strings 408 is shown according to some aspects of this application. Figure 5 As shown, the NAND memory string 408 may include a stacked structure 510, which includes multiple gate layers 511 and multiple insulating layers 512 stacked alternately in sequence, and a memory string 408 perpendicularly penetrating the gate layers 511 and insulating layers 512. The gate layers 511 and insulating layers 512 may be stacked alternately, with adjacent gate layers 511 separated by an insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 determines the number of memory cells included in the memory array 401.

[0098] The constituent materials of the gate layer 511 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 511 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding a memory cell. The gate layer 511 at the top of the stacked structure 510 may extend laterally as an upper select gate line 513, the gate layer 511 at the bottom of the stacked structure 510 may extend laterally as a lower select gate line 514, and the gate layer 511 extending laterally between the upper and lower select gate lines may serve as a word line layer 503.

[0099] In some embodiments, the stacked structure 510 may be disposed on the substrate 501. The substrate 501 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0100] In some embodiments, the NAND memory string 408 includes a channel structure extending vertically through the stacked structure 510. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0101] Return to reference Figure 3The peripheral circuitry 302 can be coupled to the memory array 401 via bit line 316, word line 418, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 316, word line 418, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 406. The peripheral circuitry 302 can include various types of circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensing amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, control logic 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional circuitry not shown.

[0102] Page buffer / sensor amplifier 604 can be configured to read data from memory array 401 and program (write) data to memory array 401 according to control signals from control logic 612. In one example, page buffer / sensor amplifier 604 can store programming data (write data) to be programmed into memory array 401. In another example, page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 604 can also sense a low-power signal from bit line 316 representing data bits stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 606 can be configured to be controlled by control logic 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generator 610.

[0103] The row decoder / word line driver 608 can be configured to be controlled by control logic 612 and to select / deselect memory blocks 404 of memory array 401 and select / deselect word lines 418 of memory blocks 404. The row decoder / word line driver 608 can also be configured to drive word lines 418 using word line voltages generated from voltage generator 610. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive BSG lines 315 and TSG lines 313. The row decoder / word line driver 608 can be configured to perform programming operations on memory cells 406 coupled to one or more of the selected word lines 418. The voltage generator 610 can be configured to be controlled by control logic 612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 401.

[0104] Control logic 612 can be coupled to the various circuits described above and is configured to control the operation of each circuit. Register 614 can be coupled to control logic 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 616 can be coupled to control logic 612 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 612, as well as to buffer status information received from control logic 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bitline driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 401.

[0105] In 3D NAND memory devices, single-cell memory (SLC) holds a certain share of the memory market due to its advantages such as fast read / write speed, high reliability, and long lifespan; while double-cell memory (MLC), triple-cell memory (TLC), and quad-cell memory (QLC) are becoming the development trend of the memory market due to their higher storage density and larger storage capacity.

[0106] As the number of bits in a storage unit increases and the number of stacking layers increases, in order to achieve multi-bit storage, a page of 420 is divided into multiple data states, such as... Figure 7 The TLC shown and Figure 8The QLC shown has the following characteristics: TLC contains 8 data states (P0, P1, P2, P3, P4, P5, P6, P7), and the threshold voltage of the memory cell corresponding to data states P0 to P7 increases progressively; QLC contains 16 data states (P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15), and the threshold voltage of the memory cell corresponding to data states P0 to P15 increases progressively.

[0107] Based on the above settings, in order to correctly store and retrieve a data state, the threshold voltage distribution width of each data state needs to be compressed to improve the read window margin (RWM). RWM is a crucial parameter for the memory device to correctly retrieve stored data from memory cells. There are two definitions of RWM: First, RWM is the sum of the intervals between the threshold voltage distributions corresponding to two adjacent data states of a memory cell, for example, ... Figure 9 The threshold voltage distribution of the MLC type memory cell is illustrated. For example... Figure 9 As shown, the first RWM of an MLC-type memory cell can be the voltage range between the erase state P1 and the data state P2. Secondly, the RWM can be defined as the voltage range between the programming verification voltage of the memory cell's programming state and the read voltage used to distinguish the programming state from its adjacent data state, for example... Figure 9 The RWM includes the voltage ranges between VRD1 and VFY1, VRD2 and VFY2, and VRD3 and VFY3. VRD1, VRD2, and VRD3 are the read voltages distinguishing between erase state P1 and data state P2, data state P2 and data state P3, and data state P3 and data state P4, respectively. VFY1, VFY2, and VFY3 are the programming verification voltages for data state P2, data state P3, and data state P4, respectively. As the data density that a single memory cell can store further increases, the width of the RWM decreases, such as... Figure 7 The threshold voltage distribution of the TLC type memory cell shown and Figure 8 The threshold voltage distribution of the QLC type memory cell shown, and the RWM ratio exhibited by the two. Figure 9 The RWM corresponding to the MLC type memory cell shown is narrow.

[0108] like Figure 7 and Figure 8As shown, the threshold voltage Vt of the memory cell corresponding to the highest data state (such as P8 or P15) is usually relatively high. In this case, more charge enters the storage layer of the memory cell. The more charge there is, and the more intense the charge movement during high-temperature baking, the more severe the charge loss in the memory cell, leading to poor memory device retention characteristics. Of course, it should be understood that memory cells corresponding to other data states will also lose charge, even without baking, and the higher the data state, the more severe the charge loss in its corresponding memory cell. This is even more severe at high temperatures. The operating method provided in this application is applicable to any of the above situations.

[0109] To address one or more of the aforementioned problems, embodiments of this application provide an operation method for a memory device. In two adjacent memory cells within the same memory string, the reference verification information used in the verification operation of the latter programmed memory cell is obtained based on the data state to which the former programmed memory cell was programmed. Thus, appropriate reference verification information is obtained based on the data state of the former memory cell, and the latter memory cell is verified based on the determined reference verification information to improve the retention characteristics of the memory device.

[0110] The memory device includes a first memory cell and a second memory cell that belong to the same memory string and are adjacent to each other. Specifically, for example... Figure 10 As shown, the operation method may include:

[0111] S1001: Perform a first programming operation, causing the first storage unit to be programmed into a first data state;

[0112] S1002: Perform a second programming operation; the second programming operation includes: programming the second storage unit; and verifying the second storage unit according to the first reference verification information determined by the first data state.

[0113] Here, the memory string referred to is like the aforementioned memory string 408. The operation method can be a programming and verification method for a memory device, wherein the programming and verification method for the memory device can employ a multi-pass programming algorithm to achieve a tighter threshold voltage distribution. Specifically, the multi-pass programming algorithm can include two-pass programming, three-pass programming, etc., wherein the two-pass programming can include coarse programming and fine programming; the three-pass programming can include a first coarse programming, a second coarse programming, and fine programming. Here, the last programming pass in the multi-pass programming is fine programming; the first coarse programming and the second coarse programming are collectively referred to as coarse programming, or both can be referred to as non-last programming. In some embodiments, both non-last programming and fine programming can be incremental step pulse programming (ISPP), which can be a method of gradually increasing the word line bias voltage based on step voltage while programming the memory cells in the selected memory page several times. To balance programming speed with a wide RWM (Range Width Limit), in some embodiments, during non-final programming passes (coarse programming stages), a programming voltage pulse with a large set step size (e.g., 0.5 volts (V)) is applied to the selected word line (the word line selected to be coupled with the memory cell to be programmed) to quickly program the memory cell coupled to the selected word line to an intermediate data state. In the fine programming stage following each coarse programming stage, a programming voltage pulse with a smaller set step size (e.g., 0.2V) is applied to the selected word line to accurately program the memory cell coupled to the selected word line to the final data state or target data state. That is, in some embodiments, in each of the multiple programming passes, the programming voltage / pulse applied during the programming operation increases according to different set step sizes, the specific set step size of which can be set by the designer according to the actual programming situation. The intermediate data states refer to one or more data states before the programmed memory cell is programmed to its final data state. For example, when programming a TLC type memory cell, if the final data state of a certain memory cell is P3, then its intermediate data states can be at least one of P1 and P2; or other verifiable data states. The final data state is the data state that the user expects the programmed memory cell to be programmed to, for example, in the aforementioned programming of a TLC type memory cell, the final data state is P3.

[0114] It should be understood that during the programming of memory cells, in order to determine whether the programmed memory cell has been programmed to the target programmed data state, a verification operation is added between the application of two programming voltage pulses (the process of applying programming voltage pulses is also called a programming operation) to determine whether the programmed memory cell has been programmed to the target data state. That is, the programming operation and the verification operation are performed alternately. The verification operation can be one or a group of verification voltage pulses. Based on the foregoing description, the multi-pass programming can include at least one coarse programming pass and one fine programming pass, each programming pass including at least one programming operation and at least one verification operation.

[0115] Here, the first programming operation enables the first storage unit to be programmed into the first data state. That is, programming and verification are performed on the first storage unit, and only if the verification is successful can the first storage unit be placed in the first data state. This first data state can refer to an intermediate data state or a target data state of the first storage unit, which is related to the programming and verification algorithm used for the entire memory string. Detailed explanations will not be repeated here.

[0116] The technical solution described here can also be understood as follows: For two adjacent memory cells, the data state of the first memory cell, programmed first, guides the programming of the second memory cell, which is then programmed. Specifically, the first data state is used to determine first reference verification information for verifying the programming of the second memory cell. In other words, the operation method may include: first, performing a first programming operation on the first memory cell to program it into the first data state; then, performing a second programming operation on the second memory cell. In this second programming operation, the second memory cell is programmed, and the second memory cell is verified based on the first reference verification information determined by the first data state to determine whether the programming was successful. Thus, by using the data state of the first-programmed memory cell to guide the programming verification of the second-programmed memory cell, the charge loss of the second-programmed memory cell during high-temperature baking is reduced.

[0117] In some embodiments, the memory cells of the memory device can be programmed to any one of a plurality of data states including the first data state; the method may further include:

[0118] Obtain a first mapping relationship between the plurality of data states and reference verification information used to verify the programming results of the storage unit;

[0119] The first reference verification information is determined based on the first data state and the first mapping relationship.

[0120] It should be noted that, based on the aforementioned description of storage unit types, when the storage unit type is MLC, TLC, QLC, or other types capable of storing more bits, the storage units contained in a page 420 can be programmed into multiple data states. Furthermore, each storage unit can be programmed into any one of these multiple data states; that is, the storage units of the memory device can be programmed into any one of these multiple data states, and these multiple data states should include a first data state. For example, as described above... Figure 4 As shown, within the same page 420, they are coupled to, for example, Figure 3 On the same word line 418 shown, these memory cells can be programmed to any of a plurality of data states, wherein one or more memory cells are programmed to the first data state. In specific implementation, when the word line coupled to the first memory cell is the selected word line, a set of programming pulses is applied to the selected word line to perform a first programming operation, thereby programming the first memory cell to the first data state, while other memory cells coupled to the first memory cell on the same word line are disabled from programming under the control of the bit line voltage.

[0121] Under these conditions, determining the first reference verification information may include: obtaining a first mapping relationship, and determining the first reference verification information based on the first mapping relationship and the first data state. That is, in this embodiment, before obtaining the first reference verification information, it is necessary to first obtain the first mapping relationship between the plurality of data states and the reference verification information used to verify the programming results of the storage unit. Then, the first reference verification information is obtained by analyzing the first data state and the first mapping relationship for later use. Of course, it is understood that the first mapping relationship may be pre-stored or determined based on the plurality of data states when needed.

[0122] Here, in some embodiments, the reference verification information may include a reference verification voltage or a reference sensing time; obtaining the first mapping relationship between the plurality of data states and the reference verification information used to verify the programming results of the memory cell may include:

[0123] The multiple data states are divided into multiple data groups;

[0124] Obtain a first sub-mapping relationship between the plurality of data groups and the reference verification voltage; or, obtain a second sub-mapping relationship between the plurality of data groups and the reference sensing time;

[0125] The first mapping relationship includes: a first sub-mapping relationship and / or a second sub-mapping relationship.

[0126] It should be noted that the verification of a memory cell typically requires pre-charging the sensing node coupled to the memory cell to a high potential (e.g., an initial precharge bit). Then, the sensing node undergoes at least one discharge operation. The sensing circuit senses the voltage at the sensing node (SO) corresponding to different discharge stages of the memory cell. Based on this sensing result, it is determined whether the verification of the memory cell is complete. The verification result can be stored in a page buffer to reflect the programming result of the memory cell.

[0127] For example, such as Figure 11 The verification operation of the 4BL BIAS programming method shown requires three sensing steps: 3BL sensing, 4BL sensing, and Pass sensing, to determine whether the threshold voltage of the memory cell being verified is programmed to the 3BL, 4BL, or Pass range, respectively. It should be noted that the 3BL sensing process corresponds to... Figure 11 The 3BL verification (VFY) shown; the 4BL sensing process corresponds to Figure 11 The 4BL VFY shown corresponds to the Pass sensing process. Figure 1 The Pass VFY shown. The 3BL interval can refer to... Figure 11 The area to the left of 3BL VFY; the 4BL range can refer to Figure 11 The overlapping area between the right side of the 3BL VFY and the left side of the 4BL VFY; the Pass interval can refer to Figure 11 The diagram shows the overlapping area between the right side of 4BL VFY and the left side of Pass VFY. When a memory cell in different intervals is programmed again, the bias voltage applied to the bit line is different to more accurately program the memory cell to the target programmed state. For example, when a memory cell in the 3BL interval is programmed, its corresponding bit line is applied with 0 volts (V); when a memory cell in the 4BL interval is programmed, its corresponding bit line is applied with voltage VBL3; and when a memory cell in the Pass interval is programmed, its corresponding bit line is applied with voltage VBL4.

[0128] The reference verification information used for verification may include a reference verification voltage or a reference sensing time. Therefore, the first mapping relationship may include a first sub-mapping relationship between multiple data sets and the reference verification voltage, and / or a second sub-mapping relationship between multiple data sets and the reference sensing time.

[0129] Here, the reference verification voltage can refer to a target verification voltage that is compared with, for example, the potential of SO after discharging from the initial precharge bit for a period of time, to determine whether the programming of the memory cell was successful. Specifically, such as... Figure 12 The relationship between discharge duration and SO potential is shown. The SO potential is negatively correlated with the discharge duration; that is, the longer the discharge duration, the lower the SO potential. Based on this, a preset potential is set during the verification process. Discharge begins from the initial pre-charge position at the SO potential. After a period of discharge, if the SO potential is greater than or equal to the preset potential, the memory cell is turned on, indicating that the memory cell has passed the target verification voltage verification and has been successfully programmed. If the SO potential is less than the preset potential, the memory cell is turned off, indicating that the memory cell has not passed the target verification voltage verification and has not been successfully programmed. Furthermore, the higher the target verification voltage, the higher the threshold voltage for successfully programmed memory cells.

[0130] Here, the reference sensing time can refer to a target discharge duration, such as the time set by SO to discharge from the initial precharge position. Based on this, according to Figure 12 The relationship shown illustrates that during the verification process, a preset potential is set. Discharge begins at the initial pre-charge potential of SO or the potential after the previous discharge stage. If, within the target discharge duration, the SO potential has not been programmed to the preset potential, the memory cell is turned off, indicating that the memory cell has not been successfully programmed and verified. Conversely, if, within the target discharge duration, the SO potential has been programmed to the preset potential, the memory cell is turned on, indicating that the memory cell has been successfully programmed and verified. Furthermore, with a fixed preset potential, a longer target discharge duration results in a smaller induced current and a lower threshold voltage for successfully programmed memory cells; conversely, a shorter target discharge duration results in a larger induced current and a higher threshold voltage for successfully programmed memory cells.

[0131] Here, the partitioning of multiple data states can have various combinations. One feasible partitioning method, whereby the multiple data states are divided to form multiple data groups, may include:

[0132] The multiple data states are divided into a first data group and a second data group, wherein the threshold voltage corresponding to the data state in the first data group is less than the threshold voltage corresponding to the data state in the second data group.

[0133] In this case, the first mapping relationship may include: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or, a second sub-mapping relationship between the first data group, the second data group and the reference sensing time;

[0134] The first sub-mapping relationship may include: the correspondence between the first data group and the first reference verification voltage, and the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, and the correspondence between the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

[0135] That is, in the first sub-mapping relationship, the first reference verification voltage corresponding to the data state contained in the first data group is greater than the second reference verification voltage corresponding to the data state contained in the second data group; in the second sub-mapping relationship, the first reference sensing time corresponding to the data state contained in the first data group is greater than the second reference sensing time corresponding to the data state contained in the second data group.

[0136] In some embodiments, the first data group and the second data group among the plurality of data groups contain the same number of data states. In other embodiments, the first data group and the second data group among the plurality of data groups may contain different numbers of data states.

[0137] In some embodiments, the plurality of data states include 16 data states from L0 to L15; the first data group includes data states from L0 to L7; and the second data group includes data states from L8 to L15.

[0138] In some embodiments, determining the first reference verification information based on the first data state and the first mapping relationship may include:

[0139] The data group to which the first data state belongs is determined according to a preset second mapping relationship, wherein the second mapping relationship includes the correspondence between the plurality of data groups and the plurality of data states;

[0140] The first reference verification information is determined based on the data group to which it belongs and the first sub-mapping relationship, or the first reference verification information is determined based on the data group to which it belongs and the second sub-mapping relationship;

[0141] Specifically, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

[0142] Here, research indicates that the poor retention characteristics caused by charge loss in memory cells are mainly due to two factors: vertical charge loss and lateral charge loss. Among these, for example... Figure 13 and Figure 14 As shown, vertical charge loss can refer to the charge loss of a memory cell perpendicular to the memory string direction; lateral charge loss can refer to the charge loss of a memory cell parallel to the memory string direction. Studies have shown that in the vertical direction, the charge loss of a memory cell is related to its threshold voltage Vt; the higher Vt, the more severe the charge loss. In the lateral direction, the charge loss of a memory cell is related not only to its threshold voltage but also to the data state of adjacent memory cells. Specifically, when adjacent memory cells are in a high data state (already programmed to a high data state), the lateral charge loss corresponding to the memory cell being programmed is small. However, when adjacent memory cells are in a low data state (already programmed to a low data state), the lateral change loss corresponding to the memory cell being programmed is severe. In this case, the lateral charge loss is more severe than the charge loss caused by the vertical charge loss, and the charge loss becomes even more severe after high-temperature baking, resulting in a broadening of the threshold voltage distribution of the memory cells, and consequently, severe RWM loss. It should be noted that in... Figure 13 In the diagram, H represents a memory cell with a high data state; L represents a memory cell with a low data state; and R represents a memory cell being programmed, which can be programmed to any possible data state. Arrows perpendicular to the memory string represent vertical charge loss; arrows parallel to the memory string represent lateral charge loss. Figure 14In the diagram, WLn represents the word line coupled to the memory cell being programmed, or the selected word line. The curve represents the threshold voltage distribution of the memory cell corresponding to WLn. Dashed line 1 represents the threshold voltage distribution of the memory cell corresponding to WLn when the adjacent memory cell corresponding to WLn+1 is in a high data state; dashed line 2 represents the threshold voltage distribution of the memory cell corresponding to WLn when the adjacent memory cell corresponding to WLn+1 is in a low data state. In practical applications, adjacent memory cells corresponding to WLn+1 may be in a high data state or a low data state. Therefore, solid line 3 represents the threshold voltage distribution of the memory cell corresponding to WLn when the adjacent memory cells corresponding to WLn+1 are in both high and / or low data states. Figure 14 As shown, after high-temperature baking, the threshold voltage of the memory cell corresponding to WLn is further broadened.

[0143] Based on this, when using the first sub-mapping relationship, if the first data state belongs to the first data group, the first reference verification information is the first reference verification voltage; if the first data state belongs to the second data group, the first reference verification information is the second reference verification voltage. When using the second sub-mapping relationship, if the first data state belongs to the first data group, the first reference verification information is the first reference sensing time; if the first data state belongs to the second data group, the first reference verification information is the second reference sensing time.

[0144] In some embodiments, the memory string may further include a third memory cell adjacent to the second memory cell; the method may further include:

[0145] Perform a third programming operation to program the first storage unit to the first target programming state;

[0146] Perform a fourth programming operation to program the third storage unit into a second data state;

[0147] In the second programming operation, the second storage unit is not programmed to the second target data state; the second data state is not the target data state.

[0148] In some embodiments, the memory string further includes: a fourth memory cell adjacent to the first memory cell; before performing the first programming operation, the method further includes:

[0149] Perform the fifth programming operation to program the fourth storage unit to the third data state;

[0150] Perform the sixth programming operation to program the second memory cell to the fourth data state;

[0151] Perform the seventh programming operation to program the fourth storage unit to the third target data state;

[0152] Wherein, the first data state, the third data state, and the fourth data state are not target data states; under the second programming operation, the storage unit is programmed into the second target data state.

[0153] It should be noted that, as described above, the programming and verification methods for memory devices can employ multi-pass programming algorithms. Therefore, the implementation of the above-described methods is applicable to both coarse and fine programming within multi-pass programming algorithms.

[0154] In the operation method provided in this application embodiment, when the first data state is not the target data state, during execution Figure 10 Following the steps shown, a third programming operation may be added to program the first storage cell to a first target state; and a fourth programming operation to program the third storage cell adjacent to the second storage cell to a second data state. In this operation, the second storage cell is not programmed to a second target data state under the second programming operation, and the second data state is not the target data state. The above process is equivalent to two steps in two-way programming: the first step includes the first and second programming operations, which is coarse programming of the first and second storage cells; the second step includes the third and fourth programming operations, which is fine programming of the first storage cell and coarse programming of the third storage cell.

[0155] When the first data state is not the target data state, during execution Figure 10 Before the steps shown, the process may further include: performing a fifth programming operation to program the fourth storage unit to a third data state; a sixth programming operation to program the second storage unit to a fourth data state; and a seventh programming operation to program the fourth storage unit to a third target data state. The above process is equivalent to two steps in two-way programming: the first step includes the fifth, sixth, and seventh programming operations, i.e., coarse programming of the fourth storage unit, coarse programming of the second storage unit, and fine programming of the fourth storage unit; the second step includes the first and second programming operations, i.e., coarse programming of the first storage unit and fine programming of the second storage unit.

[0156] It should be noted that the first data state can also be the target data state. Specifically, given the sequentially adjacent positional relationship of the first, second, and third storage units, the data state of the first storage unit's fine programming is used as a guide during the fine programming of the second storage unit.

[0157] The above situation is understood as follows: Figure 15 As shown, it illustrates a flowchart of two-sided programming provided in an embodiment of this application.

[0158] exist Figure 15 In this programming process, the two-sided programming includes: First, coarse programming of WLn-1 and WLn; second, fine programming of WLn-1 and coarse programming of WLn+1; then, third, fine programming of WLn and coarse programming of WLn+2, and so on. In this location structure, the first storage unit can be the storage unit corresponding to WLn-1; the second storage unit is the storage unit corresponding to WLn; and the third storage unit is the storage unit corresponding to WLn+1. Figure 10 The operation performed is the first step in the two-sided programming, namely, coarse programming of the memory cells corresponding to WLn-1 and WLn; the third and fourth programming operations are the second step in the two-sided programming, namely, fine programming of the memory cells corresponding to WLn-1 and coarse programming of the memory cells corresponding to WLn+1.

[0159] exist Figure 15 In the positional structure shown, the first storage unit can also be the storage unit corresponding to WLn+1, the second storage unit can be the storage unit corresponding to WLn, and the fourth storage unit is the storage unit corresponding to WLn-1. In this case... Figure 10 Before executing any operations, the coarse programming of the memory cells corresponding to WLn-1, the coarse programming of the memory cells corresponding to WLn, and the fine programming of the memory cells corresponding to WLn-1 are performed first; then... Figure 10 Perform coarse programming on the memory cell corresponding to WLn+1, and fine programming on the memory cell corresponding to WLn.

[0160] In other words, regardless of the programming and verification algorithm, the embodiments of this application are applicable, utilizing the data state of the storage unit where the previous programming was successful to determine the programming of the next storage unit, thereby improving retention.

[0161] To understand the operation method provided in the embodiments of this application, a QLC type storage cell and the method used for that type of storage cell are described below. Figure 15 The two-sided programming and verification algorithm shown is used as an example for explanation. Based on the previous description of the operation method, the 16 data states are divided into a first data group and a second data group. The first data group includes data states L0 to L7; the second data group includes data states L8 to L15. The first data group corresponds to the first reference verification voltage V1 or the first reference sensing time T1; the second data group corresponds to the second reference verification voltage V2 or the second reference sensing time T2. For the specific implementation process, please refer to [link / reference]. Figures 16 to 19 As shown. Among them, Figure 16 This is a schematic diagram of the programming verification process when coarse programming is performed on the memory cell corresponding to WLn and verified using a reference verification voltage, as provided in an embodiment of this application. Figure 17 This is a schematic diagram of the programming verification process when coarse programming is performed on the memory cell corresponding to WLn and verification is performed using a reference sensing time, as provided in an embodiment of this application. Figure 18 This is a schematic diagram of the programming verification process when fine programming the memory cell corresponding to WLn is performed and verified using a reference verification voltage, as provided in an embodiment of this application. Figure 19 This is a schematic diagram of the programming verification process when fine programming the memory cell corresponding to WLn and verifying it using a reference sensing time, as provided in an embodiment of this application.

[0162] exist Figure 16 The specific implementation process may include:

[0163] S1601: The 16 data states of the memory cell corresponding to WLn-1 are divided into a first data group G1 and a second data group G2, wherein the first data group includes data states L0 to L7; and the second data group includes data states L8 to L15.

[0164] S1602: During the verification operation after coarse programming of the memory cell corresponding to WLn, in the same memory string, when the data state of the memory cell corresponding to WLn-1 belongs to the first data group, the first reference verification voltage V1 is selected to verify the memory cell corresponding to WLn; when the data state of the memory cell corresponding to WLn-1 belongs to the second data group, the second reference verification voltage V2 is selected to verify the memory cell corresponding to WLn.

[0165] S1603: If verification is successful, disable programming operations on the storage unit and end the process;

[0166] S1604: If verification fails, proceed to the next programming loop.

[0167] It should be noted that in the specific implementation, G1 corresponds to V1 and G2 corresponds to V2, which have already been stored in the circuit or control logic. In actual use, "0" is latched in the latch of the page buffer in the memory device. At this time, V1 corresponding to G1 is selected to verify the memory cell corresponding to WLn. When "1" is latched in the latch of the page buffer in the memory device, V2 corresponding to G2 is selected to verify the memory cell corresponding to WLn.

[0168] exist Figure 17 The specific implementation process may include:

[0169] S1701: The 16 data states of the memory cell corresponding to WLn-1 are divided into a first data group G1 and a second data group G2, wherein the first data group includes data states L0 to L7; and the second data group includes data states L8 to L15.

[0170] S1702: During the verification operation after coarse programming of the memory cell corresponding to WLn, in the same memory string, when the data state of the memory cell corresponding to WLn-1 belongs to the first data group, the first reference sensing time T1 is selected to verify the memory cell corresponding to WLn; when the data state of the memory cell corresponding to WLn-1 belongs to the second data group, the second reference sensing time T2 is selected to verify the memory cell corresponding to WLn.

[0171] S1703: If verification is successful, disable programming operations on the memory unit and end the process;

[0172] S1704: If verification fails, proceed to the next programming loop.

[0173] It should be noted that the embodiments provided in this application... Figure 17 process and Figure 16 The process is basically the same, the difference is: Figure 17 The verification is performed using a reference sensing time, which means that... Figure 16 The reference verification voltage can be replaced with the reference sensing time (first reference sensing time T1 or second reference sensing time T2).

[0174] exist Figure 18 The specific implementation process may include:

[0175] S1801: The 16 data states of the memory cell corresponding to WLn+1 are divided into a first data group G1 and a second data group G2, wherein the first data group includes data states L0 to L7; and the second data group includes data states L8 to L15.

[0176] S1802: During the verification operation after fine programming of the memory cell corresponding to WLn, in the same memory string, when the data state of the memory cell corresponding to WLn+1 belongs to the first data group, the first reference verification voltage V1 is selected to verify the memory cell corresponding to WLn; when the data state of the memory cell corresponding to WLn+1 belongs to the second data group, the second reference verification voltage V2 is selected to verify the memory cell corresponding to WLn.

[0177] S1803: If verification is successful, disable programming operations on the memory unit and end the process;

[0178] S1804: If verification fails, proceed to the next programming loop.

[0179] It should be noted that, Figure 18 This describes the procedures for selecting the reference verification voltage during the verification operation after fine-programming the memory cell corresponding to WLn. The reference verification voltage used here is determined based on the data group to which the data state of the memory cell corresponding to WLn+1 belongs.

[0180] exist Figure 19 The specific implementation process may include:

[0181] S1901: The 16 data states of the memory cell corresponding to WLn+1 are divided into a first data group G1 and a second data group G2, wherein the first data group includes data states L0 to L7; and the second data group includes data states L8 to L15.

[0182] S1902: During the verification operation after fine programming of the memory cell corresponding to WLn, in the same memory string, when the data state of the memory cell corresponding to WLn+1 belongs to the first data group, the first reference sensing time T1 is selected to verify the memory cell corresponding to WLn; when the data state of the memory cell corresponding to WLn+1 belongs to the second data group, the second reference sensing time T2 is selected to verify the memory cell corresponding to WLn.

[0183] S1903: If verification is successful, disable programming operations on the memory unit and end the process;

[0184] S1904: If verification fails, proceed to the next programming loop.

[0185] It should be noted that the embodiments provided in this application... Figure 19 process and Figure 18 The process is basically the same, the difference is: Figure 19 The verification is performed using a reference sensing time, which means that... Figure 18 The reference verification voltage can be replaced with the reference sensing time (first reference sensing time T1 or second reference sensing time T2).

[0186] The operation method provided in the embodiments of this application can be summarized as follows: Figure 20 and Figure 21 As shown in the figure. Curve 1 corresponds to the threshold voltage distribution of the memory cell corresponding to the low (data) state of memory cell WLn+1; curve 2 corresponds to the threshold voltage distribution of the memory cell corresponding to the high (data) state of memory cell WLn+1. Solid line 3 shows the threshold voltage distribution of the memory cell corresponding to WLn when adjacent memory cells corresponding to WLn+1 are in the high data state and / or low data state.

[0187] When selecting WLn to start rough programming, the adjacent WLn-1 has been programmed. Using the data written in WLn-1, the 16 programming states of WLn-1 are divided into multiple groups (G1, G2, not limited to 2 groups). For each programming state of WLn, there are multiple verify levels (V1 < V2). For the group where WLn-1 is in the low state (G1), the rough programming verify level of WLn is V2. For the group where WLn-1 is in the high state (G2), the rough programming verify level of WLn is V1. Similarly, immediately following is the fine programming of WLn-1 and the rough programming of WLn+1. Before starting the fine programming of WLn, similarly, the data of WLn+1 is divided into multiple groups (G1’, G2’, not limited to 2 groups). For each programming state of WLn, there are multiple verify levels (V1’ < V2’). For the group where WLn+1 is in the low state (G1’), the pgm verify level of WLn is V2’. For the group where WLn+1 is in the high state (G2’), the pgm verify level of WLn is V1’. Using this corresponding relationship between WLn and the adjacent WL Vt to improve the high-temperature retention characteristics.

[0188] Alternatively, when selecting WLn to start rough programming, the adjacent WLn-1 has been programmed. Using the data written in WLn-1, the 16 programming states of WLn-1 are divided into multiple groups (G1, G2, not limited to 2 groups). For each programming state of WLn, there are multiple sensing times (T1 < T2). For the group where WLn-1 is in the low state (G1), the rough programming verify sensing time of WLn is long (T2). For the group where WLn-1 is in the high state (G2), the rough programming verify sensing time of WLn is short (T1). Similarly, immediately following is the fine programming of WLn-1 and the rough programming of WLn+1. Before starting the fine programming of WLn, similarly, the data of WLn+1 is divided into multiple groups (G1’, G2’, not limited to 2 groups). For each programming state of WLn, there are multiple verify levels (T1’ < T2’). For the group where WLn+1 is in the low state (G1’), the fine programming verify sensing time of WLn is long (T2’). For the group where WLn+1 is in the high state (G2’), the fine programming verify sensing time of WLn is short (T1’). Using this corresponding relationship between WLn and the adjacent WL Vt to improve the high-temperature retention characteristics.

[0189] Based on the same inventive concept, such as Figure 22As shown, this application embodiment also provides a memory device 2200, including:

[0190] The memory array 2201 includes: a first memory cell and a second memory cell that belong to the same memory string and are adjacent to each other;

[0191] Peripheral circuit 2202, coupled to the memory array, is configured as follows:

[0192] Perform a first programming operation to program the first storage unit into a first data state;

[0193] Perform a second programming operation; the second programming operation includes: programming the second storage unit; and verifying the second storage unit according to the first reference verification information determined by the first data state.

[0194] In some embodiments, the memory cell of the memory device can be programmed into any one of a plurality of data states including the first data state; the peripheral circuitry is further configured to: obtain a first mapping relationship between the plurality of data states and reference verification information for verifying the programming result of the memory cell; and determine the first reference verification information based on the first data state and the first mapping relationship.

[0195] In some embodiments, the reference verification information includes a reference verification voltage or a reference sensing time; the peripheral circuit is further configured to: divide the plurality of data states to form a plurality of data groups; obtain a first sub-mapping relationship between the plurality of data groups and the reference verification voltage; or, obtain a second sub-mapping relationship between the plurality of data groups and the reference sensing time; wherein the first mapping relationship includes: the first sub-mapping relationship and / or the second sub-mapping relationship.

[0196] In some embodiments, the peripheral circuit is further configured to divide the plurality of data states into a first data group and a second data group, wherein the threshold voltage corresponding to the data state in the first data group is less than the threshold voltage corresponding to the data state in the second data group.

[0197] In some embodiments, the first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or, a second sub-mapping relationship between the first data group, the second data group and the reference sensing time;

[0198] The first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, and the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, and the correspondence between the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

[0199] In some embodiments, the memory string further includes a third memory cell adjacent to the second memory cell; the peripheral circuit is further configured to: perform a third programming operation, such that the first memory cell is programmed to a first target programming state; perform a fourth programming operation, such that the third memory cell is programmed to a second data state; wherein, under the second programming operation, the second memory cell is not programmed to a second target data state; the second data state is not a target data state.

[0200] In some embodiments, the memory string further includes: a fourth memory cell adjacent to the first memory cell; the peripheral circuitry is further configured to: before performing the first programming operation,

[0201] Perform the fifth programming operation to program the fourth storage unit to the third data state;

[0202] Perform the sixth programming operation to program the second memory cell to the fourth data state;

[0203] Perform the seventh programming operation to program the fourth storage unit to the third target data state;

[0204] Wherein, the first data state, the third data state, and the fourth data state are not target data states; under the second programming operation, the storage unit is programmed into the second target data state.

[0205] In some embodiments, the peripheral circuit is further configured to: determine the data group to which the first data state belongs according to a preset second mapping relationship, wherein the second mapping relationship includes the correspondence between the plurality of data groups and the plurality of data states;

[0206] The first reference verification information is determined based on the data group to which it belongs and the first sub-mapping relationship, or the first reference verification information is determined based on the data group to which it belongs and the second sub-mapping relationship;

[0207] Specifically, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

[0208] It should be noted that the memory device provided in the embodiments of this application is used to perform the aforementioned operation method. Therefore, the features mentioned here have been described above and can be understood with reference to the above description, and will not be repeated here.

[0209] This application also provides a memory system, including one or more memory devices as described above.

[0210] In some embodiments, the memory system is contained in a solid-state drive (SSD) or a memory card.

[0211] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as those applicable to a person skilled in the art upon reading the above description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined to simplify the application. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the disclosure may lie in fewer than all features of a particular disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of this application should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A method for operating a memory device, characterized in that, The memory device includes a first memory cell and a second memory cell that belong to the same memory string and are adjacent to each other; the method includes: Perform a first programming operation to program the first storage unit into a first data state; wherein the first data state is not the target data state; Perform a second programming operation; the second programming operation includes: programming the second storage unit; and verifying the second storage unit according to the first reference verification information determined by the first data state.

2. The operating method according to claim 1, characterized in that, The memory device's storage cells can be programmed to any one of a plurality of data states containing the first data state; the method further includes: Obtain a first mapping relationship between the plurality of data states and reference verification information used to verify the programming results of the storage unit; The first reference verification information is determined based on the first data state and the first mapping relationship.

3. The operating method according to claim 2, characterized in that, The reference verification information includes a reference verification voltage or a reference sensing time; obtaining the first mapping relationship between the plurality of data states and the reference verification information used to verify the programming results of the memory cell includes: The multiple data states are divided into multiple data groups; Obtain a first sub-mapping relationship between the plurality of data groups and the reference verification voltage; or, obtain a second sub-mapping relationship between the plurality of data groups and the reference sensing time; The first mapping relationship includes: the first sub-mapping relationship and / or the second sub-mapping relationship.

4. The operating method according to claim 3, characterized in that, The process of dividing the multiple data states into multiple data groups includes: The multiple data states are divided into a first data group and a second data group, wherein the threshold voltage corresponding to the data state in the first data group is less than the threshold voltage corresponding to the data state in the second data group.

5. The operating method according to claim 4, characterized in that, The first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data group and the reference verification voltage; and / or, a second sub-mapping relationship between the first data group, the second data group and the reference sensing time; The first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, and the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, and the correspondence between the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

6. The operating method according to claim 1, characterized in that, The memory string further includes a third memory cell adjacent to the second memory cell; the method further includes: Perform a third programming operation to program the first storage unit to the first target programming state; Perform a fourth programming operation to program the third storage unit into a second data state; In the second programming operation, the second storage unit is not programmed to the second target data state; the second data state is not the target data state.

7. The operating method according to claim 1, characterized in that, The memory string further includes a fourth memory cell adjacent to the first memory cell; before performing the first programming operation, the method further includes: Perform the fifth programming operation to program the fourth storage unit to the third data state; Perform the sixth programming operation to program the second memory cell to the fourth data state; Perform the seventh programming operation to program the fourth storage unit to the third target data state; Wherein, the third data state and the fourth data state are not target data states; under the second programming operation, the storage unit is programmed into the second target data state.

8. The operating method according to claim 3, characterized in that, The first and second data groups among the plurality of data groups contain the same number of data states.

9. The operating method according to claim 8, characterized in that, The multiple data states include 16 data states from L0 to L15; the first data group includes data states from L0 to L7; and the second data group includes data states from L8 to L15.

10. The operating method according to claim 5, characterized in that, Determining the first reference verification information based on the first data state and the first mapping relationship includes: The data group to which the first data state belongs is determined according to a preset second mapping relationship, wherein the second mapping relationship includes the correspondence between the plurality of data groups and the plurality of data states; The first reference verification information is determined based on the data group to which it belongs and the first sub-mapping relationship, or the first reference verification information is determined based on the data group to which it belongs and the second sub-mapping relationship; Specifically, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

11. A memory device, characterized in that, include: A memory array includes: a first memory cell and a second memory cell that belong to the same memory string and are adjacent to each other; The peripheral circuitry, coupled to the memory array, is configured as follows: Perform a first programming operation to program the first storage unit into a first data state; wherein the first data state is not the target data state; Perform a second programming operation; the second programming operation includes: programming the second storage unit; and verifying the second storage unit according to the first reference verification information determined by the first data state.

12. The memory device according to claim 11, characterized in that, The memory cell of the memory device can be programmed into any one of a plurality of data states including the first data state; the peripheral circuit is further configured to: obtain a first mapping relationship between the plurality of data states and reference verification information for verifying the programming result of the memory cell; and determine the first reference verification information based on the first data state and the first mapping relationship.

13. The memory device according to claim 12, characterized in that, The reference verification information includes a reference verification voltage or a reference sensing time; the peripheral circuit is further configured to: divide the plurality of data states into a plurality of data groups; and obtain a first sub-mapping relationship between the plurality of data groups and the reference verification voltage; Alternatively, a second sub-mapping relationship can be obtained between the plurality of data groups and the reference sensing time; wherein the first mapping relationship includes: the first sub-mapping relationship and / or the second sub-mapping relationship.

14. The memory device according to claim 13, characterized in that, The peripheral circuit is further configured to divide the plurality of data states into a first data group and a second data group, wherein the threshold voltage corresponding to the data state in the first data group is less than the threshold voltage corresponding to the data state in the second data group.

15. The memory device according to claim 14, characterized in that, The first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data group and the reference verification voltage; and / or, a second sub-mapping relationship between the first data group, the second data group and the reference sensing time; The first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, and the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, and the correspondence between the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

16. The memory device according to claim 11, characterized in that, The memory string further includes a third memory cell adjacent to the second memory cell; the peripheral circuit is further configured to: perform a third programming operation, such that the first memory cell is programmed to a first target programming state; perform a fourth programming operation, such that the third memory cell is programmed to a second data state; wherein, under the second programming operation, the second memory cell is not programmed to a second target data state; the second data state is not a target data state.

17. The memory device according to claim 11, characterized in that, The memory string further includes a fourth memory cell adjacent to the first memory cell; the peripheral circuitry is further configured to: before performing the first programming operation, Perform the fifth programming operation to program the fourth storage unit to the third data state; Perform the sixth programming operation to program the second memory cell to the fourth data state; Perform the seventh programming operation to program the fourth storage unit to the third target data state; Wherein, the third data state and the fourth data state are not target data states; under the second programming operation, the storage unit is programmed into the second target data state.

18. The memory device according to claim 15, characterized in that, The peripheral circuit is further configured to: determine the data group to which the first data state belongs according to a preset second mapping relationship, wherein the second mapping relationship includes the correspondence between the plurality of data groups and the plurality of data states; The first reference verification information is determined based on the data group to which it belongs and the first sub-mapping relationship, or the first reference verification information is determined based on the data group to which it belongs and the second sub-mapping relationship; Specifically, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

19. A memory system, characterized in that, include: One or more memory devices according to any one of claims 11 to 18.

20. The memory system according to claim 19, characterized in that, The memory system is contained in a solid-state drive (SSD) or a memory card.

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