Semiconductor structure, semiconductor structure forming method and electronic equipment

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a forming method of the semiconductor structure and electronic equipment. The shallow trench isolation structure is formed from the first surface of the substrate, and the deep trench isolation structure is formed from the second surface of the substrate; at least two active regions located in the substrate; the polycrystalline silicon resistance layer is formed at the end part, close to the first surface, of the shallow trench isolation structure; the first contact hole is formed in the surface of the active region; the second contact hole is formed in the surface, far away from the shallow trench isolation structure, of the polycrystalline silicon resistance layer; wherein the height difference between the first contact hole and the second contact hole is smaller than a preset height threshold value. According to the semiconductor structure provided by the embodiment of the invention, the polycrystalline silicon resistance layer is directly formed at the end part, close to the first surface, of the shallow trench isolation structure, so that the step height difference between CT-AA and CT-Poly is reduced, and a CT etch has enough process window.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure, a method for forming a semiconductor structure, and an electronic device. Background Art

[0002] Automotive three-dimensional distance imaging systems usually have high gain, high sensitivity, and high time resolution performance requirements. A common form of optical sensor for three-dimensional distance imaging systems is silicon photomultiplier (SiPM). SiPM consists of multiple single-photon avalanche diodes (SPADs) in parallel. Usually, each SPAD unit is independently connected in series with a quenching resistor, and the cathode and anode are connected in parallel. One array outputs signals as a pixel, and multiple arrays can achieve three-dimensional imaging. The three-dimensional distance imaging system's demand for high gain of SPAD sensors requires a higher overvoltage of SPAD to obtain higher photon detection efficiency. However, excessively high operating voltage poses higher challenges to the device's electrical isolation / direct current resistance (DCR) reduction requirements.

[0003] In order to meet the design requirements, high voltage is usually applied between the polysilicon resistor (Poly) layer and the deep trench isolation structure (DTI). In order to achieve electrical isolation between Poly and DTI under high voltage, silicon carbide and an isolation layer (Dep SIN and OX) are usually deposited on the substrate, and a polysilicon resistor layer (Poly) is formed on the isolation layer. However, in the related technology, there is a step height difference of nearly 2000 angstroms between the contact hole (CT-AA) formed on the active area (AA) and the contact hole (CT-Poly) formed on the Poly. The step height difference is too large, resulting in insufficient process window (process window) for the contact hole etching (CT etch) process, thereby affecting the acceptance test (Wafer Acceptance Test, WAT) performance of the semiconductor device. Summary of the invention

[0004] The present application provides a semiconductor structure, a method for forming a semiconductor structure, and an electronic device to at least solve the problem in the related art that the step height difference between CT-AA and CT-Poly is too large, resulting in a CT etch process without sufficient process window, thereby affecting the WAT performance of the semiconductor device.

[0005] In order to solve the above technical problems, the technical solution of this application is as follows:

[0006] According to a first aspect of an embodiment of the present application, there is provided a semiconductor structure, including:

[0007] a substrate comprising opposing first and second surfaces;

[0008] forming a shallow trench isolation structure located in the substrate from a first surface of the substrate, and forming a deep trench isolation structure located in the substrate from a second surface of the substrate;

[0009] at least two active regions located in the substrate, adjacent active regions being separated by the shallow trench isolation structure and the deep trench isolation structure;

[0010] A polysilicon resistor layer is formed at an end of the shallow trench isolation structure close to the first surface; the polysilicon resistor layer is electrically connected to the active area;

[0011] A first contact hole formed on the surface of the active area, and a second contact hole formed on the surface of the polysilicon resistance layer away from the shallow trench isolation structure;

[0012] The height difference between the first contact hole and the second contact hole is less than a preset height threshold, and the preset height threshold is a threshold that enables the formation process of the first contact hole and the second contact hole to meet a preset process window.

[0013] In an optional embodiment, the preset height threshold is proportional to the thickness of the polysilicon resistance layer.

[0014] In an optional embodiment, the preset height threshold is 500 angstroms to 1000 angstroms.

[0015] In an optional embodiment, there are at least two shallow trench isolation structures, and the polysilicon resistance layer is formed on ends of two adjacent shallow trench isolation structures close to the first surface.

[0016] In an optional embodiment, a distance between an end of the deep trench isolation structure away from the second surface and the first surface is greater than zero.

[0017] In an optional embodiment, a distance between an end of the deep trench isolation structure away from the second surface and the first surface is 0.5 um to 2 um.

[0018] In an optional embodiment, the deep trench isolation structure extends to the shallow trench isolation structure, and an end of the deep trench isolation structure away from the second surface contacts an end of the shallow trench isolation structure away from the polysilicon resistance layer.

[0019] In an optional embodiment, there are at least two shallow trench isolation structures, and the shallow trench isolation structures are distributed in the surrounding area of ​​the deep trench isolation structure.

[0020] In an optional embodiment, the deep trench isolation structure is located between two adjacent shallow trench isolation structures, the end of the deep trench isolation structure away from the second surface is in contact with the ends of two adjacent shallow trench isolation structures away from the polysilicon resistance layer, and the distance between the two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

[0021] In an optional embodiment, the semiconductor structure further includes a light limiting groove located on the second surface, and the light limiting groove is used to adjust the amount of light irradiated to the second surface.

[0022] In an optional embodiment, the light-limiting groove is an inverted triangle structure.

[0023] According to a second aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, comprising:

[0024] Providing a substrate; the substrate comprising a first surface and a second surface opposite to each other;

[0025] forming a shallow trench isolation structure in the substrate from a first surface of the substrate;

[0026] forming at least two active regions in the substrate;

[0027] A polysilicon resistance layer is formed at an end of the shallow trench isolation structure close to the first surface; the polysilicon resistance layer is electrically connected to the active area;

[0028] A first contact hole is formed on the active area, and a second contact hole is formed on a surface of the polysilicon resistor layer away from the shallow trench isolation structure; wherein a height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, and the preset height threshold is a threshold value that enables the formation process of the first contact hole and the second contact hole to meet a preset process window;

[0029] A deep trench isolation structure is formed in the substrate from the second surface of the substrate; the deep trench isolation structure and the shallow trench isolation structure are used to isolate adjacent active areas.

[0030] In an optional embodiment, forming a shallow trench isolation structure located in the substrate from the first surface of the substrate includes:

[0031] An isolation layer is formed on the first surface of the substrate, and a zero-layer mask layer is formed on the isolation layer; the zero-layer mask layer is recombined with a zero-layer mark pattern and a first-layer main chip area pattern; the first-layer main chip area pattern defines the size of the shallow trench isolation structure, and defines the positional relationship between the shallow trench isolation structure and the deep trench isolation structure;

[0032] Using the zero-layer mask layer as a mask, the isolation layer and part of the substrate are etched in sequence to form the shallow trench isolation structure in the substrate and a zero-layer mark in the cutting path area; the end of the deep trench isolation structure away from the second surface is in contact with the end of the shallow trench isolation structure away from the polysilicon resistance layer.

[0033] In an optional embodiment, there are at least two shallow trench isolation structures, and the deep trench isolation structure is located between two adjacent shallow trench isolation structures. The end of the deep trench isolation structure away from the second surface is in contact with the ends of the two adjacent shallow trench isolation structures away from the polysilicon resistance layer, and the distance between the two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

[0034] In an optional embodiment, after forming a shallow trench isolation structure located in the substrate from the first surface of the substrate, the method further includes:

[0035] Filling an insulating material in the shallow trench isolation structure by a high-density plasma method to obtain a filled shallow trench isolation structure;

[0036] The filled shallow trench isolation structure is subjected to chemical mechanical polishing, and the polishing is stopped at a surface of the isolation layer away from the first surface, so as to obtain a shallow trench isolation structure after the polishing.

[0037] In an optional embodiment, there are at least two shallow trench isolation structures, and the polysilicon resistance layer is formed at the end of the shallow trench isolation structure close to the first surface, including:

[0038] The polysilicon resistance layer is deposited on the end of the target shallow trench isolation structure close to the first surface; the target shallow trench isolation structure is two adjacent shallow trench isolation structures after polishing.

[0039] In an optional embodiment, after forming a first contact hole on the active area and forming a second contact hole on a surface of the polysilicon resistor layer away from the shallow trench isolation structure, the method further comprises:

[0040] forming a metal stack at an end of the first contact hole away from the active area and an end of the second contact hole away from the polysilicon resistance layer;

[0041] Melt-bonding the structure forming the metal stack to the carrier wafer, and flipping the bonded structure;

[0042] The step of forming a deep trench isolation structure in the substrate from the second surface of the substrate comprises:

[0043] The deep trench isolation structure is formed from the upper surface of the flipped structure; wherein the upper surface of the flipped semiconductor structure is the second surface.

[0044] In an optional embodiment, forming the deep trench isolation structure from the upper surface of the flipped structure includes:

[0045] forming a photoresist layer having a deep trench isolation structure pattern on the upper surface of the flipped semiconductor structure; the photoresist layer defines the size of the deep trench isolation structure;

[0046] The substrate is etched in the direction of the shallow trench isolation structure using the deep trench isolation structure pattern as a mask, and the etching is stopped when the end of the shallow trench isolation structure away from the polysilicon resistance layer is reached to form the deep trench isolation structure.

[0047] In an optional embodiment, a distance between an end of the deep trench isolation structure away from the second surface and the first surface is greater than zero.

[0048] In an optional embodiment, a distance between an end of the deep trench isolation structure away from the second surface and the first surface is 0.5 um to 2 um.

[0049] In an optional embodiment, the preset height threshold is proportional to the thickness of the polysilicon resistance layer.

[0050] In an optional embodiment, the preset height threshold is 500 angstroms to 1000 angstroms.

[0051] In an optional embodiment, the method further includes:

[0052] A light limiting groove is formed on the second surface; wherein the light limiting groove is used to adjust the amount of light irradiated to the second surface

[0053] According to a third aspect of an embodiment of the present application, an electronic device is provided, wherein the electronic device comprises the semiconductor structure as described above.

[0054] The technical solution provided by the embodiments of the present application brings at least the following beneficial effects: the method for preparing the semiconductor structure provided by the embodiments of the present application, by forming a shallow trench isolation structure located in the substrate from the first surface of the substrate, directly forming a polysilicon resistance layer at the end of the shallow trench isolation structure close to the first surface, forming a first contact hole on the active area, and forming a second contact hole on the surface of the polysilicon resistance layer away from the shallow trench isolation structure, removes the Dep SIN and OX processes in the original FSI loop process, simplifies the FSI loop process flow, reduces the step height difference between CT-AA and CT-Poly, and allows CT etch to have sufficient process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0055] The semiconductor structure provided by the embodiment of the present application includes: a substrate, including a first surface and a second surface relative to each other; a shallow trench isolation structure located in the substrate is formed from the first surface of the substrate, and a deep trench isolation structure located in the substrate is formed from the second surface of the substrate; at least two active areas are located in the substrate, and adjacent active areas are separated by the shallow trench isolation structure and the deep trench isolation structure; a polysilicon resistor layer is formed at the end of the shallow trench isolation structure close to the first surface; the polysilicon resistor layer is electrically connected to the active area; a first contact hole is formed on the surface of the active area, and a second contact hole is formed on the surface of the polysilicon resistor layer away from the shallow trench isolation structure; wherein the height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, and the preset height threshold is a threshold that allows the formation process of the first contact hole and the second contact hole to meet a preset process window. It can be seen that the semiconductor structure provided in the embodiment of the present application directly forms a polysilicon resistance layer at the end of the shallow trench isolation structure close to the first surface, and removes the SIN layer and the OX layer deposited in the original process, thereby reducing the step height difference between CT-AA and CT-Poly, so that CT etch has a sufficient process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0056] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application, and do not constitute an improper limitation on the present application.

[0058] Figure 1 The figure is a schematic flow chart of a method for forming a semi-semiconductor structure according to an exemplary embodiment.

[0059] Figure 2 It is a schematic diagram of a cross-sectional structure of a substrate according to an exemplary embodiment.

[0060] Figure 3 FIG. 4 is a top view of a zero-layer mask layer according to an exemplary embodiment.

[0061] Figure 4 FIG. 4 is a top view of a reorganized zero-layer mask layer according to an exemplary embodiment.

[0062] Figure 5 The figure is a schematic cross-sectional structure diagram of a shallow trench isolation structure according to an exemplary embodiment.

[0063] Figure 6 It is a schematic diagram of a cross-sectional structure after high-density plasma deposition and chemical mechanical polishing according to an exemplary embodiment.

[0064] Figure 7 FIG. 1 is a schematic cross-sectional structure diagram obtained by a FSI loop process according to an exemplary embodiment.

[0065] Figure 8 It is a schematic diagram of a cross-sectional structure after flipping according to an exemplary embodiment.

[0066] Fig. 9 The figure is a schematic cross-sectional structure diagram showing a method of forming a deep trench isolation structure according to an exemplary embodiment.

[0067] Fig.10 It is a schematic diagram of the cross-sectional structure of a deposition dock after dock grinding by chemical mechanical polishing according to an exemplary embodiment.

[0068] Fig.11 It is a schematic diagram of the cross-sectional structure of a deposition dock after dock grinding by chemical mechanical polishing according to an exemplary embodiment.

[0069] The following is a supplementary explanation of the reference numerals:

[0070] 11-substrate; 1101-first surface; 1102-second surface; 12-shallow trench isolation structure; 13-isolation layer; 14-zero layer marking pattern; 15-main chip area; 16-first layer main chip area pattern; 17-deep trench isolation structure pattern; 18-cutting area; 19-active area; 111-polysilicon resistance layer; 112-nitride blocking layer; 113-dielectric layer; 114-first contact hole; 115-second contact hole; 116-first metal layer; 117-second metal layer; 118-carrier wafer; 119-deep trench isolation structure; 120-optical isolation material; 121-metal aluminum layer. DETAILED DESCRIPTION

[0071] The following content provides many different embodiments or examples for implementing the different features of the provided subject matter. The specific examples of the components and configurations described below are disclosed in a simplified manner. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of the first feature above or on the second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the application may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0072] Additionally, spatially relative terms, such as "below," "beneath," "lower," "on," "upper," "front," "back," "above," and the like, may be used in this application for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

[0073] As described in the background art, the step height difference between CT-AA and CT-Poly formed by the process in the related art is too large, and the performance needs to be improved urgently. Now, a method for forming a semiconductor structure is described and analyzed.

[0074] Figure 1 is a flow chart of a method for forming a semi-semiconductor structure according to an exemplary embodiment. Figure 1 , the method for forming the semiconductor structure may include:

[0075] S101. Provide a substrate; the substrate comprises a first surface and a second surface opposite to each other.

[0076] Figure 2is a schematic diagram of a cross-sectional structure of a substrate according to an exemplary embodiment. Figure 2 As shown, the substrate 11 has a first surface 1101 and a second surface 1102 opposite to the first surface 1101. The first surface 1101 can be considered as the front surface, and the second surface 1102 can be considered as the back surface. In one embodiment, in a front side illumination process (FSI loop), the first surface 1101 is a surface that receives light, i.e., a light-receiving surface. In another embodiment, in a BSI process, the second surface 1102 is a surface that receives light, i.e., a light-receiving surface.

[0077] Optionally, the material of the substrate 11 may include, but is not limited to, silicon, a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), germanium on insulator (GOI), or another type of semiconductor material capable of generating charges from photons of incident light. Among them, the multi-element semiconductor material composed of III-V elements includes indium phosphide (InP), gallium arsenide (GaAs), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs) or indium gallium arsenide phosphide (InGaAsP).

[0078] Optionally, at least two photodiodes (not shown) are formed in the substrate 11. In the BSI process, the at least two photodiodes are adapted for light irradiation at the second surface, i.e., for converting photons incident on the substrate from the second surface 1102 into electrical signals. Exemplarily, the photodiodes may be single photon avalanche diodes.

[0079] Optionally, at least two photodiodes may be arranged in an array in the substrate 11. Specifically, the single-photon avalanche diode may be formed by: ion implantation is performed on a region of the substrate 11 where the single-photon avalanche diode is to be formed, so as to form a doped region having a doping type opposite to that of the substrate 11, and the doped region and the substrate 11 constitute a single-photon avalanche diode. For example, an N-type doped region may be formed in a P-type semiconductor substrate, and the N-type doped region and the P-type substrate constitute a single-photon avalanche diode.

[0080] S103. Form a shallow trench isolation structure in the substrate from the first surface of the substrate.

[0081] In this embodiment, at least two shallow trench isolation (STI) structures located in the substrate 11 can be formed from the first surface 1101 of the substrate 11, that is, from the front side of the substrate 11. Specifically, the shallow trench isolation structure 12 is formed on the side of the pixel region of the substrate 11, which is used to provide an isolation structure for the SPAD, for example, it can reduce the optical crosstalk of adjacent SPADs forming the semiconductor structure. Furthermore, the shallow trench isolation structure 12 can be formed between adjacent pixel regions of the substrate 11.

[0082] In some embodiments, the STI structure may include a reflective material so that the STI structure blocks light from an adjacent pixel region of the semiconductor structure and / or directs light in the pixel region back to the SPAD. In some implementations, the reflective material may be a reflective metal stack or a multilayer oxide structure with different refractive indices (e.g., to form a total internal reflection structure).

[0083] It should be noted that the embodiment of the present application does not limit the shape of the shallow trench isolation structure, and the shape of its cross-sectional structure may include but is not limited to: rectangular, trapezoidal, etc.

[0084] Optionally, the embodiment of the present application may form the shallow trench isolation structure 12 in a variety of ways, which are not specifically limited.

[0085] In one embodiment, in the above step S103, the forming of a shallow trench isolation structure located in the substrate from the first surface of the substrate may include:

[0086] An isolation layer 13 is formed on the first surface 1101 of the substrate 11, and a zero-layer mask layer is formed on the isolation layer 13; the zero-layer mask layer has a zero-layer marking pattern and a first-layer main chip area pattern recombined therein; the first-layer main chip area pattern defines the size of the shallow trench isolation structure, and defines the positional relationship between the shallow trench isolation structure and the deep trench isolation structure.

[0087] The isolation layer 13 and a portion of the substrate 11 are sequentially etched using the zero-layer mask layer as a mask to form the shallow trench isolation structure in the substrate 11 and a zero-layer mark in the cutting path area.

[0088] The above-mentioned process of "forming a shallow trench isolation structure located in the substrate from the first surface of the substrate" can be referred to as "Zero PH and ET" in the FSI loop, wherein Zero refers to a zero mask layer (Zero mask), PH is the abbreviation of Photo-lithography, and its Chinese name is lithography, and ET refers to the abbreviation of Etch, and its Chinese name is etching.

[0089] Figure 3 is a top view of a zero-layer mask layer according to an exemplary embodiment. Figure 4 FIG. 1 is a top view of a reorganized zero-layer mask layer according to an exemplary embodiment. Figure 4 As shown, the FSI loop in the embodiment of the present application is Figure 3 The zero-level mask layer is shown retooling, except Figure 3 In addition to the original zero-layer marking pattern 14, a first-layer main chip area pattern 16 (zero pattern) is added to the main chip area 15 (main chip area). The zero pattern can be distributed around the deep trench isolation structure pattern 17 (DTI pattern) of the BSI loop. The deep trench isolation structure pattern 17 is located between the areas corresponding to two adjacent SPADs. It can be seen that the zero pattern not only defines the size of the shallow trench isolation structure 12, but also defines the positional relationship between the shallow trench isolation structure and the deep trench isolation structure: that is, the two adjacent shallow trench isolation structures are distributed in the surrounding area of ​​the deep trench isolation structure, and the spacing between the two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

[0090] The zero pattern is used to enable the high density plasma (HDP) subsequently deposited in the shallow trench isolation structure (Dep) to perfectly contact the deep trench isolation structure (DTI) of the BSI. The zero layer mark pattern exposes the zero layer mark (zero mark) used for alignment to the substrate 11. The zero layer mark is used to align each layer with the zero mark when stacking layers on the substrate 11, so as to ensure that the overlay error between each layer meets the requirements.

[0091] The isolation layer and part of the substrate 11 are sequentially etched using the zero-layer mask layer as a mask, thereby forming the shallow trench isolation structure in the substrate 11 and forming a zero-layer mark in the cutting path area 18. Since the embodiment of the present application adds a zero pattern in the main chip area in addition to the original zero-layer mark pattern 14, the zero pattern can be distributed around the DTI pattern of the BSI loop. The zero pattern is used to enable the HDP subsequently deposited in the shallow trench isolation structure to be in perfect contact with the DTI of the BSI, so that the end of the deep trench isolation structure obtained in the end is away from the second surface and can be in perfect contact with the end of the shallow trench isolation structure away from the polysilicon resistance layer, and then the devices can be effectively isolated through the joint action of the deep trench isolation structure and the shallow trench isolation structure, and the problem of electrical crosstalk between devices can be effectively solved.

[0092] The following is an explanation of the above-mentioned "Zero PH and ET" process:

[0093] Figure 5 FIG. 1 is a schematic cross-sectional structure diagram of a shallow trench isolation structure according to an exemplary embodiment. Figure 5 As shown, a semiconductor processing tool (eg, a deposition tool) may be used to deposit the isolation layer 13 on the first surface 1101 of the substrate 11. For example, the isolation layer may be an oxide layer formed by a local oxidation of silicon (LOCOS) process, a thermal oxidation process, or a chemical vapor deposition process.

[0094] The present embodiment does not limit the formation process of the isolation layer. For example, the isolation layer 13 may be formed on the first surface 1101 by a plasma enhanced atomic layer deposition process, or may be formed on the first surface 1101 in an oxygen vapor environment. Optionally, the material of the isolation layer may include, but is not limited to, silicon oxide, oxynitride, composite oxide, and the like.

[0095] In this embodiment, one or more semiconductor tools can form a shallow trench isolation structure from the first surface 1101 of the substrate 11. For example, a deposition tool can form a zero-layer mask layer on the first surface 1101 of the substrate 11, an exposure tool exposes the zero-layer mask layer to a radiation source to pattern the zero-layer mark pattern and the first-layer main chip area pattern in the zero-layer mask layer, a developer tool can develop and remove part of the zero-layer mask layer to expose the pattern, and an etching tool can sequentially etch the isolation layer 13 and part of the substrate 11 to form the shallow trench isolation structure 12 in the substrate 11 and form a zero-layer mark in the cutting road area 18. After the shallow trench isolation structure is obtained, the inner wall of the shallow trench isolation structure 12 can also be subjected to surface oxidation treatment, for example, oxygen is introduced into the reaction chamber, and the oxygen reacts with the single crystal silicon on the exposed surface of the silicon substrate to generate a silicon oxide layer. The substrate 11 having formed the STI structure is subjected to chemical mechanical polishing (CMP) to flatten the upper surface of the substrate 11.

[0096] It should be noted that the depth of the substrate 11 etched is set according to actual production requirements and is not specifically limited thereto. Figure 5 Only one shallow trench isolation structure is shown in the figure. In actual applications, multiple shallow trench isolation structures may be distributed at certain intervals on the first surface 1101 of the substrate 11. The embodiment of the present application does not limit the number and distribution of the shallow trench isolation structures.

[0097] In an optional embodiment, the method for forming the semiconductor structure may further include:

[0098] A reflective layer (not shown) may also be formed on the first surface 1101 of the substrate 11. The reflective layer is a layer used to reflect light toward the SPAD during operation of the semiconductor structure. For example, the reflective layer may reflect any incident light back toward the SPAD (e.g., acting as a mirror), thereby enhancing the absorption of light by the SPAD and improving the light sensitivity of the semiconductor structure. In some implementations, the reflective layer includes a metal material, such as copper or another type of metal material having reflective properties.

[0099] In some implementations, one or more semiconductor processing tools may be used to form the reflective layer. For example, a deposition tool may form the reflective layer above the first surface 1101 of the substrate 11. Next, the deposition tool may form a photoresist layer above the reflective layer, the exposure tool may expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool may develop and remove portions of the photoresist layer to expose the pattern, and the etching tool may etch one or more portions of the reflective layer to remove portions of the reflective layer such that portions above the SPADs remain. In some implementations, the photoresist removal tool removes the remaining portions of the photoresist layer after the etching tool etches the reflective layer.

[0100] S105. Form at least two active regions in the substrate.

[0101] In this embodiment, after obtaining multiple shallow trench isolation structures, active areas 19 (Active Area, AA) can be defined according to the multiple shallow trench isolation structures, and the adjacent active areas 19 are separated from each other by the formed multiple shallow isolation trenches. The above-mentioned photodiode can be formed in the active area.

[0102] In some embodiments, after forming a shallow trench isolation structure located in the substrate 11 from the first surface 1101 of the substrate 11, the method may further include:

[0103] An insulating material is filled in the shallow trench isolation structure by a high-density plasma method to obtain a filled shallow trench isolation structure.

[0104] The filled shallow trench isolation structure is subjected to chemical mechanical polishing, and the polishing process is stopped at the surface of the isolation layer away from the first surface 1101, so as to obtain a shallow trench isolation structure after the polishing process.

[0105] The process of "high density plasma deposition and chemical mechanical polishing" can be referred to as "HDP Fill + HDP CMP Stop on OX" in FSIloo p, where HDP is the abbreviation of High Density Plasma, the Chinese name is high density plasma, and Fill means filling in Chinese. The "OX" in "Stop on OX" can be an isolation layer 13, and the material of the isolation layer 13 can include but is not limited to: silicon oxide, nitrogen oxide, composite oxide, etc.

[0106] The following is an explanation of the "HDP Fill+HDP CMP Stop on OX" process:

[0107] Figure 6 FIG. 1 is a schematic diagram of a cross-sectional structure after high-density plasma deposition and chemical mechanical polishing according to an exemplary embodiment. Figure 6 As shown, the semiconductor processing tool can form a liner isolation layer on the surface of the shallow trench isolation structure by the HDP method, and then fill the insulating layer by the HDP method. The embodiment of the present application can use a variety of methods to perform HDP Fill, which is not specifically limited. In one embodiment, the HDP method can be used to first fill the insulating material to a position half the height of the shallow trench isolation structure to complete the first step of the HDP Fill filling process. Then, the reaction gas flow ratio of the HDP is adjusted according to the surface roughness of the substrate 11, and the substrate 11 is rotated by a certain angle, and then the insulating material is filled to the top of the shallow trench isolation structure to complete the second step of the HDP Fill filling process. The two-step HDP Fill filling process can greatly reduce the surface roughness after the HDP process, which is conducive to the smooth progress of subsequent processes.

[0108] In some embodiments, in order to reduce the damage of the HDP method to the active area, the active area can be divided into a sparse active area area and a dense active area area. The HDP method has different filling capabilities for the sparse active area area and the dense active area area. For the sparse active area area, protection strips can be added on both sides of the active area in the sparse active area area, and the distance between adjacent protection strips and the respectively protected active areas is adjusted so that the spacing between two adjacent protection strips satisfies the filling capability of the HDP for the shallow trench isolation structure between the active areas in the dense active area area. Among them, the sparse area is a region where the distance between the active areas is relatively large, and the dense area is a region where the distance between the active areas is relatively small.

[0109] After the HDP Fill process is completed, the filled insulating material can be planarized by CMP until the isolation layer 13 is exposed. In some embodiments, in order to avoid damage to the isolation layer 13 and the substrate 11 by CMP, a protective layer (not shown) can be deposited on the isolation layer 13 in advance. The protective layer can be a double-layer structure with a hard upper layer and a soft lower layer. When the structure after HDP is subjected to CMP, when the upper harder protective layer is encountered, the CMP stops, and the lower softer protective layer can protect the isolation layer 13 and the substrate 11 layer. Then, the barrier layer is removed by etching, thereby avoiding the adverse effects of CMP on the isolation layer 13 and the substrate 11 layer, and ensuring the flatness of the end of the shallow trench isolation structure.

[0110] This embodiment uses the process of HDP Fill+HDP CMP Stop on OX. On the one hand, HDP Fill can form a uniform insulator in the trench isolation structure to effectively isolate the devices, thereby effectively solving the problem of electrical crosstalk between devices. On the other hand, the HDP CMP Stop on OX process can ensure the flatness of the ends of the shallow trench isolation structure and the isolation layer 13, thereby being able to prepare a high-quality semiconductor structure. Figure 6 As shown, the shallow trench isolation structure prepared by the HDP Fill+HDP CMP Stopon OX process is uniformly filled with an insulating material, and the end of the shallow trench isolation structure and the OX layer have high flatness.

[0111] S107. Form a polysilicon resistance layer at an end of the shallow trench isolation structure close to the first surface; the polysilicon resistance layer is electrically connected to the active area.

[0112] In this embodiment, the FSI loop process can be simplified by removing the Dep SIN and OX processes in the original FSI loop process, and directly forming the polysilicon resistance layer 111 at the end of the shallow trench isolation structure 12 close to the first surface 1101. In the FSI loop process, the "end of the shallow trench isolation structure close to the first surface 1101" may refer to the top of the shallow trench isolation structure.

[0113] Exemplarily, the polysilicon resistor layer 111 may be referred to as a poly resistor layer, which may be used as a quenching resistor, which is a unique resistor type in CMOS. The polysilicon resistor layer 111 may be electrically connected to the active area, specifically to the photodiode in the active area.

[0114] Optionally, the top view shape of the polysilicon resistor layer may be a conventional shape such as a strip, an S shape, a spiral shape, etc. In the embodiment of the present application, the top view shape of the polysilicon resistor layer is a strip.

[0115] The above-mentioned process of forming the polysilicon resistance layer can be referred to as "Poly Dep". The embodiment of the present application can use a variety of methods to form the polysilicon resistance layer 111 at the end of the shallow trench isolation structure 12 close to the first surface 1101, which is not specifically limited here.

[0116] In one embodiment, the above-mentioned Poly Dep may be:

[0117] Figure 7 FIG. 1 is a schematic diagram of a cross-sectional structure obtained by a FSI loop process according to an exemplary embodiment. Figure 7 As shown, a semiconductor tool can be used to form an isolation layer 13 on the first surface 1101 of the substrate 11, a polysilicon film is formed on the surface of the isolation layer 13 away from the first surface 1101 (including the end of the shallow trench isolation structure close to the first surface 1101), and the polysilicon film is ion doped. The polysilicon film is etched to form a strip-shaped polysilicon resistor layer 111. A nitride shielding layer 112 (for example, the nitride shielding layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride) is formed on the surface of the polysilicon resistor layer 111 away from the isolation layer 13 and the surface of the isolation layer 13 away from the first surface 1101. The nitride shielding layer is used to protect the surface of the polysilicon resistor layer 111, so that the surface of the covered polysilicon resistor layer 111 will not form undesirable metal silicide. A dielectric layer 113 (eg, OX layer) is formed on the surface of the nitride shielding layer away from the polysilicon resistor layer 111, and a conductive plug is formed in the dielectric layer 113. The polysilicon resistor layer 111 is connected to other circuits, for example, electrically connected to a single photon avalanche diode, by using the conductive plug.

[0118] Exemplarily, the process of forming the polysilicon film may include: using a low pressure chemical vapor deposition process (LPCVD) to form a polysilicon film on the surface of the isolation layer 13 away from the first surface 1101 (including the end of the shallow trench isolation structure close to the first surface 1101), the polysilicon film is doped with N-type or P-type impurity ions, the N-type impurity ions are one or more of boron, gallium, and indium, and the P-type impurity ions are one or more of phosphorus, arsenic, and antimony.

[0119] Exemplarily, the specific process of forming the polysilicon resistor may include: forming a photoresist layer (not shown) on the surface of the polysilicon film, and exposing and developing the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, etching the polysilicon film to form a polysilicon resistor layer 111 at the end of the shallow trench isolation structure 12 close to the first surface 1101. In the embodiment of the present application, the polysilicon resistor layer 111 is completely located on the surface of the isolation layer 13, so that the polysilicon resistor layer is electrically isolated from the substrate 11, and no short circuit occurs.

[0120] In another embodiment, there are at least two shallow trench isolation structures, and the above-mentioned Poly Dep can be: depositing the polysilicon resistance layer on the end of the target shallow trench isolation structure close to the first surface; the target shallow trench isolation structure is two adjacent shallow trench isolation structures after polishing.

[0121] like Figure 7 As shown, the polysilicon resistance layer 111 is directly deposited on the top of two adjacent shallow trench isolation structures 12 after polishing (i.e., the end close to the first surface 1101), and the process of removing Dep SIN and OX in the original FSI loop process is removed, which simplifies the FSI loop process flow, reduces the step height difference h between CT-AA and CT-Poly, and makes CT etch have enough process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0122] The embodiment of the present application does not limit the relationship between the size of the polysilicon resistor layer and the distance between two adjacent shallow trench isolation structures. In some embodiments, the length of the polysilicon resistor layer is greater than or equal to the distance between two adjacent shallow trench isolation structures. In other embodiments, the length of the polysilicon resistor can also be less than the distance between two adjacent shallow isolation trench structures.

[0123] S109. Form a first contact hole on the active area, and form a second contact hole on the surface of the polysilicon resistance layer away from the shallow trench isolation structure; wherein the height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, and the preset height threshold is a threshold that makes the formation process of the first contact hole and the second contact hole meet a preset process window.

[0124] In this embodiment, after the polysilicon resistance layer is obtained, other front illumination processes (other FSI processes), fusion bonding processes (FB loop), flipping processes, etc. may be performed.

[0125] Optionally, the other FSI process may include but is not limited to: a process of forming a nitride blocking layer 112 on a surface of the polysilicon resistor layer 111 away from the isolation layer 13 and on a surface of the isolation layer 13 away from the first surface 1101. A process of forming a dielectric layer 113 on a surface of the nitride blocking layer 112 away from the polysilicon resistor layer 111. A process of forming a first contact hole 114 on the active area 19, and a process of forming a second contact hole 115 on a surface of the polysilicon resistor layer 111 away from the shallow trench isolation structure 12. A process of forming a metal stack, etc.

[0126] The embodiment of the present application may form the first contact hole 114 and the second contact hole 115 in a variety of ways, which are not specifically limited here. In one embodiment, the process of forming the first contact hole 114 on the active area 19 may include: depositing a photoresist layer on the surface of the dielectric layer 113 away from the nitride blocking layer 112 by a semiconductor tool, exposing and developing the photoresist layer, defining the position of the first contact hole 114, and then using the photoresist layer as a mask. The dielectric layer 113, the nitride blocking layer 112, and the isolation layer 13 thereunder are etched in sequence, and the etching is stopped when the upper surface of the active area 19 is reached to obtain the first contact hole 114. For example, the cross-sectional shape of the first contact hole 114 may be a rectangle or an inverted trapezoid, which is not specifically limited. In one embodiment, the process of forming the second contact hole 115 on the surface of the polysilicon resistor layer 111 away from the shallow trench isolation structure 12 may include: depositing a photoresist layer on the surface of the dielectric layer 113 away from the nitride shielding layer 112 by a semiconductor tool, exposing and developing the photoresist layer, defining the position of the second contact hole 115, and then using the photoresist layer as a mask. Etching the dielectric layer 113 and the nitride shielding layer 112 thereunder, stopping when etching reaches the upper surface of the polysilicon resistor layer 111 (i.e., the surface away from the shallow trench isolation structure 12), and obtaining the second contact hole 115. For example, the cross-sectional shape of the second contact hole 115 may be a rectangle or an inverted trapezoid, which is not specifically limited.

[0127] The height difference between the height of the first contact hole 114 and the height of the second contact hole 115 is less than a preset height threshold, and the preset height threshold is a threshold that satisfies a preset process window during the formation of the first contact hole 114 and the second contact hole 115. The height difference between the height of the first contact hole 114 and the height of the second contact hole 115 can be understood as the height between the upper surface of the polysilicon resistance layer 111 (i.e., the surface away from the shallow trench isolation structure 12) and the upper surface of the active area 19 (i.e., the surface close to the first surface 1101).

[0128] The process window refers to a window used to control the size of semiconductor wafers in the photolithography process, which limits the size range that can be controlled during the photolithography process. In order to ensure the quality and performance of semiconductor wafers, a suitable process window needs to be maintained. When the process window becomes too small, the controllability of the photolithography process will be limited, which may lead to size deviation and semiconductor wafer quality problems.

[0129] In order to ensure the quality and performance of the wafer, CT etching needs to control the loss of the polysilicon resistor layer 111 and AA within a certain range. If the height difference between the first contact hole 114 and the second contact hole 115 is large, when CT etches onto the polysilicon resistor layer 111, AA has not yet been etched, which will cause poly loss. When the loss is large, AA will start to be etched. This places high requirements on the CT etching process, limits the possibility of CT etching, and thus makes the CT etching process have no preset process window. The embodiment of the present application directly deposits the polysilicon resistor layer on the top of two adjacent shallow trench isolation structures after polishing (i.e., the end close to the first surface 1101), eliminates the process of removing Dep SIN and OX in the original FSI loop process, simplifies the FSI loop process flow, reduces the step height difference between CT-AA and CT-Poly, and when CT is etched onto the polysilicon resistor layer 111, CT-AA etching can be performed in a shorter time, thereby reducing the loss of the polysilicon resistor layer 111 and AA during the CT etching process, so that the loss of the polysilicon resistor layer 111 and AA is controlled within a certain range, thereby making the CT etching process controllable, and further allowing CT etch to have a sufficient process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0130] In some embodiments, the size of the preset height threshold is proportional to the thickness of the polysilicon resistor layer 111. In an exemplary embodiment, the preset height threshold is 500 angstroms to 1000 angstroms. Since the height difference between the height of the first contact hole and the height of the second contact hole can be understood as the height between the upper surface of the polysilicon resistor layer (i.e., the surface away from the shallow trench isolation structure 12) and the upper surface of the active area (i.e., the surface close to the first surface 1101), the size of the preset height threshold is proportional to the thickness of the polysilicon resistor layer. The thicker the polysilicon resistor layer, the greater the height difference, and vice versa. Since the polysilicon resistor layer is directly deposited at the end of the shallow trench isolation groove close to the first surface 1101, and the second contact hole is formed on the polysilicon resistor layer, the height difference is mainly related to the thickness of the polysilicon resistor layer. Therefore, the size of the height threshold is set to be proportional to the thickness of the polysilicon resistor layer, and the preset height threshold is specifically set to 500 angstroms to 1000 angstroms. The accuracy of determining the size of the height threshold can be improved, so that the formation process of the first contact hole and the second contact hole can well meet the preset process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0131] The process of forming a metal stack, the fusion bonding process (FB loop), and the flipping process in the embodiment of the present application can be implemented in a variety of ways, which are not specifically limited here.

[0132] In one embodiment, after forming a first contact hole on the active area and forming a second contact hole on a surface of the polysilicon resistor layer away from the shallow trench isolation structure, the method further comprises:

[0133] A metal stack is formed at an end of the first contact hole away from the active region and an end of the second contact hole away from the polysilicon resistance layer.

[0134] The structure forming the metal stack is melt-bonded to the carrier wafer, and the bonded structure is flipped over.

[0135] Exemplarily, the metal stack may include a first metal layer, at least one low-K layer (i.e., a layer formed of a material having a low dielectric constant (K), such as SiOx or SiXNx), a second metal layer, etc. The forming of the metal stack at the end of the first contact hole away from the active region and the end of the second contact hole away from the polysilicon resistance layer may include: continuing as follows Figure 7As shown, a semiconductor processing tool (e.g., a deposition tool) may deposit a metal material (e.g., copper) on the dielectric layer 113, the first contact hole 114, and the second contact hole 115 to form a first metal layer 116. Then, the semiconductor processing tool (deposition tool) may deposit a low-K material on the first metal layer to form a low-K layer. Then, the semiconductor processing tool (e.g., a deposition tool) may deposit another metal material layer on the substrate (e.g., on the low-K layer) to form a second metal layer 117.

[0136] For example, melt bonding the semiconductor structure forming the metal stack to the carrier wafer 118 may include: Figure 7 As shown, the semiconductor processing tool can achieve the bonding effect by utilizing the Si-O-Si bond on the surface of the carrier wafer. In addition to melt bonding, the semiconductor structure forming the metal stack can also be temporarily bonded to the carrier wafer by adhesive, wherein the temperature of the temporary bonding is less than 200 degrees Celsius. By temporarily bonding the semiconductor structure forming the metal stack to the carrier wafer by adhesive, the deformation of the semiconductor structure caused by the high temperature during the melt bonding process and the high temperature during the annealing process can be avoided, thereby reducing the heat load of the semiconductor structure.

[0137] After bonding, the bonded structure can be turned over, and the upper surface of the turned structure is the second surface 1102 of the substrate 11, so that the second surface 1102 of the substrate 11 can be processed later. Figure 8 is a schematic diagram of a cross-sectional structure after flipping according to an exemplary embodiment. Figure 8 As shown, the upper surface of the flipped structure is the second surface 1102 .

[0138] Therefore, after the FSI loop and FB loop are completed, the obtained structure can be flipped to perform BSIloo p, so that the photodiode is adapted for light irradiation at the second surface 1102 without passing through the metal wiring layer, thereby reducing photon loss and improving quantum efficiency (QE, Quantum Efficiency).

[0139] S111. A deep trench isolation structure is formed in the substrate from the second surface of the substrate; wherein the second surface is opposite to the first surface, and the deep trench isolation structure and the shallow trench isolation structure are used to isolate adjacent active areas.

[0140] In an embodiment of the present application, a deep trench isolation structure 119 (DTI) located in the substrate 11 can be formed from the second surface 1102 of the substrate 11, and the second surface 1102 is a surface on the substrate 11 opposite to the first surface 1101. The deep trench isolation structure 119 is used to provide isolation for the SPAD in the active area (for example, to reduce optical crosstalk from adjacent SPADs of the semiconductor structure). The DTI structure can be formed between a pixel area and an adjacent pixel area (not shown) of the substrate. In some implementations, the DTI structure may include a reflective material so that the DTI component blocks light from an adjacent pixel area of ​​the semiconductor structure and / or directs light in the pixel area back toward the SPAD. In some implementations, the reflective material can be a reflective metal or a multilayer oxide structure with different refractive indices (for example, to form a total internal reflection structure).

[0141] In one embodiment, the deep trench isolation structure 119 can be formed from the upper surface of the flipped structure, wherein the upper surface of the flipped semiconductor structure is the second surface 1102. In other embodiments, the semiconductor processing tool can also form a deep trench isolation structure located in the substrate 11 from the second surface 1102 of the substrate 11 by an appropriate process without flipping, and flip the structure after forming the deep trench isolation structure.

[0142] The process of forming the deep trench isolation structure from the upper surface of the flipped structure may be referred to as “DTIPH and ET”, which may include:

[0143] Fig. 9 FIG. 1 is a schematic cross-sectional structure diagram of forming a deep trench isolation structure according to an exemplary embodiment. Fig. 9As shown, a photoresist layer having a deep trench isolation structure pattern is formed on the upper surface (i.e., the second surface 1102) of the flipped semiconductor structure; the size of the deep trench isolation structure 119 is defined in the photoresist layer; the substrate 11 is etched in the direction of the shallow trench isolation structure using the deep trench isolation structure pattern as a mask, and the etching is stopped when the end of the shallow trench isolation structure 12 is away from the polysilicon resistor layer 111, thereby forming the deep trench isolation structure 119. That is, the end of the deep trench isolation structure 119 away from the second surface 1101 is in contact with the end of the shallow trench isolation structure 12 away from the polysilicon resistor layer 111. Optionally, "in contact" may mean that: the deep trench isolation structure is located between two adjacent shallow trench isolation structures, and the end of the deep trench isolation structure away from the second surface is in contact with the ends of the two adjacent shallow trench isolation structures away from the polysilicon resistor layer. As an example, the end of the deep trench isolation structure 119 away from the second surface 1101 intersects with the ends of the two adjacent shallow trench isolation structures 12 away from the polysilicon resistance layer 111 in the substrate 11. Or, as another example: the sidewall of the end of the deep trench isolation structure 119 away from the second surface 1101 contacts with the sidewall of the ends of the two adjacent shallow trench isolation structures 12 away from the polysilicon resistance layer 111 in the substrate 11.

[0144] In some implementations, a deposition tool may form a photoresist layer on the second surface 1102 of the substrate 11, wherein the size of the deep trench isolation structure is defined in the photoresist layer. An exposure tool may expose the photoresist layer to a radiation source to pattern the photoresist layer, a developer tool may develop and remove several portions of the photoresist layer to expose the pattern, and an etching tool may etch the substrate 11 to a preset depth from the second surface 1102 in the direction where the shallow trench isolation structure is located, and stop when etching reaches the end of the shallow trench isolation structure 12 away from the polysilicon resistor layer 111, so that the end of the deep trench isolation structure 119 away from the second surface 1102 contacts the end of the shallow trench isolation structure 12 away from the polysilicon resistor layer 111, and obtain one or more portions to form one or more DTIs. In some implementations, a photoresist removal tool removes the remaining portion of the photoresist layer after the etching tool etches the substrate 11.

[0145] Thus, the flipped structure can be subjected to DTIPH and ET to obtain DTI that provides isolation for the SPAD, thereby reducing the optical crosstalk from adjacent SPADs of the semiconductor structure, thereby reducing the problem of electrical crosstalk between devices; in addition, the deep trench isolation structure and the shallow trench isolation structure are in contact with each other at the end away from the polysilicon resistance layer, and the devices can be effectively isolated through the joint action of the deep trench isolation structure and the shallow trench isolation structure, thereby effectively solving the problem of electrical crosstalk between devices.

[0146] In actual applications, in order to meet the design requirements of the BSI SIPM sensor, high voltage is usually applied between Poly and DTI. In order to make the gap between Poly and DTI resist high voltage, the substrate 11 can be prevented from being etched through during the DTIPH and ET processes, that is, a certain thickness of Si is retained at the bottom of DTI. In addition, a certain thickness of Si at the bottom of DTI can also ensure that the Poly and DTI can be electrically isolated at high potential. In some embodiments, continue as Fig. 9 As shown, the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101 (as shown in FIG. Fig. 9 The end of the deep trench isolation structure away from the second surface 1102 can be understood as the bottom of the DTI.

[0147] It should be noted that the embodiment of the present application does not limit the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101, which can be set according to actual business needs. Taking the material of the semiconductor substrate as Si as an example, usually the intrinsic Si with a thickness of about 100nm can withstand a voltage of 3V. Based on this characteristic and combined with the actual high-voltage resistance requirements, the thickness of Si retained at the bottom of the DTI can be set. In some embodiments, the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101 is 0.5um to 2um. That is, 0.5um to 2um thick silicon is retained at the bottom of the DTI. The 0.5um to 2um silicon enables the poly and DTI to withstand high voltage, and can better achieve electrical isolation between Poly and DTI at high potential. Therefore, when an operating voltage is applied between Poly and DTI, the voltage can be blocked by a certain thickness of silicon retained between the deep trench isolation structure and the first surface of the substrate, thereby achieving better electrical isolation between Poly and DTI, ensuring that the thin film between Poly and DTI will not be broken down under high voltage, solving the leakage problem of the semiconductor device at high operating voltage (for example, an operating voltage exceeding 40V), and enabling the semiconductor device to meet the requirements of the automotive three-dimensional range imaging system for higher gain performance of the image sensor.

[0148] In some embodiments, in order to enable the HDP deposited in the shallow trench isolation structure to perfectly contact the DTI of the BSI, so that the end of the deep trench isolation structure finally obtained is away from the second surface, and can perfectly contact the end of the shallow trench isolation structure away from the polysilicon resistance layer, and then the devices can be effectively isolated through the joint action of the deep trench isolation structure and the shallow trench isolation structure, and the electrical crosstalk problem between devices can be effectively solved, the deep trench isolation structure can be set to at least two, at least two deep trench isolation structures are set in the surrounding area of ​​​​the DTI, and the distance between two adjacent deep trench isolation structures is less than or equal to the width of the deep trench isolation structure.

[0149] In an optional embodiment, after DTIPH and ET, W dep and W CMP processes may be performed. W refers to a metal dock, W dep refers to a deposition dock, and W CMP refers to dock polishing using chemical mechanical polishing. The W dep and W CMP processes are described below: Fig.10 FIG. 1 is a schematic diagram of a cross-sectional structure of a deposition dock after the dock is polished by chemical mechanical polishing according to an exemplary embodiment. Fig.10 As shown, the deposition tool can use chemical vapor deposition to fill one or more DTIs with optical isolation material 120 (e.g., W), and the planarization tool can use W CMP technology to remove excess material. Depositing W in the DTI can block the photomask and prevent optical crosstalk between adjacent SPADs. In other embodiments, the optical isolation material can also be: an oxide material such as silicon oxide (SiOx) or another type of dielectric material.

[0150] In another optional embodiment, after the W dep and W CMP processes, AL dep and other BSI processes may be performed. Exemplarily, AL dep may include: Fig.11 FIG. 1 is a schematic diagram of a cross-sectional structure of a deposition dock after the dock is polished by chemical mechanical polishing according to an exemplary embodiment. Fig.11 As shown, metal aluminum is filled on the deposited metal W in the isolation groove to form a metal aluminum layer 121; the metal aluminum layer 121 is exposed and patterned etched to form an aluminum pad; a through silicon via is formed on the second surface 1102 to expose the tungsten metal layer; and the metal W is connected to the aluminum pad.

[0151] Exemplarily, the other BSI process may include forming a metal grid structure on the second surface 1102, forming a high-K dielectric layer (HK layer), forming a filter on the second surface 1102, and the like. It should be noted that the embodiments of the present application do not limit the specific process of the other BSI process. In some implementations, the filter (e.g., a membrane or a thin film) filters the incident light to allow incident light of a specific wavelength to pass through to the SPAD (and block other wavelengths from passing through). In some implementations, the thickness of the filter may be designed to control (e.g., extend) the integration time (e.g., total integration time) of the SPAD. In some implementations, the filter may include, for example, titanium or titanium nitride. In some implementations, the thickness of the filter may vary between SPADs of the semiconductor structure. In some implementations, a semiconductor processing tool (e.g., a deposition tool) may use chemical vapor deposition (CVD) technology, physical vapor deposition (PVD) technology, atomic layer deposition (ALD) technology, or another type of deposition technology to deposit the filter.

[0152] In other embodiments, in order to increase the amount of light entering the semiconductor structure, thereby improving the photoelectron detection efficiency (PDE), the method for forming the semiconductor structure may further include: forming a light-limiting groove (not shown) on the second surface 1102; wherein the light-limiting groove is used to adjust the amount of light irradiated to the second surface 1102. The specific forming process of the light-limiting groove may be: a deposition tool may form a photoresist layer on the second surface 1102 of the substrate 11, wherein the size of the limited light groove is defined in the photoresist layer. An exposure tool may expose the photoresist layer to a radiation source to pattern the photoresist layer, a developer tool may develop and remove several portions of the photoresist layer to expose the pattern, and an etching tool may etch the substrate 11 from the second surface 1102 to obtain the light-limiting groove. In some implementations, the photoresist removal tool removes the remaining portion of the photoresist layer after the etching tool etches the substrate 11.

[0153] It should be noted that the forming process of the light limiting groove can be before forming DFI. When depositing W to DTI, in order to prevent W from filling into the light limiting groove and affecting PDE, an oxide layer can be pre-attached to the bottom and sidewalls of the light limiting groove and DTI.

[0154] The embodiment of the present application does not limit the shape and size of the light-limiting groove, and the cross-sectional shape of the light-limiting groove may be an inverted triangle, an ellipse, an inverted trapezoid, etc.

[0155] The following is an overall description of the method for forming the semiconductor structure:

[0156] 1) Provide a substrate 11.

[0157] 2) Retooling Zero mask: In addition to the original zero mark, zero patterns are added in the main chip area. These patterns are distributed around the BSI loop DTI pattern.

[0158] 3) Zero PH&ET: An isolation layer 13 is formed on the first surface 1101 of the substrate 11, and a zero-layer mask layer is formed on the isolation layer; the isolation layer and a portion of the substrate 11 are sequentially etched using the zero-layer mask layer as a mask to form the shallow trench isolation structure 12 in the substrate 11 and a zero-layer mark in the cutting path area. An active area 19 is defined according to the shallow trench isolation structure. A single-photon avalanche diode is formed in the active area.

[0159] 4) HDP Fill+HDP CMP Stop on OX: filling the shallow trench isolation structure with an insulating material by a high-density plasma method to obtain a filled shallow trench isolation structure; performing chemical mechanical polishing on the filled shallow trench isolation structure, stopping at a surface of the isolation layer away from the first surface 1101, to obtain a polished shallow trench isolation structure.

[0160] 5) Poly Dep+other FSI process+FB loop: remove the original FSI loop Dep SIN+OX, directly Dep Poly, and simplify the FSI loop process flow; form a first contact hole 114 on the active area 19, and form a second contact hole 115 on the surface of the polysilicon resistance layer 111 away from the shallow trench isolation structure 12; form a metal stack at the end of the first contact hole 114 away from the active area 19 and the end of the second contact hole 115 away from the polysilicon resistance layer 111; melt-bond the structure formed by the metal stack to the carrier wafer 118.

[0161] 6) Flip: Flip the bonded structure.

[0162] 7) DTIPH and ET: forming the deep trench isolation structure 119 from the upper surface of the flipped structure; wherein the upper surface of the flipped semiconductor structure is the second surface 1102 .

[0163] 8) W dep and W CMP: One or more DTIs are filled with optically isolating materials (eg, W) using chemical vapor deposition methods, and excess material can be removed using W CMP techniques.

[0164] 9) AL dep and other BSI process: fill metal aluminum on the deposited metal W in the isolation trench to form a metal aluminum layer; expose and pattern-etch the metal aluminum layer to form an aluminum pad; form a through silicon via on the second surface 1102 to expose the tungsten metal layer; connect the metal W to the aluminum pad. Form a metal grid structure on the first surface 1101, form a high-K dielectric layer (HK layer), and form a filter on the second surface 1102.

[0165] The present application also provides a semiconductor structure, which may include:

[0166] A substrate comprising a first surface and a second surface opposite to each other; a shallow trench isolation structure is formed in the substrate from the first surface of the substrate, and a deep trench isolation structure is formed in the substrate from the second surface of the substrate

[0167] At least two active regions are located in the substrate, and adjacent active regions are separated by the shallow trench isolation structure and the deep trench isolation structure.

[0168] A polysilicon resistance layer is formed at an end of the shallow trench isolation structure close to the first surface; the polysilicon resistance layer is electrically connected to the active area.

[0169] A first contact hole is formed on the surface of the active area, and a second contact hole is formed on the surface of the polysilicon resistance layer away from the shallow trench isolation structure; wherein the height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, and the preset height threshold is a threshold that makes the formation process of the first contact hole and the second contact hole meet a preset process window.

[0170] like Fig.11 As shown, after flipping, the second surface 1102 of the substrate 11 is located at the top, and the first surface 1101 is located at the bottom. In the BSI process, the second surface 1102 is the light-receiving surface.

[0171] Optionally, the end of the shallow trench isolation structure 12 close to the first surface 1101 may be the bottom of the shallow trench isolation structure 12 after flipping, that is, the polysilicon resistance layer 111 is located at the bottom of the shallow trench isolation structure after flipping.

[0172] Optionally, after the surface of the active region 19 is flipped, it may be below the active region, that is, after the flipping, the first contact hole 114 is located below the active region 19 .

[0173] Optionally, the polysilicon resistor layer 111 is away from the surface of the shallow trench isolation structure 12 and may be the lower surface of the polysilicon resistor layer 111 after flipping, that is, the second contact hole 115 is located at the lower surface of the polysilicon resistor layer 111 after flipping.

[0174] The semiconductor structure provided in the embodiment of the present application simplifies the FSI loop process flow by forming a shallow trench isolation structure located in the substrate from the first surface of the substrate, directly forming a polysilicon resistor layer at the end of the shallow trench isolation structure close to the first surface, forming a first contact hole on the active area, and forming a second contact hole on the surface of the polysilicon resistor layer away from the shallow trench isolation structure, so that the original silicon carbide layer and oxide layer deposited on the poly are removed from the formed semiconductor structure, the step height difference between CT-AA and CT-Poly is reduced, and CT etch has a sufficient process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0175] In some embodiments, the size of the preset height threshold is proportional to the thickness of the polysilicon resistor layer 111. In some embodiments, the preset height threshold is 500 angstroms to 1000 angstroms. Since the height difference between the height of the first contact hole and the height of the second contact hole can be understood as the height between the upper surface of the poly resistor close to the second contact hole and the upper surface of the active area close to the first contact hole, the size of the preset height threshold is proportional to the thickness of the polysilicon resistor layer. The thicker the thickness of the polysilicon resistor layer, the greater the height difference, and vice versa. Since the polysilicon resistor layer is directly deposited at the end of the shallow trench isolation groove close to the first surface, and the second contact hole is formed on the polysilicon resistor layer, the height difference is mainly related to the thickness of the polysilicon resistor layer. Therefore, setting the size of the height threshold is proportional to the thickness of the polysilicon resistor layer, and specifically setting the preset height threshold to 500 angstroms to 1000 angstroms can improve the accuracy of determining the size of the height threshold, so that the formation process of the first contact hole and the second contact hole can well meet the preset process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0176] In some embodiments, there are at least two shallow trench isolation structures, and the polysilicon resistance layer 111 is formed on ends of two adjacent shallow trench isolation structures 12 close to the first surface 1101 .

[0177] In some embodiments, the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101 is greater than 0. Since a certain thickness of Si can be retained at the bottom of the DTI, the poly and the DTI can withstand high voltage, and the substrate 11 can be prevented from being etched through during the DTIPH and ET processes; in addition, a certain thickness of Si retained at the bottom of the DTI can also ensure that the poly and the DTI can meet electrical isolation at high potential.

[0178] In some embodiments, the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101 is 0.5um to 2um. That is, 0.5um to 2um of silicon is reserved at the bottom of the DTI, and the 0.5um to 2um of silicon enables the poly and the DTI to withstand high voltage and can better achieve electrical isolation between the poly and the DTI at high potential.

[0179] In some embodiments, the deep trench isolation structure 119 extends to the shallow trench isolation structure 12, and the end of the deep trench isolation structure 12 away from the second surface 1102 contacts the end of the shallow trench isolation structure 12 away from the polysilicon resistance layer 111. After flipping, the "end of the deep trench isolation structure away from the second surface" is the bottom of the DTI, and the "end of the shallow trench isolation structure away from the polysilicon resistance layer" is the top of the shallow trench isolation structure, that is, the bottom of the DTI extends to the shallow trench isolation structure, and the bottom of the DTI contacts the top of the shallow trench isolation structure. Thus, the devices can be effectively isolated through the joint action of the deep trench isolation structure and the shallow trench isolation structure, and the problem of electrical crosstalk between devices can be effectively solved.

[0180] In some embodiments, there are at least two shallow trench isolation structures 12, and the shallow trench isolation structures 12 are distributed in the surrounding area of ​​the deep trench isolation structure 119. In some embodiments, the deep trench isolation structure is located between two adjacent shallow trench isolation structures, and the end of the deep trench isolation structure away from the second surface is in contact with the ends of the two adjacent shallow trench isolation structures away from the polysilicon resistance layer, and the distance between the two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure. As a result, the HDP deposited in the shallow trench isolation structure can perfectly contact the DTI of the BSI, so that the end of the deep trench isolation structure obtained is away from the second surface, and can perfectly contact the end of the shallow trench isolation structure away from the polysilicon resistance layer, and then the devices can be effectively isolated through the joint action of the deep trench isolation structure and the shallow trench isolation structure, effectively solving the problem of electrical crosstalk between devices.

[0181] In some embodiments, the semiconductor structure further includes a light-limiting groove located on the second surface 1102, and the light-limiting groove is used to adjust the amount of light irradiated to the second surface 1102. In some embodiments, the light-limiting groove is an inverted triangle structure. By providing the light-limiting groove, the amount of light entering the semiconductor structure can be increased, thereby improving the photoelectron detection efficiency (PDE).

[0182] In some embodiments, the semiconductor structure may further include: a nitride shielding layer 112 (for example, the nitride shielding layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride) located on the surface of the polysilicon resistor layer and the surface away from the isolation layer and the surface of the isolation layer away from the first surface, the nitride shielding layer is used to protect the surface of the polysilicon resistor layer so that the covered polysilicon resistor surface will not form undesirable metal silicide. A dielectric layer 113 (for example, an OX layer) located on the surface of the nitride shielding layer away from the polysilicon resistor layer.

[0183] In some embodiments, the semiconductor structure may further include: a metal stack layer located on a surface of the dielectric layer (e.g., OX layer) away from the nitride blocking layer. The metal stack may include a first metal layer, at least one low-K layer (i.e., a material with a low dielectric constant (K), such as SiO x or Si x N x formed layer), a second metal layer, etc.

[0184] In some embodiments, the semiconductor structure may further include: a carrier wafer 118 located on a surface of the metal stack layer away from the dielectric layer (eg, OX layer).

[0185] In some embodiments, the semiconductor structure may further include: a metal grid structure located on the second surface 1102 , a high-K dielectric layer (HK layer), an optical filter, and the like.

[0186] It should be noted that the embodiment of the semiconductor structure has the same inventive concept as the embodiment of the method for forming the semiconductor structure described above.

[0187] In an exemplary embodiment, an electronic device is also provided. The electronic device includes the semiconductor structure described above. The electronic device may include any electronic components such as MOS devices, non-MOS devices, other integrated circuits, electronic devices, etc.

[0188] The electronic device of this embodiment can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a laptop computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a handheld game console (PlayStation Portable, PSP), etc., and can also be any intermediate product including the above-mentioned semiconductor device.

[0189] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0190] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate comprising opposing first and second surfaces; forming a shallow trench isolation structure located in the substrate from a first surface of the substrate, and forming a deep trench isolation structure located in the substrate from a second surface of the substrate; at least two active regions located in the substrate, adjacent active regions being separated by the shallow trench isolation structure and the deep trench isolation structure; A polysilicon resistor layer is formed at an end of the shallow trench isolation structure close to the first surface; the polysilicon resistor layer is electrically connected to the active area; A first contact hole is formed on the surface of the active area, and a second contact hole is formed on the surface of the polysilicon resistance layer away from the shallow trench isolation structure; wherein the height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, and the preset height threshold is a threshold that makes the formation process of the first contact hole and the second contact hole meet a preset process window.

2. The semiconductor structure according to claim 1, characterized in that: The size of the preset height threshold is proportional to the thickness of the polysilicon resistance layer.

3. The semiconductor structure according to claim 1, characterized in that: The preset height threshold is 500 angstroms to 1000 angstroms.

4. The semiconductor structure according to claim 1, characterized in that: There are at least two shallow trench isolation structures, and the polysilicon resistance layer is formed on ends of two adjacent shallow trench isolation structures close to the first surface.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: A distance between an end of the deep trench isolation structure away from the second surface and the first surface is greater than zero.

6. The semiconductor structure according to claim 5, characterized in that: The distance between the end of the deep trench isolation structure away from the second surface and the first surface is 0.5 um to 2 um.

7. The semiconductor structure according to claim 5, characterized in that: The deep trench isolation structure extends to the shallow trench isolation structure, and an end of the deep trench isolation structure away from the second surface contacts an end of the shallow trench isolation structure away from the polysilicon resistance layer.

8. The semiconductor structure according to claim 7, characterized in that: There are at least two shallow trench isolation structures, and the shallow trench isolation structures are distributed in the surrounding areas of the deep trench isolation structure.

9. The semiconductor structure according to claim 8, characterized in that: The deep trench isolation structure is located between two adjacent shallow trench isolation structures, and the end of the deep trench isolation structure away from the second surface is in contact with the ends of two adjacent shallow trench isolation structures away from the polysilicon resistance layer, and the distance between the two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

10. The semiconductor structure according to claim 5, characterized in that: The semiconductor structure further includes a light-limiting groove located on the second surface, and the light-limiting groove is used to adjust the amount of light irradiated to the second surface.

11. The semiconductor structure according to claim 10, characterized in that: The light-limiting groove is an inverted triangle structure.

12. A method for forming a semiconductor structure, characterized in that: The forming method comprises: Providing a substrate; the substrate comprising a first surface and a second surface opposite to each other; forming a shallow trench isolation structure in the substrate from a first surface of the substrate; forming at least two active regions in the substrate; A polysilicon resistance layer is formed at an end of the shallow trench isolation structure close to the first surface; the polysilicon resistance layer is electrically connected to the active area; A first contact hole is formed on the active area, and a second contact hole is formed on a surface of the polysilicon resistor layer away from the shallow trench isolation structure; wherein a height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, and the preset height threshold is a threshold value that enables the formation process of the first contact hole and the second contact hole to meet a preset process window; A deep trench isolation structure is formed in the substrate from the second surface of the substrate; the deep trench isolation structure and the shallow trench isolation structure are used to isolate adjacent active areas.

13. The method for forming a semiconductor structure according to claim 12, wherein: The forming of a shallow trench isolation structure located in the substrate from the first surface of the substrate comprises: An isolation layer is formed on the first surface of the substrate, and a zero-layer mask layer is formed on the isolation layer; the zero-layer mask layer is recombined with a zero-layer mark pattern and a first-layer main chip area pattern; the first-layer main chip area pattern defines the size of the shallow trench isolation structure, and defines the positional relationship between the shallow trench isolation structure and the deep trench isolation structure; Using the zero-layer mask layer as a mask, the isolation layer and part of the substrate are etched in sequence to form the shallow trench isolation structure in the substrate and a zero-layer mark in the cutting path area; the end of the deep trench isolation structure away from the second surface is in contact with the end of the shallow trench isolation structure away from the polysilicon resistance layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: There are at least two shallow trench isolation structures, and the deep trench isolation structure is located between two adjacent shallow trench isolation structures. The end of the deep trench isolation structure away from the second surface is in contact with the ends of two adjacent shallow trench isolation structures away from the polysilicon resistance layer, and the distance between the two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

15. The method for forming a semiconductor structure according to claim 13, wherein: After forming a shallow trench isolation structure in the substrate from the first surface of the substrate, the method further includes: Filling an insulating material in the shallow trench isolation structure by a high-density plasma method to obtain a filled shallow trench isolation structure; The filled shallow trench isolation structure is subjected to chemical mechanical polishing, and the polishing is stopped at a surface of the isolation layer away from the first surface, so as to obtain a shallow trench isolation structure after the polishing.

16. The method for forming a semiconductor structure according to claim 15, characterized in that: There are at least two shallow trench isolation structures, and a polysilicon resistance layer is formed at the end of the shallow trench isolation structure close to the first surface, including: depositing the polysilicon resistance layer on the end of the target shallow trench isolation structure close to the first surface; the target shallow trench isolation structure is two adjacent shallow trench isolation structures after polishing.

17. The method for forming a semiconductor structure according to claim 12, wherein: After forming a first contact hole on the active area and forming a second contact hole on a surface of the polysilicon resistor layer away from the shallow trench isolation structure, the method further includes: forming a metal stack at an end of the first contact hole away from the active area and an end of the second contact hole away from the polysilicon resistance layer; Melt-bonding the structure forming the metal stack to the carrier wafer, and flipping the bonded structure; The step of forming a deep trench isolation structure in the substrate from the second surface of the substrate comprises: The deep trench isolation structure is formed from the upper surface of the flipped structure; wherein the upper surface of the flipped semiconductor structure is the second surface.

18. The method for forming a semiconductor structure according to claim 17, wherein: The forming of the deep trench isolation structure from the upper surface of the flipped structure comprises: forming a photoresist layer having a deep trench isolation structure pattern on the upper surface of the flipped semiconductor structure; the photoresist layer defines the size of the deep trench isolation structure; The substrate is etched in the direction of the shallow trench isolation structure using the deep trench isolation structure pattern as a mask, and the etching is stopped when the end of the shallow trench isolation structure away from the polysilicon resistance layer is reached to form the deep trench isolation structure.

19. The method for forming a semiconductor structure according to claim 12, wherein: A distance between an end of the deep trench isolation structure away from the second surface and the first surface is greater than zero.

20. The method for forming a semiconductor structure according to claim 19, wherein: The distance between the end of the deep trench isolation structure away from the second surface and the first surface is 0.5 um to 2 um.

21. The method for forming a semiconductor structure according to claim 12, wherein: The size of the preset height threshold is proportional to the thickness of the polysilicon resistance layer.

22. The method for forming a semiconductor structure according to claim 21, characterized in that: The preset height threshold is 500 angstroms to 1000 angstroms.

23. The method for forming a semiconductor structure according to claim 12, wherein: The method further comprises: A light-limiting groove is formed on the second surface, wherein the light-limiting groove is used to adjust the amount of light irradiated to the second surface.

24. An electronic device, characterized in that: The electronic device comprises the semiconductor structure as described in any one of claims 1-11.

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