Solid state storage device and instruction acquisition method thereof
By designing the instruction acquisition and execution mechanism of controller and cache in solid-state storage devices, the problem of low access instruction acquisition efficiency caused by limited hardware resources of traditional solid-state storage devices is solved, and the write or read efficiency is improved.
Patent Information
- Application Number
- CN202311121986.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-01
- Publication Date
- 2025-03-04
AI Technical Summary
Due to limited hardware resources, traditional solid-state storage devices are difficult to continuously retrieve access instructions from the host side, resulting in the cache being occupied by retrieved but not yet executed instructions, reducing the write or read efficiency.
A solid state storage device is designed, including a controller, a cache, a volatile memory and a non-volatile memory. By storing the access instructions retrieved from the host in the first area of the cache, backing it up in volatile memory, the backup instructions are finally stored in the second area of the cache and executed.
It realizes that the solid-state storage device can continuously retrieve access instructions from the host side, avoid cache occupancy issues, and improve write or read efficiency.
Smart Images
Figure CN119556844A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a solid-state storage device, and in particular to a solid-state storage device and an instruction acquisition method thereof. Background Art
[0002] Solid state storage devices use non-volatile memory to store data. With the development of technology, they have been widely used in different computer systems. However, due to the characteristics of non-volatile memory, the number of times data is read and written to the non-volatile memory is closely related to the service life of the non-volatile memory. When the host wants to send a large number of access instructions to a traditional solid state storage device, the traditional solid state storage device is often unable to continuously capture access instructions from the host due to its limited hardware resources, and it is easy to cause the cache of the solid state storage device to be occupied by access instructions that have been captured but not yet executed, thereby reducing the write or read performance of the solid state storage device. Summary of the invention
[0003] Therefore, the present invention provides a solid-state storage device and an instruction fetching method thereof to solve the above-mentioned problems.
[0004] In one embodiment, the present invention provides a solid-state storage device configured to be electrically connected to a host. The solid-state storage device includes: a controller; a cache electrically connected to the controller, wherein the cache includes a first area and a second area; a volatile memory electrically connected to the controller; and a non-volatile memory electrically connected to the controller. The controller is configured to retrieve access instructions from the host and store the access instructions in the first area. The controller is configured to back up the access instructions stored in the first area in the volatile memory. The controller is configured to store the access instructions backed up in the volatile memory in the second area and execute the access instructions stored in the second area.
[0005] In another embodiment, the present invention further provides an instruction capture method for a solid-state storage device, the solid-state storage device is electrically connected to a host, and the solid-state storage device includes a controller, a cache, a volatile memory, and a non-volatile memory. The method includes: using the controller to capture access instructions from the host, and storing the access instructions in a first area of the cache; using the controller to back up the access instructions stored in the first area in the volatile memory; and using the controller to store the access instructions backed up in the volatile memory in the second area, and executing the access instructions stored in the second area. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention.
[0007] Figure 2A FIG. 4 is a schematic diagram of a cache according to an embodiment of the present invention.
[0008] Figures 2B to 2D According to the present invention Figure 2A Schematic diagram of a cache usage scenario of an embodiment.
[0009] Figure 3A FIG. 4 is a schematic diagram of a cache memory according to another embodiment of the present invention.
[0010] Figure 3B-3C According to the present invention Figure 3A A schematic diagram of a usage scenario of a cache in an embodiment.
[0011] Figure 4 FIG. 4 is a schematic diagram of a command fetching and command executing process of a solid-state storage device according to an embodiment of the present invention.
[0012] Figure 5 Flow chart of a method for fetching instructions for a solid-state storage device according to an embodiment of the present invention.
[0013] Figure 6 FIG. 4 is a schematic diagram of a cache in yet another embodiment of the present invention. DETAILED DESCRIPTION
[0014] The following description is a preferred implementation of the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the following claims.
[0015] It must be understood that the words "comprise", "include" and the like used in this specification are intended to indicate the existence of specific technical features, values, method steps, operation processing and / or components, but do not exclude the addition of more technical features, values, method steps, operation processing, components, or any combination of the above.
[0016] The words "first", "second", "third", etc. used in the claims are used to modify the components in the claims and are not used to indicate a priority order, a prior relationship, or that one component precedes another component, or a temporal sequence in executing method steps. They are only used to distinguish components with the same name.
[0017] The term "configured to" may describe or claim that various units, circuits, or other components are "configured to" perform a task or tasks. In such contexts, the term "configured to" is used to imply structure by indicating that the units / circuits / components include structure (e.g., circuitry) that performs those task(s) during operation. Thus, even when a given unit / circuit / component is not currently operating (e.g., not turned on), the unit / circuit / component may still be said to be configured to perform the task. The units / circuit / components used with the term "configured to" include hardware - e.g., circuits, memory (storing program instructions executable to perform operations), etc. In addition, "configured to" may include generic structures (e.g., generic circuitry) that are manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the task(s) to be solved. "Configured to" may also include adapting a manufacturing process (eg, a semiconductor manufacturing facility) to produce devices (eg, integrated circuits) adapted to perform or execute one or more tasks.
[0018] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention.
[0019] like Figure 1 As shown, the computer system 1 includes a solid-state storage device 10 and a host 20, wherein the solid-state storage device 10 is electrically connected to the host 20 via a bus 11 to perform command and data transmission. In some embodiments, the bus 11 can be a Universal Serial Bus (USB), a Serial Advanced Technology Attachment (SATA) bus, a Peripheral Component Interconnect Express (PCI Express, PCIe) bus, etc., but the present disclosure is not limited thereto.
[0020] The solid-state storage device 10 includes a controller 102, a cache 104, a volatile memory 106, and a non-volatile memory 108. The controller 102 is electrically connected to the cache 104, the volatile memory 106, and the non-volatile memory 108, and is used to control data access to the cache 104, the volatile memory 106, and the non-volatile memory 108. In some embodiments, the controller 102 may be, for example, a general-purpose processor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc., but the present disclosure is not limited thereto.
[0021] The cache 104 includes, for example, a static random access memory (SRAM). The volatile memory 106 includes, for example, a dynamic random access memory (DRAM), but the present disclosure is not limited thereto. In some embodiments, the cache 104 and the volatile memory 106 may be disposed outside the controller 102. In other embodiments, the cache 104 and the volatile memory 106 may be integrated into the controller 102. The non-volatile memory 108 may be, for example, a NAND flash memory for storing write data provided by the host 20.
[0022] The host 20 includes, for example, a processor 202 and a system memory 204, and the processor 202 is electrically connected to the system memory 204. In some embodiments, the processor 202 includes, for example, a central processing unit (CPU), a general purpose processor, a microprocessor, etc., but the disclosure is not limited thereto. In addition, the processor 202 includes a controller (not shown) for controlling data access to the system memory 204. The system memory 204 includes, for example, a dynamic random access memory, but the disclosure is not limited thereto.
[0023] In some embodiments, the host 20 may support the non-volatile memory communication protocol (NVM Express, NVMe), and the system memory 204 is configured with a submission queue 2041, a completion queue 2042, and a data buffer 2043. The submission queue 2041 is used to record the access instructions issued by the processor 202, and the completion queue 2042 is used to record the status of the solid-state storage device 10 responding to the completed access instructions. The data buffer 2043 is used to store the data that the host 20 wants to write to the solid-state storage device 10 and to store the data read by the host 20 from the solid-state storage device 10.
[0024] In some embodiments, the solid-state storage device 10 may support, for example, a non-volatile memory communication protocol (NVM Express, NVMe), and the controller 102 may retrieve access instructions, such as write instructions, read instructions, etc., from the commit queue 2041 of the host 20 and store the retrieved access instructions in the cache 104.
[0025] The non-volatile memory 108 includes a plurality of blocks, and each block includes a plurality of pages. For example, the non-volatile memory 108 includes 1024 blocks, and each block includes 64 pages. Assuming that the capacity of each page is 16Kbytes, the capacity of each block is 1Mbyte. The above data is only for illustration, and the manufacturer of the non-volatile memory 108 can determine the number of pages in each block and the capacity of each page.
[0026] Figure 2A FIG. 4 is a schematic diagram of a cache according to an embodiment of the present invention. Figures 2B to 2D According to the present invention Figure 2A Schematic diagram of a cache usage scenario of an embodiment.
[0027] In some embodiments, compared to the number of access instructions that can be stored in the commit queue 2041 of the host 20 (up to 64K), because the capacity of the cache 104 of the solid-state storage device 10 is usually limited, the number of access instructions that can be stored in the cache 104 is also quite limited. In some embodiments, the cache 104 includes 256 entries S0-S255, and each entry S0-S255 has a corresponding mask bit MB0-MB255. The controller 102 determines whether to store the access instruction captured from the commit queue 2041 of the host 20 in the empty entry S0-S255 according to the value of each mask bit MB0-M255. It should be noted that the number of entries in the cache 104 can be changed depending on the actual capacity of the cache 104, and the 256 entries in the above embodiment are only for illustration, but the present invention is not limited thereto.
[0028] For example, the access instruction size of the NVMe standard is fixed to 64 bytes, and the size of each item in the submission queue 2041 also conforms to this fixed instruction size. In addition, the size of each item in the cache 104 also conforms to this fixed instruction size.
[0029] In some embodiments, if the value of the mask bit corresponding to a specific item is 0, it indicates that the specific item is an empty item. Therefore, the controller 102 can store an access instruction captured from the submit queue 2041 of the host 20 to the specific item. If the value of the mask bit corresponding to the specific item is 1, it indicates that the specific item is occupied or masked. Therefore, when the controller 102 captures an access instruction from the submit queue 2041 of the host 20, the controller 102 will not store the captured access instruction in the specific item.
[0030] In some embodiments, when the solid-state storage device 10 is powered on, each entry S0-S255 in the cache 104 is an empty entry, and the value of the mask bit corresponding to each entry S0-S255 is 0. Figure 2B When the controller 102 captures one or more access instructions from the commit queue 2041 of the host 20, the controller 102 writes the captured one or more access instructions into the empty items in the cache 104 one by one. For example, the controller 102 writes the captured access instructions CMD0-CMD2 into items S0, S1 and S2 starting from item S0, and modifies the values of the corresponding mask bits MB0, MB1 and MB2 of items S0, S1 and S2 to 1, as shown in FIG. Figure 2CWhen the number of access instructions captured by the controller 102 from the commit queue 2041 of the host 20 is sufficient, all items S0-S255 in the cache 104 will store an access instruction (e.g., access instructions CMD0-CMD255), and the value of the corresponding mask bit of each item S0-S255 will be modified to 1, as shown in FIG. Figure 2D shown.
[0031] However, when Figure 2D When the situation occurs, it means that all entries in the cache 104 are occupied, so the controller 102 can no longer retrieve access instructions from the commit queue 2041 of the host 20. In addition, not all entries S0-S255 in the cache 104 are used to temporarily store access instructions, and some entries are used in the command execution stage and the command completion stage. Therefore, the number of entries in the cache 104 that can be used to temporarily store access instructions is less than 256.
[0032] Figure 3A FIG. 4 is a schematic diagram of a cache memory according to another embodiment of the present invention. Figure 3B-3C According to the present invention Figure 3A A schematic diagram of a usage scenario of a cache in an embodiment.
[0033] In some embodiments, the cache 104 can be divided into an instruction capture area 310 and an instruction execution area 320. The instruction capture area 310 is used to store access instructions captured by the controller 102 from the commit queue 2041 of the host 20. The instruction execution area 320 is used to store one or more access instructions executed by the controller 102 during the instruction execution stage, and the instruction execution area 320 can also be regarded as the commit queue of the solid-state storage device 10. In detail, when the solid-state storage device 10 is turned on, a first part of the 256 items S0-S255 in the cache 104 will be configured by the controller 102 as the instruction capture area 310, and a second part will be configured by the controller 102 as the instruction execution area 320. The number of items in the instruction capture area 310 and the instruction execution area 320 can be adjusted according to actual conditions.
[0034] Specifically, when the solid-state storage device 10 is powered on, each item in the instruction capture area 310 and the instruction execution area 320 is an empty item, and the controller 102 initializes the value of the mask bit corresponding to each item in the instruction capture area 310 to 0 (e.g., a first value), and initializes the value of the mask bit corresponding to each item in the instruction execution area 320 to 1 (e.g., a second value). Figure 3AAs shown. After the values of the mask bits corresponding to the items in the instruction execution area 320 are initialized, the controller 102 will no longer modify the values of the mask bits corresponding to any item in the instruction execution area 320. That is, the values of the mask bits corresponding to the items in the instruction execution area 320 will remain at 1. Therefore, when the controller 102 retrieves access instructions from the commit queue 2041 of the host 20, the controller 102 will not store the retrieved access instructions in the instruction execution area 320.
[0035] When the controller 102 captures one or more access instructions (e.g., access instructions CMD0, CMD1, and CMD2) from the submit queue 2041 of the host 20, the controller 102 writes the captured one or more access instructions into the empty items of the instruction capture area 310 one by one. For example, the controller 102 writes the captured access instructions into items S0, S1, and S2 starting from item S0, and modifies the values of the corresponding mask bits MB0, MB1, and MB2 of items S0, S1, and S2 to 1, such as Figure 3B It should be noted that, in the above process of storing the retrieved access instruction, the value of the mask bit corresponding to each item in the instruction execution area 320 is maintained at 1.
[0036] When the controller 102 writes the captured one or more access instructions one by one into the empty entries of the instruction capture area 310, the controller 102 also backs up the access instructions stored in the instruction capture area 310 to the volatile memory 106, for example, by backing up one by one or in batches. Figure 3C As shown, in addition to writing the captured access instruction CMD3 to the item S3 and modifying the value of the corresponding mask bit, the controller 102 also backs up the access instructions CMD0-CMD2 originally stored in the items S0-S2 to the volatile memory 106, and modifies the values of the mask bits MB0-MB2 corresponding to the items S0-S2 to 0. In some embodiments, when the controller 102 backs up the access instructions stored in the instruction capture area 310 to the volatile memory 106, the controller 102 may modify the value of the mask bit corresponding to the item of the access instruction to 0 to indicate that the item is an empty item, and then write the subsequent captured access instruction to the item. In other embodiments, when the controller 102 backs up the access instructions stored in the instruction capture area 310 to the volatile memory 106, the controller 102 may clear the content of the item of the access instruction and modify the value of the mask bit corresponding to the item of the access instruction to 0.
[0037] Figure 4 Schematic diagram of the instruction acquisition and instruction execution process of a solid-state storage device according to an embodiment of the present invention. Figure 1 , Figure 3A and Figure 4 .
[0038] When the processor 202 issues an access instruction (e.g., a write instruction or a read instruction), the processor 202 writes the access instruction to the commit queue 2041 (arrow 402). If the access instruction is a write instruction, the processor 202 writes the data corresponding to the access instruction to the data buffer 2043 (arrow 404). The controller 102 of the solid-state storage device 10 will periodically check whether there is a new access instruction submitted in the commit queue 2041. If there is a new access instruction in the commit queue 2041, the controller 102 captures the newly submitted access instruction from the commit queue 2041 (arrow 406), and stores the captured access instruction in the instruction capture area 310 in the cache 104 (arrow 408).
[0039] The controller 102 then backs up the access instructions stored in the instruction capture area 310 to the volatile memory 106 (arrow 410), and clears the value of the mask bit of the access instruction that has been backed up (arrow 412). The operations of the arrows 410 and 412 can be repeated. When the controller 102 enters the instruction run time to execute the access instructions, the controller 102 writes one or more access instructions backed up to the volatile memory 106 to the instruction execution area 320 of the cache 104 (arrow 414), and reads one of the access instructions from the instruction execution area 320 and executes it (arrow 416). If the access instruction to be executed is a write instruction, the controller 102 will retrieve the write data corresponding to the access instruction from the data buffer 2043 of the host 20 (arrow 418), and store the write data in the cache 104 (instruction execution area 320) (arrow 420). The controller 102 then programs the write data stored in the cache 104 to the non-volatile memory 108 (arrow 422 ).
[0040] When the access instruction to be executed is a read instruction, the controller 102 also reads the access instruction from the instruction execution area 320 and executes it (arrow 424). If the data of the access instruction is not temporarily stored in the cache 104 or the volatile memory 106, the controller 102 reads the read data corresponding to the access instruction from the non-volatile memory 108 (arrow 426), and writes the read data to the data buffer 2043 of the host 20 (arrow 428).
[0041] It should be noted that although Figure 4The completion queue 2042 of the host 20 is not shown in the process. When the controller 102 completes an access instruction (which may be a write instruction or a read instruction), the controller 102 writes the instruction completion information of the access instruction into the completion queue (not shown in FIG. 1 ) in the cache 104, and then deletes the completed access instruction from the commit queue (not shown in FIG. 1 ) of the cache 104. Then, the controller 102 writes the instruction completion information of the completed access instruction into the completion queue 2042 of the host 20, and deletes the completed access instruction from the commit queue 2041 of the host 20.
[0042] In some embodiments, the multiple access instructions issued by the processor 202 of the host 20 may be multiple sequential write instructions or multiple sequential read instructions for the solid-state storage device 10. However, because the operating system (not shown) running on the host 20 may need to write a system log file to the solid-state storage device 10 or read a system log file from the solid-state storage device 10 at any time, the write instruction or read instruction of the system log file may be interspersed between the multiple consecutive write instructions / read instructions. In this case, the controller of the conventional solid-state storage device will determine that the access instructions are random write instructions or random read instructions, which will affect the write or read performance of the conventional solid-state storage device. However, through the design of the instruction capture area 310 and the instruction execution area 320 of the cache 104 of the present invention, the controller 102 can back up the access instructions stored in the instruction capture area 310 in the volatile memory 106, and store the access instructions to be executed in the instruction execution area 320 at the instruction execution time. Therefore, the controller 102 can not only continuously capture new access instructions from the commit queue 2041 of the host 20, but also filter out the write instructions of the system log file issued by the host 20 from the access instructions backed up in the volatile memory 106, so that the access instructions to be executed subsequently stored in the instruction execution area 320 can constitute continuous write instructions, thereby improving the performance of the solid-state storage device 10.
[0043] Figure 5 This is a flow chart of a method for acquiring instructions for a solid-state storage device according to an embodiment of the present invention. Figure 1 , Figure 3A and Figure 5 .
[0044] In step 510, the controller 102 retrieves access instructions from the commit queue 2041 of the host 20, and stores the access instructions in the instruction capture area 310 of the cache 104. For example, the cache 104 can be divided into the instruction capture area 310 and the instruction execution area 320. The instruction capture area 310 is used to store the access instructions retrieved by the controller 102 from the commit queue 2041 of the host 20. The instruction execution area 320 is used to store one or more access instructions executed by the controller 102 in the instruction execution stage.
[0045] In step 520, the controller 102 backs up the access instructions stored in the instruction capture area 310 in the volatile memory 106. For example, the processor 202 of the host 20 issues a large number of access instructions and stores the access instructions in the commit queue 2041. In addition, before the controller 102 of the solid-state storage device 10 executes the access instructions, the controller 102 needs to store the access instructions captured from the commit queue 2041 in the instruction capture area 310 of the cache 104. However, the capacity of the instruction capture area 310 is limited, so when the controller 102 writes the access instruction captured from the submit queue 2041 to the instruction capture area 310, the controller 102 simultaneously backs up the access instruction stored in the instruction capture area 310 to the volatile memory 106, and clears the value of the mask bit corresponding to the item of the backed-up access instruction (for example, sets it to 0), thereby clearing the occupied items in the instruction capture area 310 to empty items, so that the controller 102 can further capture more access instructions from the submit queue 2041 of the host 20. In one embodiment, the backed-up access instruction is the same as the access command just captured from the submit queue 2041 of the host 20, that is, when the controller 102 stores the access instruction captured from the submit queue 2041 to the instruction capture area 310 of the cache 104, the access instruction is synchronously backed up to the volatile memory 106. In one embodiment, the backed-up access command is different from the access command just captured from the submit queue 2041 of the host 20, that is, the access command backed up by the controller 102 is the access command previously stored in the command capture area 310, rather than the access command just captured from the submit queue 2041 of the host 20.
[0046] In step 530, the controller 102 stores the access instruction stored in the volatile memory 106 in the instruction execution area 320 of the cache 104. For example, when the controller 102 enters the instruction run time to execute the access instruction, the controller 102 writes the access instruction backed up in the volatile memory 106 to the instruction execution area 320 of the cache 104, and reads one of the access instructions from the instruction execution area 320 and executes it.
[0047] In step 540 , the controller 102 executes the access instruction stored in the instruction execution area 320 , and clears the entry corresponding to the access instruction in the instruction execution area 320 .
[0048] Figure 6 FIG. 4 is a schematic diagram of a cache in yet another embodiment of the present invention.
[0049] In some embodiments, the cache 104 can be divided into an instruction capture area 310, an instruction execution area 320, and an instruction completion area 330. The functions of the instruction capture area 310 and the instruction execution area 320 are described in detail in detail in the accompanying drawings. Figure 3A The instruction completion area 330 is used to store instruction completion information of the access instructions that have been executed by the controller 102 in the instruction execution area 320, so the instruction completion area 330 can also be regarded as a completion queue of the solid-state storage device 10. The number of items in the instruction capture area 310, the instruction execution area 320 and the instruction completion area 330 can be adjusted according to actual conditions.
[0050] In detail, Figure 6 The design of the cache 104 can further divide the access instruction into the instruction fetching stage, the instruction running stage and the instruction completion stage, and the instruction completion stage has a separate instruction completion area 330 to store the instruction completion information of the access instruction that has been executed, so that the instruction completion information and the access instruction to be executed do not need to be mixed in the instruction execution area 320. Therefore, in some cases, Figure 6 The design of the cache 104 can further improve the performance of the solid-state storage device 10.
[0051] Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the appended claims.
[0052] [Explanation of Symbols]
[0053] 1 Computer System
[0054] 10 Solid-state storage device
[0055] 11 Bus
[0056] 20 Host
[0057] 102 Controller
[0058] 104 Cache
[0059] 106 Volatile Memory
[0060] 108 Non-volatile memory
[0061] 202 Processor
[0062] 204 System Memory
[0063] 310 Command capture area
[0064] 320 Instruction execution area
[0065] 330 Command completion area
[0066] 402-428 Arrow
[0067] 500 Methods
[0068] Steps 510-540
[0069] 2041 Submission Queue
[0070] 2042 Completed Queue
[0071] 2043 Data Buffer
[0072] CMD0-CMD255 access instructions
[0073] MB0-MB255 mask bits
[0074] S0-S255 items.
Claims
1. A solid-state storage device configured to be electrically connected to a host, the solid-state storage device comprising: Controller; A cache electrically connected to the controller, wherein the cache includes a first area and a second area; a volatile memory electrically connected to the controller; as well as a non-volatile memory electrically connected to the controller; wherein the controller is configured to retrieve access instructions from the host and store the access instructions in the first area; wherein the controller is configured to back up the access instructions stored in the first area in the volatile memory; The controller is configured to store the access instruction backed up in the volatile memory in the second area and execute the access instruction stored in the second area.
2. The solid-state storage device according to claim 1, wherein: The first area is an instruction fetching area, and the second area is an instruction executing area.
3. The solid-state storage device according to claim 1, wherein: The first region includes a plurality of first items, and each of the first items has a corresponding first mask bit, The second area includes a plurality of second items, and each of the second items has a corresponding second mask bit.
4. The solid-state storage device according to claim 3, wherein: When the solid-state storage device is powered on, the controller initializes the value of the first mask bit corresponding to each of the first items to a first value, and initializes the value of the second mask bit corresponding to each of the second items to a second value.
5. The solid-state storage device according to claim 4, wherein: The controller is configured to write the first access instruction retrieved from the host into one of the first items, and to modify the value of the first mask bit corresponding to the first item written into the first access instruction into the second value.
6. The solid-state storage device according to claim 5, wherein: When the controller backs up the access instruction stored in the first area in the volatile memory, the controller is further configured to modify the value of the first mask bit corresponding to the first item of the backed-up access instruction to the first value.
7. The solid-state storage device according to claim 1, wherein: The cache further includes a third area for storing instruction completion information corresponding to the access instruction that has been executed in the second area.
8. A method for acquiring instructions for a solid-state storage device, the solid-state storage device being electrically connected to a host and comprising a controller, a cache, a volatile memory and a non-volatile memory, the method comprising: utilizing the controller to retrieve access instructions from the host and storing the access instructions in a first area of the cache; Backing up the access instruction stored in the first area in the volatile memory by using the controller; as well as The controller is used to store the access instruction backed up in the volatile memory in the second area of the cache, and the access instruction stored in the second area is executed.
9. The method of claim 8, wherein: The first area is an instruction fetching area, and the second area is an instruction executing area.
10. The method of claim 8, wherein: The first region includes a plurality of first items, and each of the first items has a corresponding first mask bit, The second area includes a plurality of second items, and each of the second items has a corresponding second mask bit.
11. The method of claim 10, further comprising: When the solid-state storage device is powered on, the controller is used to initialize the value of the first mask bit corresponding to each of the first items to a first value, and to initialize the value of the second mask bit corresponding to each of the second items to a second value.
12. The method of claim 11, further comprising: The controller is used to write the access instruction captured from the host into one of the first items, and the value of the first mask bit corresponding to the first item written into the access instruction is modified to the second value.
13. The method of claim 12, further comprising: When the access instruction stored in the first area is backed up in the volatile memory, the controller is used to modify the value of the first mask bit corresponding to the first item of the backed-up access instruction to the first value.
14. The method of claim 8, wherein: The cache further includes a third area for storing instruction completion information corresponding to the access instruction that has been executed in the second area.