A display device and a corner voltage generating circuit

Abstract

The present application relates to a display device and a corner cutting voltage generating circuit, the display device comprising a liquid crystal panel, a gate driver, a source driver and a corner cutting voltage generating circuit, wherein the corner cutting voltage generating circuit can divide the voltage difference between the gate on voltage VGH end of PMIC and the gate off voltage VGL end of PMIC to obtain a corner cutting voltage, and the division ratio of the corner cutting voltage generating circuit when dividing is adjustable. According to the embodiment of the present application, the gate driver can generate a scan signal with a falling edge having an inclined portion according to the corner cutting voltage, reduce the Feed-Through effect of the near-end thin film transistor near the gate driver when it is off, and further reduce the flicker difference at each position in the liquid crystal panel; and the division ratio of the corner cutting voltage generating circuit to the voltage difference is adjustable, so that the corner cutting voltage can be adjusted conveniently and efficiently without changing the hardware structure.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display device and a beveled voltage generation circuit. Background Technology

[0002] In the field of display technology, current LCD panels rely on a common voltage to adjust pixel grayscale to achieve ideal image display effects. Theoretically, to achieve a better display state, the common voltage should be precisely at the center of the positive and negative polarities of each grayscale voltage, thereby ensuring that the panel will not exhibit flickering, image retention, or screen splitting issues after prolonged display.

[0003] In practical applications, a feed-through effect also exists. This effect mainly stems from the capacitive coupling caused by the gate-drain capacitance when the gate driver is off. During the operation of the LCD panel, when the gate driver voltage changes, this capacitive coupling affects the display electrode voltage, leading to an imbalance in the positive and negative bias voltages of the liquid crystal pixel electrodes and causing flickering. To compensate for this effect, the common voltage must be adjusted, and the adjustment amount must match the voltage change caused by the feed-through effect to achieve the desired display effect.

[0004] However, the relative positions of the thin-film transistors (TFTs) corresponding to each sub-pixel in a liquid crystal panel differ from those of the gate drivers that control the switching on and off of these TFTs. This results in varying transmission path lengths for the scan signals emitted by the gate drivers. When the gate driver sends a turn-off signal, the turn-off voltage received by the TFTs at different locations varies significantly. Specifically, the signal waveform received by the near-end TFT, closer to the gate driver, is more square-shaped. When the TFT is turned off, the voltage difference across it is larger, resulting in a larger feed-through effect. Conversely, the signal waveform received by the far-end TFT is flatter. When the TFT is turned off, the voltage difference across it is smaller, resulting in a smaller feed-through effect.

[0005] It is evident that different locations within the LCD panel will experience varying degrees of feed-through effect, which means that a single fixed common voltage cannot meet the display requirements of the entire screen, resulting in significant differences in flickering across different areas of the LCD panel. Summary of the Invention

[0006] The present invention provides a display device and a beveled voltage generation circuit to address the shortcomings of related technologies.

[0007] According to a first aspect of the present invention, a display device is provided, comprising:

[0008] The liquid crystal panel has multiple sub-pixels arranged in an array and thin-film transistors corresponding to each sub-pixel. The gate of the thin-film transistor controls the conduction state of the thin-film transistor according to the scan signal provided by the gate driver.

[0009] A beveled voltage generation circuit is used to divide the voltage difference between the gate turn-on voltage VGH terminal and the gate turn-off voltage VGL terminal of the power management integrated circuit (PMIC) to obtain a beveled voltage, and to provide the beveled voltage to the gate driver; wherein, the voltage division ratio of the beveled voltage generation circuit in dividing the voltage difference is adjustable.

[0010] A gate driver is configured to generate a scan signal with a falling edge and a tilted portion based on the chamfered voltage, and transmit the scan signal to the gate of the thin-film transistor corresponding to the sub-pixel;

[0011] A source driver for providing data signals to the sub-pixel through the source of the thin-film transistor.

[0012] In one possible implementation, the beveled voltage generation circuit includes a P-MOS transistor, a first resistor, a second resistor, and a third resistor;

[0013] The input terminal of the chamfered voltage generation circuit is connected to the gate of the P-MOS transistor, and the output terminal of the chamfered voltage generation circuit is connected to the source of the P-MOS transistor.

[0014] The drain of the P-MOS transistor is connected to the analog ground via a first resistor;

[0015] The source of the P-MOS transistor is connected to the gate turn-on voltage VGH terminal of the PMIC via a second resistor.

[0016] The source of the P-MOS transistor is connected to the gate turn-off voltage VGL terminal of the PMIC via a third resistor.

[0017] In one possible implementation, the chamfered voltage generation circuit further includes a fourth resistor, and the output terminal of the chamfered voltage generation circuit is connected to the source of the P-MOS transistor through the fourth resistor.

[0018] In one possible implementation, the chamfered voltage generating circuit includes a first resistor and a second resistor;

[0019] The first resistor and the second resistor are connected in series between the gate turn-on voltage VGH terminal and the gate turn-off voltage VGL terminal of the PMIC, and the output terminal of the chamfered voltage generation circuit is located between the first resistor and the second resistor.

[0020] Wherein, at least one of the first resistor and the second resistor is a variable resistor element.

[0021] According to a second aspect of the present invention, a chamfered voltage generating circuit is provided, comprising:

[0022] The first terminal is connected to the gate turn-on voltage VGH terminal of the PMIC;

[0023] The second terminal is connected to the gate shutdown voltage VGL terminal of the PMIC;

[0024] The third terminal is used to output the beveled voltage;

[0025] A beveling module is connected to the first terminal, the second terminal, and the third terminal respectively, and is used to divide the voltage difference between the VGH terminal and the VGL terminal to obtain the beveling voltage; wherein, the voltage division ratio of the beveling module for dividing the voltage difference is adjustable.

[0026] In one possible implementation, the chamfered voltage generation circuit further includes a fourth terminal, which is connected to the regulated voltage output terminal of the PMIC.

[0027] The beveled module includes a P-MOS transistor, a first resistor, a second resistor, and a third resistor;

[0028] The gate of the P-MOS transistor is connected to the fourth terminal, and the source of the P-MOS transistor is connected to the third terminal.

[0029] The drain of the P-MOS transistor is connected to the analog ground via a first resistor;

[0030] The source of the P-MOS transistor is connected to the first terminal via a second resistor;

[0031] The source of the P-MOS transistor is connected to the second terminal via a third resistor.

[0032] In one possible implementation, the chamfering module further includes a fourth resistor, through which the source of the P-MOS transistor is connected to the third terminal.

[0033] In one possible implementation, the chamfering module includes a first resistor and a second resistor;

[0034] The first resistor and the second resistor are connected in series between the first terminal and the second terminal, and the third terminal is connected to the connection line between the first resistor and the second resistor;

[0035] Wherein, at least one of the first resistor and the second resistor is a variable resistor element.

[0036] According to a third aspect of the present invention, a display panel is provided, including a beveled voltage generating circuit as described in the second aspect.

[0037] According to a fourth aspect of the present invention, a display device is provided, comprising a display panel as described in the third aspect.

[0038] As described in the above embodiments, the modified display device provided by the present invention includes a liquid crystal panel, a gate driver, a source driver, and a chamfered voltage generation circuit. The chamfered voltage generation circuit divides the voltage difference between the gate-on voltage VGH and the gate-off voltage VGL of the power management integrated circuit (PMIC) to obtain a chamfered voltage. Subsequently, the gate driver generates a scanning signal with a sloping falling edge based on the chamfered voltage, reducing the feed-through effect of the near-end thin-film transistor (TFT) when it is off, making it closer to the feed-through effect of the far-end TFT when it is off. Based on this, even using a single fixed common voltage, the display effect requirements of the entire liquid crystal panel can be met, solving the problem of significant differences in flicker across different areas. Furthermore, when dividing the voltage difference between the gate-on voltage VGH and the gate-off voltage VGL, the voltage division ratio of the chamfered voltage generation circuit in this embodiment is adjustable, thus allowing for convenient and efficient adjustment of the chamfered voltage without changing the hardware structure. If the corner-cutting voltage generation circuit is applied to different display devices, the corner-cutting voltage can be configured individually for each display device in a highly efficient manner to adapt to the differences in characteristics of different display devices, thereby ensuring that each display device can achieve the best display effect.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0041] Figure 1 This is a schematic diagram illustrating the relationship between the Feed-Through effect and the common voltage according to an embodiment of the present invention.

[0042] Figure 2 This is a schematic diagram of a scanning signal of a near-far end thin-film transistor according to an embodiment of the present invention.

[0043] Figure 3 This is a schematic diagram illustrating a method for beveling a scanning signal according to an embodiment of the present invention.

[0044] Figure 4 This is a schematic diagram of a beveled voltage generation circuit according to an embodiment of the present invention.

[0045] Figure 5(a) is a schematic diagram of a chamfering module according to an embodiment of the present invention.

[0046] Figure 5(b) is a schematic diagram of a chamfered module using a sliding rheostat according to an embodiment of the present invention.

[0047] Figure 5(c) is a schematic diagram of another chamfered module using a sliding rheostat according to an embodiment of the present invention.

[0048] Figure 6 This is a schematic diagram of another beveling module according to an embodiment of the present invention.

[0049] Figure 7 This is a schematic diagram illustrating the relationship between bevel voltage and bevel waveform according to an embodiment of the present invention. Detailed Implementation

[0050] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0051] In the field of display technology, the core structure of a liquid crystal panel includes multiple sub-pixels arranged in an array. These sub-pixels are the basic units that constitute an image, and each sub-pixel corresponds to a thin-film transistor (TFT). The gate of the TFT receives a scan signal from the gate driver (also known as the gate IC) to precisely control its conduction state. When the gate of any TFT receives a specific voltage signal, the TFT can turn on or off according to the signal, thus determining whether current is allowed to pass. Based on this, and in conjunction with the data signal provided by the source driver (also known as the source IC), the arrangement of liquid crystal molecules in the corresponding sub-pixel can be controlled, changing the transmittance of incident light, thereby controlling the color and brightness of each sub-pixel, and ultimately completing the image display.

[0052] Specifically, during operation, the gate driver sequentially selects each row or column of the liquid crystal panel (depending on the specific design) and provides a scan signal to that row or column. When the scan signal provided by the gate driver is high, the corresponding thin-film transistor (TFT) is in the on state, meaning the TFT is conducting, allowing the data signal provided by the source driver to be transmitted to the liquid crystal layer through the TFT. When the gate driver provides a low level, the corresponding TFT is in the off state, meaning the TFT is cut off, preventing the data signal from passing through, thus keeping the current state of the liquid crystal molecules unchanged. In other words, the gate driver provides a scan signal, which controls the conduction state of the TFTs corresponding to each sub-pixel, and the source driver provides a data signal, which is transmitted to the corresponding sub-pixel through the conducting TFT to adjust its display state.

[0053] To prevent liquid crystal materials from aging or producing image retention due to prolonged exposure to a unidirectional electric field, the polarity of the voltage is periodically changed to reduce the impact of DC bias. Furthermore, the LCD panel relies on a common voltage (Vcom) to precisely adjust the voltage difference of each pixel, achieving ideal image display and smooth grayscale transitions. Theoretically, the common voltage Vcom must be precisely located at the center of the positive and negative polarities of each grayscale level, meaning it should be at the midpoint between the positive and negative voltages. Only under this ideal state can the liquid crystal molecules achieve optimal alignment under the influence of the electric field, ensuring that light passing through the liquid crystal layer accurately displays the required brightness and color. When the common voltage Vcom is at its center, the liquid crystal molecules, under the combined action of the positive and negative voltages, can achieve a smooth transition between different grayscale levels, effectively avoiding excessive or insufficient twisting of the liquid crystal molecules due to voltage imbalance. This not only helps improve image contrast and color accuracy but also ensures that the LCD panel does not experience serious visual problems such as flickering, image retention, and screen splitting after prolonged continuous display.

[0054] However, in practical LCD panel applications, the feed-through effect must also be considered. The feed-through effect primarily stems from electrical phenomena triggered when the gate driver is turned off. Specifically, when the gate driver is off, the gate-drain capacitance (Cgd) between the gate and drain of the thin-film transistor generates capacitive coupling. Specifically, during normal operation of the LCD panel, whenever the level of the scan signal provided by the gate driver changes, the capacitive coupling formed by the gate-drain capacitance interferes with the voltage of the display electrode below each sub-pixel, which receives data signals through the thin-film transistor. This interference directly leads to an imbalance in the positive and negative bias voltages of the liquid crystal pixel electrodes, disrupting the originally stable voltage balance and causing flickering.

[0055] The flickering problem arises because liquid crystal molecules are extremely sensitive to voltage changes. Even minute voltage fluctuations can alter the twisting angle of the liquid crystal molecules, thus affecting light transmittance. When the positive and negative bias voltages are unbalanced, the liquid crystal molecules cannot accurately modulate the light, causing the human eye to perceive unstable changes in screen brightness and color—this is the flickering phenomenon. To effectively compensate for the negative impact of the feed-through effect, the common voltage Vcom must be adjusted synchronously, and the adjustment magnitude should match the voltage changes caused by the feed-through effect.

[0056] like Figure 1 As shown, waveform A is used to characterize the waveform of the scan signal provided by the gate driver, waveform B is used to characterize the ideal waveform of the data signal provided by the source driver, and waveform C is used to characterize the waveform of the voltage actually received by the display electrode.

[0057] Ideally, the voltage of the display electrode should be the same as the waveform of the data signal, and the voltage difference between the positive polarity voltage and the standard common voltage Vcom should be the same as the voltage difference between the negative polarity voltage and the standard common voltage Vcom. However, in practical applications, taking the stage where the data signal is positive as an example, when the rising edge of waveform A arrives, the gate of the thin-film transistor turns on, and the data signal provided by the source driver is transmitted to the display electrode, which receives the data signal in waveform C. Subsequently, when the falling edge of waveform A arrives, the gate of the thin-film transistor turns off. Ideally, the voltage of the display electrode should be the same as the voltage of waveform B. However, due to the feed-through effect, there is a voltage difference between the voltage of the display electrode and the voltage of the data signal shown in waveform B, as indicated by label 11. Similarly, when the data signal is negative, there is also a voltage difference between the voltage of the display electrode and the voltage of the data signal shown in waveform B, as indicated by label 12. In this case, the original common voltage Vcom is not located at the exact center of the positive and negative polarity voltages of the display electrode. Therefore, the common voltage Vcom needs to be adjusted, and the adjustment should match the voltage change caused by the Feed-Through effect. That is, the common voltage Vcom should be adjusted based on the voltage difference shown in Identifier 11 or Identifier 12.

[0058] However, a deeper examination of the internal structure and signal transmission path of LCD panels reveals another key factor affecting display consistency: the relative positional differences between the thin-film transistors (TFTs) and gate drivers for each sub-pixel. Due to the large size of LCD panels, especially in large-screen displays (such as long, rectangular screens in automobiles), these relative positional differences are even more pronounced. The scan signal emitted by the gate driver needs to be transmitted to each TFT through a complex circuit layout, and the distance between the TFT and the gate driver varies at different locations, directly resulting in significant differences in the transmission path length of the scan signal.

[0059] Furthermore, when the gate driver sends a scan signal, this difference in transmission path length will cause significant differences in the voltage received by thin-film transistors at different locations, thereby triggering different degrees of feed-through effect. Figure 2 A schematic diagram of a scanning signal for a near-far end thin-film transistor is shown. See details below. Figure 2 If we consider the leftmost thin-film transistor (TFT) as the proximal TFT closest to the gate driver, the distance between each TFT and the gate driver increases from left to right. For the proximal TFTs closest to the gate driver, such as the leftmost TFT, the shorter transmission path between it and the gate driver reduces the impact of resistance and capacitance, resulting in less signal attenuation and delay. Therefore, the waveform of the received scan signal is closer to a square wave, as shown in waveform A. This square wave causes a large voltage difference across the TFT at the moment of turn-off. The fast falling edge of the square wave causes the TFT to quickly switch from the on state to the off state, generating a large voltage change in a short time, thus triggering a strong feed-through effect. Conversely, for the far-end TFTs farther from the gate driver, such as... Figure 2 The rightmost thin-film transistor in the diagram exhibits waveform distortion and smoothing due to the long transmission path required for the scan signal. This distortion is caused by factors such as line resistance and capacitance, resulting in a flatter waveform, as shown in waveform B. When this smoother waveform reaches the thin-film transistor, the voltage difference across it is relatively small at the moment of its shutdown, thus minimizing the feed-through effect.

[0060] It is evident that because the feed-through effect generated by the thin-film transistors at different locations within the LCD panel varies in degree, a single, fixed common voltage Vcom is clearly insufficient to meet the diverse display requirements of different areas of the screen. In the near-end area, the larger feed-through effect leads to a larger voltage deviation, which should be compensated for by adjusting the common voltage Vcom to create a larger voltage difference; while in the far-end area, the smaller feed-through effect should be compensated for by adjusting the common voltage Vcom to create a smaller voltage difference. Therefore, using a uniform common voltage Vcom will inevitably result in different flicker patterns in different areas, leading to significant differences in flicker performance across different regions.

[0061] To address the aforementioned problems, this invention provides a display device comprising a chamfered voltage generation circuit that divides the voltage difference between the gate-on voltage VGH and the gate-off voltage VGL of a power management integrated circuit (PMIC) to obtain a chamfered voltage, also known as VGN. Subsequently, the gate can generate a scanning signal with a sloping falling edge based on the chamfered voltage, reducing the feed-through effect of the near-end thin-film transistor (TFT) when it is off, making it closer to the feed-through effect of the far-end TFT when it is off. Based on this, even using a single fixed common voltage, the problem of significant differences in flicker across different areas of the entire liquid crystal panel can be addressed to meet the display requirements. Furthermore, when dividing the voltage difference between the gate-on voltage VGH and the gate-off voltage VGL, the chamfered voltage generation circuit in this embodiment of the invention allows for adjustable voltage division ratios, thus enabling convenient and efficient adjustment of the chamfered voltage without altering the hardware structure. The technical solution of this invention will now be described in detail.

[0062] In one embodiment, the display device includes a liquid crystal panel, a beveled voltage generation circuit, a gate driver, and a source driver.

[0063] As mentioned earlier, a liquid crystal panel contains an array of sub-pixels and thin-film transistors (TFTs) corresponding to each sub-pixel. Each TFT has a gate, a source, and a drain. The gate of a TFT can control the conduction state of its corresponding TFT based on a scan signal provided by a gate driver. The gate driver can transmit the scan signal to the gate of the TFT corresponding to each sub-pixel, while the source driver can provide data signals to the corresponding sub-pixel through the source of each TFT. When the gate of any TFT receives a high-level scan signal, its corresponding TFT is in the ON state, i.e., the TFT is conducting, and the sub-pixel corresponding to that TFT can receive the data signal provided by the source driver. When the gate of any TFT receives a low-level scan signal, its corresponding TFT is in the OFF state, i.e., the TFT is off, and the sub-pixel corresponding to that TFT cannot receive the data signal provided by the source driver; the state of the liquid crystal molecules in the sub-pixel remains unchanged.

[0064] It should be noted that in the display device, the number and position of the source driver, the gate driver, and the chamfered voltage generation circuit described below can be adjusted according to actual needs, and the present invention does not impose any restrictions on this.

[0065] The bevel voltage generation circuit can divide the voltage difference between the gate turn-on voltage VGH terminal and the gate turn-off voltage VGL terminal of the power management integrated circuit (PMIC) to obtain the bevel voltage, and provide the bevel voltage to the gate driver.

[0066] A Power Management Integrated Circuit (PMIC) is a highly integrated chip used to manage power supply. It is responsible for the distribution, conversion, monitoring, and control of electrical energy, and can provide appropriate gate-on voltage (VGH) and gate-off voltage (VGL) for the thin-film transistors (TFTs) in an LCD panel. The gate-on voltage (VGH) is the voltage used to turn on the gate of the TFT in the LCD panel; it is typically a high positive value, and its specific value depends on the design and manufacturing process of the LCD panel. The VGH pin is the pin or port on the PMIC that outputs the gate-on voltage VGH. The gate-off voltage (VGL) is the voltage used to turn off the gate of the TFT in the LCD panel; its value is typically negative, and its specific value also depends on the design and manufacturing process of the LCD panel. The VGL pin is the pin or port on the PMIC that outputs the gate-off voltage VGL.

[0067] Based on this, it can be understood that there should be a certain voltage difference between the gate enable voltage VGH and the gate disable voltage VGL. Therefore, by dividing the voltage difference between the PMIC's gate enable voltage VGH and gate disable voltage VGL, a new voltage value can be obtained, which can be used as the chamfering voltage. In this embodiment of the invention, the gate driver can chamfer the falling edge of the scan signal according to a certain stable voltage value. That is, the gate driver can generate a scan signal with a slanted falling edge according to the chamfering voltage provided by the chamfering generation circuit.

[0068] Figure 3 A schematic diagram of a scanning signal undergoing beveling is shown, where waveform A is the scanning signal without beveling, and waveform B is the scanning signal after beveling. Figure 3 As shown, when the gate of the thin-film transistor receives the gate turn-off voltage VGL, the voltage difference at the falling edge 31 of waveform A is relatively large, with a voltage difference ΔV1 = VGH - VGL. If a chamfering process is performed, the gate driver will gradually reduce the gate turn-on voltage VGH to a certain voltage value Vx before providing the gate turn-off voltage VGL, and then provide the gate turn-off voltage VGL. As shown in waveform B, its falling edge 32 has a sloping portion 33, and the voltage difference when the thin-film transistor is turned off is ΔV2 = Vx - VGL. When Vx < VGH, ΔV2 < ΔV1. It is understandable that since the magnitude of the feed-through effect is related to the voltage difference, reducing the voltage difference at the instant the thin-film transistor is turned off can effectively reduce the feed-through effect.

[0069] Specifically, since the waveform of the scan signal received by the near-end thin-film transistor (TFT) is closer to a square wave, meaning the voltage difference of the TFT is larger at the moment of shutdown, after the gate driver performs beveling on the scan signal to generate a scan signal with a slanted falling edge, transmitting this scan signal to each TFT can effectively reduce the voltage difference of the near-end TFT close to the gate driver at the moment of shutdown, thus effectively reducing the feed-through effect of the near-end TFT. Meanwhile, since the voltage difference of the far-end TFT is already relatively small at the moment of shutdown, the beveling process has less impact on the far-end TFT. Based on this, the feed-through effect of the near-end TFT can be made closer to that of the far-end TFT, thereby reducing flicker differences at various locations within the liquid crystal panel.

[0070] It should also be emphasized that when the bevel voltage generation circuit in the embodiment of the present invention divides the gate turn-on voltage VGH terminal and the gate turn-off voltage VGL terminal, the voltage division ratio is adjustable, so the bevel voltage generation circuit can generate different bevel voltages.

[0071] It is understandable that for multiple display devices with the same or different models and specifications, there will inevitably be differences between the liquid crystal panels. To effectively address the flickering problem of each liquid crystal panel, the chamfering voltage of each display panel needs to be adjusted accordingly. Furthermore, for the same liquid crystal panel, when multiple gate drivers are provided, the gate turn-on voltage (VGH) and gate turn-off voltage (VGH) received by different gate drivers may differ due to their different positions, resulting in different feed-through effects in the near-end thin-film transistors. In both of these cases, multiple chamfering voltage generation circuits provided in this embodiment of the invention can be correspondingly provided. Since these chamfering voltage generation circuits can generate different chamfering voltages, the chamfering voltage can be conveniently and efficiently adjusted without changing the hardware to suit different degrees of feed-through effects. This allows for efficient processing of flickering in multiple display devices or flickering between different positions on the same liquid crystal panel, quickly adjusting the display device to its optimal display effect.

[0072] The structure of the beveled voltage generation circuit will be described in detail below.

[0073] Figure 4 A schematic diagram of a beveled voltage generation circuit is shown. (For example...) Figure 4 As shown, the beveled voltage generation circuit includes:

[0074] The first terminal 41 is connected to the gate turn-on voltage VGH terminal of the PMIC.

[0075] The second terminal 42 is connected to the gate turn-off voltage VGL terminal of the PMIC;

[0076] The third terminal 43 is used to output the beveled voltage;

[0077] The beveling module 44 is connected to the first terminal, the second terminal and the third terminal respectively, and is used to divide the voltage difference between the VGH terminal and the VGL terminal to obtain the beveling voltage; wherein, the voltage division ratio of the beveling module for dividing the voltage difference is adjustable.

[0078] The gate enable voltage VGH and gate disable voltage VGL of the PMIC are as described above and will not be repeated here. The first and second terminals of the chamfered voltage generation circuit are connected to the gate enable voltage VGH and gate disable voltage VGL of the PMIC, respectively, while the third terminal of the chamfered voltage generation circuit is used to output the chamfered voltage VGN to the gate driver. It should be noted that the first, second, and third terminals, as well as the fourth terminal mentioned in the following embodiments, are merely identifiers used to distinguish different pins or ports and do not imply any specific function or physical location; they are only used for convenient description and differentiation of the various connection points.

[0079] In one embodiment, the chamfering module 44 includes a first resistor 51 and a second resistor 52. As shown in FIG5(a), the first resistor 51 and the second resistor 52 are connected in series between the first terminal 41 and the second terminal 42. That is, one end of the first resistor 51 is connected to the gate turn-on voltage VGH terminal of the PMIC, and the other end is connected to the second resistor 52; while one end of the second resistor 52 is connected to the gate turn-off voltage VGL terminal of the PMIC, and the other end is connected to the first resistor 51. At the same time, the third terminal 43 for outputting the chamfering voltage VGN is connected to the connection line between the first resistor 51 and the second resistor 52, that is, the third terminal 43 is located between the first resistor 51 and the second resistor 52. Among them, at least one of the first resistor 51 and the second resistor 52 is a variable resistance element. A variable resistance element refers to an element with variable resistance characteristics, including mechanical (such as a sliding rheostat) and electronic variable resistors (such as a digital potentiometer). When the first resistor 51 is a sliding rheostat, the beveled voltage generation circuit is shown in Figure 5(b); when the second resistor 52 is a sliding rheostat, the beveled voltage generation circuit is shown in Figure 5(c).

[0080] When the PMIC outputs the gate-on voltage VGH at its gate-on voltage VGH terminal and the PMIC outputs the gate-off voltage VGL at its gate-off voltage VGL terminal, current I flows from the gate-on voltage VGH terminal to the gate-off voltage VGL terminal in the series resistor circuit composed of the first resistor 51 and the second resistor 52. Based on this, the chamfered voltage VGN is the gate-off voltage VGL plus the voltage drop across the second resistor 52. In this way, the voltage difference between the gate-on voltage VGH terminal connected to the first terminal 41 and the gate-off voltage VGL terminal connected to the second terminal 42 can be divided by the first resistor 51 and the second resistor 52 to obtain the chamfered voltage VGN, which is then output from the third terminal 43.

[0081] In one embodiment, the beveled voltage generating circuit further includes a fourth terminal. For example... Figure 6As shown, the fourth terminal 45 is connected to the regulated voltage output terminal of the PMIC. Meanwhile, the chamfering module 44 includes a P-MOS transistor 60, a first resistor 61, a second resistor 62, and a third resistor 63.

[0082] The gate G of the P-MOS transistor 60 is connected to the fourth terminal 45, and the source S of the P-MOS transistor 60 is connected to the third terminal 43.

[0083] The drain D of the P-MOS transistor 60 is connected to analog ground GND through a first resistor 61.

[0084] The source S of the P-MOS transistor 60 is connected to the first terminal 41 via a second resistor 62;

[0085] The source S of the P-MOS transistor 60 is connected to the second terminal 42 via a third resistor 63.

[0086] In this embodiment, in addition to the gate enable voltage VGH terminal and the gate disable voltage VGL terminal, the PMIC also has an adjustable voltage output terminal. The PMIC can be connected via an IIC (Inter-Integrated Circuit, also known as IIC). 2 C) The method of programming to change the register value changes the voltage output by the PMIC's regulating voltage output terminal.

[0087] In this embodiment, the voltage division ratio can be adjusted by discharging the P-MOS transistor 60 and by regulating the voltage output of the PMIC's regulating voltage output terminal. Specifically, when the voltage at node Vs is greater than the voltage received at terminal 45, the source S and drain D of the P-MOS transistor 60 are turned on, meaning that node Vs is connected to node Vd, which is connected to drain D. At this time, the circuit slowly discharges to ground through resistor R4. When node Vs discharges to a voltage equal to the voltage at terminal 45, the source S and drain D of the P-MOS transistor 60 are turned off. At this time, the circuit can keep the voltage at node Vs consistent with the voltage at terminal 45. Since node Vs is connected to terminal 43, meaning the source S of the P-MOS transistor 60 is connected to terminal 43, and terminal 43 is used to output the chamfered voltage VGN, different chamfered voltages VGN can be generated by changing the voltage received at terminal 45, that is, by changing the voltage output at the PMIC's regulating voltage output terminal.

[0088] The first resistor 61 and the second resistor 62 are used to adjust and limit the magnitude of the chamfered voltage VGN. Generally, the gate turn-off voltage VGL + preset value ≤ chamfered voltage VGN ≤ gate turn-on voltage VGL. Figure 7As shown, the chamfering voltages VGN1 > VGN2 > VGN3, and these three different chamfering voltages correspond to different chamfering waveforms. It can be seen that the larger the value of the chamfering voltage VGN, the steeper the slope of the falling edge of the scan signal generated by the gate driver based on that chamfering voltage VGN. When the chamfering voltage VGN is equal to the gate turn-on voltage VGL, it is equivalent to not performing chamfering. Of course, when changing the voltage output from the PMIC's regulating voltage output terminal, it is usually limited. The specific value can be set by a technician according to the actual situation; this invention does not impose such limitations.

[0089] It should also be noted that the first resistor 61, the second resistor 62, the third resistor 63, and the fourth resistor 64 mentioned in the following embodiments are only used as resistor identifiers to distinguish different resistors, and the resistance values ​​of each resistor can be set by technicians according to the actual situation. This invention does not impose any restrictions on this.

[0090] In one embodiment, such as Figure 6 The beveling module also includes a fourth resistor 64. The source S of the P-MOS transistor 60 is connected to the third terminal 43 via this fourth resistor 64. Specifically, one end of the fourth resistor 64 is connected to the source S of the P-MOS transistor 60, which is equivalent to connecting this end of the fourth resistor 64 to node Vs. The other end of the fourth resistor 64 is connected to the third terminal 43, which is used to output the beveling voltage VGN. In this embodiment of the beveling module, when the P-MOS transistor 60 is turned off, keeping the voltage at node Vs consistent with the voltage at the fourth terminal 45, the voltage at node Vs will be used as the input voltage in the subsequent voltage divider circuit. This voltage divider circuit consists of the fourth resistor 64 and the third resistor 63. The voltage divider principle of multiple series resistors can be found in the previous embodiment and will not be repeated here. By adding the fourth resistor, high-frequency noise and power supply ripple can be suppressed to a certain extent, providing a buffering and stabilizing effect on the voltage at node Vs, and reducing the impact of power supply fluctuations on the beveling voltage.

[0091] As can be seen from the above embodiments, the present invention provides two different design methods for the beveled corner module, enabling the beveled corner module to divide the voltage difference between the VGH and VGL terminals to obtain a reasonably sized beveled corner voltage. More importantly, both beveled corner modules can obtain different beveled corner voltages by adjusting the voltage division ratio, thus allowing for more flexible and convenient adjustment of the beveled corner voltage. If this beveled corner voltage generation circuit is applied to different display devices, a beveled corner voltage can be efficiently configured individually for each display device to adapt to the different characteristics of different display devices, thereby ensuring that each display device achieves the best display effect.

[0092] Accordingly, the present invention also provides a display panel including any of the corner-cutting voltage generation circuits in the above embodiments. The embodiments of the corner-cutting voltage generation circuits described above are applicable to the display panel provided in this embodiment, and will not be repeated here. The above embodiments and their beneficial effects are also applicable to this embodiment, and the same parts will not be repeated. It is understood that the display panel may include other structures such as a driving circuit in addition to the corner-cutting voltage generation circuit; other structures can be found in the display panels described in related technologies, and are not limited here.

[0093] Embodiments of the present invention also provide a display device, including a housing and the display panel described in the above embodiments. It should be noted that the display device in this embodiment can be any product or component with display functionality, such as electronic paper, mobile phone, tablet computer, television, laptop computer, digital photo frame, or navigator.

[0094] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0095] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. The invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0096] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A display device, characterized by comprising: include: The liquid crystal panel has multiple sub-pixels arranged in an array and thin-film transistors corresponding to each sub-pixel. The gate of the thin-film transistor controls the conduction state of the thin-film transistor according to the scan signal provided by the gate driver. A beveled voltage generation circuit is used to divide the voltage difference between the gate enable voltage VGH terminal and the gate disable voltage VGL terminal of a power management integrated circuit (PMIC) to obtain a beveled voltage, and to provide the beveled voltage to the gate driver; wherein the voltage division ratio of the beveled voltage generation circuit is adjustable; the beveled voltage generation circuit includes a first resistor and a second resistor; the first resistor and the second resistor are connected in series between the gate enable voltage VGH terminal and the gate disable voltage VGL terminal of the PMIC, and the output terminal of the beveled voltage generation circuit is located between the first resistor and the second resistor; wherein at least one of the first resistor and the second resistor is a variable resistor element. A gate driver is configured to generate a scan signal with a falling edge and a tilted portion based on the chamfered voltage, and transmit the scan signal to the gate of the thin-film transistor corresponding to the sub-pixel; A source driver for providing data signals to the sub-pixel through the source of the thin-film transistor.

2. The display device according to claim 1, wherein The beveled voltage generation circuit includes a P-MOS transistor, a first resistor, a second resistor, and a third resistor; The input terminal of the chamfered voltage generation circuit is connected to the gate of the P-MOS transistor, and the output terminal of the chamfered voltage generation circuit is connected to the source of the P-MOS transistor. The drain of the P-MOS transistor is connected to the analog ground via a first resistor; The source of the P-MOS transistor is connected to the gate turn-on voltage VGH terminal of the PMIC via a second resistor. The source of the P-MOS transistor is connected to the gate turn-off voltage VGL terminal of the PMIC via a third resistor.

3. The display device according to claim 2, wherein The chamfered voltage generation circuit also includes a fourth resistor, and the output terminal of the chamfered voltage generation circuit is connected to the source of the P-MOS transistor through the fourth resistor.

4. A corner rounding voltage generating circuit characterized by comprising: include: The first terminal is connected to the gate turn-on voltage VGH terminal of the PMIC; The second terminal is connected to the gate shutdown voltage VGL terminal of the PMIC; The third terminal is used to output the beveled voltage; A beveling module is connected to the first terminal, the second terminal, and the third terminal respectively, for dividing the voltage difference between the VGH terminal and the VGL terminal to obtain the beveling voltage; wherein the voltage division ratio of the beveling module for dividing the voltage difference is adjustable; the beveling module includes a first resistor and a second resistor; the first resistor and the second resistor are connected in series between the first terminal and the second terminal, and the third terminal is connected to the connecting line between the first resistor and the second resistor; wherein at least one of the first resistor and the second resistor is a variable resistor element.

5. The corner rounding voltage generating circuit according to claim 4, wherein The beveled voltage generation circuit further includes: a fourth terminal, which is connected to the adjustable voltage output terminal of the PMIC; The beveled module includes a P-MOS transistor, a first resistor, a second resistor, and a third resistor; The gate of the P-MOS transistor is connected to the fourth terminal, and the source of the P-MOS transistor is connected to the third terminal. The drain of the P-MOS transistor is connected to the analog ground via a first resistor; The source of the P-MOS transistor is connected to the first terminal via a second resistor; The source of the P-MOS transistor is connected to the second terminal via a third resistor.

6. The corner rounding voltage generating circuit according to claim 5, wherein The beveling module also includes a fourth resistor, through which the source of the P-MOS transistor is connected to the third terminal.

7. A display panel, characterized by, Includes the beveled voltage generation circuit as described in any one of claims 4-6.

8. A display device, characterized in that, It includes the housing and the display panel as described in claim 7.

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