Solid state storage device and dynamic temperature control method thereof
By adopting a dynamic temperature control method in a solid-state storage device, the temperature sensor and controller calculate the temperature difference and accumulated value, and determine the temperature control state, the efficiency fluctuation caused by the traditional temperature control mechanism is solved, and the balance between temperature and efficiency is achieved.
Patent Information
- Application Number
- CN202311133009.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-04
- Publication Date
- 2025-03-04
AI Technical Summary
The temperature control mechanism of traditional solid-state storage devices relies on a single fixed temperature threshold, resulting in excessive fluctuations in performance changes during cooling, affecting the user's operating experience.
The dynamic temperature control method is used to detect the temperature of the non-volatile memory regularly through the temperature sensor, and the controller is used to calculate the temperature difference and accumulated value, and the current temperature control state is determined from the temperature control state table to balance the cooling and the amplitude of the performance change.
It effectively reduces the temperature of the solid-state storage device, while controlling the amplitude of performance changes, avoiding the rapid change in temperature to destroy the balance between cooling and efficiency.
Smart Images
Figure CN119559976A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a solid-state storage device, and in particular to a solid-state storage device and a dynamic temperature control method thereof. Background Art
[0002] With the development of technology, solid state storage devices have been widely used in different computer systems, and the performance of solid state storage devices has gradually improved. However, as the performance of solid state storage devices has improved, some overheating problems have also occurred. The temperature control mechanism used by traditional solid state storage devices usually adopts a single fixed temperature threshold; when the temperature of the solid state storage device is detected to exceed the temperature threshold, the solid state storage device is cooled by reducing the performance of the solid state storage device. However, this method will cause the performance of the solid state storage device to fluctuate too much, affecting the user's operating experience. Therefore, how to effectively cool the solid state storage device and control the amplitude of the performance change, and achieve a balance between cooling and performance, is one of the problems that technicians in this field want to solve. Summary of the invention
[0003] Therefore, the present invention provides a solid state storage device and a dynamic temperature control method thereof to solve the above problems.
[0004] In one embodiment, the present invention provides a solid-state storage device. The solid-state storage device includes: a non-volatile memory; a temperature sensor configured to periodically detect the current temperature of the non-volatile memory; and a controller electrically connected to the non-volatile memory and the temperature sensor, configured to periodically obtain the current temperature from the temperature sensor. The controller is configured to activate a dynamic temperature control mechanism of the solid-state storage device, and the dynamic temperature control mechanism includes a temperature control state table, which includes a plurality of temperature control states and their corresponding state values. The controller is further configured to calculate the temperature difference between the current temperature and the previous temperature of the non-volatile memory, and accumulate the temperature difference to obtain a temperature accumulation value. The controller is further configured to determine the current temperature control state from the temperature control state table based on the temperature accumulation value.
[0005] In other embodiments, the present invention further provides a dynamic temperature control method for a solid-state storage device, wherein the solid-state storage device includes a controller, a temperature sensor and a non-volatile memory, the method comprising: using the temperature sensor to periodically detect the current temperature of the non-volatile memory; using the controller to periodically obtain the current temperature from the temperature sensor; when the controller determines that the current temperature is greater than a first temperature threshold, using the controller to activate a dynamic temperature control mechanism of the solid-state storage device, wherein the dynamic temperature control mechanism includes a temperature control state table, the temperature control state table includes a plurality of temperature control states and their corresponding state values; using the controller to calculate a temperature difference between the current temperature and a previous temperature of the non-volatile memory, and accumulating the temperature difference to obtain a temperature accumulation value; and using the controller to determine a current temperature control state from the temperature control state table based on the temperature accumulation value. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention.
[0007] Figure 2 FIG. 4 is a schematic diagram of a multi-stage temperature control method according to an embodiment of the present invention.
[0008] Figure 3 FIG. 4 is a flow chart of a dynamic temperature control method for a solid-state storage device according to another embodiment of the present invention.
[0009] Figure 4 According to the present invention Figure 2 and Figure 3 Schematic diagram of performance comparison of the methods of the embodiments.
[0010] Figure 5 According to the present invention Figure 2 and Figure 3 Schematic diagram of temperature comparison of the method of the embodiment. DETAILED DESCRIPTION
[0011] The following description is a preferred implementation of the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the following claims.
[0012] It must be understood that the words "comprise", "include" and the like used in this specification are intended to indicate the existence of specific technical features, values, method steps, operation processing and / or components, but do not exclude the addition of more technical features, values, method steps, operation processing, components, or any combination of the above.
[0013] The words "first", "second", "third", etc. used in the claims are used to modify the components in the claims and are not used to indicate a priority order, a prior relationship, or that one component precedes another component, or a temporal sequence in executing method steps. They are only used to distinguish components with the same name.
[0014] The term "configured to" may describe or claim that various units, circuits, or other components are "configured to" perform a task or tasks. In such contexts, the term "configured to" is used to imply structure by indicating that the units / circuits / components include structure (e.g., circuitry) that performs those task(s) during operation. Thus, even when a given unit / circuit / component is not currently operating (e.g., not turned on), the unit / circuit / component may still be said to be configured to perform the task. The units / circuits / components used with the term "configured to" include hardware - e.g., circuits, memory (storing program instructions executable to perform operations), etc. In addition, "configured to" may include generic structures (e.g., generic circuitry) that are manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the task(s) to be solved. "Configured to" may also include adapting a manufacturing process (eg, a semiconductor manufacturing facility) to produce devices (eg, integrated circuits) adapted to perform or execute one or more tasks.
[0015] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention.
[0016] like Figure 1 As shown, the computer system 1 includes a solid-state storage device 10 and a host 20, wherein the solid-state storage device 10 is electrically connected to the host 20 via a bus 11 to perform command and data transmission. In some embodiments, the bus 11 can be a Universal Serial Bus (USB), a Serial Advanced Technology Attachment (SATA) bus, a Peripheral Component Interconnect Express (PCI Express, PCIe) bus, etc., but the present disclosure is not limited thereto.
[0017] The solid-state storage device 10 includes a controller 102, a volatile memory 106, a non-volatile memory 108, a temperature sensor 110, and a clock generator 112. The controller 102 is electrically connected to the volatile memory 106 and the non-volatile memory 108, and is used to control data access of the volatile memory 106 and the non-volatile memory 108. In some embodiments, the controller 102 may be, for example, a general-purpose processor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc., but the present disclosure is not limited thereto.
[0018] The volatile memory 106 includes, for example, a dynamic random access memory (DRAM) and / or a static random access memory (SRAM), but the present disclosure is not limited thereto. In some embodiments, the volatile memory 106 may be disposed outside the controller 102, for example. In other embodiments, the volatile memory 106 may be integrated into the controller 102, for example. The non-volatile memory 108 may be, for example, a NAND flash memory for storing write data provided by the host 20.
[0019] In some embodiments, the temperature sensor 110 is configured to periodically detect temperature information (e.g., current temperature) of the non-volatile memory 108, and report the detected temperature information to the controller 102. The clock generator 112 is configured to provide a first clock signal CLK1 to the controller 102, and provide a second clock signal CLK2 to the non-volatile memory 108. Because the operating frequency of the controller 102 is usually greater than the operating frequency of the non-volatile memory 108, the clock generator 112 can provide the first clock signal CLK1 and the second clock signal CLK2 of different frequencies to the controller 102 and the non-volatile memory 108, respectively, wherein the frequency of the first clock signal CLK1 is greater than the second clock signal CLK2. In addition, when the solid-state storage device 10 enters any temperature control state, the controller 102 can control the frequency division ratio or the number of steps of the first clock signal CLK1 and the second clock signal CLK2, so as to reduce the frequency of the first clock signal CLK1 and the second clock signal CLK2 to reduce the temperature of the solid-state storage device 10.
[0020] The host 20 includes, for example, a processor 202 and a system memory 204, and the processor 202 is electrically connected to the system memory 204. In some embodiments, the processor 202 includes, for example, a central processing unit (CPU), a general purpose processor, a microprocessor, etc., but the disclosure is not limited thereto. In addition, the processor 202 includes a controller (not shown) for controlling data access to the system memory 204. The system memory 204 includes, for example, a dynamic random access memory, but the disclosure is not limited thereto.
[0021] In some embodiments, the host 20 may support the non-volatile memory communication protocol (NVM Express, NVME), and the system memory 204 is configured with a submission queue 2041, a completion queue 2042, and a data buffer 2043. The submission queue 2041 is used to record the access instructions issued by the processor 202, and the completion queue 2042 is used to record the status of the solid-state storage device 10 in response to the completed access instructions. The data buffer 2043 is used to store the data that the host 20 wants to write to the solid-state storage device 10 and to store the data read by the host 20 from the solid-state storage device 10.
[0022] The non-volatile memory 108 includes a plurality of blocks, and each block includes a plurality of pages. For example, the non-volatile memory 108 includes 1024 blocks, and each block includes 64 pages. Assuming that the capacity of each page is 16Kbytes, the capacity of each block is 1Mbyte. The above data is only for illustration, and the manufacturer of the non-volatile memory 108 can determine the number of pages in each block and the capacity of each page.
[0023] Figure 2 This is a schematic diagram of a multi-stage temperature control method according to an embodiment of the present invention. Figure 1 and Figure 2 .
[0024] In this embodiment, the temperature control mechanism of the solid state storage device 10 includes a non-temperature control state and multiple temperature control states, wherein the temperature control state can be sequentially divided into a light temperature control state, a heavy temperature control state, a first protection state, a second protection state and an overheating state. The controller 102 can set multiple temperature thresholds (e.g., T0-T5) to switch between the non-temperature control state and the temperature control state, wherein the temperature thresholds T0-T5 can be designed according to actual needs. In addition, the overheating protection means corresponding to different temperature control states may also be slightly different, and the overheating protection means corresponding to the light temperature control state to the overheating state will also become more and more stringent, that is, the efficiency of the solid state storage device 10 will become lower and lower. For example, the difference between the light temperature control state and the heavy temperature control state is that the frequency division ratios of the first clock signal CLK1 and the second clock signal CLK2 are different, and the heavy temperature control state has a higher frequency division ratio. In the first protection state, the controller 102 may further add other overheat protection means, such as: delaying the acquisition of access instructions from the host 20, delaying the sending of access instructions to the non-volatile memory 108. In the second protection state, the controller 102 may further add other overheat protection means, such as: stopping the acquisition of access instructions from the host 20 or stopping the execution of the acquired access instructions. In the overheat state, the controller 102 may further add other overheat protection means, such as: stopping the execution of background firmware events, such as garbage collection and erasing virtual blocks, etc. It should be noted that the overheat protection means corresponding to the above temperature control state are only for illustration purposes, and the present invention is not limited thereto.
[0025] The temperature sensor 110 can periodically detect the current temperature T of the non-volatile memory 108 and report it to the controller 102. The controller 102 can determine the temperature control state of the solid-state storage device 10 according to the current temperature T of the non-volatile memory 108. In the first scenario, the current temperature T of the non-volatile memory 108 gradually rises from the temperature threshold T0. When the controller 102 determines that the current temperature T is less than the temperature threshold T1, the controller 102 controls the solid-state storage device 10 to maintain in the non-temperature control state. When the controller 102 determines that the current temperature T is greater than or equal to the temperature threshold T1 and less than the temperature threshold T2, the controller 102 controls the solid-state storage device 10 to enter the light temperature control state from the non-temperature control state. When the controller 102 determines that the current temperature T is greater than or equal to the temperature threshold T2 and less than the temperature threshold T3, the controller 102 controls the solid-state storage device 10 to enter the heavy temperature control state from the light temperature control state. When the controller 102 determines that the current temperature T is greater than or equal to the temperature threshold T3 and less than the temperature threshold T4, the controller 102 controls the solid-state storage device 10 to enter the first protection state from the severe temperature control state. When the controller 102 determines that the current temperature T is greater than or equal to the temperature threshold T4 and less than the temperature threshold T5, the controller 102 controls the solid-state storage device 10 to enter the second protection state from the first protection state. When the controller 102 determines that the current temperature T is greater than or equal to the temperature threshold T5, the controller 102 controls the solid-state storage device 10 to enter the overheating state from the second protection state.
[0026] In the second scenario, the solid-state storage device 10 is in an overheated state, and the current temperature T of the non-volatile memory 108 gradually decreases from the temperature threshold T5. When the controller 102 determines that the current temperature T is less than the temperature threshold T4 and greater than or equal to the temperature threshold T3, the controller 102 controls the solid-state storage device 10 to enter the second protection state from the overheated state. When the controller 102 determines that the current temperature T is less than the temperature threshold T3 and greater than or equal to the temperature threshold T2, the controller 102 controls the solid-state storage device 10 to enter the first protection state from the second protection state. When the controller 102 determines that the current temperature T is less than the temperature threshold T2 and greater than or equal to the temperature threshold T1, the controller 102 controls the solid-state storage device 10 to enter the heavy temperature control state from the first protection state. When the controller 102 determines that the current temperature T is less than the temperature threshold T1 and greater than or equal to the temperature threshold T0, the controller 102 controls the solid-state storage device 10 to enter the light temperature control state from the heavy temperature control state. When the controller 102 determines that the current temperature T is less than the temperature threshold T0 , the controller 102 controls the solid state storage device 10 to enter the non-temperature control state from the light temperature control state.
[0027] It should be noted that when the solid-state storage device 10 is actually running, the temperature of the non-volatile memory 108 does not necessarily increase or decrease according to the first scenario or the second scenario, that is, the temperature control state of the solid-state storage device 10 is determined based on the increase or decrease of the current temperature T and the temperature threshold interval in which the current temperature T falls, as the current temperature control state. For example, assuming that the solid-state storage device 10 is already in the heavy temperature control state, when the controller 102 determines that the current temperature T of the non-volatile memory 108 is greater than or equal to the temperature threshold T3 and less than the temperature threshold T4, the controller 102 controls the solid-state storage device 10 to enter the first protection state from the heavy temperature control state. If the overheat protection means corresponding to the first protection state can effectively reduce the temperature of the non-volatile memory 108, the current temperature T reported to the controller 102 by the temperature sensor 110 will also gradually decrease. When the controller 102 determines that the current temperature T of the non-volatile memory 108 is less than the temperature threshold T2 and greater than the temperature threshold T1, the controller 102 controls the solid-state storage device 10 to return from the first protection state to the heavy temperature control state. Similarly, if the overheat protection means corresponding to the heavy temperature control state can also effectively reduce the temperature of the non-volatile memory 108, the current temperature T reported to the controller 102 by the temperature sensor 110 will also gradually decrease. When the controller 102 determines that the current temperature T of the non-volatile memory 108 is less than the temperature threshold T1 and greater than the temperature threshold T0, the controller 102 controls the solid-state storage device 10 to enter the light temperature control state from the heavy temperature control state.
[0028] The embodiment of the above-mentioned multi-stage temperature control method is to set multiple temperature thresholds and their corresponding temperature control states, and then determine the temperature control state according to the detected current temperature T as the current temperature control state to reduce the temperature of the non-volatile memory 108. This embodiment can effectively achieve a balance between cooling and performance in the case where the temperature rises or falls gradually. However, in the case of a rapid rise or fall in temperature, for example, when the current temperature T rises from the temperature threshold T1 to the temperature threshold T4 in a short period of time, the non-volatile memory 108 is equivalent to directly switching from the mild temperature control state to the second protection state, which will cause a rapid drop in performance. Therefore, the present invention further proposes a dynamic temperature control method for a solid-state storage device, by setting a temperature control state table and using the temperature cumulative value T acc To determine the temperature control state as the current temperature control state to avoid disrupting the balance between cooling and performance due to rapid temperature changes.
[0029] Figure 3 This is a flow chart of a dynamic temperature control method for a solid state storage device according to another embodiment of the present invention. Figure 1 and Figure 3.
[0030] In this embodiment, the solid state storage device 10 has a temperature control state table, as shown in Table 1. The temperature control state table includes a non-temperature control state (state 0) and multiple temperature control states, wherein the temperature control states include at least six states, and each temperature control state has a corresponding state value and overheat protection means. In the embodiment of Table 1, the temperature control states include states 1 to 19, and each state has a corresponding overheat protection means as shown in Table 1.
[0031]
[0032] Table 1
[0033] In some embodiments, the number of segments of the first clock signal CLK1 and the second clock signal CLK2 in Table 1 represents the frequency division ratio. In other embodiments, the number of segments of the first clock signal CLK1 and the second clock signal CLK2 in Table 1 represents the frequency reduction ratio corresponding to the number of segments. In detail, in Table 1, only state 0 represents the full speed operation state, and the number of segments of the first clock signal CLK1 and the second clock signal CLK2 is 1, which means that the controller 102 and the non-volatile memory 108 can operate at full speed. In states 1 to 15, the number of segments of the first clock signal CLK1 and the second clock signal CLK2 increases with the state value. In other words, in states 1 to 15, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 decrease as the state value increases. In states 16 to 19, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 are the same as those in state 15.
[0034] In addition to reducing the frequencies of the first clock signal CLK1 and the second clock signal CLK2, in states 16 to 19, additional overheat protection means are performed on the controller 102 to further reduce the temperature of the non-volatile memory 108 or the solid-state storage device 10. For example, state 16 is, for example, the fourth highest state, and compared to state 15, state 16 additionally activates an overheat protection means of increasing the receiving delay, wherein increasing the receiving delay means increasing the delay time for the controller 102 to capture the access command from the host 20. State 17 is, for example, the third highest state, and compared to state 16, state 17 additionally activates an overheat protection means of increasing the sending delay, wherein increasing the sending delay means increasing the delay time for the controller 102 to send the access command to the non-volatile memory 108.
[0035] State 18 is, for example, the second highest state, and compared to state 17, state 18 additionally activates an overheat protection means of aborting a host command. For example, aborting a host command means that the controller 102 can stop fetching access commands from the host 20 or stop executing the fetched access commands. State 19 is, for example, the highest state, and compared to state 18, state 19 additionally activates stopping the execution of firmware event 1 and firmware event 2, wherein the above-mentioned firmware event 1 and firmware event 2 represent firmware events executed in the background, such as garbage collection and erase virtual blocks, etc. It should be noted that the firmware event 1 and firmware event 2 that are stopped in state 19 are only for illustration purposes, but the present invention is not limited thereto. In addition, the number of temperature control states in Table 1 and the corresponding overheat protection means included in each temperature control state are only for illustration purposes, and the present invention is not limited thereto.
[0036] If Figure 2 The non-temperature control state and various temperature control states described in the embodiments are Figure 3 Compared with the temperature control state table (Table 1) of the embodiment, Figure 2 The no temperature control state, the light temperature control state, the heavy temperature control state, the first protection state, the second protection state and the overheating state of the embodiment may correspond to Figure 3 State 0, state 8, state 11, state 17, state 18 and state 19 of the temperature control state table (Table 1) of the embodiment. Figure 3 The embodiment of the dynamic temperature control method sets more temperature control states and uses the temperature accumulation value T acc To determine the temperature control state, as the current temperature control state, the details are as follows.
[0037] Please also refer to Figure 1 and Figure 3 , in step 302, the process starts, and at this time the solid-state storage device 10 is in state 0. In step 304, the controller 102 obtains the current temperature Temp of the non-volatile memory 108 from the temperature sensor 110. In step 306, the controller 102 determines whether the current temperature Temp is greater than the temperature threshold T0. When the controller 102 determines that the current temperature Temp is greater than the temperature threshold T0, the process proceeds to step 308. When the controller 102 determines that the current temperature Temp is not greater than the temperature threshold T0, the process returns to step 304 to re-obtain the current temperature Temp of the non-volatile memory 108.
[0038] In step 308, the controller 102 controls the solid state storage device 10 to enter state 1. Specifically, the temperature threshold T0 represents the temperature threshold value for starting the dynamic temperature control mechanism. When the solid state storage device 10 enters state 1, the controller 102 controls the clock generator 112 to reduce the frequencies of the first clock signal CLK1 and the second clock signal CLK2 to meet the clock frequency requirements of state 1 by referring to the temperature control state table (Table 1).
[0039] In step 310, the temperature difference T is obtained. gap And the temperature accumulation value T acc For example, the controller 102 may periodically receive the current temperature Temp of the non-volatile memory 108 reported by the temperature sensor 110, and the controller 102 may record the previous temperature Temp_pre received last time in the register, and may calculate the temperature accumulation value T acc Stored in the register. Temperature difference T gap And the temperature accumulation value T acc For example, it can be expressed by formula (1) and formula (2) respectively:
[0040] T gap = Temp-Temp_pre (1)
[0041] T acc =T acc +T gap (2)
[0042] In detail, the temperature difference T gap Indicates the difference between the current temperature Temp and the previous temperature Temp_pre, and the temperature accumulation value T acc Indicates the temperature difference T gap The current accumulated value.
[0043] In step 312, the controller 102 determines whether the current state is a maximum value. That is, the controller 102 can determine whether the current state is the highest state (e.g., state 19). When the controller 102 determines that the current state is a maximum value, the process proceeds to step 324. When the controller 102 determines that the current state is not a maximum value, the process proceeds to step 314.
[0044] Specifically, when the controller 102 determines that the current state is not the maximum value, the controller 102 may determine the temperature control state according to the state value increment table shown in Table 2 as the current temperature control state. Table 2 includes the temperature accumulation value T acc The corresponding relationship with the state value increment. According to the embodiment of Table 2, it corresponds to Figure 3 The steps of the process are described below.
[0045] Temperature accumulation value Tacc range Status value increment Tacc<=N1 0 N1 <Tacc<=N2 1 Tacc>N2 3
[0046] Table 2
[0047] In step 314, the controller 102 determines the temperature accumulation value T acc When the controller 102 determines whether the temperature accumulation value T acc is greater than the first value N1, the process proceeds to step 316. When the controller 102 determines that the temperature accumulation value T acc If the value is not greater than the first value N1, the process returns to step 310. In some embodiments, the first value N1 is equal to 3, for example.
[0048] In step 316, the controller 102 determines the temperature accumulation value T acc When the controller 102 determines whether the temperature accumulation value T acc is greater than the first value N2, the process proceeds to step 320. When the controller 102 determines that the temperature accumulation value T acc If the second value N2 is not greater than the first value N1, the process proceeds to step 318. In some embodiments, the second value N2 is equal to 5, for example.
[0049] In step 318, the controller 102 adds 1 to the current state value. If the previous embodiment state is continued, the temperature control state will switch from state 1 to state 2. In step 320, the controller 102 adds 3 to the current state value. If the previous embodiment state is continued, the temperature control state will switch from state 1 to state 4. In step 322, the controller 102 resets the temperature accumulation value T acc , for example reset to 0.
[0050] Specifically, in the process of steps 314 to 322, the temperature accumulation value T acc Refer to Table 2 to perform the corresponding steps. If the temperature of the non-volatile memory 108 rises gradually, the controller 102 obtains the current temperature Temp of the non-volatile memory 108 each time and calculates the temperature difference T gap may be very small values, and the temperature accumulation value T acc It will also increase slowly. If the temperature accumulation value T acc is not greater than the first value N1, the controller 102 can re-obtain the current temperature Temp of the non-volatile memory 108 and calculate the temperature difference T gap And the temperature accumulation value T acc When the temperature accumulation value T acc When the temperature is greater than the first value and not greater than the second value, the controller 102 increases the current state value by 1 (eg, step 318 ) to slowly change the temperature control state.
[0051] If the temperature of the non-volatile memory 108 rises rapidly, the controller 102 obtains the current temperature Temp of the non-volatile memory 108 and calculates the temperature difference T gap It is likely to be a larger value, and the temperature accumulation value T acc When the temperature accumulation value T acc When the current state value is greater than the second value, the controller 102 increases the current state value by 3 (e.g., step 320) to quickly change the temperature control state. After executing step 318 or 320 to increase the state value, the controller 102 will increase the temperature accumulation value T acc Reset to 0.
[0052] According to the above, the relationship between the temperature change range and the state value change range can be determined in Table 2. The present invention is not limited to the embodiment of Table 2, and those skilled in the art can set a suitable state value increment table according to actual conditions, as shown in another embodiment of Table 3, where the values of N1 to N3 can also be set according to actual conditions.
[0053] Temperature accumulation value Tacc range Status value increment Tacc <N1 0 N1≤Tacc<N2 1 N2≤Tacc<N3 3 Tacc≥N3 4
[0054] Table 3
[0055] Similarly, when the controller 102 determines that the current state is the maximum value, the controller 102 can determine the temperature control state according to the state value reduction table in Table 4 as the current temperature control state. Table 4 includes the temperature accumulation value T acc The corresponding relationship with the state value decrement. According to the embodiment of Table 4, it corresponds to Figure 3 The steps of the process are described below.
[0056] Temperature accumulation value Tacc range Decrement of status value Tacc <M1 1
[0057] Table 4
[0058] In step 324, the controller 102 determines the temperature accumulation value T acc When the controller 102 determines whether the temperature accumulation value T acc is less than the third value M1, the process proceeds to step 326. When the controller 102 determines that the temperature accumulation value T acc is not less than the third value M1, the process returns to step 310. In some embodiments, the third value M1 is, for example, equal to -2. Specifically, because the third value M1 is a negative value, if the temperature accumulation value T acc is less than the third value M1, it means that the temperature difference T calculated by the controller 102 at the current time point gap A negative value means that the current temperature Temp of the non-volatile memory 108 is lower than the previous temperature Temp_pre.
[0059] In step 326, the controller 102 decrements the current state value by 1. In step 328, the controller 102 resets the temperature accumulation value T acc , for example, reset to 0. In step 330, the controller 102 determines whether the current state is state 0. When the controller 102 determines that the current state is state 0, the process returns to step 306. When the controller 102 determines that the current state is not state 0, the process returns to step 310.
[0060] Specifically, the controller 102 may adopt a more conservative strategy when lowering the temperature control state of the solid state storage device 10. Even if the temperature accumulation value calculated at the current time point is much smaller than the third value M1, the controller 102 only reduces the state value by 1 at a time. After the above calculation, if the temperature control state of the solid state storage device is not state 0 (for example, in states 1 to 19), then Figure 3 The process may return to step 310 and then go through steps 312, 324 and 326 to reduce the state value.
[0061] Similarly, according to the above embodiment, Table 4 can determine the relationship between the temperature change range and the state value change range. The present invention is not limited to the embodiment of Table 4, and those skilled in the art can set a suitable state value reduction table according to actual conditions, such as another embodiment shown in Table 5, in which the values of M1-M2 can also be set according to actual conditions.
[0062] Temperature accumulation value Tacc range Decrement of status value Tacc <M1 3 M1≤Tacc<M2 1
[0063] Table 5
[0064] Figure 4 According to the present invention Figure 2 and Figure 3 Schematic diagram showing the performance comparison of the methods of the embodiments. Figure 5 According to the present invention Figure 2 and Figure 3 Schematic diagram of temperature comparison of the method of the embodiment. Please also refer to Figure 2 to Figure 5 .
[0065] In some embodiments, when the solid-state storage device 10 is used in the same test conditions Figure 2 Multi-stage temperature control method and Figure 3 Dynamic temperature control method can measure its performance and temperature to obtain Figure 4 and Figure 5 . Figure 4 Curves 402 and 404 in FIG. 4 represent Figure 3 and Figure 2 the effectiveness of the method. Figure 5 The curves 502 and 504 in FIG. Figure 3 and Figure 2 The temperature of the method.
[0066] In detail, Figure 3 The dynamic temperature control method has a larger number of temperature control states, and the controller 102 determines the temperature control state based on the difference between the current temperature and the previous temperature of the non-volatile memory 108. In addition, Figure 3 The difference in overheat protection means between two consecutive states of the dynamic temperature control method is relatively subtle.
[0067] Figure 2 The temperature control state of the multi-stage temperature control method is only divided into a light temperature control state, a heavy temperature control state, a first protection state, a second protection state and an overheating state, and the switching between the above temperature control states is determined by a fixed temperature threshold (such as Figure 2 The temperature thresholds T0 to T5 are determined by Figure 2 The temperature control method has obvious differences in overheat protection measures between two consecutive states.
[0068] like Figure 4 As shown, at time t2, when Figure 3 When the dynamic temperature control method enters state 3, Figure 2 The multi-stage temperature control method has entered a mild temperature control state, which is equivalent to Figure 3 State 8 of the dynamic temperature control method of the present invention. For example, the number of segments of the first clock signal CLK1 and the second clock signal CLK2 in state 3 is equal to 4, and the number of segments of the first clock signal CLK1 and the second clock signal CLK2 in state 8 is equal to 9. If the above number of segments represents the frequency division ratio, the performance of the solid-state storage device 10 in state 3 is more than twice that in state 8.
[0069] At time t3, when Figure 3 When the dynamic temperature control method enters state 4, Figure 2 The multi-stage temperature control method still maintains the light temperature control state. For example, the number of stages of the first clock signal CLK1 and the second clock signal CLK2 in state 4 is equal to 5, and the number of stages of the first clock signal CLK1 and the second clock signal CLK2 in state 8 is equal to 9. If the above number of stages represents the frequency division ratio, the performance of the solid-state storage device 10 in state 3 is approximately twice that of the performance in state 8.
[0070] For temperature control, see Figure 5 . Figure 2 The multi-stage temperature control method directly enters the mild temperature control state from time t2 and causes the temperature to drop directly, such as the temperature change of curve 504 between time t2 and time t3. Figure 3Although the dynamic temperature control method enters state 3 and state 4 at time t2 and time t3 respectively, the cooling effect produced by the overheat protection means in state 3 and state 4 is not strong. Therefore, as shown by the temperature change of curve 502 between time t2 and time t4, Figure 3 The effect of the dynamic temperature control method is mainly to slow down the rate of temperature rise, so that a certain performance can be maintained while avoiding the situation where the performance needs to be sacrificed to cool down due to excessive temperature rise.
[0071] Therefore, compared to Figure 2 Multi-stage temperature control method, Figure 3 Although the dynamic temperature control method has higher temperature (such as Figure 5 curve 502), but has better performance (such as Figure 4 402). Figure 3 The dynamic temperature control method can be fine-tuned at any time according to the current temperature T, and the temperature change range is controlled within a certain range. Correspondingly, the performance change range is also controlled within a certain range, so that a certain balance is achieved between temperature and performance.
[0072] Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the appended claims.
[0073] Explanation of symbols
[0074] 1 Computer System
[0075] 10 Solid-state storage device
[0076] 11 Bus
[0077] 20 Host
[0078] 102 Controller
[0079] 106 Volatile Memory
[0080] 108 Non-volatile memory
[0081] 110 Temperature sensor
[0082] 112 Clock Generator
[0083] 202 Processor
[0084] 204 System Memory
[0085] 2041 Submission Queue
[0086] 2042 Completed Queue
[0087] 2043 Data Buffer
[0088] Steps 302-330
[0089] 402, 404, 502, 504 curves
[0090] CLK1 First clock signal
[0091] CLK2 Second clock signal
[0092] N1 first value
[0093] N2 Second value
[0094] M1 Third value
[0095] N3, M2 values
[0096] T Current temperature
[0097] T0-T5 temperature threshold
[0098] Tgap temperature difference
[0099] t1-tn time
Claims
1. A solid-state storage device, comprising: Non-volatile memory; A temperature sensor configured to periodically detect a current temperature of the non-volatile memory; as well as A controller, electrically connected to the non-volatile memory and the temperature sensor, configured to obtain the current temperature from the temperature sensor at regular intervals; Wherein, the controller is configured to activate a dynamic temperature control mechanism of the solid-state storage device, and the dynamic temperature control mechanism includes a temperature control state table, and the temperature control state table includes a plurality of temperature control states and their corresponding state values; Wherein, the controller is further configured to calculate a temperature difference between the current temperature and a previous temperature of the non-volatile memory, and accumulate the temperature difference to obtain a temperature accumulation value; and The controller is further configured to determine the current temperature control state from the temperature control state table according to the temperature accumulation value.
2. The solid-state storage device according to claim 1, wherein: When the controller determines that the current temperature is greater than a first temperature threshold, the controller is configured to activate the dynamic temperature control mechanism of the solid-state storage device.
3. The solid-state storage device of claim 1 , further comprising a clock generator configured to provide a first clock signal to the controller and a second clock signal to the non-volatile memory, wherein the frequency of the first clock signal is greater than the second clock signal, wherein, The number of segments of the first clock signal and the second clock signal is determined by the current temperature control state.
4. The solid-state storage device according to claim 3, wherein: The number of segments of the first clock signal and the second clock signal represents the frequency division ratios of the first clock signal and the second clock signal.
5. The solid-state storage device according to claim 3, wherein: The number of segments of the first clock signal and the second clock signal represents a down-clocking ratio of the first clock signal and the second clock signal.
6. The solid-state storage device according to claim 1, wherein: When the controller is configured to start the dynamic temperature control mechanism, the controller sets an initial temperature control state from the temperature control states in the temperature control state table as the current temperature control state, wherein the state value corresponding to the initial temperature control state is 1.
7. The solid-state storage device according to claim 1, wherein: The dynamic temperature control mechanism further includes a state value increment table, the controller is further configured to determine whether the current state value corresponding to the current temperature control state is a maximum value, and when the controller determines that the current state value is not the maximum value, the controller is further configured to determine the state value increment according to the temperature accumulation value and the state value increment table; The controller is further configured to add the state value increment to the current state value as the current state value, and reset the temperature accumulation value.
8. The solid-state storage device according to claim 7, wherein: The dynamic temperature control mechanism further includes a state value decrement table, and when the controller determines that the current state value is equal to the maximum value, the controller is further configured to determine the state value decrement according to the temperature accumulation value and the state value decrement table; as well as The controller is further configured to subtract the state value decrement from the current state value as the current state value, and reset the temperature accumulation value.
9. A dynamic temperature control method for a solid-state storage device, wherein the solid-state storage device comprises a controller, a temperature sensor and a non-volatile memory, the method comprising: Using the temperature sensor to periodically detect the current temperature of the non-volatile memory; Using the controller to periodically obtain the current temperature from the temperature sensor; Using the controller to start a dynamic temperature control mechanism of the solid-state storage device, wherein the dynamic temperature control mechanism includes a temperature control state table, the temperature control state table includes a plurality of temperature control states and their corresponding state values; Utilizing the controller to calculate a temperature difference between the current temperature and a previous temperature of the non-volatile memory, and accumulating the temperature difference to obtain a temperature accumulation value; as well as The controller is used to determine the current temperature control state from the temperature control state table according to the temperature accumulation value.
10. The dynamic temperature control method according to claim 9, wherein: When the controller determines that the current temperature is greater than a first temperature threshold, the controller is used to activate the dynamic temperature control mechanism of the solid state storage device.
11. The dynamic temperature control method according to claim 9, wherein: The solid-state storage device further includes a clock generator, and the method further includes: using the clock generator to provide a first clock signal to the controller, and providing a second clock signal to the non-volatile memory, wherein the frequency of the first clock signal is greater than the second clock signal, and wherein the number of segments of the first clock signal and the second clock signal is determined by the current temperature control state.
12. The dynamic temperature control method according to claim 11, wherein: The number of segments of the first clock signal and the second clock signal represents the frequency division ratios of the first clock signal and the second clock signal.
13. The dynamic temperature control method according to claim 11, wherein: The number of segments of the first clock signal and the second clock signal represents a down-clocking ratio of the first clock signal and the second clock signal.
14. The dynamic temperature control method according to claim 9, wherein: When the controller starts the dynamic temperature control mechanism, the controller sets an initial temperature control state from the temperature control states in the temperature control state table as the current temperature control state, wherein the state value corresponding to the initial temperature control state is 1.
15. The dynamic temperature control method according to claim 9, wherein: The dynamic temperature control mechanism further includes a state value increment table, and the method further includes: Using the controller to determine whether the current state value corresponding to the current temperature control state is a maximum value; When the controller determines that the state value is not the maximum value, the controller is used to determine the state value increment by comparing the state value increment table according to the temperature accumulation value; and The controller is used to add the state value increment to the current state value as the current state value, and reset the temperature accumulation value.
16. The dynamic temperature control method according to claim 15, wherein: The dynamic temperature control mechanism further includes a state value decrement table, and the method further includes: When the controller determines that the current state value is equal to the maximum value, the controller is used to determine a state value decrement by comparing the state value decrement table according to the temperature accumulation value; and The controller is used to subtract the state value decrement from the current state value as the current state value, and reset the temperature accumulation value.