Semiconductor device and method of manufacturing the same
By designing contact holes in the interlayer dielectric layer and the first hard mask layer, making the width of the side closer to the gate structure, source region, or drain region smaller than the side farther away from these two regions, the problem of large parasitic capacitance in the vertical contact hole process is solved, thereby reducing parasitic capacitance and improving process efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN XINXIN SEMICON MFG CO LTD
- Filing Date
- 2024-11-14
- Publication Date
- 2026-05-29
Smart Images
Figure CN119560481B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] In semiconductor manufacturing, it is usually necessary to form contact holes in ILD (Inter Layer Dielectric) and then fill them with metals such as tungsten to achieve electrical connection between the bottom and top conductive dielectrics, such as the electrical connection between a transistor and a metal interconnect layer.
[0003] Most current contact holes are vertical contact holes. As chip size becomes smaller and smaller, the size of transistors in the chip and the distance between transistors also become smaller. Existing vertical contact hole technology is difficult to achieve contact hole etching and filling with metals such as tungsten, resulting in a large parasitic capacitance between the contact hole and the gate structure, which affects the performance of semiconductor devices. Summary of the Invention
[0004] This application provides a semiconductor device and a method for fabricating the same, which reduces the size of the contact hole near the gate structure, source region, or drain region, increases the contact hole photolithography process window, and reduces the parasitic capacitance between the contact hole and the gate.
[0005] To address the aforementioned technical problems, this application provides a semiconductor device, comprising: a semiconductor substrate including a first surface; a transistor structure including a gate structure, a source region, and a drain region, wherein the gate structure is formed on the first surface of the semiconductor substrate, and the source region and the drain region are formed in the semiconductor substrate and exposed through the first surface; a first hard mask layer disposed on the transistor structure; an interlayer dielectric layer disposed on the first hard mask layer; and a contact hole penetrating the interlayer dielectric layer and the first hard mask layer, exposing at least one of the gate structure, the source region, and the drain region; wherein the etching selectivity of the material of the interlayer dielectric layer is higher than that of the material of the first hard mask layer, and the width of a first portion of the contact hole near the gate structure, the source region, or the drain region is smaller than the width of a second portion of the contact hole away from the gate structure, the source region, or the drain region.
[0006] In some embodiments, the contact hole includes a gate contact hole, a source contact hole, or a drain contact hole; wherein the gate contact hole is used to expose the gate structure, the source contact hole is used to expose the source region, and the drain contact hole is used to expose the drain region.
[0007] In some embodiments, the gate contact hole, the source contact hole, or the drain contact hole are formed simultaneously.
[0008] In some embodiments, the second portion of the contact hole is formed in the interlayer dielectric layer, and the first portion includes a first sub-portion formed in the first hard mask layer; the width of at least a portion of the first sub-portion in the first hard mask layer gradually decreases from the direction away from the semiconductor substrate to the direction near the semiconductor substrate.
[0009] In some embodiments, the semiconductor device further includes: a planarization layer disposed between the semiconductor substrate and the first hard mask layer, and located on the source region and the drain region; the upper surface of the gate structure and the upper surface of the planarization layer are at the same horizontal plane.
[0010] In some embodiments, the contact hole also extends through the planarization layer, and the first portion of the contact hole further includes a second sub-portion formed in the planarization layer to expose the source region or the drain region; the width of the second sub-portion is not greater than the minimum width of the first sub-portion.
[0011] In some embodiments, the semiconductor device further includes: a resistive structure disposed on a portion of the first hard mask layer; wherein the resistive structure includes: a resistive layer disposed on a portion of the first hard mask layer; a first dielectric layer disposed on the resistive layer; and a second hard mask layer disposed on the first dielectric layer; wherein at least a portion of the interlayer dielectric layer is disposed on the second hard mask layer, and the etching selectivity of the material of the second hard mask layer is lower than the etching selectivity of the material of the interlayer dielectric layer.
[0012] In some embodiments, the contact hole further includes a resistive device contact hole that penetrates the interlayer dielectric layer, the second hard mask layer, and the first dielectric layer on the resistive structure to expose the resistive layer; the width of the first portion of the resistive device contact hole near the resistive layer is smaller than the width of the second portion of the resistive device contact hole away from the resistive layer.
[0013] To address the aforementioned technical problems, this application also provides a method for fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a transistor structure on the semiconductor substrate, the transistor structure including a gate structure, a source region, and a drain region; sequentially forming a first hard mask layer and an interlayer dielectric layer on the semiconductor substrate and the transistor structure; etching the interlayer dielectric layer and the first hard mask layer to form a contact hole, the contact hole exposing at least one of the gate structure, the source region, and the drain region; wherein the etching selectivity of the material of the interlayer dielectric layer is higher than the etching selectivity of the material of the first hard mask layer, and the width of a first portion of the contact hole near the gate structure, the source region, or the drain region is smaller than the width of a second portion of the contact hole away from the gate structure, the source region, or the drain region.
[0014] In some embodiments, after forming the first hard mask layer and before forming the interlayer dielectric layer, the method further includes: forming a resistive structure, the resistive structure including a resistive layer, a first dielectric layer and a second hard mask layer, wherein the etching selectivity of the material of the second hard mask layer is lower than the etching selectivity of the material of the interlayer dielectric layer; the etching of the interlayer dielectric layer and the first hard mask layer to form a contact hole further includes: etching the interlayer dielectric layer on the resistive structure and the resistive structure to form a resistive device contact hole, wherein the width of a first portion of the resistive device contact hole near the resistive layer is smaller than the width of a second portion of the resistive device contact hole away from the resistive layer.
[0015] This application provides a semiconductor device and a method for fabricating the same. The semiconductor device includes: a semiconductor substrate with a first surface; a transistor structure including a gate structure, a source region, and a drain region, wherein the gate structure is formed on the first surface of the semiconductor substrate, and the source and drain regions are formed in the semiconductor substrate and exposed through the first surface; a first hard mask layer disposed on the transistor structure; an interlayer dielectric layer disposed on the first hard mask layer; and a contact hole penetrating the interlayer dielectric layer and the first hard mask layer, exposing at least one of the gate structure, the source region, and the drain region. The etching selectivity of the interlayer dielectric layer is higher than that of the first hard mask layer, and the width of a first portion of the contact hole near the gate structure, the source region, or the drain region is smaller than the width of a second portion of the contact hole away from the gate structure, the source region, or the drain region. This reduces the size of the contact hole near the gate structure, the source region, or the drain region, increases the contact hole's photolithography window, and simultaneously reduces the parasitic capacitance between the contact hole and the gate. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0017] Figure 1 This is a schematic diagram of the structure of a semiconductor device and its contact holes in the prior art;
[0018] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application;
[0019] Figure 3 A schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this application;
[0020] Figure 4 The semiconductor devices provided in some embodiments of this application have been modified. Figure 3 A schematic diagram of the structure after step S1, in which the first hard mask layer is formed;
[0021] Figure 5 A schematic diagram of a semiconductor device forming a resistive structure provided in some embodiments of this application;
[0022] Figure 6 The semiconductor devices provided in some embodiments of this application have been... Figure 3 A schematic diagram of the structure formed after step S2. Detailed Implementation
[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0024] The terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0025] In this application, all directional indicators (such as up, down, left, right, front, back, top, bottom, etc.) are only used to explain the relative positional relationship and movement of each component in a specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0026] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.
[0027] Unless otherwise defined, the term “approximately” as used in this application can be understood, in relation to numerical quantities or quantitative relationships, as a range of approximately ±15% of a given value.
[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0029] See Figure 1 , Figure 1 This is a schematic diagram of the structure of a semiconductor device and its contact holes in the prior art. (Example:) Figure 1 As shown, the contact hole 91 of the current semiconductor device 90 is a vertical contact hole. As the chip size gradually decreases, it is difficult to achieve etching of the contact hole 91 and filling of metals such as tungsten with this vertical contact hole process. This results in a large parasitic capacitance between the contact hole 91 and the gate structure 92, which affects the performance of the semiconductor device 90.
[0030] To address the aforementioned technical problems, this application provides a semiconductor device 100, see [link to relevant documentation]. Figure 2 , Figure 2This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application. The semiconductor device 100 includes a semiconductor substrate 110 and a transistor structure 120. The semiconductor substrate 110 includes a first surface 111, and the transistor structure 120 includes a gate structure 121, a source region 122, and a drain region 123. The gate structure 121 is formed on the first surface 111 of the semiconductor substrate 110, and the source region 122 and drain region 123 are formed on the side of the semiconductor substrate 110 near the first surface 111 and exposed through the first surface 111. Further, the semiconductor device 100 also includes a first hard mask layer 130 and an interlayer dielectric layer 140. The first hard mask layer 130 is disposed on the transistor structure 120, such as... Figure 2 As shown, in some embodiments, the first hard mask layer 130 is in direct contact with the gate structure 121; the interlayer dielectric layer 140 is disposed on the first hard mask layer 130. The contact hole 150 penetrates the interlayer dielectric layer 140 and the first hard mask layer 130, and exposes at least one of the gate structure 121, the source region 122, and the drain region 123. In this application, the etching selectivity of the interlayer dielectric layer 140 is higher than that of the first hard mask 130. Specifically, when the semiconductor device 100 etches to form the contact hole 150, whether using the same etching gas for dry etching or chemical reagents for wet etching, the etching rate of the interlayer dielectric layer 140 is greater than the etching rate of the first hard mask layer 130. This results in the width of the first portion 151 of the contact hole 150 near the gate structure 121, source region 122, or drain region 123 being smaller than the width of the second portion 152 of the contact hole 150 away from the gate structure 121, source region 122, or drain region 123. Therefore, the semiconductor device 100 provided by this application reduces the size of the contact hole 150 near the gate structure 121, source region 122, or drain region 123, increases the photolithography window of the contact hole 150, and thus reduces the parasitic capacitance between the contact hole 150 and the gate structure 121, improving the performance of the semiconductor device 100.
[0031] In some embodiments, the interlayer dielectric layer 140 is made of a low dielectric constant material such as silicon dioxide, BD1 (Black Diamond 1), or BD2 (Black Diamond 2), and the thickness of the interlayer dielectric layer 140 is [missing information]. The first hard mask layer 130 is made of materials with a lower etching selectivity than silicon dioxide, such as NIT, SiC, or Si. The thickness of the first hard mask layer 130 is... See Figure 2In some embodiments, the contact hole 150 includes a gate contact hole 153, a source contact hole 154, and / or a drain contact hole 155. The gate contact hole 153 exposes the gate structure 121, the source contact hole 154 exposes the source region 122, and the drain contact hole 155 exposes the drain region 123. This allows the gate contact hole 153, the source contact hole 154, and / or the drain contact hole 155 to be filled with a metal such as tungsten, enabling electrical connection between the gate structure 121, the source region 122, and the drain region 123 and the upper conductive material. In some embodiments, the gate contact hole 153, the source contact hole 154, and / or the drain contact hole 155 are formed by simultaneous etching to reduce process steps and improve semiconductor process efficiency.
[0032] See also Figure 2 In some embodiments, the contact hole 150 includes a first portion 151 and a second portion 152, the second portion 152 being formed in the interlayer dielectric layer 140, and the first portion 151 including a first sub-portion 1511 and a second sub-portion 1512, wherein the first sub-portion 1511 is formed in the first hard mask layer 130. Furthermore, since the etching selectivity of the material of the interlayer dielectric layer 140 is higher than that of the material of the first hard mask layer 130, when etching the semiconductor device 100 to form the contact hole 150, the etching rate of the etching gas or chemical reagent from the interlayer dielectric layer 140 to the first hard mask layer 130 decreases, and the polymer generated during etching gradually accumulates at the first hard mask layer 130. This results in at least a portion of the width of the first sub-portion 1511 located in the first hard mask layer 130 gradually decreasing in the direction from away from the semiconductor substrate 110 to near the semiconductor substrate 110.
[0033] See also Figure 2 In some embodiments, the semiconductor device 100 further includes a planarization layer 160 disposed between the semiconductor substrate 110 and the first hard mask layer 130, and located on the source region 122 and the drain region 123. The upper surface of the gate structure 121 is at the same level as the upper surface of the planarization layer 160, so that the first hard mask layer 130 can be formed on the transistor structure 120 and in direct contact with the gate structure 121. In some embodiments, the material of the planarization layer 160 is the same as the material of the interlayer dielectric layer 140. In some embodiments, contact holes 150, particularly source contact holes 154 and drain contact holes 155, penetrate the planarization layer 160. Second sub-partitions 1512a of the first portion 151a of the source contact holes 154 and drain contact holes 155 are formed in the planarization layer 160 to expose the source region 122 and drain region 123, respectively, and the width of the second sub-partition 1512a is not greater than the width of the first sub-partition 1511a. In some embodiments, such as... Figure 2As shown, the second sub-portion 1512b of the gate contact hole 153 extends into the gate structure 121.
[0034] See also Figure 2 In some embodiments, the semiconductor device 100 further includes a resistive structure 170 disposed on a portion of the first hard mask layer 130. The resistive structure 170 can function as a voltage divider and current limiter. In some embodiments, the resistive structure 170 includes a resistive layer 171, a first dielectric layer 172, and a second hard mask layer 173. In this embodiment, a resistive layer 171 is disposed on a portion of the first hard mask layer 130; a first dielectric layer 172 is disposed on the resistive layer 171. In some embodiments, the material of the first dielectric layer 172 is the same as that of the interlayer dielectric layer 140; a second hard mask layer 173 is disposed on the first dielectric layer 172, and the etching selectivity of the material of the second hard mask layer 173 is lower than that of the material of the interlayer dielectric layer 140. That is, when dry etching is performed using the same etching gas or wet etching is performed using chemical reagents, the etching rate of the gas or chemical reagents on the interlayer dielectric layer 140 is greater than the etching rate of the second hard mask layer 173. In some embodiments, the material of the second hard mask layer 173 is the same as that of the first hard mask layer 130. At least a portion of the interlayer dielectric layer 140 is disposed on the second hard mask layer 173, that is, the resistive structure 170 is covered by the interlayer dielectric layer 140. In some embodiments, the semiconductor device 100 further includes a dummy transistor, such as... Figure 2 As shown, the dummy gate structure 180 of the dummy transistor is disposed on the same layer as the gate structure 121, and the dummy gate structure 180 and the resistive structure 170 are disposed correspondingly in the thickness direction of the semiconductor device 100.
[0035] Further details can be found by referring to [link / reference]. Figure 2 In some embodiments, the contact hole 150 further includes a resistive device contact hole 156, which penetrates the interlayer dielectric layer 140, the second hard mask layer 173, and the first dielectric layer 172 on the resistive structure 170 to expose the resistive layer 171. This allows the resistive device contact hole 156 to be filled with a metal such as tungsten to achieve electrical connection between the resistive layer 171 and the upper conductive material. Similarly, the resistive device contact hole 156 includes a first portion 151c close to the resistive layer 171 and a second portion 152c away from the resistive layer 171. Because the etching selectivity of the material of the second hard mask layer 173 is lower than that of the material of the interlayer dielectric layer 140, the width of the first portion 151c of the resistive device contact hole 156 is smaller than the width of the second portion 152c.
[0036] To further address the aforementioned technical problems, this application also provides a method for fabricating a semiconductor device. See [link to application]. Figure 3 , Figure 3This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this application. The method for fabricating the semiconductor device includes:
[0037] Step S1: Provide a semiconductor substrate and form a transistor structure on the semiconductor substrate, the transistor structure including a gate structure, a source region and a drain region.
[0038] See Figure 4 , Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application after step S1 and the formation of a first hard mask layer. The semiconductor device 100 includes a semiconductor substrate 110, and a transistor structure 120 is formed on the first surface 111 of the semiconductor substrate 110. The transistor structure 120 includes a gate structure 121, a source region 122, and a drain region 123. In some embodiments, step S1 further includes forming a dummy transistor, wherein the dummy gate structure 180 in the dummy transistor is disposed on the same layer as the gate structure 121.
[0039] Step S2: A first hard mask layer and an interlayer dielectric layer are sequentially formed on the semiconductor substrate and the transistor structure.
[0040] See Figures 4-6 , Figure 5 A schematic diagram of a semiconductor device forming a resistive structure provided in some embodiments of this application; Figure 6 This is a schematic diagram of the structure of a semiconductor device formed after step S2 according to some embodiments of this application. A first hard mask layer 130 and an interlayer dielectric layer 140 are sequentially formed on the semiconductor substrate 110 and the transistor structure 120, and the etching selectivity of the material of the interlayer dielectric layer 140 is higher than that of the material of the first hard mask layer 130. In some embodiments, before forming the first hard mask layer 130, a planarization layer 160 is further formed on the semiconductor substrate 110, the source region 122, and the drain region 123. The upper surface of the gate structure 121 is at the same level as the upper surface of the planarization layer 160, and the material of the planarization layer 160 is the same as that of the interlayer dielectric layer 140. In some embodiments, after forming the first hard mask layer 130 and before forming the interlayer dielectric layer 140, a resistive structure 170 is further formed. Figure 4As shown, in some embodiments, forming the resistive structure 170 includes: sequentially forming a resistive material layer 171a, a first dielectric material layer 172a, a second hard mask material layer 173a, a first anti-reflective layer 191, and a patterned first photoresist layer 192 on a first hard mask layer 130; etching the first anti-reflective layer 191, the second hard mask material layer 173a, the first dielectric material layer 172a, and the resistive material layer 171a using the patterned first photoresist layer 192 as a mask; removing the first photoresist layer 192 and the remaining first anti-reflective layer 191; the remaining resistive layer 171, the first dielectric layer 172, and the second hard mask layer 173a form the resistive structure 170, which is disposed corresponding to the dummy gate structure 180 in the thickness direction of the semiconductor device 100. In some embodiments, the etching selectivity of the material of the second hard mask layer 173 is lower than the etching selectivity of the material of the interlayer dielectric layer 140. Interlayer dielectric layer 140 covers first hard mask layer 130 and resistive structure 170. First anti-reflective layer 191 is used to reduce light reflection that occurs during photolithography. In some embodiments, first anti-reflective layer 191 is BARC (Bottom Anti-reflective Coating).
[0041] Step S3: Etch the interlayer dielectric layer and the first hard mask layer to form a contact hole, the contact hole exposing at least one of the gate structure, the source region and the drain region.
[0042] See Figure 2 and Figure 6An amorphous carbon layer 193, a second anti-reflection layer 194, a first oxide layer 195, a third anti-reflection layer 196, and a patterned second photoresist layer 197 are sequentially formed on the interlayer dielectric layer 140. The patterned second photoresist layer 197 is used as a mask for etching to form a contact hole 150. Specifically, the third anti-reflection layer 196, the first oxide layer 195, the second anti-reflection layer 194, the amorphous carbon layer 193, the interlayer dielectric layer 140, and the first hard mask layer 130 are etched using the patterned second photoresist layer 197 as a mask to form a gate contact hole 153 exposing the gate structure 121; the third anti-reflection layer 196, the first oxide layer 195, the second anti-reflection layer 194, the amorphous carbon layer 193, and the interlayer dielectric layer 146 are etched using the patterned second photoresist layer 197 as a mask. 0. A first hard mask layer 130 and a planarization layer 160 are used to form source contact holes 154 and drain contact holes 155, respectively exposing source region 122 and drain region 123. Using a patterned second photoresist layer 197 as a mask, a third anti-reflection layer 196, a first oxide layer 195, a second anti-reflection layer 194, an amorphous carbon layer 193, an interlayer dielectric layer 140, a second hard mask layer 173, and a first dielectric layer 172 are etched to form resistive device contact holes 156, exposing resistive layer 171. The second photoresist layer 197, the third anti-reflection layer 196, the first oxide layer 195, the second anti-reflection layer 194, and the amorphous carbon layer 193 are removed to form... Figure 2 The semiconductor device structure is shown. As described above, since the etching selectivity of the material of the interlayer dielectric layer 140 is higher than that of the first hard mask layer 130 and the second hard mask layer 173, when dry etching is performed using the same etching gas or wet etching is performed using chemical reagents, the etching rate of the interlayer dielectric layer 140 by the gas or chemical reagents is greater than the etching rate of the first hard mask layer 130 and the second hard mask layer 173. Therefore, the gate contact hole 153, source contact hole 154, and drain contact hole 15... The width of the first portion 151 near the gate structure 121, source region 122, and drain region 123 is smaller than the width of the second portion 152 away from the gate contact hole 153, source contact hole 154, and drain contact hole 155; the width of the first portion 151c of the resistive device contact hole 156 near the resistive layer 171 is smaller than the width of the second portion 152c of the resistive device contact hole 156 away from the resistive layer 171. In some embodiments, the second antireflective layer 194 is the same as the first antireflective layer 191, and the third antireflective layer 196 is a DAR (Durable Anti-reflective Coating).
[0043] The semiconductor device 100 provided in this application includes: a semiconductor substrate 110 and a transistor structure 120. The semiconductor substrate 110 includes a first surface 111; the transistor structure 120 includes a gate structure 121, a source region 122, and a drain region 123, wherein the gate structure 121 is formed on the first surface 111 of the semiconductor substrate 110, and the source region 122 and drain region 123 are formed in the semiconductor substrate 110 and exposed through the first surface 111. Further, a first hard mask layer 130 is disposed on the transistor structure 120; an interlayer dielectric layer 140 is disposed on the first hard mask layer 130; a contact hole 150 penetrates the interlayer dielectric layer 140 and the first hard mask layer 130, and exposes at least one of the gate structure 121, the source region 122, and the drain region 123; wherein the etching selectivity of the material of the interlayer dielectric layer 140 is higher than that of the material of the first hard mask layer 130, so that the semiconductor device 100 is etched and formed... When contacting the via 150, whether dry etching is performed using the same etching gas or wet etching is performed using chemical reagents, the etching rate of the interlayer dielectric layer 140 by the gas or chemical reagents is greater than the etching rate of the first hard mask layer 130. This results in the width of the first portion 151 of the contact via 150 near the gate structure 121, source region 122, or drain region 123 being smaller than the width of the second portion 152 of the contact via 150 away from the gate structure 121, source region 122, or drain region 123. This reduces the size of the contact via 150 near the gate structure 121, source region 122, or drain region 123, increases the process window for photolithography of the contact via 150, and simultaneously reduces the parasitic capacitance between the contact via 150 and the gate 121.
[0044] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.
Claims
1. A semiconductor device, characterized in that, include: A semiconductor substrate, including a first surface; A transistor structure includes a gate structure, a source region, and a drain region, wherein the gate structure is formed on a first surface of the semiconductor substrate, and the source region and the drain region are formed in the semiconductor substrate and exposed through the first surface; A first hard mask layer is disposed on the transistor structure; An interlayer dielectric layer is disposed on the first hard mask layer; The contact hole penetrates the interlayer dielectric layer and the first hard mask layer, and exposes at least one of the gate structure, the source region, and the drain region; Wherein, the etching selectivity of the material of the interlayer dielectric layer is higher than that of the material of the first hard mask layer, and the width of the first part of the contact hole near the gate structure, the source region or the drain region is smaller than the width of the second part of the contact hole away from the gate structure, the source region or the drain region; The semiconductor device further includes: A resistive structure is disposed on a portion of the first hard mask layer; wherein the resistive structure includes: A resistive layer is disposed on a portion of the first hard mask layer; A first dielectric layer is disposed on the resistive layer; A second hard mask layer is disposed on the first dielectric layer; Wherein, at least a portion of the interlayer dielectric layer is disposed on the second hard mask layer; The contact hole also includes a resistive device contact hole, which penetrates the interlayer dielectric layer, the second hard mask layer, and the first dielectric layer on the resistive structure to expose the resistive layer; The width of the first portion of the resistive device contact hole near the resistive layer is smaller than the width of the second portion of the resistive device contact hole away from the resistive layer.
2. The semiconductor device according to claim 1, characterized in that, The contact hole includes a gate contact hole, a source contact hole, or a drain contact hole; The gate contact hole is used to expose the gate structure, the source contact hole is used to expose the source region, and the drain contact hole is used to expose the drain region.
3. The semiconductor device according to claim 2, characterized in that, The gate contact hole, the source contact hole, or the drain contact hole are formed simultaneously.
4. The semiconductor device according to claim 1, characterized in that, The second portion of the contact hole is formed in the interlayer dielectric layer, and the first portion includes a first sub-portion formed in the first hard mask layer; The width of at least a portion of the first sub-part in the first hard mask layer gradually decreases from the direction away from the semiconductor substrate to the direction closer to the semiconductor substrate.
5. The semiconductor device according to claim 4, characterized in that, Further includes: A planarization layer is disposed between the semiconductor substrate and the first hard mask layer, and is located on the source region and the drain region; The upper surface of the gate structure is on the same horizontal plane as the upper surface of the planarization layer.
6. The semiconductor device according to claim 5, characterized in that, The contact hole also penetrates the planarization layer, and the first portion of the contact hole further includes a second sub-portion formed in the planarization layer to expose the source region or the drain region; The width of the second sub-part is not greater than the minimum width of the first sub-part.
7. The semiconductor device according to claim 1, characterized in that, Also includes: The etching selectivity of the material of the second hard mask layer is lower than that of the material of the interlayer dielectric layer.
8. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, on which a transistor structure is formed, the transistor structure including a gate structure, a source region and a drain region; A first hard mask layer and an interlayer dielectric layer are sequentially formed on the semiconductor substrate and the transistor structure; The interlayer dielectric layer and the first hard mask layer are etched to form a contact hole, which exposes at least one of the gate structure, the source region, and the drain region; Wherein, the etching selectivity of the material of the interlayer dielectric layer is higher than that of the material of the first hard mask layer, and the width of the first part of the contact hole near the gate structure, the source region or the drain region is smaller than the width of the second part of the contact hole away from the gate structure, the source region or the drain region; After forming the first hard mask layer and before forming the interlayer dielectric layer, the method further includes: A resistive structure is formed, the resistive structure comprising: a resistive layer, a first dielectric layer, and a second hard mask layer; At least a portion of the interlayer dielectric layer is disposed on the second hard mask layer; The etching of the interlayer dielectric layer and the first hard mask layer to form a contact hole further includes: The interlayer dielectric layer on the resistive structure and the resistive structure are etched to form a resistive device contact hole. The width of the first portion of the resistive device contact hole near the resistive layer is smaller than the width of the second portion of the resistive device contact hole away from the resistive layer.
9. The manufacturing method according to claim 8, characterized in that, The etching selectivity of the material of the second hard mask layer is lower than that of the material of the interlayer dielectric layer.