A polymorphic asynchronous routing network device

Abstract

The application discloses a polymorphic asynchronous routing network architecture, comprising an input asynchronous bus, a fan-out layer, an intermediate layer, a fan-in layer, an output asynchronous bus and a configuration register; the fan-out layer is used for driving 1-in-2-out type asynchronous routing nodes in the layer to fan out event data packets on the input asynchronous bus to the intermediate layer; the intermediate layer is used for driving 2-in-2-out type asynchronous routing nodes in the layer to transmit the event data packets from the fan-out layer to the fan-in layer; the fan-in layer is used for driving 2-in-1-out type asynchronous routing nodes in the layer to fan in the event data packets of the intermediate layer to the output asynchronous bus; and the configuration register is used for storing preconfigured routing schemes corresponding to the fan-out layer, the intermediate layer and the fan-in layer respectively. The application does not need to reconfigure the circuit when switching between unicast, multicast, broadcast and other modes, so as to cause data transmission pipeline to be stalled; and there is no dynamic power consumption of the routing nodes and the bus.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of hardware communication, and particularly relates to a polymorphic asynchronous routing network architecture. BACKGROUND

[0002] As an important channel for data transmission between modules in a computer system, the design of a bus directly affects the performance and reliability of the system. In traditional synchronous systems, the bus protocol is usually driven by a clock signal; in different application scenarios, the synchronous bus needs to handle different numbers of input sources, output targets and source (target) routing positioning in different data transmission tasks, which are generally divided into the following three cases:

[0003] 1. Unicast: In unicast communication, a data packet is sent from one source node to a specific destination node; this communication method is the most common in networks and is suitable for point-to-point communication;

[0004] 2. Multicast: Multicast communication refers to sending a data packet from one source node to multiple specific destination nodes; this method efficiently supports group communication and avoids repeatedly sending data to each receiving node;

[0005] 3. Broadcast: Broadcast communication is sending a data packet from a source node to all destination nodes in the network to ensure that each node can receive the information; broadcast plays an important role in applications such as ARP request and DHCP service in a local area network.

[0006] In the design of a synchronous bus, due to the dependence on clock edges for driving, these three methods often need to be implemented through different hardware protocols, which means a large redundant circuit cost; some research attempts to use configuration registers to realize the reconfigurability of bus functions, which realizes the functional reuse of a single circuit at the cost of redundant functions and additional configuration time. However, this scheme has high cost when switching functions, and its application effect is not good in high-speed systems such as AI accelerators;

[0007] Asynchronous circuits, also known as self-timed circuits, have significant advantages such as reduced power consumption, event triggering, and improved electromagnetic compatibility because they do not rely on a global clock signal for synchronization. These features make asynchronous circuits increasingly popular in high-performance computing, bandwidth-limited devices, and noise-sensitive applications. Since the data flow of an asynchronous circuit can be used to drive the control flow, by designing asynchronous data packets with special information fields and customizing node circuits with identification and routing selection functions, it is possible to achieve a low-cost communication scheme challenge; however, a unified hardware protocol design for unicast, multicast, and broadcast communication methods has not yet been fully realized. SUMMARY

[0008] To address the deficiencies in the prior art, this application proposes a polymorphic asynchronous routing network architecture, which is detailed as follows:

[0009] A polymorphic asynchronous routing network architecture, comprising:

[0010] Input asynchronous bus, fan-out layer, middle layer, fan-in layer, output asynchronous bus and configuration register;

[0011] The fan-out layer includes a 1-input 2-output asynchronous routing node, which is used to drive the 1-input 2-output asynchronous routing node to fan out the event data packet on the input asynchronous bus to the middle layer;

[0012] The middle layer includes a 2-input 2-output asynchronous routing node, which is used to drive the 2-input 2-output asynchronous routing node to transfer event data packets from the fan-out layer to the fan-in layer;

[0013] The fan-in layer includes a 2-input 1-output asynchronous routing node, which is used to drive the 2-input 1-output asynchronous routing node to fan in the event data packets of the middle layer to the output asynchronous bus;

[0014] The configuration register is used to store pre-configured routing schemes corresponding to the fan-out layer, the middle layer, and the fan-in layer respectively.

[0015] Optionally, the format of the event data packet includes a data field and an information field, the data field is used to carry the event content; the information field is marked with an information stamp to provide various types of asynchronous routing nodes with the result of determining whether the event content implements the data stream structure.

[0016] Optionally, the information stamp includes:

[0017] Code stamp, used to write the code number to the target object of the event data packet transmission;

[0018] Address stamp, used to further encode the target object based on the coding number written into the target object;

[0019] Function reserved stamp, used to customize routing behavior.

[0020] Optionally, the written code numbers are the same or different.

[0021] Optionally, after receiving the event data packet input, the 1-input 2-output asynchronous routing node extracts the code number in the event data packet and compares it with the threshold code in the corresponding preconfigured routing scheme. If the code number in the event data packet is the same as the threshold code, the event data packet is transmitted to the straight branch of the 1-input 2-output asynchronous routing node; otherwise, it is transmitted to the side branch of the 1-input 2-output asynchronous routing node.

[0022] Optionally, the driving 2-in-1-out asynchronous routing node fan-in event data packets of the intermediate layer to the output asynchronous bus, including: only event data packets of one of the upper input branch or the lower input branch of the 2-in-1-out asynchronous routing node are normally processed, and when the event data packets of one of the branches of the 2-in-1-out asynchronous routing node are processed, the other branch needs to wait for the processing of the one branch to be completed before continuing to process.

[0023] Optionally, when the event data packets of one of the branches of the 2-in-1-out asynchronous routing node are processed, the other branch needs to wait for the processing of the one branch to be completed before continuing to process, and click signal generation and chip selection logic circuit are adopted.

[0024] Optionally, the 2-in-2-out asynchronous routing node is composed of a combination of a 1-in-2-out asynchronous routing node and a 2-in-1-out asynchronous routing node.

[0025] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects:

[0026] 1. When switching between unicast, multicast, broadcast and other modes, the circuit does not need to be reconfigured, so that the data transmission pipeline is not stalled;

[0027] 2. The data transmission on the polymorphic asynchronous routing network architecture is event-driven data transmission, and there is no dynamic power consumption on the routing node and the bus without data packets;

[0028] 3. The data transmission on the polymorphic asynchronous routing network architecture is not sensitive to timing, has high robustness, and can well adapt to the working scene with a large number of input objects and output targets and various types, which has high demand for versatility.

[0029] Other features and advantages of the present application will be described in the following description, and some will become apparent from the description, or will be understood by those skilled in the art through implementation of the present application. The purposes and other advantages of the present application are realized and obtained by the structures specifically pointed out in the specification, claims and drawings.

[0030] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are specifically described below, and the accompanying drawings are described in detail as follows.

[0031] The advantages of the additional aspects of the present application will be partially given in the following description, some will become apparent from the following description, or will be understood by those skilled in the art through implementation of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 This is a diagram of a polymorphic asynchronous routing network architecture shown in an embodiment of the present application;

[0034] Figure 2 A diagram showing the data packet format of a polymorphic asynchronous routing network according to an embodiment of the present application;

[0035] Figure 3 This is a diagram of a polymorphic asynchronous routing network structure at the 4-layer link layer shown in an embodiment of the present application;

[0036] Figure 4 This is an example diagram of routing behavior of a polymorphic asynchronous routing network of a 4-layer link layer in unicast mode as shown in an embodiment of the present application;

[0037] Figure 5 This is an example diagram of routing behavior of a polymorphic asynchronous routing network of a 4-layer link layer in broadcast and multicast modes as shown in an embodiment of the present application;

[0038] Figure 6 This is an example diagram of routing behavior of a polymorphic asynchronous routing network of a 4-layer link layer in a multi-transmitter multicast mode as shown in an embodiment of the present application;

[0039] Figure 7 This is an example diagram of routing behavior of a random object simplex transmission behavior combined with three working modes shown in an embodiment of the present application;

[0040] Figure 8 This is a working principle diagram of three basic asynchronous routing nodes shown in the embodiments of this application;

[0041] Figure 9 This is a basic configuration structure diagram of the three basic asynchronous routing nodes shown in the embodiments of this application. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0043] When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of methods and systems consistent with certain aspects of the present application as detailed in the appended claims.

[0044] In the description of this application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances. In addition, in the description of this application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0045] This application designs a low-cost, flexible and efficient hardware communication protocol by utilizing the characteristics of data flow driving control flow in the asynchronous circuit paradigm. By defining the routing data packet protocol and customizing several basic routing node circuits, a complex asynchronous polymorphic simplex routing NoC (Network On Chip) structure is finally constructed; this routing NoC can support unicast, multicast and broadcast communication modes at the same time by simply setting the configuration register without redundant routing circuits, control structures and additional routing delays. Due to its polymorphic and simplex characteristics, the number of input objects and the number of output objects are arbitrary. The polymorphic asynchronous routing network architecture of this application is also named as random object emission asynchronous routing network. It can improve the bandwidth utilization of the bus while ensuring the asynchronous pipeline timing correctness and data integrity of the data, and can provide technical support for the extensive data transmission needs of complex circuit architectures.

[0046] The technical solutions provided in this application are detailed as follows:

[0047] A polymorphic asynchronous routing network architecture, such as Figure 1 Shown, including:

[0048] Input asynchronous bus, fan-out layer, middle layer, fan-in layer, output asynchronous bus and configuration register;

[0049] The fan-out layer includes a 1-input 2-output asynchronous routing node, which is used to drive the 1-input 2-output asynchronous routing node to fan out the event data packet on the input asynchronous bus to the middle layer;

[0050] The middle layer includes a 2-input 2-output asynchronous routing node, which is used to drive the 2-input 2-output asynchronous routing node to transfer event data packets from the fan-out layer to the fan-in layer;

[0051] The fan-in layer includes a 2-input 1-output asynchronous routing node, which is used to drive the 2-input 1-output asynchronous routing node to fan in the event data packets of the middle layer to the output asynchronous bus;

[0052] The configuration register is used to store pre-configured routing schemes corresponding to the fan-out layer, the middle layer, and the fan-in layer respectively.

[0053] Specifically, in this embodiment, a polymorphic asynchronous routing network architecture (abbreviated as polymorphic asynchronous NoC) with in-flight simplex transmission characteristics is primarily composed of an input asynchronous bus, a fan-out layer, a bufferfly layer (equivalent to the middle layer of the polymorphic asynchronous routing network architecture in this application), a fan-in layer, an output asynchronous bus layer, and configuration registers. The fan-out layer, bufferfly layer, and fan-in layer perform the primary routing task, responsible for transferring data from any number of input asynchronous buses at any location to any number of output asynchronous buses at any location. The fan-out layer is mainly responsible for fanning out the data on the corresponding input asynchronous bus to 2. Its function is implemented by the basic asynchronous routing node 1to2 (equivalent to the 1-input 2-output asynchronous routing node in this application); the fan-in layer is the opposite, fanning the data of the two branches into the same output asynchronous bus. Its function is implemented by the basic asynchronous routing node 2to1 (equivalent to the 2-input 1-output asynchronous routing node in this application); the bufferfly layer is configured as a commonly used bufferfly NoC structure, and its function is implemented by the basic asynchronous routing node 2to2 (equivalent to the 2-input 2-output asynchronous routing node in this application).

[0054] The main advantages of the polymorphic asynchronous NoC architecture in this embodiment are:

[0055] 1. Data flow is control flow: Data packets are transmitted in the routing network, and the routing information encoded in the data packets directly determines the routing behavior of the polymorphic asynchronous NoC. This feature is jointly implemented by each asynchronous routing node, so there is no independent control module;

[0056] 2. Data transmission on the polymorphic asynchronous NoC is event-driven data transmission. There is no dynamic power consumption on the routing nodes and buses without data packets.

[0057] 3. The polymorphic asynchronous NoC supports broadcast, multicast, and unicast modes simultaneously. The NoC can switch between the three modes without changing the configuration information in the registers.

[0058] In a feasible specific implementation scheme, the format of the event data packet includes a data field and an information field, wherein the data field is used to carry the event content; an information stamp is marked inside the information field to provide various types of asynchronous routing nodes with the result of determining whether the event content implements the data stream structure;

[0059] Specifically, the format of the data packet transmitted on the polymorphic asynchronous NoC in this embodiment is as follows: Figure 2 As shown in Figure 1, it can be mainly divided into the data domain and the information domain. The data domain is used to carry specific data bits, which is the content subject to be transmitted; the information domain is marked with various information stamps, which are used to provide asynchronous routing nodes to determine the specific data flow structure. Figure 2 In the figure, x represents the bit width of info, which includes three types of information: ID, remain, and pixel coordinates, and n represents the bit width of the data part in the transmitted data packet.

[0060] In a feasible specific implementation scheme, the information stamp includes:

[0061] Code stamp, used to write the code number to the target object of the event data packet transmission;

[0062] Address stamp, used to further encode the target object based on the coding number written into the target object;

[0063] Function reserved stamp, used to customize routing behavior.

[0064] Specifically in this embodiment, the information stamps within the information domain include: a write ID stamp (equivalent to the coding stamp in the application), an Address stamp (address stamp) and a Remain stamp (function reserved stamp), wherein the write ID stamp is the write ID number of the transmission target object of the data packet. Since the write IDs of the transmission targets can be the same, the polymorphic asynchronous NoC can easily implement random object transmission behavior; the Address stamp is more specific address information, which is used for further encoding based on the write ID; the Remain stamp is a reserved information domain, which is used to customize specific routing behaviors in combination with various applications.

[0065] In a feasible specific implementation scheme, after receiving the event data packet input, the 1-input 2-output asynchronous routing node will extract the code number in the event data packet and compare it with the threshold code in the corresponding pre-configured routing scheme. If the code number in the event data packet is the same as the threshold code, the event data packet will be transmitted to the straight branch of the 1-input 2-output asynchronous routing node, otherwise it will be transmitted to the side branch of the 1-input 2-output asynchronous routing node.

[0066] In a feasible specific implementation scheme, the driving 2-input 1-output asynchronous routing node fans in the event data packet of the middle layer to the output asynchronous bus, including: only the event data packet of one branch of the upper input branch or the lower input branch of the 2-input 1-output asynchronous routing node is processed normally, when the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other branch needs to wait for the processing of one branch to be completed before continuing processing.

[0067] In a feasible specific implementation scheme, when the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other side needs to wait for the processing of one side to be completed before continuing to process, which is achieved by using click signal generation and chip selection logic circuit.

[0068] In a feasible specific implementation scheme, the 2-input 2-output asynchronous routing node is composed of a combination of a 1-input 2-output asynchronous routing node and a 2-input 1-output asynchronous routing node.

[0069] In order to explain the neuron circuit of the present application in more detail, a specific example is given below. Taking n=4 as an example, the overall principle block diagram of the technical solution of the present application is as follows: Figure 3 As shown, it mainly includes: 4 input asynchronous buses, 4 output asynchronous buses, a dedicated configuration register group for each asynchronous routing layer, and a 4-layer asynchronous routing network with a Bufferfly-like structure. The first layer of the asynchronous routing network consists of 4 1to2 asynchronous routing nodes. After receiving event packets from the input asynchronous buses, these nodes will determine the routing scheme based on the information in the configuration register and the specific information field in the event packet: full transmission, forwarding the straight branch, or forwarding the side branch. The second and third asynchronous routing layers are composed of 2to2 asynchronous routing nodes. After receiving an event on either the input branch above or below the node, the node can drive the node to pass data to the next layer, using the same transmission method as the 1to2 routing node. The fourth asynchronous routing layer is composed of 4 2to1 asynchronous routing nodes. Its asynchronous event fan-in processing method is the same as the 2to2 type. This node combines the input events of the two input branches and sends them to a corresponding output asynchronous bus.

[0070] Polymorphic asynchronous routing networks enable delay-free switching between data transmission modes, specifically unicast, multicast, and broadcast modes. This makes them particularly suitable for complex data transmission applications, such as AI neural network acceleration or on-board buses. The specific routing behavior of polymorphic asynchronous routing networks is complex and difficult to describe with formulas or code. The following examples illustrate this.

[0071] The specific routing situation of polymorphic asynchronous NoC in unicast mode is as follows Figure 4As shown in Figure 1, four specific cases are shown, corresponding to the routing behaviors when the input source is block 1 and the target is four different rows, where t1 represents the specific transmission position of the data packet at the first asynchronous time step. Figure 4 Block 1 represents the first asynchronous input bus. Due to its symmetry, the specific block of the data source in unicast mode has no essential effect on the routing behavior of the polymorphic asynchronous NoC. Since the shortest routing path (number of hops is 3) is achieved when the asynchronous input bus (block) corresponds to the asynchronous output data block (row), the polymorphic asynchronous NoC achieves the minimum data transmission delay at this time, consuming only 3 asynchronous time steps, as shown in Figure 1. Figure 4 (c) shows that when the time is not corresponding, it takes 5 asynchronous time steps, as shown in Figure 4 (c) It is worth noting that data transmission is carried out in a pipeline form, that is, Figure 4 The throughput of the four routing cases is the same, and only the delay time is different.

[0072] In broadcast and multicast modes, the specific routing of polymorphic asynchronous NoC is as follows: Figure 5 As shown, 8 cases are shown, corresponding to different routing situations when the input source is block 1 and the output object is different numbers and positions of rows. This behavior relies on the data packet's written ID information stamp and the data interaction between the asynchronous routing nodes. All 8 cases do not rely on circuit reconstruction. Figure 5 (c) shows the routing behavior when broadcasting to all four rows. In this case, except for row 1, all other rows require a delay of five asynchronous time steps to construct the asynchronous pipeline, following the same principle as in unicast mode. The behavior of the polymorphic asynchronous NoC in broadcast mode can be considered an overlay of unicast mode, a feature that relies on the event-driven nature of the asynchronous routing nodes and inter-node buses. Polymorphic asynchronous routing nodes allow for the switching of multicast objects without interrupting the pipeline, a feature achieved by relying on the duplication of written ID information stamps.

[0073] In the case of multiple transmitters, the specific routing of the polymorphic asynchronous NoC is as follows: Figure 6 As shown, all enabled data sources are shown ( Figure 6 (a)), partially enabled ( Figure 6 (b)) and the worst case with all data sources enabled ( Figure 6 (c)) four cases; a, b, c, d represent data packets from different asynchronous input buses, and their subscripts represent different moments; for example, a1 represents the location of the data packet at time step 1 ( Figure 7 similar).

[0074] When all data sources are enabled, each block and row performs multicast transmission in a one-to-one correspondence. At this time, the four asynchronous data streams do not pass through the same routing node, there is no arbitration behavior of asynchronous events, and the transmission delay is the shortest (3 asynchronous time steps). When the data source is partially enabled, only some links are enabled. Since there are no events in the remaining links and no digital signal 01 flip, there is no dynamic power consumption. Figure 6 As shown in (c), one of the worst working conditions in multicast mode is that the data source and the target row are completely misaligned. At this time, each block and row do not correspond to each other, and asynchronous data streams compete with each other for key asynchronous routing nodes (2to2). This may increase the throughput of the data stream while increasing the delay.

[0075] By utilizing the characteristics of asynchronous circuit data flow, i.e. control flow, a non-redundant multi-state routing network is constructed without a controller. The random object simplex transmission behavior implemented based on this network is as follows: Figure 7 As shown. Among them, Figure 7 (a) shows the extreme case of four input sources and only one output destination. In this case, due to the limited bandwidth of the output asynchronous bus, the four data flows are regulated by an arbitration mechanism implemented by the asynchronous routing nodes. This arbitration mechanism relies on the specific blocking behavior of the asynchronous routing nodes during the asynchronous handshake. Figure 7 (b) illustrates the multi-source, multi-destination scenario. More specifically, data from four input blocks is simultaneously delivered to two destination rows. In this scenario, the data from all blocks can be considered multicast to rows 0 and 3, and the data flows of each block adhere to the multicast behavior specifications. In this scenario, the data bandwidth overhead is doubled, but due to the event-driven nature of the asynchronous routing nodes and the structural characteristics of the multi-path asynchronous NoC architecture, the two aggregated output data flows do not incur an increase in latency, achieving the same throughput and latency as the multi-source, single-destination scenario. Figure 7 (c) shows the multi-source, multi-destination case, with two input sources and three output rows. Unlike the multi-source, multi-destination case, block 1's data is unicast to rows 0 and 3, while block 2's data is unicast to row 3. The data flows of blocks 1 and 2 adhere to multicast behavior. This hybrid, delay-free switching between unicast, multicast, and broadcast transmission modes enables the polymorphic asynchronous NoC to execute data transmission with any number and location of input sources and any number and location of input destinations, thus endowing the data transmission with strong robustness, versatility, and flexibility.

[0076] like Figure 3 As shown, the polymorphic asynchronous NoC is mainly composed of three basic routing nodes: 1to2, 2to2, and 2to1. Its working principle is as follows Figure 8 As shown. Among them, Figure 8(a) shows the working principle of 1 to 2 routing node, which extracts the write ID (routing ID) information in the data packet information field after receiving the external data input and compares it with the threshold ID (i.e. threshold encoding) in the corresponding register. If the routing ID information is the same as the threshold ID, the data is transmitted to the straight branch, otherwise it is transmitted to the deflection branch. Figure 8 (b) shows the working principle of 2 to 1 asynchronous routing node, which has two branches above and below the input. Under the action of the chip selection signal, only the data of one branch can be normally processed, and the other branch needs to wait for processing to be completed. This mechanism uses the handshake mechanism of asynchronous click circuit to achieve it, using its feature of blocking the next event handshake application when processing the current handshake signal. Both branches will block the back handshake behavior to the previous node of each branch when there is no chip selection signal until the current handshake processing is completed. The working principle of 2 to 2 asynchronous routing node is shown in Figure 8 (c) shows that it can be regarded as the combination of 1 to 2 asynchronous routing node and 2 to 1 asynchronous routing node, that is, the data output of 2 to 1 asynchronous routing node is equivalent to the external data input of 1 to 2 asynchronous routing node.

[0077] The specific circuit of the three basic routing nodes constituting the polymorphic asynchronous routing network is shown in Figure 9 , which is the reconstruction and variant of click's Fork, merge circuit components. Among them, the circuit structure of 1 to 2 asynchronous routing node is shown in Figure 9 (a), the key routing components are marked with a gray box, including several nand and or gates. After the InA_Req signal is valid, a MUX circuit with a comparator compares Threshold (threshold ID) with Info (write ID), and sequentially Figure 8 , the same as the discrimination scheme shown in (a), pulls up outB_Req or OutC_Req. After the next level asynchronous routing component responds to the handshake request, it will pull up the corresponding ACK signal, which will drive the core circuit to generate a click signal and drive the core circuit to generate a back handshake signal InA_Ack signal for handshake with the previous level asynchronous routing component. Figure 9(b) shows the specific circuit of 2to1 asynchronous routing node, which is composed of fused two groups of click signals and chip select logic circuit. Among them, the handshake signal of one branch will drive the corresponding sel_a / sel_b signal generation after generation, and this signal will drive the or gate to generate a click_out signal, which will pass the handshake request signal OutC_Req to the next stage routing component. When the next stage responds to the handshake and generates the corresponding handshake signal OutC_Ack, a click_in signal will be generated. This signal will also be affected by the chip select signal sel_a / sel_b, and will generate a handshake response signal on the corresponding branch. In this way, the 2to1 asynchronous routing node can realize the working principle shown in Figure 8 (b) as shown. Figure 9 (c) shows the circuit of 2to2 asynchronous routing node, which can be regarded as a combination of 1to2 and 2to1 asynchronous routing nodes.

[0078] The application provides a polymorphic asynchronous routing network architecture, and the design of the routing network achieves the following beneficial technical effects:

[0079] 1. When switching between unicast, multicast, broadcast and other modes, the circuit does not need to be reconfigured, so that the data transmission pipeline is not stalled;

[0080] 2. The data transmission on the polymorphic asynchronous NoC is event-driven data transmission, and there is no dynamic power consumption on the routing node and bus without data packets;

[0081] 3. The data transmission on the polymorphic asynchronous NoC is not sensitive to timing, has high robustness, and can well adapt to the working scene with a large number of input objects and output targets and various types, which has high general-purpose requirement.

[0082] Although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description manner of the specification is only for the sake of clarity. The skilled person should consider the specification as a whole, and the technical solutions in each embodiment can be combined appropriately to form other embodiments that can be understood by the skilled person.

[0083] In the description of this application, it should be noted that relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, invention, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, invention, article, or device. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of other identical elements in the process, invention, article, or device comprising the element.

[0084] Therefore, the above description is only a preferred embodiment of the present application and is not intended to limit the scope of implementation of the present application; that is, all equivalent modifications made according to the scope of the claims of the present application are within the scope of protection of the claims of the present application.

[0085] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-mentioned embodiments within the technical scope disclosed in the present application, or perform equivalent replacements for some of the technical features thereof. These modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0086] The applicant of this application has made detailed explanations and descriptions of the implementation examples of this application in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation plans of this application, and the detailed description is only to help readers better understand the spirit of this application, and is not a limitation on the scope of protection of this application. On the contrary, any improvements or modifications based on the inventive spirit of this application should fall within the scope of protection of this application.

Claims

1. A polymorphic asynchronous routing network device, characterized in that: include: Input asynchronous bus, fan-out layer, middle layer, fan-in layer, output asynchronous bus and configuration register; The fan-out layer includes a 1-input 2-output asynchronous routing node, which is used to drive the 1-input 2-output asynchronous routing node to fan out the event data packet on the input asynchronous bus to the middle layer; The middle layer includes a 2-input 2-output asynchronous routing node, which is used to drive the 2-input 2-output asynchronous routing node to transfer event data packets from the fan-out layer to the fan-in layer; The fan-in layer includes a 2-input 1-output asynchronous routing node, which is used to drive the 2-input 1-output asynchronous routing node to fan in the event data packets of the middle layer to the output asynchronous bus; The configuration register is used to store pre-configured routing schemes corresponding to the fan-out layer, the middle layer, and the fan-in layer respectively.

2. The polymorphic asynchronous routing network device according to claim 1, wherein: The format of the event data packet includes a data field and an information field. The data field is used to carry the event content; the information field is marked with an information stamp to provide various types of asynchronous routing nodes with the result of determining whether the event content implements the data stream structure.

3. The polymorphic asynchronous routing network device according to claim 2, wherein: The information stamp includes: Code stamp, used to write the code number to the target object of the event data packet transmission; Address stamp, used to further encode the target object based on the coding number written into the target object; Function reserved stamp, used to customize routing behavior.

4. The polymorphic asynchronous routing network device according to claim 3, wherein: The written code numbers are the same or different.

5. The polymorphic asynchronous routing network device according to claim 1, wherein: After receiving the event data packet input, the 1-input 2-output asynchronous routing node extracts the code number in the event data packet and compares it with the threshold code in the corresponding pre-configured routing scheme. If the code number in the event data packet is the same as the threshold code, the event data packet is transmitted to the straight branch of the 1-input 2-output asynchronous routing node; otherwise, it is transmitted to the side branch of the 1-input 2-output asynchronous routing node.

6. The polymorphic asynchronous routing network device according to claim 1, wherein: The driving 2-input 1-output asynchronous routing node fans in the event data packet of the middle layer to the output asynchronous bus, including: only the event data packet of one branch of the upper input branch or the lower input branch of the 2-input 1-output asynchronous routing node is processed normally, when the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other branch needs to wait for the processing of one branch to be completed before continuing processing.

7. The polymorphic asynchronous routing network device according to claim 6, wherein: When the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other branch needs to wait for the processing of one branch to be completed before continuing to process, which is achieved by using click signal generation and chip selection logic circuit.

8. The polymorphic asynchronous routing network device according to claim 1, wherein: The 2-input 2-output asynchronous routing node is composed of a combination of a 1-input 2-output asynchronous routing node and a 2-input 1-output asynchronous routing node.

Images