Voltage drop control method and device, electronic equipment, storage medium and chip

Abstract

The disclosure provides a voltage drop control method, which comprises the following steps: obtaining a to-be-executed instruction path; determining whether the to-be-executed instruction path is a marked instruction path; and enabling a preset current limiting strategy to execute the to-be-executed instruction path in the case that the to-be-executed instruction path is the marked instruction path, wherein the current limiting strategy is used to adjust voltage before triggering the voltage drop. The embodiment of the application can suppress voltage drop in advance by suppressing control voltage before the execution of the to-be-executed instruction path, suppress voltage drop with a small performance cost, reduce the triggering probability of frequency reduction for suppressing voltage drop, and further reduce the power consumption gain of the operating voltage of the CPU.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a method, apparatus, electronic device, storage medium, and chip for controlling voltage drops. Background Technology

[0002] With the widespread development of mobile terminal devices, users have placed higher demands on the performance of mobile System-on-Chip (SOC). Currently, suppressing voltage drops by reducing the frequency after a voltage drop is detected is a reactive measure, and suppressing voltage drops by reducing the frequency requires a significant performance penalty from the SOC to quickly suppress the drop, thus having a substantial impact on the SOC's performance. Summary of the Invention

[0003] This disclosure provides a voltage drop control method and apparatus, electronic device, storage medium, and chip to solve problems in related technologies. By suppressing voltage drops in advance through suppression control, voltage drops can be suppressed at a small performance cost, reducing the probability of triggering voltage drop suppression by frequency reduction, and further reducing the operating voltage of the CPU to obtain power consumption benefits.

[0004] A first aspect of this disclosure provides a method for controlling voltage sag, the method comprising:

[0005] Obtain the path to the instruction to be executed;

[0006] Determine whether the path of the instruction to be executed is a marked instruction path;

[0007] If the path to be executed is determined to be the marked path, a preset current limiting strategy is enabled to execute the path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

[0008] In some embodiments, determining whether the instruction path to be executed is a marked instruction path includes:

[0009] The path of the instruction to be executed is compared with the preset record information; the preset record information records the instruction path that triggers the voltage drop, as well as the preset instruction path;

[0010] Based on the comparison result between the path of the instruction to be executed and the preset record information, it is determined whether the path of the instruction to be executed is a marked instruction path.

[0011] In some embodiments, determining whether the instruction path to be executed is a marked instruction path based on the comparison result between the instruction path to be executed and the preset record information includes:

[0012] If it is determined that the path of the instruction to be executed is recorded in the preset record information, then the path of the instruction to be executed is determined to be the marked instruction path;

[0013] If it is determined that the path of the instruction to be executed is not recorded in the preset record information, then it is determined that the path of the instruction to be executed is not the marked instruction path.

[0014] In some embodiments, before comparing the path of the instruction to be executed with preset record information, the method further includes:

[0015] Monitor for the presence of target instruction segments that trigger a voltage drop;

[0016] After a target instruction segment that triggers a voltage drop is found, the execution path entering the target instruction segment is recorded;

[0017] The execution path to the target instruction fragment is stored in the preset record information.

[0018] In some embodiments, recording the execution path into the target instruction segment after a trigger voltage drop includes:

[0019] Record the function call path and the jump path within the function corresponding to the target instruction fragment.

[0020] In some embodiments, enabling a preset rate limiting policy to execute the instruction path to be executed includes:

[0021] The number of times the instruction execution unit of the processor is executed per unit time is controlled, wherein the instruction execution unit is used to execute the instruction path to be executed;

[0022] And / or, control the number of available processor instruction execution units.

[0023] In some embodiments, before comparing the path of the instruction to be executed with preset record information, the method further includes:

[0024] Determine whether multiple processors share a power supply;

[0025] If so, the multiple processors are configured to share the same preset record information.

[0026] In some embodiments, after enabling a preset rate limiting policy to execute the instruction path to be executed, the method further includes:

[0027] Determine whether the address corresponding to the path of the instruction to be executed exists in the return stack;

[0028] When it is determined that the address corresponding to the path of the instruction to be executed does not exist in the return stack, the preset rate limiting policy is switched to the off state.

[0029] A second aspect of this disclosure provides a voltage sag control device, the device comprising:

[0030] The acquisition unit is used to acquire the path of the instruction to be executed;

[0031] The first determining unit is used to determine whether the instruction path to be executed is a marked instruction path;

[0032] The control unit is configured to execute the instruction path to be executed by enabling a preset rate limiting strategy when it is determined that the instruction path to be executed is the marked instruction path.

[0033] In some embodiments, the first determining unit includes:

[0034] The comparison module is used to compare the instruction path to be executed with preset record information; the preset record information records the instruction path that triggers the voltage drop, as well as the preset instruction path;

[0035] The determination module is used to determine whether the instruction path to be executed is a marked instruction path based on the comparison result between the instruction path to be executed and the preset record information.

[0036] In some embodiments, the determining module is further configured to:

[0037] If it is determined that the path of the instruction to be executed is recorded in the preset record information, then the path of the instruction to be executed is determined to be the marked instruction path;

[0038] If it is determined that the path of the instruction to be executed is not recorded in the preset record information, then it is determined that the path of the instruction to be executed is not the marked instruction path.

[0039] In some embodiments, the apparatus further includes:

[0040] The monitoring unit is used to monitor whether there is a target instruction segment that triggers a voltage drop before comparing the instruction path to be executed with preset recorded information.

[0041] A recording unit is used to record the execution path into the target instruction segment after a target instruction segment with a trigger voltage drop exists;

[0042] A storage unit is used to store the execution path of the target instruction fragment in the preset record information.

[0043] In some embodiments, the recording unit is further configured to:

[0044] Record the function call path and the jump path within the function corresponding to the target instruction fragment.

[0045] In some embodiments, the control unit is further configured to:

[0046] The number of times the instruction execution unit of the processor is executed per unit time is controlled, wherein the instruction execution unit is used to execute the instruction path to be executed;

[0047] And / or, control the number of available processor instruction execution units.

[0048] In some embodiments, the apparatus further includes:

[0049] The second determining unit is used to determine whether multiple processors share a power supply before comparing the path of the instruction to be executed with preset record information.

[0050] A configuration unit is configured, if so, to allow the plurality of processors to share the same preset record information.

[0051] In some embodiments, the apparatus further includes:

[0052] The third determining unit is used to determine whether the address corresponding to the instruction path to be executed exists in the return stack after the preset rate limiting strategy is enabled to execute the instruction path;

[0053] The switching unit is used to switch the preset rate limiting strategy to the off state when it is determined that there is no address corresponding to the path of the instruction to be executed in the return stack.

[0054] A third aspect of this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of this disclosure.

[0055] A fourth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the first aspect of this disclosure.

[0056] A fifth aspect of this disclosure provides a chip including one or more interfaces and one or more processors; the interfaces are configured to receive signals from the memory of an electronic device and send signals to the processors, the signals including computer instructions stored in the memory, which, when executed by the processor, cause the electronic device to perform the methods described in the first aspect of this disclosure.

[0057] In summary, the voltage sag control method proposed in this disclosure includes obtaining a path of instructions to be executed, determining whether the path of instructions to be executed is a marked instruction path, and, if the path of instructions to be executed is determined to be a marked instruction path, enabling a preset current limiting strategy to execute the path of instructions to be executed. The current limiting strategy is used to adjust the voltage before triggering the voltage sag. This embodiment of the application suppresses voltage sag by controlling the voltage before the execution of the instruction path, thereby reducing the probability of triggering frequency reduction to suppress voltage sag and further reducing the CPU's operating voltage to achieve power consumption benefits.

[0058] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0059] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0060] Figure 1 A schematic diagram of a voltage drop control system provided in an embodiment of this disclosure;

[0061] Figure 2 A flowchart of a voltage sag control method provided in this disclosure embodiment;

[0062] Figure 3 A flowchart of a voltage sag control method provided in this disclosure embodiment;

[0063] Figure 4 A flowchart of a voltage sag control method provided in this disclosure embodiment;

[0064] Figure 5 A flowchart of a voltage sag control method provided in this disclosure embodiment;

[0065] Figure 6 This is a schematic diagram of the structure of a voltage drop control device provided in an embodiment of the present disclosure;

[0066] Figure 7 This is a schematic diagram of the structure of a voltage drop control device provided in an embodiment of the present disclosure;

[0067] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure;

[0068] Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of the present disclosure. Detailed Implementation

[0069] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0070] With the widespread development of mobile terminal devices, users have placed higher demands on the performance of mobile System-on-Chip (SOC). Currently, suppressing voltage drops by reducing the frequency after a voltage drop is detected is a reactive measure, and suppressing voltage drops by reducing the frequency requires a significant performance penalty from the SOC to quickly suppress the drop, thus having a substantial impact on the SOC's performance.

[0071] Therefore, in order to solve the problems existing in the related technologies, this disclosure proposes a voltage drop control method, which obtains the instruction path to be executed, determines whether the instruction path to be executed is a marked instruction path, and if the instruction path to be executed is determined to be the marked instruction path, enables a preset current limiting strategy to execute the instruction path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

[0072] This scheme suppresses voltage drops by controlling the voltage before the instruction path is executed, at a small performance cost, thereby reducing the probability of triggering the frequency reduction to suppress voltage drops. This can further reduce the CPU's operating voltage and gain power consumption benefits.

[0073] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0074] In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0075] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0076] In this embodiment of the disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular expression or a plural expression.

[0077] In some embodiments, the terms “in response to…”, “in response to determining…”, “in the case of…”, “when…”, “if…”, “if…”, etc., can be used interchangeably.

[0078] In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”.

[0079] The prefixes such as "first" and "second" in the embodiments of this disclosure are only for distinguishing different descriptive objects and do not constitute restrictions on the position, order, priority, number or content of the descriptive objects. For the description of the descriptive objects, please refer to the description in the claims or the context of the embodiments. The use of prefixes should not constitute unnecessary restrictions.

[0080] In the embodiments of this disclosure, "multiple" refers to two or more.

[0081] In the embodiments disclosed herein, terms such as “import”, “input”, and “read in” can be used interchangeably.

[0082] In some embodiments, devices, etc., can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as “device”, “equipment”, “circuit”, “network element”, “node”, “function”, “unit”, “section”, “system”, “network”, “chip”, “chip system”, “entity”, and “subject” can be used interchangeably.

[0083] In some embodiments, "terminal", "terminal device", "user equipment (UE)", "user terminal", and "mobile station" are used.

[0084] The terms "mobile station (MS)," "mobile terminal (MT)," "subscriber station," "mobile unit," "subscriber unit," "wireless unit," "remote unit," "mobile device," "wireless device," "wireless communication device," "remote device," "mobile subscriber station," "access terminal," "mobile terminal," "wireless terminal," "remote terminal," "handset," "user agent," "mobile client," and "client" are interchangeable.

[0085] like Figure 1 As shown, Figure 1 This schematic diagram illustrates a voltage drop control system according to an embodiment of the present disclosure, including: a voltage drop detection module 11, a frequency modulation controller 12, a jump recording unit 13, a return stack recording unit 14, a central processing unit (CPU) 15, and a path detection unit 16. The voltage drop detection module 11 detects the operating voltage of the CPU, and upon detecting a trigger voltage drop, sends a notification message to the frequency modulation controller 12.

[0086] The frequency controller 12 suppresses voltage drops by reducing the frequency. At the same time, the voltage drop detection module 11 sends a notification message to the jump record unit 13 and the return stack record unit 14 so that the jump record unit 13 and the return stack record unit 14 can record and mark the current return stack and jump record of the CPU.

[0087] Figure 2This is a flowchart illustrating a voltage sag control method provided in an embodiment of this disclosure. This method can be applied to application scenarios such as smart terminals, for example, executed by a mobile terminal with integrated SOC functionality or a processor within the terminal, or executed by other devices suitable for CPU voltage sag suppression processing; this disclosure does not limit its application. Figure 2 As shown, the voltage drop control method includes steps 201-203.

[0088] Step 201: Obtain the path of the instruction to be executed.

[0089] The embodiments of this application can be applied to scenarios where the CPU operates under large current variations, and can suppress the drop in CPU operating voltage with a small performance cost.

[0090] During CPU instruction execution, the instruction path that has not been executed is called the instruction path to be executed.

[0091] Step 202: Determine whether the instruction path to be executed is a marked instruction path.

[0092] The marked instruction path described in this application embodiment indicates that the instruction path is a high-power instruction path, and the marked instruction path will trigger a CPU voltage drop.

[0093] Therefore, when the CPU executes the instruction path to be executed, it determines in real time whether the instruction path to be executed is a marked instruction path, that is, whether the execution of the instruction path to be executed will trigger a voltage drop.

[0094] In some embodiments, the marked instruction path may be marked when the trigger voltage drops for the first time. In other embodiments, the marked instruction path may also be a pre-defined instruction path that may be triggered. Specifically, the marking method of the marked instruction path is not limited in the embodiments of this application.

[0095] In practical applications, the marked paths can also be stored in a table, which can be queried in real time during CPU instruction execution to improve real-time efficiency. Alternatively, the marked paths can be stored in other forms, without limitation.

[0096] Step 203: If the path to be executed is determined to be the marked instruction path, a preset current limiting strategy is enabled to execute the path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

[0097] If the instruction path to be executed is identified as a marked instruction path, it indicates that the execution of this instruction path may trigger a voltage drop. Therefore, in order to prevent the voltage drop from occurring, this embodiment of the application adopts a method of suppressing voltage drops in advance. That is, before the voltage drop is triggered, the voltage drop is suppressed in advance by a preset current limiting strategy inside the CPU. The current limiting strategy is used to adjust the voltage before the voltage drop is triggered.

[0098] The specific preset current limiting strategy is used to limit the current of high-power instruction paths to avoid peak execution, control the CPU load in advance, and suppress voltage drops. By suppressing voltage drops in advance in a targeted manner, the probability of frequency reduction triggering is reduced at a lower cost.

[0099] In some embodiments, the preset rate limiting strategy includes, but is not limited to, limiting the number of times the processor's instruction execution units execute per unit time and / or limiting whether instruction execution units can execute simultaneously. It can be dynamically adjusted based on the actual power consumption of the instruction path to be executed. For example, when the power consumption of the instruction path to be executed is relatively low, a rate limiting strategy that limits the number of times the processor's instruction execution units execute per unit time, or that limits whether the processor can execute simultaneously, is adopted. When the power consumption of the instruction path to be executed is relatively high, a rate limiting strategy that simultaneously limits the number of times the processor's instruction execution units execute per unit time and limits whether the processor's instruction execution units can execute simultaneously is adopted.

[0100] In summary, the voltage sag control method proposed in this disclosure includes obtaining a path of instructions to be executed, determining whether the path of instructions to be executed is a marked instruction path, and, if the path of instructions to be executed is determined to be a marked instruction path, enabling a preset current limiting strategy to execute the path of instructions to be executed. The current limiting strategy is used to adjust the voltage before triggering the voltage sag. This embodiment of the application suppresses voltage sag by controlling the voltage before the execution of the instruction path, thereby reducing the probability of triggering frequency reduction to suppress voltage sag and further reducing the CPU's operating voltage to achieve power consumption benefits.

[0101] Figure 3 A flowchart of a voltage sag control method proposed in this disclosure is further shown. Based on Figure 2 The illustrated embodiment further explains step 202. Figure 3 This may include the following steps:

[0102] Step 301: Compare the instruction path to be executed with preset record information; the preset record information records the instruction path that triggers the voltage drop, as well as the preset instruction path;

[0103] Step 302: Determine whether the instruction path to be executed is a marked instruction path based on the comparison result between the instruction path to be executed and the preset record information.

[0104] If it is determined that the path of the instruction to be executed is recorded in the preset record information, then step 303 is executed; if it is determined that the path of the instruction to be executed is not recorded in the preset record information, then step 304 is executed.

[0105] Step 303: Determine that the instruction path to be executed is the marked instruction path;

[0106] Step 304: Determine that the path of the instruction to be executed is not the marked instruction path.

[0107] Figure 4 A flowchart of a voltage sag control method proposed in this disclosure is further shown. Figure 4 This may include the following steps:

[0108] Step 401: Monitor whether there is a target instruction segment that triggers a voltage drop.

[0109] In embodiments of this disclosure, the target instruction fragment includes an instruction fragment or a combination of two or more instructions.

[0110] Please continue reading. Figure 1 During the execution of instructions by CPU 15, voltage drop detection module 11 monitors whether there is a target instruction segment that triggers voltage drop. When voltage drop detection module 11 detects that there is a target instruction segment that triggers voltage drop, it sends notification messages to jump record unit 13 and return stack record unit 14 respectively.

[0111] In some embodiments, the target instruction fragment includes, but is not limited to, floating-point operations, matrix operations, vector operations, etc. The embodiments of this application do not limit the type of the target instruction fragment.

[0112] In addition to determining the target instruction segment through real-time monitoring, high-power target instruction segments can also be obtained through preliminary testing and microarchitecture analysis.

[0113] Step 402: After a target instruction segment that triggers a voltage drop exists, record the execution path that enters the target instruction segment.

[0114] In practical applications, the target instruction fragment can be a high-power hotspot function. Therefore, the target instruction fragment may occur during function calls or during function jumps. Thus, after determining the target instruction fragment, it is necessary to obtain the entry path to the target instruction fragment, that is, to obtain and record the corresponding function call path and the jump path within the function.

[0115] The execution function call path corresponding to the target instruction fragment is recorded in the CPU's current return stack, and the jump path within the execution function is recorded in the most recent jump record.

[0116] Step 403: Store the execution path of the target instruction fragment in the preset record information.

[0117] The execution function call path and the jump path within the execution function corresponding to the target instruction fragment are stored in preset record information. The form of the preset record information is not limited in this embodiment. For example, it can be a table, log, or other similar format.

[0118] Step 404: Obtain the path of the instruction to be executed.

[0119] Step 405: Determine whether the path of the instruction to be executed is recorded in the preset record information.

[0120] If it is determined that the path of the instruction to be executed is recorded in the preset record information, then step 406 is executed; if it is determined that the path of the instruction to be executed is not recorded in the preset record information, then step 407 is executed.

[0121] For explanations of steps 404 and 405, please refer to [link / reference needed]. Figure 1 The detailed descriptions of the relevant information are not repeated here in the embodiments of this application.

[0122] Step 406: Execute the instruction path to be executed by enabling the preset rate limiting strategy.

[0123] Preset rate limiting strategies (also known as rate limiting and peak shaving strategies) include: limiting the number of times the processor's instruction execution units execute per unit of time; and / or controlling the number of available processor instruction execution units.

[0124] When executing the instruction path to be executed through a preset rate limiting strategy, the number of executions within the instruction execution unit per unit time of the processor can be dynamically set. This number of executions can be controlled by setting the threshold value of the instruction execution unit, and / or by dynamically setting the number of available instruction execution units of the processor, that is, limiting the number of instruction execution units that can be executed simultaneously.

[0125] In another implementation of this application, the number of times a high-power instruction to be executed is limited per unit time, and / or the number of high-power instructions to be executed simultaneously is limited. The fixed number of executions and the fixed number can be set by test results, and the specific implementation of this application is not limited.

[0126] The method provided in this application embodiment will not trigger a large voltage drop because of the advance current limiting, and therefore will not trigger the related technical solutions that suppress voltage drop by reducing frequency.

[0127] Step 407: Execute the path of the instruction to be executed.

[0128] In the specific implementation of this application embodiment, after enabling the preset rate limiting strategy to execute the instruction path to be executed, the method further includes: determining whether there is an address corresponding to the instruction path to be executed in the return stack, and when it is determined that there is no address corresponding to the instruction path to be executed in the return stack, switching the preset rate limiting strategy to the off state.

[0129] When the CPU's return stack does not contain the address corresponding to the instruction path to be executed, it means that the CPU has finished executing the high-power code (instruction path to be executed). Therefore, the CPU's internal current limiting and peak shaving can be canceled, that is, the preset current limiting strategy can be switched to the off state to restore the system's processing performance in a timely manner.

[0130] In practical applications, there may be scenarios where multiple CPUs share a single power supply. In such scenarios, CPU1 might execute instructions that call a high-power function A, while CPU2 might execute instructions that call both high-power functions A and C. This indicates a shared marked instruction path. Therefore, to facilitate rate limiting management for multiple CPUs, this application provides the following supplementary solutions. Figure 5 As shown, the method includes:

[0131] Step 501: Determine whether multiple processors share a power supply.

[0132] In scenarios where multiple processors are identified, it is necessary to determine whether these processors share a power supply. The number of processors is set at the factory, and this can be determined by reading the relevant configuration information to ascertain whether the smart device contains multiple processors, i.e., whether these processors share a power supply.

[0133] Step 502: If yes, configure the multiple processors to share the same preset record information.

[0134] Therefore, different CPUs may call the same execution function. Thus, multiple CPUs are configured to share the same preset record information. It should be noted that multiple CPUs can be all CPUs in the smart terminal, multiple CPUs currently enabled in the smart terminal, or multiple CPUs in the smart terminal exceeding a preset load threshold, etc. The specific definition is not limited.

[0135] Corresponding to the voltage sag control method described above, this invention also proposes a voltage sag control device. Since the device embodiments of this invention correspond to the method embodiments described above, details not disclosed in the device embodiments can be referred to in the method embodiments described above, and will not be repeated here.

[0136] Figure 6 This is a schematic diagram of a voltage sag control device 600 provided in an embodiment of the present disclosure. The voltage sag control device includes:

[0137] Acquisition unit 61 is used to acquire the path of the instruction to be executed;

[0138] The first determining unit 62 is used to determine whether the instruction path to be executed is a marked instruction path;

[0139] The control unit 63 is configured to enable a preset current limiting strategy to execute the instruction path when it is determined that the instruction path to be executed is the marked instruction path, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

[0140] In summary, the voltage drop control device proposed in this disclosure includes acquiring a path of instructions to be executed, determining whether the path of instructions to be executed is a marked instruction path, and, if the path of instructions to be executed is determined to be a marked instruction path, enabling a preset current limiting strategy to execute the path of instructions to be executed. The current limiting strategy is used to adjust the voltage before triggering the voltage drop. This embodiment of the application suppresses voltage drop by controlling the voltage before the execution of the instruction path, thereby reducing the probability of triggering frequency reduction to suppress voltage drop and further reducing the CPU's operating voltage to achieve power consumption benefits.

[0141] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 7 As shown, the first determining unit 62 includes:

[0142] The comparison module 621 is used to compare the instruction path to be executed with preset record information; the preset record information records the instruction path that triggers the voltage drop, as well as the preset instruction path.

[0143] The determining module 622 is used to determine whether the instruction path to be executed is a marked instruction path based on the comparison result between the instruction path to be executed and the preset record information.

[0144] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 7 As shown, the determining module 622 is further configured to:

[0145] If it is determined that the path of the instruction to be executed is recorded in the preset record information, then the path of the instruction to be executed is determined to be the marked instruction path;

[0146] If it is determined that the path of the instruction to be executed is not recorded in the preset record information, then it is determined that the path of the instruction to be executed is not the marked instruction path.

[0147] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 7 As shown, the device further includes:

[0148] The monitoring unit 64 is used to monitor whether there is a target instruction segment that triggers a voltage drop before comparing the instruction path to be executed with preset recorded information.

[0149] The recording unit 65 is used to record the execution path of entering the target instruction segment after a target instruction segment with a trigger voltage drop exists;

[0150] Storage unit 66 is used to store the execution path of entering the target instruction segment in the preset record information.

[0151] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 7 As shown, the recording unit 65 is further used for:

[0152] Record the function call path and the jump path within the function corresponding to the target instruction fragment.

[0153] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 7 As shown, the control unit 63 is further configured to:

[0154] The number of times the instruction execution unit of the processor is executed per unit time is controlled, wherein the instruction execution unit is used to execute the instruction path to be executed;

[0155] And / or, control the number of available processor instruction execution units.

[0156] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 7 As shown, the device further includes:

[0157] The second determining unit 67 is used to determine whether multiple processors share a power supply before comparing the path of the instruction to be executed with preset record information.

[0158] Configuration unit 68 is configured, if so, to allow the plurality of processors to share the same preset record information.

[0159] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 7 As shown, the device further includes:

[0160] The third determining unit 69 is used to determine whether the address corresponding to the instruction path to be executed exists in the return stack after the preset rate limiting strategy is enabled to execute the instruction path to be executed.

[0161] The switching unit 610 is used to switch the preset rate limiting strategy to the off state when it is determined that there is no address corresponding to the path of the instruction to be executed in the return stack.

[0162] Since the apparatus provided in this embodiment corresponds to the methods provided in the above embodiments, the implementation of the methods is also applicable to the apparatus provided in this embodiment, and will not be described in detail in this embodiment.

[0163] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.

[0164] Figure 8 This is a block diagram illustrating an electronic device 800 for implementing the voltage drop control method described above, according to an exemplary embodiment. For example, the electronic device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0165] Reference Figure 8 The electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power supply component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0166] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 1020 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0167] Memory 804 is configured to store various types of data to support the operation of electronic device 800. Examples of such data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0168] Power supply component 806 provides power to various components of electronic device 800. Power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800.

[0169] Multimedia component 808 includes a screen that provides an output interface between electronic device 800 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When electronic device 800 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0170] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0171] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0172] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 can detect the on / off state of electronic device 800, the relative positioning of components such as the display and keypad of electronic device 800, changes in position of electronic device 800 or a component of electronic device 800, the presence or absence of user contact with electronic device 800, orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0173] Communication component 816 is configured to facilitate wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0174] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0175] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, which can be executed by a processor 1020 of an electronic device 800 to perform the above-described method for image processing. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0176] Embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the above embodiments of this disclosure.

[0177] For cases where electronic devices can be chips or chip systems, see [link to relevant documentation]. Figure 9 The diagram shows the structure of the chip. Figure 9 The chip shown includes a processor 901 and an interface 902. There can be one or more processors 901, and multiple interfaces 902.

[0178] Optionally, the chip also includes a memory 903, which is used to store necessary computer programs and data.

[0179] Those skilled in the art will also understand that the various illustrative logical blocks and steps listed in the embodiments of this application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the functionality using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of this application.

[0180] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0181] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0182] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0183] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0184] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0185] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium. When executed, the program includes one or a combination of the steps of the method embodiments.

[0186] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0187] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for controlling voltage sag, characterized in that, The method includes: Obtain the path to the instruction to be executed; Determining whether the instruction path to be executed is a marked instruction path includes: comparing the instruction path to be executed with preset record information; the preset record information records instruction paths that trigger voltage drops, as well as preset instruction paths; and determining whether the instruction path to be executed is a marked instruction path based on the comparison result between the instruction path to be executed and the preset record information. If the path to be executed is determined to be the marked instruction path, a preset current limiting strategy is enabled to execute the path to be executed, wherein the current limiting strategy is used to adjust the voltage before the trigger voltage drops; Specifically, before comparing the path of the instruction to be executed with the preset record information, it is monitored whether there is a target instruction segment that triggers a voltage drop; after a target instruction segment that triggers a voltage drop is found, the execution function call path and the jump path within the execution function corresponding to the target instruction segment are recorded; the execution path that enters the target instruction segment is stored in the preset record information.

2. The method according to claim 1, characterized in that, The step of determining whether the instruction path to be executed is a marked instruction path based on the comparison result between the instruction path to be executed and the preset record information includes: If it is determined that the path of the instruction to be executed is recorded in the preset record information, then the path of the instruction to be executed is determined to be the marked instruction path; If it is determined that the path of the instruction to be executed is not recorded in the preset record information, then it is determined that the path of the instruction to be executed is not the marked instruction path.

3. The method according to claim 1, characterized in that, The path for executing the instruction to be executed by enabling the preset rate limiting strategy includes: The number of times the instruction execution unit of the processor is executed per unit time is controlled, wherein the instruction execution unit is used to execute the instruction path to be executed; And / or, control the number of available processor instruction execution units.

4. The method according to claim 1, characterized in that, Before comparing the path of the instruction to be executed with the preset record information, the method further includes: Determine whether multiple processors share a power supply; If so, the multiple processors are configured to share the same preset record information.

5. The method according to claim 1, characterized in that, After enabling a preset rate limiting policy to execute the instruction path to be executed, the method further includes: Determine whether the address corresponding to the path of the instruction to be executed exists in the return stack; When it is determined that the address corresponding to the path of the instruction to be executed does not exist in the return stack, the preset rate limiting policy is switched to the off state.

6. A voltage sag control device, characterized in that, The device includes: The acquisition unit is used to acquire the path of the instruction to be executed; The first determining unit is used to determine whether the instruction path to be executed is a marked instruction path, including: comparing the instruction path to be executed with preset recording information; the preset recording information records instruction paths that trigger voltage drops, as well as preset instruction paths; and determining whether the instruction path to be executed is a marked instruction path based on the comparison result between the instruction path to be executed and the preset recording information. The control unit is configured to enable a preset current limiting strategy to execute the instruction path when it is determined that the instruction path to be executed is the marked instruction path, wherein the current limiting strategy is used to adjust the voltage before the trigger voltage drops; Specifically, before comparing the path of the instruction to be executed with the preset record information, it is monitored whether there is a target instruction segment that triggers a voltage drop; after a target instruction segment that triggers a voltage drop is found, the execution function call path and the jump path within the execution function corresponding to the target instruction segment are recorded; the execution path that enters the target instruction segment is stored in the preset record information.

7. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

8. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-5.

9. A chip, characterized in that, It includes one or more interfaces and one or more processors; the interfaces are used to receive signals from the memory of an electronic device and send the signals to the processors, the signals including computer instructions stored in the memory, which, when executed by the processors, cause the electronic device to perform the method of any one of claims 1-5.

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