Vertical cavity surface emitting laser and array

Abstract

The utility model provides a vertical cavity surface emitting laser and an array, and relates to the technical field of semiconductor lasers. The vertical-cavity surface-emitting laser comprises a substrate, an N-type Bragg reflection layer, an active region and a P-type Bragg reflection layer which are stacked in sequence, wherein one side, close to the active region, of the P-type Bragg reflection layer or a P-type region of the active region is provided with a non-oxidized semi-insulating current limiting layer growing at the temperature of 200-430 DEG C, the current limiting layer is provided with a first through hole, one side, close to the active region, of the P-type Bragg reflection layer is provided with a boss, the first through hole is filled with the boss, and the first through hole is provided with a second through hole. The area where the boss is located is a current injection area.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor laser technology, and in particular to a vertical cavity surface-emitting laser and array. Background Technology

[0002] A vertical-cavity surface-emitting laser (VCSEL) is a semiconductor laser with a special structure and function, characterized by laser light emitted perpendicularly to its top surface. Compared to other types of lasers, VCSELs offer advantages such as superior spectral characteristics, narrow spectral lines, single-mode operation, and excellent and stable wavelength uniformity, making them widely applicable in fields such as optical communication, data centers, 3D sensing, autonomous driving, and consumer electronics.

[0003] To achieve current confinement, VCSELs can be categorized into ion-implanted and oxide-confined types. Ion-implanted VCSELs introduce lattice damage and defects in the implanted region, and the size of the current-implanted region is difficult to control precisely. In oxide-confined VCSELs, the oxide confinement layer, with its high Al content, transforms from AlGaAs to Al2O3 during fabrication. This volume reduction leads to mismatches, and the introduced stress easily generates various defects, resulting in a series of reliability issues. Overcoming these problems to achieve current confinement while simultaneously achieving optical field confinement remains a crucial research topic in this field. Utility Model Content

[0004] In view of the above problems, embodiments of the present invention provide a vertical cavity surface-emitting laser and an array.

[0005] One aspect of this invention provides a vertical cavity surface-emitting laser, comprising: a substrate, an N-type Bragg reflector, an active region, and a P-type Bragg reflector, stacked sequentially; wherein, a non-oxidized semi-insulating current-limiting layer grown at a temperature of 200°C to 430°C is provided on the side of the P-type Bragg reflector near the active region or in the P-type region of the active region, the current-limiting layer having a first via, and the side of the P-type Bragg reflector near the active region having a boss, the boss filling the first via, the area where the boss is located being a current injection region.

[0006] According to an embodiment of the present invention, a cap layer is provided on the surface of the current limiting layer near the P-type Bragg reflector layer, and a second through hole is provided in the area of ​​the cap layer opposite to the first through hole. The second through hole has the same cross-sectional shape as the first through hole, and the boss also fills the second through hole.

[0007] According to an embodiment of the present invention, the thickness of the cap layer is less than or equal to one-quarter of the optical wavelength.

[0008] According to an embodiment of the present invention, the cross-sectional shape of the first through hole includes a circle, and the diameter of the circle ranges from 1μm to 50μm.

[0009] According to an embodiment of the present invention, at least one oxide layer is provided on the side of the current limiting layer away from the active region, and a third through hole is provided in the region corresponding to the first through hole in each oxide layer. The size of the third through hole is larger than the size of the first through hole. When multiple oxide layers are provided, the size of each third through hole remains unchanged or increases with the increase of the distance from the first through hole.

[0010] According to an embodiment of the present invention, an ion implantation region is provided on the side of the current limiting layer away from the active region.

[0011] According to an embodiment of the present invention, the number of active regions is one or more; wherein, in the case of multiple active regions, a tunnel junction is provided between adjacent active regions.

[0012] According to an embodiment of the present invention, the vertical cavity surface-emitting laser further includes: a P electrode and an N electrode, the P electrode and the N electrode being disposed on the same side or different sides of the active region, the P electrode being provided with a light-transmitting region; and a lens disposed in the light-transmitting region.

[0013] Another aspect of this invention provides a vertical cavity surface-emitting laser array, comprising a plurality of vertical cavity surface-emitting lasers as described in any embodiment of this invention.

[0014] According to embodiments of this invention, a non-oxidized semi-insulating current-limiting layer generated at low temperatures (200℃~430℃) directly contacts the current-injection region to form a unified structure with lattice matching, thus effectively limiting the current and at least partially overcoming the technical problem of stress defects caused by oxidation-generated current-limiting layers. Simultaneously, the current-injection region is formed concurrently with the P-type Bragg reflector layer, and its shape is a convex waveguide structure, providing excellent confinement of the optical field. Combined, these two features result in a VCSEL of this invention exhibiting excellent confinement of both current and optical field. Attached Figure Description

[0015] The above-mentioned contents, other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

[0016] Figure 1 A schematic diagram of a vertical cavity surface-emitting laser according to an embodiment of the present invention is shown.

[0017] Figure 2 A schematic diagram of a vertical cavity surface-emitting laser according to another embodiment of the present invention is shown.

[0018] Figure 3 This schematic diagram illustrates the structure of a vertical cavity surface-emitting laser with an oxide layer according to an embodiment of the present invention.

[0019] Figure 4 The diagram schematically illustrates the structure of a vertical cavity surface-emitting laser with an ion implantation region according to an embodiment of the present invention.

[0020] Figure 5 The diagram schematically illustrates the structure of a vertical cavity surface-emitting laser with multiple active regions according to an embodiment of the present invention.

[0021] [Explanation of Labels in the Attached Image]

[0022] 100, 200, 300, 400, 500 - Vertical-cavity surface-emitting laser; 10 - Substrate; 20 - N-type Bragg reflector layer; 30 - Active region; 40 - P-type Bragg reflector layer; 41, 41' - Current injection region; 42 - Intermediate layer; 43 - Current confinement layer; 51 - P-electrode; 52 - N-electrode; 60 - Cap layer; 70 - Oxide layer; 80 - Ion implantation region; 90 - Tunnel junction. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0024] It should be noted that similar or identical parts are referred to by the same reference numerals in the accompanying drawings or description. The technical features of the various embodiments exemplified in the specification can be freely combined to form new solutions without conflict, and the shape or thickness of the embodiments may be enlarged in the drawings and indicated in a simplified or convenient manner. Furthermore, elements or implementations not shown or described in the drawings are those known to those skilled in the art. Additionally, while this document provides examples of parameters containing specific values, it should be understood that the parameters need not be exactly equal to the corresponding values ​​but can approximate them within acceptable error tolerances or design constraints.

[0025] Unless there are technical obstacles or contradictions, the various embodiments of this utility model described above can be freely combined to form other embodiments, all of which are within the protection scope of this utility model.

[0026] Although the present invention has been described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to illustrate preferred embodiments of the present invention and should not be construed as limiting the present invention. The dimensions and proportions in the drawings are merely illustrative and should not be construed as limiting the present invention.

[0027] While some embodiments of the present invention have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present invention.

[0028] Figure 1 A schematic diagram of a vertical cavity surface-emitting laser 100 according to an embodiment of the present invention is shown.

[0029] like Figure 1 As shown, a vertical-cavity surface-emitting laser 100 is provided. In this embodiment, the vertical-cavity surface-emitting laser 100 may include a substrate 10, an N-type Bragg reflector layer 20, an active region 30, and a P-type Bragg reflector layer 40 stacked sequentially. The substrate 10 may be, for example, a GaAs substrate or a Si substrate. When using a Si substrate, a buffer layer (not shown) may be provided between the substrate 10 and the N-type Bragg reflector layer 20 to reduce or eliminate stress or defects introduced by mismatch. The N-type Bragg reflector layer 20 can be used to improve the reflection efficiency of light within the laser and enhance light output. The active region 30 is located above the N-type Bragg reflector layer 20 and is used to generate laser light. The active region 30 may include a quantum well and P-type and N-type regions on both sides. The active region 30 may be, for example, an InGaAs / AlGaAs quantum well active region. The P-type Bragg reflector layer 40 is located above the active region 30 and is used to improve light reflectivity. As an example, an N-type and P-type distributed Bragg reflector (DBR) may be an Al₂O₃ with different Al compositions. y Ga 1-y As / Al z Ga 1-z As is grown alternately, and the thickness of each layer corresponds to one-quarter of the optical wavelength.

[0030] Continue reading Figure 1 A current-limiting layer 43 is provided on the side of the P-type Bragg reflector layer 40 near the active region 30 or in the P-type region of the active region 30. The current-limiting layer 43 is grown at a temperature of 200℃ to 430℃ and is a non-oxidized semi-insulating material. For example, the material of the current-limiting layer 43 can be Al. x Ga 1-x As, 0 ≤ x ≤ 1. For example, the current confinement layer 43 can be grown using molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). In this embodiment, a semi-insulating Al grown at low temperature is used. x Ga 1-xAs replaces the oxidation-limited Al2O3, the VCSEL fabricated with this structure has high reliability and can meet the requirements of optical field and current limitation, which can avoid a series of reliability problems caused by the mismatch stress introduced by Al2O3 formed by the oxidation-limited process and AlGaAs / GaAs.

[0031] like Figure 1 As shown, a first through-hole (the area shown by the dashed line in the figure) is provided on the current limiting layer 43. In some embodiments, the cross-sectional shape of the first through-hole can be circular, and the diameter of the circle ranges from 1 μm to 50 μm. The P-type Bragg reflector layer 40 has a boss on the side near the active region 30. Figure 1 The area indicated by the dashed line (where the boss fills the first through-hole) is the current injection region 41. Simultaneously, the current injection region 41 can be formed during the formation of the P-type Bragg reflector layer 40. The current injection region 41 has a convex waveguide structure, which provides excellent confinement of the optical field. In summary, the VCSEL of this invention provides excellent confinement of both current and optical field.

[0032] The following describes two methods for fabricating a vertical-cavity surface-emitting laser 100.

[0033] In the first preparation method, semi-insulating Al can be obtained by low-temperature generation. x GaAs serves as the current confinement layer 43, by etching or removing the Al in the current injection region 41. x GaAs, using regrowth to form a current injection region 41.

[0034] Specifically, an N-type Bragg reflector layer 20, an active region 30, and an intermediate layer 42 can be epitaxially grown on a substrate 10. The substrate 10 can be a GaAs substrate. The active region 30 can be an InGaAs / AlGaAs multi-quantum-well structure. The intermediate layer 42 is made of the same material as the P-type Bragg reflector layer 40, and can be GaAs or Al. x GaAs. Then, the growth temperature was lowered to 200℃~430℃ to grow non-conductive semi-insulating Al at a low temperature. x Ga 1-x As material. Next, the etching mask for the current injection region 41 is defined using photolithography, and some non-conductive Al is removed using dry or wet etching. x Ga 1-xAs, a current-confining layer 43 with a first via is obtained. Next, the etching mask material can be removed, and the sample can be surface-treated before regrowth. Finally, the sample is placed in the growth chamber, and the surface is further cleaned to complete the growth of a P-type Bragg reflector layer 40 on the current-confining layer 43. The P-type Bragg reflector layer 40 forms a boss, i.e., the current injection region 41, in the portion of the current-confining layer 43 where the first via is grown.

[0035] In the second preparation method, low-temperature selective epitaxial growth (LT-SAG) can be used to form non-conductive Al. x GaAs serves as the current confinement layer 43, and the size of the current injection region 41 can be determined by the size of the dielectric mask defined by photolithography. After the SAG low-temperature growth is completed, the dielectric mask is removed, and then a P-type Bragg reflector layer 40 with protrusions is formed by epitaxial growth.

[0036] Specifically, an N-type Bragg reflector layer 20, an active region 30, and an intermediate layer 42 can be epitaxially grown on a substrate 10. The substrate 10 can be a GaAs substrate. The intermediate layer 42 is made of the same material as the P-type Bragg reflector layer 40, and can be either GaAs or Al. x GaAs. This step is the same as the first preparation method. Next, low-temperature grown semi-insulating GaAs or Al can be prepared. x The GaAs dielectric mask has the same size and shape as the current injection region 41. Next, selective epitaxial growth of semi-insulating Al is performed on the intermediate layer 42. x Ga 1-x As, the growth temperature is 200℃~430℃ to obtain the current confinement layer 43. Then, the dielectric mask is removed to form the first via of the current confinement layer 43, and the sample is cleaned. Next, the sample is placed into the growth chamber, and the sample surface is treated. Finally, p-type doped GaAs or Al is grown on the current confinement layer 43. x GaAs is used to obtain a P-type Bragg reflector layer 40. The P-type Bragg reflector layer 40 is grown in the portion of the first via of the current confinement layer 43 to form a boss, which is the current injection region 41.

[0037] The vertical-cavity surface-emitting laser 100 fabricated using any of the above methods has at least the following advantages: 1) Since it does not use Al xGaAs can avoid a series of reliability issues caused by oxide layers by being oxidized to Al2O3 with wet oxygen. 2) It can simultaneously achieve effective confinement of optical field and current. 3) It is not only suitable for VCSELs with small apertures, such as VCSELs for high-speed applications, single-mode or multi-mode, but also for VCSELs with large apertures, such as those requiring high-power applications. Specifically, the aperture range of the current injection region 41 can be 1μm~50μm. 4) The entire epitaxial structure of the VCSEL, that is, the semiconductors that make up each layer of the VCSEL, are composed of lattice-matched binary and ternary compound semiconductors, which further increases the reliability of the VCSEL. 5) Doping of the current injection region can be completed during growth. 6) To further improve the performance of the VCSEL, ion implantation can be combined, for example, for higher speeds and multi-junction VCSELs. This will be explained further later.

[0038] It should be emphasized that, in any of the above preparation methods, to ensure the low-temperature growth of semi-insulating GaAs or Al... x The surface of GaAs can support secondary epitaxial growth, but the oxide layer formed on the surface needs to be removed. For Al with a large x value... x Ga 1- x As, surface oxidation is severe, making cleaning more difficult. In in-situ surface treatment, especially heat treatment under a protected atmosphere, deviations in the surface chemical composition are easily caused. Specifically, this can lead to Al... x Ga atoms detach from the GaAs surface, forming Ga vacancies; Al atoms accumulate on the surface; and atoms in the surface layer become mixed with each other. These factors create new defects on the surface and interfaces of the epitaxial layer, reducing its quality. Therefore, for aluminum-containing Al... x Removing the surface oxide layer is crucial for the secondary epitaxial growth of GaAs.

[0039] In the above preparation method, the surface treatment can be performed in two steps: The first step involves a rigorous cleaning process to remove the oxide layer from the sample surface before loading it into the growth chamber. For example, one or a combination of H2SO4, NH4OH, HCl, and HF can be used, or the sample surface can be sulfided to remove the oxide layer. The second step involves in-situ surface treatment after loading the sample into the growth chamber, before growth, to remove any remaining oxide layer. Thanks to the pretreatment step in the first step, the oxide layer present on the sample surface during the second step is mainly formed during sample loading. For example, a conventional deoxidation process can be used, or the sample surface can be cleaned at a lower temperature. This avoids deviations in the chemical composition of the sample surface atoms due to excessive surface treatment, and the resulting surface and interface defects, thereby improving the overall quality of the epitaxial layer structure. These two oxide removal steps ensure that the sample surface is free of oxides before epitaxial growth.

[0040] Based on the above embodiments, in order to reduce the difficulty of regrowth, high-component Al can be grown at low temperatures. x Ga 1-x After As, grow a layer of GaAs or Al with a lower composition. x Ga 1-x As serves as the surface coating layer. Figure 2 A schematic diagram of a vertical cavity surface-emitting laser 200 according to another embodiment of the present invention is shown.

[0041] like Figure 2 As shown, a vertical-cavity surface-emitting laser 200 is provided. The vertical-cavity surface-emitting laser 200 may include a cap layer 60. The cap layer 60 may serve as a cover layer on the surface of the current-limiting layer 43. The material of the cap layer 60 may be GaAs or Al with a lower Al composition. x Ga 1-x As. A second through hole is provided in the area of ​​the cap layer 60 opposite to the first through hole. The second through hole has the same cross-sectional shape as the first through hole. (The boss...) Figure 2 The area shown by the dashed line is filled with the second through-hole to form a new current injection region 41'. That is, the current injection region 41' is formed by filling the first and second through-holes with the boss structure of the P-type Bragg reflector layer 40. In this embodiment, the cap layer 60 and the current limiting layer 43 can be grown simultaneously at low temperature, have semi-insulating characteristics, and simultaneously limit the current.

[0042] In the fabrication of vertical-cavity surface-emitting lasers 100 and 200, the fabrication processes of current injection regions 41 and 41' can be identical; that is, the upper cap layer 60 and the lower current-confining layer 43 can be simultaneously removed using wet or dry methods, exposing the surface of the intermediate layer 42, thereby defining the position and size of the current injection regions. The difference lies in the fact that, in the fabrication of vertical-cavity surface-emitting laser 200, after photolithography, etching, and cleaning processes, the exposed surface outside the current injection regions is the cap layer 60. The material of the cap layer 60 can be, for example, GaAs or Al with a low Al content. x Ga 1-x As such, when loading the sample into the growth chamber for secondary growth, the complex steps of removing the oxide layer can be avoided, simplifying the process. Due to the presence of Al... x Ga 1-x The current-limiting layer 43 and the cap layer 60 made of As material can also be conductive or doped at normal growth temperature, or they can be Al with low aluminum content. x Ga 1-x As.

[0043] The thickness of the cap layer 60 should meet a quarter optical wavelength requirement. Specifically, the thickness of the cap layer 60 is less than or equal to a quarter optical wavelength. If the thicknesses of the current-limiting layer 43 and the cap layer 60 above it are both less than a quarter optical wavelength, they need to be supplemented with materials of appropriate thickness and composition to meet the quarter optical wavelength requirement. In other words, the cap layer 60, in addition to serving as a high-aluminum component Al... x Ga 1-x In addition to the protective layer of the As current-limiting layer 43, it also becomes one of the layers of the P-type Bragg reflector layer 40.

[0044] Based on the above embodiments, an oxide layer 70 can be provided in the P-type Bragg reflector layer 40. Figure 3 The diagram schematically illustrates a structure of a vertical cavity surface-emitting laser 300 having an oxide layer 70 according to an embodiment of the present invention.

[0045] like Figure 3As shown, a vertical-cavity surface-emitting laser (VCSEL) 300 is provided. At least one oxide layer 70 can be disposed on the side of the current-limiting layer 43 away from the active region 30. For example, it can be one, two, or more layers. A third via (also called an oxide via or oxide ring) is disposed in the region corresponding to the first via (i.e., the current injection region 41) of the oxide layer 70. The size of the third via is larger than that of the first via. The cross-sectional shape of the first via can be circular, with a diameter ranging from 1 μm to 50 μm. Correspondingly, the cross-sectional shape of the third via can also be circular. The oxide layer is, for example, composed of aluminum oxide (Al2O3) formed by the oxidation of AlGaAs. This material has good insulating properties, which helps to reduce capacitance and also serves to limit current and optical field. By providing an oxide layer on the side of the current-limiting layer 43 away from the active region 30, the capacitance of the device can be reduced, thereby increasing the bandwidth of the VCSEL.

[0046] Continue reading Figure 3 With multiple oxide layers 6, the size of the third via can gradually increase with the increase of distance from the current limiting layer 43. In other embodiments, the size of the third via can remain constant with the increase of distance from the current limiting layer 43. By precisely designing the size and position of the oxide holes, precise control of the current distribution can be achieved, thereby improving the efficiency and stability of the laser. This design has good scalability, and the number of oxide layers and the size of the oxide holes can be adjusted according to specific needs; this invention does not impose specific limitations.

[0047] Based on the above embodiments, an ion implantation region 80 can be provided in the P-type Bragg reflector layer 40. Figure 4 The diagram schematically illustrates the structure of a vertical cavity surface-emitting laser 400 having an ion implantation region 80 according to an embodiment of the present invention.

[0048] like Figure 4 As shown, a vertical-cavity surface-emitting laser 400 is provided. An ion-implanted region 80 is provided on the side of the current-limiting layer 43 away from the active region 30, thereby further reducing the capacitance of the device and increasing the bandwidth.

[0049] As an example, the implanted ion in ion implantation region 80 could be H. + O + N + and F + One or more of these ions. These ions possess different electrical properties in semiconductor materials, and precise control of the implantation conditions and distribution can achieve fine manipulation of the electric field and capacitance. The ion implantation energy can be adjusted according to specific material and design requirements. For example, for H... + The ion implantation energy can be set between 300 keV and 420 keV to form a suitable charge distribution.

[0050] Based on the above embodiments, when there are multiple active regions 30, a tunnel junction 90 can be set between adjacent active regions 30. Figure 5 The diagram schematically illustrates the structure of a vertical cavity surface-emitting laser 500 having a plurality of active regions 30 according to an embodiment of the present invention.

[0051] like Figure 5 As shown, a vertical-cavity surface-emitting laser 500 is provided. To increase output power, multiple active regions 30 can be designed. A tunnel junction (also called a PN junction) 90 can be arranged between adjacent active regions 30. The tunnel junction 90 is configured to allow charge carriers (electrons or holes) to tunnel from one active region to another without overcoming a large energy barrier. Through the design of the tunnel junction 90, electrical coupling between adjacent active regions 30 can be achieved, allowing optical signals from different active regions 30 to be superimposed, thereby increasing the total output power.

[0052] As an example, the tunnel junction can be made of GaAs / AlGaAs material, with a thickness of, for example, 15-30 nm. The design of the tunnel junction can comprehensively consider factors such as material selection, thickness, and doping concentration to achieve high tunneling efficiency. By optimizing the design of the tunnel junction, the overall performance of the laser can be improved, including output power, bandwidth, and response speed.

[0053] Understandably, current-limiting layers could be added to both sides of the tunnel junction 90, or combined with ion implantation, to further optimize the current distribution.

[0054] By designing multiple active regions 30 within the VCSEL and connecting them using tunnel junctions 90, the output power of the laser can be significantly improved. This design is highly advantageous for applications requiring high power output, such as autonomous driving and LiDAR.

[0055] like Figures 1 to 5 As shown, the vertical cavity surface-emitting laser of any of the above embodiments may further include a P-electrode 51 and an N-electrode 52, which may be disposed on different sides of the active region 30. The P-electrode 51 is provided with a light-transmitting area, which can emit laser light from the front.

[0056] In some embodiments, such as VCSELs with wavelengths greater than 870 nm, the P electrode 51 and N electrode 52 can also be disposed on the same side of the active region 30, for example, both the P electrode 51 and N electrode 52 are located at the bottom of the VCSEL. That is, the laser can be emitted from the back side of the VCSEL. Back-emitting VCSELs can be better compatible with silicon-based optoelectronic integrated circuits, so that light can be emitted from the bottom of the chip (the side in contact with silicon-based electronic devices).

[0057] Whether emitting light from the front or the back, VCSELs can be integrated with lenses (not shown in the figure) to improve beam focusing and coupling efficiency. Lenses can be integrated directly above or below the light-transmitting area, or implemented through an external optical system. Lenses can be made by adding one or more layers of transparent material (such as glass or plastic) above or around the light-transmitting area, with these materials having specific shapes (such as hemispherical or parabolic) to focus or collimate the light output.

[0058] In a front-emitting VCSEL, a lens can be integrated above the light-transmitting area of ​​the P-electrode 51 to focus the light within a smaller angular range, thereby improving the efficiency of light coupling to optical fibers or other optical components. In a back-emitting VCSEL, the lens can be integrated at the bottom of the chip or used as an external component in conjunction with the chip to enhance the directionality of light emitted from the back.

[0059] Another aspect of this invention provides a vertical cavity surface-emitting laser array, comprising a plurality of vertical cavity surface-emitting lasers as described in any embodiment of this invention.

[0060] Vertical cavity surface-emitting laser arrays can be 1D or 2D addressable laser arrays.

[0061] In some embodiments, a 1D addressable laser array refers to a laser array in which the VCSEL units can be independently controlled in a one-dimensional manner (e.g., from left to right). This array structure is suitable for applications requiring horizontal scanning or linear detection.

[0062] For example, in the LiDAR system of autonomous vehicles, a 1D addressable VCSEL array can be used for horizontal scanning to detect obstacles in front of the vehicle. By controlling the lighting sequence and frequency of each VCSEL unit, fast and accurate horizontal scanning can be achieved, thereby generating a 3D point cloud map of the surrounding environment.

[0063] For example, in optical communication systems, 1D addressable VCSEL arrays can be used to construct multi-channel fiber optic communication links. Each VCSEL unit can independently modulate and transmit data, thereby improving the system's data transmission capacity and flexibility.

[0064] 2D addressable laser arrays allow for independent two-dimensional (i.e., horizontal and vertical) control of each VCSEL unit. This array structure offers greater flexibility and control precision, making it suitable for applications requiring complex scanning patterns or high-resolution detection.

[0065] For example, 2D addressable VCSEL arrays are widely used in 3D imaging and facial recognition systems in consumer electronics products such as smartphones and tablets. By controlling the lighting order and intensity of each VCSEL unit in the array, accurate 3D point cloud maps can be generated, enabling high-precision facial recognition, gesture recognition, and other functions.

[0066] For example, in the perception systems of autonomous vehicles, 2D addressable VCSEL arrays can be used to build high-precision solid-state LiDAR. This type of LiDAR can scan in two directions (such as horizontal and vertical), thus providing a more comprehensive perception of pedestrians, vehicles, and other obstacles in the surrounding environment.

[0067] The size of a VCSEL array can be customized to meet specific application requirements. For example, a VCSEL array can reach a size of 2440×2430μm, suitable for applications requiring high power output.

[0068] The emission wavelength and power of VCSEL arrays can also be customized according to application requirements. For example, the center wavelength of the VCSEL array can be selected from 905nm and 940nm, and the output power can reach over 35W. For arrays using multi-junction VCSELs, the output power can reach 400W.

[0069] As an example, the vertical-cavity surface-emitting laser (VCSEL) of this embodiment can be used for high-speed data transmission. The wavelength can be 850nm, 880nm, 910nm, 940nm, 980nm, 1060nm, or other wavelengths. It can be a single-hole chip or array, a single-junction or multi-junction VCSEL. The wavelengths 850nm, 880nm, 910nm, and 940nm are industry-standard wavelengths for light sources using multimode fiber. Furthermore, it can also be used in sensing applications, with wavelengths of 850nm, 905nm, 940nm, or other wavelengths. It can be a single chip, multiple chips, or various array chips, a single-junction or multi-junction VCSEL.

[0070] Understandably, in addition to 1D and 2D addressing methods, there are more complex addressing methods such as interleaved emission, and the appropriate addressing method can be selected according to the specific application scenario. A vertical-cavity surface-emitting laser array can be a surface array in which the vertical-cavity surface-emitting lasers are regularly or randomly distributed.

[0071] 1D and 2D addressable laser arrays provide more flexibility and possibilities for the application of vertical cavity surface emission lasers, enabling VCSEL technology to be widely used in fields such as lidar, 3D imaging, and telecommunications.

[0072] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of this invention. The appended method embodiments provide elements of various steps in an exemplary order and are not intended to be limited to a specific order or hierarchy.

[0073] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this utility model. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted when they may cause confusion in understanding this utility model. Furthermore, the shapes, sizes, and positional relationships of the components in the drawings do not reflect their actual size, proportions, and actual positional relationships.

[0074] In the detailed description above, various features are combined together in a single embodiment to simplify the present invention. This disclosure should not be construed as reflecting such an intent.

[0075] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. The term "comprising" as used in the specification is similar in its coverage to the term "including." The use of any term "or" in the specification is intended to indicate "non-exclusive or."

[0076] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above are only specific embodiments of this utility model and are not intended to limit this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A vertical cavity surface emitting laser, characterized by, include: The substrate, N-type Bragg reflector layer, active region, and P-type Bragg reflector layer are stacked sequentially. Specifically, a non-oxidized semi-insulating current-limiting layer grown at a temperature of 200℃~430℃ is provided on the side of the P-type Bragg reflector layer near the active region or in the P-type region of the active region. A first through-hole is provided on the current-limiting layer. A boss is provided on the side of the P-type Bragg reflector layer near the active region. The boss fills the first through-hole. The area where the boss is located is the current injection region.

2. The vertical cavity surface emitting laser according to claim 1, characterized in that A cap layer is provided on the surface of the current limiting layer near the P-type Bragg reflector layer. A second through hole is provided in the area of ​​the cap layer opposite to the first through hole. The second through hole has the same cross-sectional shape as the first through hole. The boss fills the second through hole.

3. The vertical cavity surface emitting laser of claim 2, wherein, The thickness of the cap layer is less than or equal to one-quarter of the optical wavelength.

4. The vertical cavity surface emitting laser according to claim 1 or 2, characterized in that The cross-sectional shape of the first through hole includes a circle, and the diameter of the circle ranges from 1μm to 50μm.

5. The vertical cavity surface emitting laser of claim 1, wherein, At least one oxide layer is provided on the side of the current limiting layer away from the active region, and a third via is provided in the region of each oxide layer corresponding to the first via, wherein the size of the third via is larger than the size of the first via. In the case of having multiple layers of the oxide layer, the size of each of the third through holes remains constant or increases with the increase of the distance from the first through hole.

6. The vertical cavity surface emitting laser of claim 1, wherein, An ion implantation region is provided on the side of the current limiting layer away from the active region.

7. The vertical cavity surface emitting laser of claim 1, wherein, The number of active regions is one or more; In the case of multiple active regions, a tunnel junction is provided between adjacent active regions.

8. The vertical cavity surface emitting laser of claim 1, wherein, The vertical-cavity surface-emitting laser also includes: P electrode and N electrode, wherein the P electrode and the N electrode are disposed on the same side or different sides of the active region, and the P electrode is provided with a light-transmitting area; A lens is disposed in the light-transmitting area.

9. A vertical cavity surface emitting laser array, characterized by It includes multiple vertical cavity surface-emitting lasers as described in any one of claims 1 to 8.

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