Current limiter for storage device

Abstract

Including storage device: a memory arrangement (200) containing several memory cells (210) arranged in rows and columns; a control loop bias generator (400) configured to output a voltage signal to a column decoder (450) configured to output a column selection signal to the memory arrangement (200); a current limiter (300) configured to receive an output signal (VG) from the control loop bias generator (400), wherein the current limiter (300) is coupled to several columns of the memory arrangement (200), wherein the current limiter (300) comprises a cascode of a first NMOS transistor (M4) and a second coupled NMOS transistor (M2), wherein the bias generator (400) comprises a third cascode-connected NMOS transistor (M3) and a fourth cascode-connected NMOS transistor (M1) and an operational amplifier (402) configured to receive a feedback signal, where a source of the third NMOS transistor (M3) is connected to a gate of the second NMOS transistor (M2).

Description

REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over the preliminary US patent application number 62 / 796864, filed on January 25, 2019, the disclosure of which in its entirety is hereby incorporated by reference herein. BACKGROUND

[0002] Memory devices are used to store information in semiconductor devices and systems. Resistive Random Access Memory (RRAM) cells are non-volatile memory cells that store information based on changes in electrical resistance. Generally, an RRAM cell contains a memory node in which a bottom electrode, an ohmic switching layer, and an upper electrode can be stacked sequentially. The resistance of the ohmic switching layer varies according to an applied voltage. An RRAM cell can exist in multiple states, each with different electrical resistances. Each of these states can represent digital information. The state can be changed by applying a predetermined voltage or current between the electrodes. A state is retained unless a previously defined operation is performed.

[0003] Reference is made to the documents US20170004882A1, US20110149644A1 and US20180083578A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been enlarged or reduced arbitrarily for the sake of clarity. Fig. Figure 1 is a block diagram according to some embodiments, which generally illustrates an exemplary storage device comprising a bias generator coupled to an arrangement of ohmic storage cells and a current limiter. Fig. Figure 2 is a circuit diagram according to some embodiments, illustrating an exemplary bias generator circuit coupled with an exemplary current limiter circuit and an arrangement of ohmic storage cells. Fig. Figure 3 is a circuit diagram according to some embodiments illustrating another exemplary bias generator circuit coupled to another exemplary current limiter circuit. Fig. Figure 4 is a circuit diagram according to some embodiments illustrating another exemplary bias generator circuit coupled to another exemplary current limiter circuit. Fig. Figure 5 is a flowchart of a method according to some embodiments for biasing a current limiter coupled to an arrangement of ohmic storage cells. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact.Furthermore, this disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the FIGS. These spatially relative terms are also intended to encompass other orientations of the device in use or operation besides the orientation shown in the FIGS. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0007] An RRAM memory device can generally comprise an array of RRAM cells, each containing an RRAM resistor element and an access transistor. The RRAM resistor element has a resistance state that can be switched between a low-resistance and a high-resistance state. RRAM devices generally include a layer of high-k dielectric material sandwiched between conductive electrodes arranged within a back-end-of-line (BEOL) metallization stack. The reversible switching between low- and high-resistance states in an RRAM device is enabled by the selective formation of a conductive filament through the high-k dielectric layer.Applying a voltage to the RRAM cell triggers a switching event that forms a conductive filament through the layer of high-k-value dielectric material, thereby switching the RRAM device from a high-resistance state to a low-resistance state. This is known as the "SET" operation. Conversely, the switching event from a low-resistance state to a high-resistance state is known as the "RESET" operation. The low and high resistances are used to indicate a digital signal, "1" or "0," thus enabling data storage.

[0008] In each RRAM cell, the RRAM resistor has a first terminal coupled to a bit line and a second terminal connected to an access transistor. The access transistor has a gate coupled to a word line, a source coupled to a source line, and a drain coupled to the second terminal of the RRAM resistor. Activating the word line turns on the access transistor, allowing the source line to be coupled to the second terminal of the RRAM resistor.

[0009] During RRAM operations, such as RRAM creation and SET operations, a fixed current level is desirable. A current limiter circuit can be used for such RRAM creation and SET operations. A current limiter can fix the RRAM cell filament size by maintaining a fixed burden current level. To ensure good current limiting behavior, a cascode transistor structure is often used to increase the resistance (Rout) of the current limiter compared to a single-transistor current limiter. However, such structures can increase the voltage overhead during operation, thus impacting write performance, especially in charge-pump mode. These structures can also increase the additional IC chip area required for the current limiter circuitry for each column of the RRAM memory array.

[0010] Some conventional current limiters use a cascode or stacked transistor structure with a fixed gate bias applied to the upper device of the current limiter. To increase the current limiter's output, the lower transistor typically operates in saturation. The additional total operating voltage is the saturation voltage of the lower transistor plus the drain-source voltage (VDS) of the upper device. Furthermore, the total operating voltage of a cascode current limiter and the associated additional voltage can vary. Such variation can occur when a fixed gate bias is used for the upper transistor because temperature fluctuations, or differences in transistor performance due to manufacturing variations within the IC design process, can also affect the VDS of the lower transistor in the upper transistor.

[0011] Fig. Figure 1 is a block diagram according to some embodiments, which generally illustrates aspects of an exemplary memory device 100 comprising a control-loop bias generator 400 operatively coupled to an array of resistive memory cells 200 and a current limiter 300. Each RRAM cell of the array 200 has a first terminal coupled to a bit line and a second terminal coupled to an access transistor. The access transistor has a gate coupled to a word line, a source coupled to a source line, and a drain coupled to a second terminal of the RRAM resistive element.

[0012] Memory cells of the array 200 are identified for read and write operations via a memory address, which is received, for example, by a computer processor. The memory address is decoded into row and column addresses, which identify a specific row and column, respectively, of the array 200. Based on the row address, the selected word line is activated, and the corresponding access transistor is switched on so that the source line can be coupled to the second terminal of the RRAM resistor element. The column address is received by a column multiplexer (MUX) 202, which is configured to select a specific column of the array 200 in response to the column address.

[0013] In the illustrated embodiment, the current limiter 300 is operatively coupled to the arrangement 200 to limit the current applied to the RRAM resistor elements, for example, during SET operations. As explained in more detail below, examples of the MUX 202 include components that also form the current limiter 300. In other words, some elements of the MUX 202 can be shared between the MUX 202 and the current limiter 300.

[0014] The bias generator 400 is operatively coupled to the current limiter 300 to provide the bias voltage applied to the current limiter 300. Furthermore, as discussed below, examples of the bias generator include a feedback loop to maintain a desired bias voltage to the current limiter 300.

[0015] Fig. Figure 2 is a circuit diagram according to some embodiments, illustrating an example of the storage device 100 which includes a bias generator circuit 400 coupled to an exemplary current limiter circuit 300 and an arrangement of ohmic storage cells 200.

[0016] The illustrated arrangement of ohmic memory cells 200 contains several ohmic memory (for example, RRAM) cells. For the sake of simplicity, in Fig. Figure 2 shows only four RRAM memory cells 210a-d (collectively referred to as cells 210); a typical resistive memory array would contain many more RRAM memory cells. The RRAM cells 210 are arranged in rows and / or columns within the array of resistive memory cells 200. The RRAM cells 210 within a row of the array of resistive memory cells 200 are coupled by a word line; for example, RRAM cell 210a is coupled to WL[0]. The RRAM cells 210 within a column of the array of resistive memory cells 200 are coupled by a bit line BL and a source line SL. Each individual RRAM cell 210 is assigned an address defined by the word line, for example, WL[n], and the bit line / source line pairs of each column, for example, ysel[m].In the embodiment shown, the arrangement of ohmic memory cells contains 200 n+1 rows (WL[0] to WL[n]) and m+1 columns (ysel[0] to ysel[m]), where n and m are integers greater than 0.

[0017] Each of the RRAM cells 210 contains an ohmic memory element 212 and an access transistor 214. The ohmic memory element 212 has an ohmic state that can be switched between a low-ohmic state and a high-ohmic state. The ohmic states indicate a data value (for example, a "1" or "0") that is stored within the ohmic memory element 212. The ohmic memory element 212 has a first terminal coupled to the bit line BL and a second terminal coupled to the access transistor 214. The access transistor 214 has a gate coupled to the word line of the row in which the RRAM cell 210 is located, for example, WL[0], a source coupled to the source line SL, and a drain coupled to the second terminal of the ohmic memory element 212.

[0018] The arrangement of resistive memory cells 200 is configured to read data from and / or write data to the multiple RRAM cells 210. A word line signal, such as a word line voltage V, is used. WL A signal is applied to one of the word lines WL based on a received word line address, and bit line / source line signals are applied to the corresponding bit lines BL and source lines SL. By selectively applying signals to the word lines WL, bit lines BL, and source lines SL, form, SET, RESET, and READ operations can be performed on selected of the several RRAM cells 210. For example, to set data for RRAM cell 210a (SET), a word line voltage V is applied. WLA voltage is applied to the word line WL[0], and BL / SL voltages (VBL / VSL) are applied to the bit line BL and a source line SL for column m. The applied VBL / VSL causes a previously defined SET current to flow through the resistive memory element 212, forming a filament and switching the resistive memory element 212 to the low-resistance state, thereby storing a logical "1" reference point in the RRAM cell 210a.

[0019] In some embodiments, the array of resistive memory cells 200 is connected to the column MUX 202. The column MUX 202 contains several column selector transistors 304, which are operatively connected to the bit lines BL and the source lines SL of the array of resistive memory cells 200. In the embodiment in Fig. The simplified example shown contains the MUX 202 bit line selection transistors 304a and source line selection transistors 304b for each column of the memory arrangement 200.

[0020] A column decoder, for example the column decoder 450, determines the column for which an operation, for example create, SET, RESET, READ, is to be performed, and sends a signal, for example a column selection ysel[m], to the gates of the column selection transistors 304 of the corresponding column. In some embodiments, the column decoder 450 is a purely logic device that outputs a zero-voltage signal, for example no signal, for unselected columns, which disconnects the current limiter circuit from the source lines SL and bit lines BL of the unselected columns, and the column decoder 450 outputs the voltage signal VY of the operational amplifier 402, which is output for the selected column, for example ysel[m] = VY for the selected column.

[0021] In some embodiments, the current limiter circuit 300 includes a transistor cascode containing an upper transistor M4 and a lower transistor M2. In the example shown, the upper transistor M4 is the source-line selector transistor 304b, which is connected to the source line SL of a column of the array of resistive memory cells 200. Each of the transistors 304b of the illustrated array, which form the upper devices of the current limiter 300, is connected to the lower current limiter transistor M2. The upper transistors 304b further include a gate connected to the output of a column decoder, for example, the column decoder 450. The lower transistor M2 is connected to ground and has a gate connected to the bias generator 400. In some embodiments, both the upper transistor M4 and the lower transistor M2 of the cascode (the cascode circuit) can be NMOS MOSFET transistors.Other transistor types can also be used effectively in other embodiments.

[0022] Thus, in some examples, the column selection transistors 304b, which are connected to the source lines SL in column MUX 202 of the arrangement of ohmic memory cells 200, can be used as the upper transistor M4 in the current limiting circuit 300. In some embodiments, such as the one in Fig. In the example shown in Figure 2, the lower transistor M2 in the current limiter circuit 300 can be a global transistor connected to each of the column selector transistors M4 of column MUX 202 of the arrangement of ohmic memory cells 200.In comparison to the case where several lower transistors M2 are used, corresponding to each of the several columns in the arrangement of ohmic memory cells 200, the area required for the current limiter circuit 300 can be reduced by using such a global lower transistor M2 as the lower transistor for the cascode (cascode circuit) of each of the columns of the arrangement of ohmic memory cells 200. The additional area requirement in an IC that uses a memory device 100, because the current limiter circuit 300 is included for each of the columns of the arrangement of ohmic memory cells 200, is further reduced by using the column selector transistors 304 of column MUX 202 of the arrangement of ohmic memory cells 200 as the topmost transistor M4 in the current limiter circuit 300 for each of the columns.

[0023] In some embodiments, the bias generator circuit 400 includes an operational amplifier (op-amp) 402, a transistor M3, a transistor M1, a node 404, and a voltage supply terminal connected to a voltage source VDIO to provide a predefined reference current Iref. Transistor M3 has a source terminal connected to the voltage source VDIO and the gates of both transistor M1 and the lower transistor M2 of the current limiter circuit 300. Transistor M3 also has a drain terminal connected to the source terminal of transistor M1 and the inverting input terminal of the operational amplifier 402, and a gate connected to the output of the operational amplifier 402. Transistor M1 has a drain terminal connected to ground.The operational amplifier 402 has a non-inverting input terminal connected to receive a predetermined clamping voltage Vpin. The output terminal of the operational amplifier 402 is additionally connected to the column decoder 450 to route its output voltage VY to the gates of the column selector transistors 304 of column MUX 202 of the array of resistive memory cells 200, including the upper transistors M4 of each column in the array of resistive memory cells 200, as a signal ysel[m]. For example, for a column m determined by the column decoder 450, the voltage applied to the gates of the column selector transistors connected to the bit line BL and the source SL of column m, for example ysel[m], is equal to the output voltage VY of the operational amplifier 402. The operation of the bias generator circuit 400 in conjunction with the current limiter circuit 300 is described below with respect to... Fig. 3 discussed.

[0024] Fig. Figure 3 is a circuit diagram according to some embodiments, illustrating an exemplary bias generator circuit 400 coupled to an exemplary current limiter circuit 300, as shown in Fig. 2 shown. In the illustrated example, the bias generator circuit 400 includes a voltage source VDIO that injects a reference current Iref into the circuit, a transistor M3 and a transistor M1, an operational amplifier 402, and a node 404 at the drain-source junction of transistors M3 and M1, all connected as above with respect to Fig. 2 are connected as described above. The current limiter circuit 300 contains a cascade or stack arrangement comprising an upper transistor M4 and a lower transistor M2, connected as above with respect to Fig. 2 are described as connected.

[0025] In the example shown, the operational amplifier 402 outputs negative feedback within the bias generator circuit 400 to clamp the voltage at node 404 to a predetermined voltage, Vpin, and thus also clamp the drain-source voltage (VDS) of transistor M1 to the voltage Vpin. In this example, the voltage at node 404 is equal to the gate voltage of transistor M3, for example, the output voltage VY of the operational amplifier 402, minus the threshold voltage of transistor M3. In some embodiments, Vpin is less than 1 volt (V), in others it is less than 600 millivolts (mV), in still others it is 200 mV or less, and in yet others it is 100 mV or less. In some embodiments, transistor M1 and the lower transistor M2 are matched and form a current mirror.Or, put another way: The characteristics of transistor M1 and the lower transistor M2, such as channel length, width, threshold voltage, etc., are matched, and the gate voltage of both transistor M1 and the lower transistor M2 is precisely defined by the feedback loop connecting the gates of both transistors to the source of transistor M3. This results in a drain-source voltage (VDS) of transistor M2 that is equal to the VDS of transistor M1, causing the current flowing through the lower transistor M2 to mirror that flowing through transistor M1. In some embodiments, the Vpin is chosen to supply a voltage bias (VG) to the gate of the lower transistor M3, enabling it to operate in the saturation region of its characteristic MOSFET-IV curve.Thus, the lower transistor M3 acts as a variable resistor and limits the current that may flow along the source line SL during a SET operation.

[0026] In the example shown, the output (VY) of the operational amplifier 402, for example, the gain, is selected such that a gate voltage is applied to transistor M3, resulting in a reference current Iref equal to the desired, previously defined SET current. Generally, the SET current is determined by the type of resistive storage element 212 used in the RRAM cells 210. In some embodiments, the SET current is at least 100 microamperes (µA). In some embodiments, the SET current is at least 300 µA. In other embodiments, the SET current is at least 450 µA.

[0027] In some embodiments, the output VY of operational amplifier 402 can be varied via the negative feedback loop containing operational amplifier 402 in order to clamp the voltage at node 404 to Vpin and thus clamp the VDS of both transistor M1 and the "mirrored" lower transistor M2 to Vpin. Such a variation of the output VY of operational amplifier 402 can occur in response to changing transistor characteristics, for example, due to temperature fluctuations.

[0028] In some embodiments, the operating voltage for the current limiter circuit 300 is defined by the clamping voltage Vpin plus the VDS of the upper transistor M4. In some examples, an operating voltage of 0.3 V can be achieved. The VDS and gate-source voltage (VGS) of the lower transistor M2 can be fixed by the control loop arrangement. The previously fixed VDS level allows for a lower operating voltage. For example, in arrangements without the negative feedback provided by the operational amplifier 402, the operating voltage of the current limiter circuit 300 is typically 0.6 V or higher, since the gates of transistor M3 and the upper transistor M4 are usually connected to Vdd and not to the output voltage VY of the operational amplifier 402.Or, put another way: The operational amplifier 402 enables the lowering of the VDS of transistor M1 in the bias generator circuit 400, and consequently also the VDS of the lower transistor M2 in the current limiter circuit 300, while simultaneously providing sufficient voltage at the gates of transistor M3 and the upper transistor M4 so that Iref can flow with the previously defined SET current. Furthermore, the negative feedback provided by the operational amplifier 402 can adaptively adjust the gate voltage of transistor M1 to compensate for process and temperature variations, which in turn adaptively adjusts the gate voltage VG of the lower transistor M2, because the lower transistor M2 is a current mirror of transistor M1, thus stabilizing the additional voltage of the current limiter circuit 300.

[0029] In some embodiments, the bias generator circuit 400 is global for the storage device 100. For example, a single bias generator circuit 400 can be used for a storage device 100 to generate the bias voltages VG and VY for all columns of the array of resistive memory cells 200. Because the upper transistor M4 of the cascode current limiter circuit 300 is provided by the column MUX associated with the array of resistive memory cells 200, the only additional main area requirement added to the storage device 100 is the limiter with the single lower transistor M2. In some embodiments, several lower transistors M2 can be provided, one for each column of the array of resistive memory cells 200, instead of a single lower transistor M2 connected to each of the column selector transistors of the MUX, for example, upper transistors M4, as in Fig. 2 shown.

[0030] Fig. Figure 4 is a circuit diagram according to some embodiments, illustrating another exemplary bias generator circuit 400 coupled to another exemplary current limiter circuit 300. Both the one in Fig. 4 shown bias generator circuit 400 as well as the one in Fig. The four current limiter circuits shown (300) are similar to those in Fig. The three counterparts shown differ in that they use an I / O transistor 406 as transistor M1 and an I / O transistor 306 as the lower transistor M2. In some embodiments, such I / O transistors are relatively thicker and more robust than the transistors used in the array of ohmic memory cells 200. For example, the physical components of such I / O transistors, such as the N-wells, P-wells, source and drain contacts, channel width and length, polysilicon gate and gate contact, etc., are larger and designed for higher voltages and currents. In some embodiments, the use of I / O transistors can protect the current limiting circuit 300, the lower transistor M2, and transistor M1 thanks to larger physical components that can withstand higher voltages and currents.In some embodiments, the use of IO transistors can prevent gate leakage currents resulting from a high gate-source voltage, VGS, at both transistor M1 and the lower transistor M2, since these transistors have a larger gate threshold voltage.

[0031] Fig. Figure 5 is a flowchart of a method according to some embodiments for biasing a current limiter coupled to an array of resistive memory cells. In the example shown, in step 502, several memory cells are provided, arranged in rows and columns in an array. For example, RRAM memory cells 210 are provided in an array of resistive memory cells 200, as shown in Figure 5. Fig. 2 shown, provided. Furthermore, in step 502, several bit lines, source lines, and word lines are provided, and each column of the memory cells is connected between a corresponding bit line and source line, and each row of the memory cells is connected to a corresponding word line. In step 504, a multiplexer is provided which contains several column selector transistors, such as column selector transistors M4, which are connected to a corresponding source line and have gates configured to receive a column selector signal, for example, gates connected to the output voltage VY of the operational amplifier 402, which is routed through the column decoder 450, as shown in Fig. 2 shown.

[0032] In the example shown, in step 506 a bias signal is output to the gate terminal of a current limiter, such as the current-limiting transistor M2, which is coupled to each of the column selector transistors in the MUX. For example, a bias signal VG is output to the gate terminal of the lower transistor M2, which is connected to the upper transistor M4, for example, the column selector transistor M4. In step 508, a column address is received, for example, at column decoder 450. In step 510, a column selector signal, such as ysel[m], is output to one of the column selector transistors in the MUX in response to the column address received in step 508.

[0033] Accordingly, the various embodiments disclosed in the present text provide a current limiter with a lower additional operating voltage requirement, for example less than 500 mV, for the RRAM formation and SET operations, and reduce the additional voltage by more than 300 mV compared to conventional current limiters.

[0034] The various embodiments disclosed in this text also allow for a smaller additional area requirement for the current limiter and the bias generator. For example, the bias generator circuit can be global. For example, the same bias generator circuit can be used for all columns of the memory arrangement; and because the column selector transistor of the memory arrangement's multiplexer can be used as the upper transistor of the current limiter cascode, the additional area requirement for implementing the current limiter is a single transistor, for example, the lower transistor, thus reducing the additional area requirement compared to conventional current limiters.

[0035] Furthermore, the various embodiments disclosed in the present text enable adaptive adjustment of the bias voltage applied to the gate of the lower current limiting transistor in the cascode (cascode circuit), and can therefore compensate for process and temperature fluctuations in order to stabilize the additional operating voltage.

[0036] The disclosed embodiments thus include a storage device with a storage arrangement containing multiple memory cells arranged in rows and columns. A control loop bias generator is configured to output a column selection signal to the storage arrangement. A current limiter receives an output signal from the control loop bias generator, and the current limiter is coupled to multiple columns of the storage arrangement.

[0037] Further disclosed embodiments provide a storage device comprising a memory array containing multiple memory cells arranged in rows and columns, multiple bit lines, multiple source lines, and multiple word lines. Each column of memory cells is connected to a corresponding bit line and source line, and each row of memory cells is connected to a corresponding word line. A multiplexer (MUX) is connected to the multiple columns. The MUX contains multiple first transistors connected to corresponding source lines. The first transistors have respective gate terminals configured to receive a column selection signal. A current-limiting transistor is connected to each of the first transistors.

[0038] Further embodiments include a method in which several memory cells arranged in rows and columns, several bit lines, several source lines, and several word lines are provided. Each column of memory cells is connected to a corresponding bit line and source line, and each row of memory cells is connected to a corresponding word line. A multiplexer (MUX) is connected to the several columns and contains several first transistors connected to corresponding source lines. The transistors have respective gate terminals configured to receive a column selection signal. The method further includes outputting a predefined bias signal to the gate terminal of a current-limiting transistor coupled to each of the first transistors of the MUX. A column address is received, and a column selection signal is generated based on the column address.The column selection signal is output to one of the first transistors based on the received column address.

[0039] This disclosure outlines various embodiments to help the person skilled in the art better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure.

Claims

[1] Having a storage device: a memory arrangement (200) containing several memory cells (210) arranged in rows and columns; a control loop bias generator (400) configured to output a voltage signal to a column decoder (450) configured to output a column selection signal to the memory arrangement (200); a current limiter (300) configured to receive an output signal (VG) from the control loop bias generator (400), wherein the current limiter (300) is coupled to several columns of the memory arrangement (200), wherein the current limiter (300) comprises a cascode of a first NMOS transistor (M4) and a second coupled NMOS transistor (M2), wherein the bias generator (400) comprises a third cascode-connected NMOS transistor (M3) and a fourth cascode-connected NMOS transistor (M1) and an operational amplifier (402) configured to receive a feedback signal, where a source of the third NMOS transistor (M3) is connected to a gate of the second NMOS transistor (M2). [2] Storage device according to claim 1, further comprising a column multiplexer, column MUX, (202) connected to the columns of the storage arrangement (200), wherein the column MUX (202) comprises the first NMOS transistor (M4) configured to operate as a column select transistor. [3] Storage device according to claim 2, wherein the column MUX (202) contains several column selection transistors (304b), wherein each column is connected to a corresponding column selection transistor of the column selection transistors (304b), and wherein the second NMOS transistor (M2) is coupled to each of the column selection transistors (304b). [4] Storage device according to one of claims 1 to 3, wherein the operational amplifier is configured to output the voltage signal to the column decoder (450). [5] Storage device according to claim 4, wherein the bias generator (400) further comprises: a voltage input terminal connected to a source of the third NMOS transistor (M3) and a gate of the fourth NMOS transistor (M1); wherein a drain of the third NMOS transistor (M3) and a source of the fourth NMOS transistor (M1) are connected to an inverting input of the operational amplifier (402), wherein a non-inverting input of the operational amplifier (402) is configured to receive a previously set clamping voltage, and wherein an output of the operational amplifier (402) is connected to a gate of the third NMOS transistor (M3). [6] Storage device according to claim 4 or 5, wherein the output of the operational amplifier (402) is connected to a gate of the first NMOS transistor (M4). [7] Storage device according to any one of claims 1 to 6, wherein the second NMOS transistor (M2) and the fourth NMOS transistor (M1) are IO transistors. [8] Storage device according to one of the preceding claims, wherein the clamping voltage is less than 500 millivolts. [9] Storage device according to any of the preceding claims, wherein the multiple memory cells (210) are Resistive Random Access Memory, RRAM, cells. [10] comprising a storage device: a memory arrangement (200) comprising multiple memory cells (210) arranged in rows and columns, multiple bit lines, multiple source lines and multiple word lines, wherein each column of the memory cells (210) is connected to a corresponding bit line and source line, and wherein each row of the memory cells (210) is connected to a corresponding word line; a multiplexer, MUX, (202) which is connected to the multiple columns, wherein the MUX (202) contains several first transistors (M4, 304b) which are connected to corresponding source lines, wherein the first transistors (M4, 304b) each have a gate terminal which is configured to receive a column selection signal; a current limiting transistor (M2) connected to each of the first transistors (M4, 304b); a current limiter circuit (300) comprising a transistor cascode including the first transistors (M4, 304b) and the current limiter transistor (M2); and a bias generator (400) configured to output a predefined gate control voltage signal (VG) to a gate terminal of the current limiter transistor (M2) and a voltage signal to a column decoder (450) configured to output the column selection signal to a gate terminal of the first transistors (M4, 304b). [11] Storage device according to claim 10, wherein the bias generator (400) has an operational amplifier (402) configured to receive a previously determined clamping voltage. [12] Storage device according to claim 11, wherein the bias generator (400) further comprises: a power supply connection that is connected to the source of a third NMOS transistor (M3) and the gate of a fourth NMOS transistor (M1), wherein the drain of the third NMOS transistor (M3) and the source of the fourth NMOS transistor (M1) are connected to the inverting input of the operational amplifier (402), wherein the non-inverting input of the operational amplifier (402) is connected to a previously defined clamping voltage. [13] Storage device according to claim 12, wherein the output of the operational amplifier (402) is connected to the gates of the first transistors (M4, 304b), and wherein the source of the third NMOS transistor (M3) is connected to the gate of the current limiter transistor (M2). [14] Storage device according to claim 12 or 13, wherein the current limiting transistor (M2) and the fourth NMOS transistor (M1) are IO transistors. [15] Storage device according to any one of claims 11 to 14, wherein the clamping voltage is less than 500 millivolts. [16] Procedure encompassing: Providing multiple memory cells (210) arranged in rows and columns, multiple bit lines, multiple source lines and multiple word lines, wherein each column of the memory cells (210) is connected to a corresponding bit line and source line, and wherein each row of the memory cells (210) is connected to a corresponding word line; Providing a multiplexer, MUX, (202) which is connected to the multiple columns, wherein the multiplexer (202) has several first transistors (M4, 304b) which are connected to corresponding source lines, wherein the first transistors (M4, 304b) each have a gate terminal which is configured to receive a column selection signal; Output, from a bias generator circuit (400), a previously determined bias signal (VG) to a gate terminal of a current limiter transistor (M2) coupled to each of the first transistors (M4, 304b) of the MUX (202); Receiving a column address; Generating a column selection signal based on the column address; and Outputting the column selection signal to one of the first transistors (M4, 304b) based on the received column address, wherein a current limiter circuit (300) comprises a transistor cascode including the first transistors (M4, 304b) and the current limiter transistor (M2). [17] Method according to claim 16, further comprising providing the bias generator circuit (400) which is configured to output the previously determined bias signal (VG) and a voltage signal to a column decoder (450) which is configured to output the column selection signal, wherein the output of a previously determined bias signal (VG) to the gate terminal of the current limiter transistor (M2) comprises receiving a feedback signal from a mirror transistor. [18] Method according to claim 16 or 17, further comprising clamping the drain-source voltage of the current limiter transistor (M2) to a previously determined clamping voltage.

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