Display panel, driving method and display device

Abstract

Embodiments of the present application disclose a display panel, a driving method and a display device. The display panel comprises a pixel circuit and a light emitting element; the pixel circuit comprises a data writing module, a driving module and a compensation module; the compensation module is configured to be controlled by a first scanning signal; the data writing module is configured to be controlled by a second scanning signal; V11V11', or V11V12; wherein V11 is a high level voltage of the first scanning signal in a refresh frame, V11' is a high level voltage of the first scanning signal in a holding frame, and V12 is a high level voltage of the second scanning signal in the refresh frame. Embodiments of the present application can avoid the compensation module from generating a leakage current in the light emitting stage of the refresh frame, or prevent the compensation module from being unable to be turned off in the bias adjustment stage of the holding frame, thereby stabilizing the voltage at the gate of the driving transistor, preventing the light emitting element from generating a deviation between the light emitting brightness and the target brightness, and avoiding flickering and abnormal screen flashing of the display panel.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, in particular to a display panel, a driving method and a display device. BACKGROUND

[0002] With the continuous development of display technology, more and more electronic devices with display function are widely used in people's daily life and work, which brings great convenience to people's daily life and work.

[0003] Electronic products will adopt different refresh rates for display in different application scenarios, such as using a higher refresh rate driving mode to drive display of dynamic pictures (such as game scenes) to ensure the smoothness of the display picture; using a lower refresh rate driving mode to drive display of slow-motion images or static pictures to reduce power consumption.

[0004] However, the current display device will have flickering phenomenon when using different refresh modes, especially low frequency refresh, and even abnormal flashing screen, which will seriously affect the display effect. SUMMARY

[0005] The present application provides a display panel, a driving method and a display device to avoid flickering and even abnormal flashing screen of the display panel, and improve the display quality.

[0006] In a first aspect, embodiments of the present application provide a display panel, comprising a pixel circuit and a light emitting element;

[0007] The pixel circuit comprises a data writing module, a driving module and a compensation module;

[0008] The driving module comprises a driving transistor;

[0009] The data writing module is connected between a data signal input end and a first electrode of the driving transistor;

[0010] The compensation module is connected between a gate electrode and a second electrode of the driving transistor;

[0011] The picture display process of the display panel comprises a display frame, and the display frame comprises a refresh frame and a holding frame;

[0012] The compensation module is configured to be controlled by a first scan signal; the first scan signal satisfies: V11 < V11'; wherein V11 is a high voltage of the first scan signal in the refresh frame, and V11' is a high voltage of the first scan signal in the holding frame.

[0013] In a second aspect, embodiments of the present application further provide a display panel, comprising a pixel circuit and a light emitting element;

[0014] The pixel circuit comprises a data writing module, a driving module and a compensation module;

[0015] The driving module comprises a driving transistor;

[0016] The data writing module is connected between a data signal input end and a first electrode of the driving transistor;

[0017] The compensation module is connected between a gate electrode and a second electrode of the driving transistor;

[0018] The picture display process of the display panel comprises a display frame, and the display frame comprises a refresh frame;

[0019] The compensation module is configured to be controlled by a first scanning signal, and the data writing module is configured to be controlled by a second scanning signal;

[0020] The first scanning signal and the second scanning signal satisfy V11 < V12;

[0021] V11 is a high voltage of the first scanning signal in the refresh frame, and V12 is a high voltage of the second scanning signal in the refresh frame.

[0022] In a third aspect, an embodiment of the present application further provides a driving method of a display panel, the display panel comprising a pixel circuit and a light emitting element;

[0023] The pixel circuit comprises a data writing module, a driving module and a compensation module;

[0024] The driving module comprises a driving transistor;

[0025] The data writing module is connected between a data signal input end and a first electrode of the driving transistor;

[0026] The compensation module is connected between a gate electrode and a second electrode of the driving transistor;

[0027] The picture display process of the display panel comprises a plurality of display frames, and the plurality of display frames comprise a refresh frame and a holding frame;

[0028] The driving method of the display panel comprises:

[0029] The compensation module is controlled by a first scanning signal, and the first scanning signal satisfies V11 < V11'; V11 is a high voltage of the first scanning signal in the refresh frame, and V11' is a high voltage of the first scanning signal in the holding frame.

[0030] In a fourth aspect, the embodiments of the present application further provide a display device comprising any one of the display panels provided by the embodiments of the present application.

[0031] In the technical solution of the embodiments of the present application, the compensation module is configured to be controlled by the first scan signal, and the data writing module is configured to be controlled by the second scan signal, and the first scan signal and the second scan signal satisfy: V11 BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a structural schematic diagram of a display panel provided by the embodiments of the present application;

[0033] Figure 2 is Figure 1 is a circuit structure diagram of a pixel circuit and a light emitting element in the display panel shown in FIG. 1;

[0034] Figure 3 is a pixel circuit driving timing diagram in the related art;

[0035] Figure 4 is a pixel circuit driving timing diagram provided by the embodiments of the present application;

[0036] Figure 5 is a display panel display brightness comparison diagram under two kinds of first scan signals provided by the embodiments of the present application;

[0037] Figure 6 is a first scan signal high voltage and display panel flicker condition curve diagram in a refresh frame provided by the embodiments of the present application;

[0038] Figure 7 is a first scan signal high voltage and display panel flicker condition curve diagram in a refresh frame provided by the embodiments of the present application;

[0039] Figure 8 is a flowchart of a display panel driving method provided by the embodiments of the present application;

[0040] Figure 9 is another pixel circuit driving timing diagram provided by an embodiment of the present application;

[0041] Figure 10 is another pixel circuit driving timing diagram provided by an embodiment of the present application;

[0042] Figure 11 is another structure schematic diagram of a display panel provided by an embodiment of the present application;

[0043] Figure 12 is Figure 11 is a part signal timing diagram of different partitions in the display panel shown in FIG. 8;

[0044] Figure 13 is another structure schematic diagram of a display panel provided by an embodiment of the present application;

[0045] Figure 14 is another structure schematic diagram of a display panel provided by an embodiment of the present application;

[0046] Figure 15 is another structure schematic diagram of a display panel provided by an embodiment of the present application;

[0047] Figure 16 is another pixel circuit driving timing diagram provided by an embodiment of the present application;

[0048] Figure 17 is a structure schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0049] The present application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0050] The terms used in the embodiments of the present application are merely used for the purpose of describing particular embodiments and are not intended to limit the present application. It should be noted that the positional words such as "upper", "lower", "left", "right", etc. described in the embodiments of the present application are described in the angle shown in the drawings, and should not be understood as the limitation of the embodiments of the present application. In addition, it should be understood in the context that when referring to one element being formed "on" or "under" another element, it can be directly formed "on" or "under" another element, or indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only for the purpose of description and do not represent any order, quantity or importance, but are only used to distinguish different components. The specific meanings of the above terms in the present application can be understood by the person skilled in the art according to the specific circumstances.

[0051] The term "comprising" and its variants used in the present application are open and include "but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment".

[0052] It should be noted that the concepts of "first", "second", etc. mentioned in the present application are only used to distinguish the corresponding content, and are not used to limit the order or mutual dependency.

[0053] It should be noted that the modification of "one" or "multiple" in the present application is illustrative and not limiting, and those skilled in the art should understand that unless the context clearly indicates otherwise, it should be understood as "one or more".

[0054] Figure 1 is a structural schematic diagram of a display panel provided by the embodiments of the present application, Figure 2 is Figure 1 the circuit structure diagram of the pixel circuit and the light emitting element in the display panel shown in FIG. 1, reference Figure 1 and Figure 2 The display panel includes a pixel circuit 10 and a light emitting element 20; the pixel circuit 10 includes a data writing module 11, a driving module 12 and a compensation module 13; the driving module 12 includes a driving transistor M2; the data writing module 11 is connected between a data signal input end Vdata and the first electrode of the driving transistor M2; the compensation module 13 is connected between the gate and the second electrode of the driving transistor M2.

[0055] In addition, the pixel circuit further comprises a gate reset module 14, an anode reset module 15, a light emitting control module 16 and a storage capacitor Cst; the gate reset module 14 is connected to a gate reset signal end Vref1 and a gate of the driving transistor M2. The anode reset module 15 is connected between an anode reset signal end Vref2 and an anode of the light emitting element 20. The light emitting control module 16 comprises a first light emitting control unit 161 and a second light emitting control unit 162; the first light emitting control unit 161, the driving module 12, the second light emitting control unit 162 and the light emitting element 20 are sequentially connected between a first power supply signal end PVDD and a second power supply signal end PVEE.

[0056] Figure 3 is a pixel circuit driving timing diagram in the related art, and the following refers to Figures 1-3 , first, the driving process and driving principle of the display panel are simply introduced. Specifically, the driving process of the pixel circuit 10 can comprise a plurality of display frames T, which can be divided into a high brush mode and a low brush mode according to a refresh frequency. In the high brush mode, the plurality of display frames T are all refresh frames Trefresh; in the low brush mode, the plurality of display frames T can comprise refresh frames Trefresh and holding frames Thold. The refresh frame Trefresh can comprise a gate reset stage ta, a data writing stage tb and a light emitting stage tc, and the holding frame Thold can comprise the light emitting stage tc.

[0057] In the gate reset stage ta, the gate reset control signal S1N received by the gate reset module 14 is low at this time, which is an enable signal, the gate reset module 14 is turned on, and the gate reset signal Vref1 is input to the gate of the driving transistor M2 to reset the gate of the driving transistor M2.

[0058] In the data writing stage tb, the data writing control signal SP received by the data writing module 11 is low at this time, which is an enable signal, the data writing module 11 is turned on; at the same time, the threshold compensation control signal S2N received by the compensation module 13 is low at this time, which is an enable signal, the compensation module 13 is turned on. The data signal Vdata is input to the gate of the driving transistor M2 through the data writing module 11, the driving module 12 and the compensation module 13, and is stored by the storage capacitor Cst.

[0059] In the light emitting stage tc, the light emitting control signal Emit received by the first light emitting control unit 161 and the second light emitting control unit 162 is low, which is an enable signal. The first light emitting control unit 161 and the second light emitting control unit 162 are turned on, the first power signal terminal PVDD and the second power signal terminal PVEE are turned on, and the conduction current is controlled by the driving transistor M2. The conduction current of the driving transistor M2 is related to the gate-source voltage difference. Specifically, the driving transistor M2 forms a certain gate-source voltage difference according to the data signal Vdata stored in the gate and the first power signal terminal PVDD, thereby controlling the conduction current of the driving transistor M2, that is, the corresponding driving current can be provided to the light emitting element 20, so that the light emitting element 20 emits light at a target brightness.

[0060] However, in the light emitting stage tc, the transistor in the compensation module 13 is controlled to be normally turned off by the threshold compensation control signal S2N, but because it is generally a P-type double-gate transistor, that is, it includes the first transistor M31 and the second transistor M32, the node connected between the two transistors is capacitively coupled with the gate, and the threshold compensation control signal S2N received by the gate is a high-level signal at this time, which raises the voltage of the middle node, reduces the gate-source voltage difference of the first transistor M31, and causes the first transistor M31 to generate a leakage current. The potential of the gate of the driving transistor M2, that is, the first node N1, continuously increases within a frame of light emitting time, causing the light emitting brightness of the light emitting element 20 to gradually decrease in the light emitting stage tc. When the display panel is driven at a low frequency and the frame of light emitting time is long, the brightness decreases significantly, and there is a significant bright-dark change between different display frames. The human eye perceives the bright-dark change as flickering.

[0061] In addition, considering that the driving transistor M2 is in a forward bias state in the light emitting stage tc of each display frame, that is, the voltage of the second node N2 is greater than the voltage of the third node N3, long-time forward bias can cause the electrical characteristic curve of the driving transistor M2 to drift, affecting the accuracy of the light emitting brightness. Continuing to refer to Figure 3, the related art will make bias adjustment for the driving transistor M2, will set a bias adjustment stage td in the holding frame Thold, write the bias adjustment signal VGMP to the driving transistor M2 through the data writing transistor M1, so that the voltage of the third node N3 of the driving transistor M2 is greater than or equal to the second node N2, in a reverse bias state, so as to compensate for the forward bias state of the driving transistor M2 in the light emitting stage tc, stabilize the electrical characteristics of the driving transistor M2, and ensure the accuracy of the light emitting brightness. However, since the high-level bias adjustment signal VGMP is written to the third node N3 in the bias adjustment stage td, for the compensation module 13 which should be turned off, the gate-source voltage difference of the transistor, especially the second transistor M32, is reduced, which will cause it cannot be completely turned off, and also affect the gate voltage of the driving transistor M2, so that the brightness of the light emitting element in the display frame is abnormal, and the phenomenon of abnormal flashing screen appears.

[0062] Figure 4 is a pixel circuit driving timing diagram provided by an embodiment of the present application, referring to Figure 1 、 Figure 2 and Figure 4 , for the above technical problems, in the embodiment of the present application, the compensation module 13 is configured to be controlled by the first scan signal S2N; the first scan signal S2N satisfies: V11

[0063] Specifically, the compensation module 13 includes a first transistor M31 and a second transistor M32, which are connected in series between the gate and the second electrode of the driving transistor M2 in sequence. The first transistor M31 and the second transistor M32 can be both P-type channel transistors, and their gates receive a first scanning signal S2N. As described above, when the first scanning signal S2N is in a low voltage state, the first transistor M31 and the second transistor M32 are turned on, and the pixel circuit 10 enters the data writing stage tb. When the first scanning signal S2N is in a high voltage state, the first transistor M31 and the second transistor M32 are turned off, and the pixel circuit 10 can be in the gate reset stage ta, the light emitting stage tc, and the bias adjustment stage td and the light emitting stage tc of the holding frame Thold. In the embodiment of the present application, the high voltage of the first scanning signal S2N is set differently in the refresh frame Trefresh and the holding frame Thold, that is, the high voltage of the first scanning signal S2N in the refresh frame Trefresh (for example, 7.8V) is lower than the high voltage of the first scanning signal S2N in the holding frame Thold (for example, 8V). On the one hand, the first scanning signal S2N can control the first transistor M31 and the second transistor M32 to be turned off in the light emitting stage tc of the refresh frame Trefresh at a relatively low high voltage, thereby reducing the coupling effect of the intermediate nodes of the two transistors on the gate, avoiding the voltage of the intermediate nodes from being lifted due to the capacitive coupling to generate a leakage current, and preventing the voltage of the gate of the driving transistor M2, i.e., the first node N1, from affecting the luminance of the light emitting element 20 due to the leakage current of the first transistor M31. On the other hand, the first scanning signal S2N can control the first transistor M31 and the second transistor M32 to be turned off in the bias adjustment stage td of the holding frame Thold at a relatively high high voltage, thereby avoiding the situation that the first transistor M31 and the second transistor M32 cannot be turned off due to the third node N3 writing a high voltage bias adjustment signal VGMP, and preventing the phenomenon of abnormal screen flashing.In other words, if the first scanning signal S2N adopts the same high voltage level in the refresh frame Trefresh and the holding frame Thold, for example, both adopt a high voltage level of 7.8V, and if the bias adjustment signal VGMP written by the data writing module 11 in the holding frame Thold is lower than the high voltage level of the first scanning signal S2N, for example, the bias adjustment signal VGMP is 7V, at this time, the third node N3 written with the bias adjustment signal VGMP is essentially lifted, that is, the voltage rise of the source of the transistor in the compensation module 13 is compensated, and the gate voltage of 7.8V and the source voltage of 7V cannot generate a sufficient gate-source voltage difference, which will cause the transistor of the compensation module 13 to fail to turn off in the holding frame Thold, which will cause the voltage of the gate of the driving transistor M2 to change more obviously, the luminance of the light emitting element 20 will be more obviously different from the target luminance, and the phenomenon of abnormal flashing screen will occur.

[0064] In order to intuitively reflect the display effect and the internal principle of the display panel in the embodiment of the present application, the corresponding experimental verification is also carried out.

[0065] Firstly, Figure 5 is a display panel display luminance comparison chart provided by the two kinds of first scanning signals in the embodiment of the present application, as Figure 5 indicated, the frame luminance of the display panel changes with time when the compensation module in the display panel pixel circuit is turned off by the two kinds of first scanning signals with a high voltage level of 6V and 8V respectively, and the fundamental frequency of the display panel is 120HZ, and the example in the figure is a 30HZ low frequency driving state, that is, three holding frames Thold are set after each refresh frame Trefresh in the example in the figure, so that the degree of change of the frame luminance is more obviously reflected. Referring to Figure 2 and Figure 5 It can be seen that in each display frame, the frame luminance will decrease to different degrees due to the leakage problem of the compensation module 13. Specifically, when the first scanning signal S2N with a high voltage level of 8V is used to drive the pixel circuit 10 and turn off the compensation module 13, the frame luminance of the display panel will decrease more obviously, and the decrease amplitude will be larger, and the display panel will present obvious bright and dark changes, that is, obvious flicker will occur. However, when the first scanning signal S2N with a high voltage level of 6V is used to drive the pixel circuit 10 and turn off the compensation module 13, the decrease amplitude of the frame luminance of the display panel will be slowed down to a certain extent, that is, the degree of luminance decrease will no longer be obvious, and the flicker phenomenon of the display panel is improved to a certain extent. The experimental verification results also prove that by appropriately reducing the high voltage level of the first scanning signal S2N in the refresh frame Trefresh, the leakage problem of the compensation module 13 can be reduced, thereby reducing the influence of the leakage on the gate voltage of the driving transistor M2, reducing the luminance change of the light emitting element in each display frame, and improving the flicker phenomenon of the display panel.

[0066] Figure 6 This is a graph showing the high-level voltage of the first scan signal in the refresh frame and the flickering of the display panel, provided in an embodiment of the present invention. Figure 6 As shown, firstly, the vertical axis, the flicker value, represents the brightness ratio during changes in brightness, and the horizontal axis represents the different high-level voltage values ​​of the first scan signal S2N. Figure 6 It can be seen that, within an appropriate range, or in other words, within a range where the pixel circuit compensation module can be turned off, the higher the high-level voltage of the first scan signal S2N in the refresh frame Trefresh, the larger its flicker value, indicating that the brightness change is more obvious and the flicker phenomenon is more easily perceived by the human eye; conversely, the lower the high-level voltage of the first scan signal S2N in the refresh frame Trefresh, the smaller its flicker value, indicating that the brightness change is less obvious and the flicker phenomenon is less easily perceived by the human eye. Therefore, in this embodiment of the invention, by appropriately reducing the high-level voltage of the first scan signal S2N in the refresh frame Trefresh, the leakage current of the transistor in the compensation module 13 can be reduced, avoiding affecting the voltage of the gate of the driving transistor M2. This prevents a significant difference between the emitted brightness and the target brightness, thus improving the flicker phenomenon of the display panel.

[0067] Figure 7 This is a curve showing the flickering of the display panel in the holding frame provided by an embodiment of the present invention, based on the high-level voltage of the first scan signal. It should be noted that, under this holding frame (Thold), in the pixel circuit of the display panel, the bias adjustment signal VGMP is written to the driving transistor M2 by the data writing module 11 for bias adjustment. For example... Figure 7 As can be seen, contrary to the pattern of the refresh frame Trefresh, within an appropriate range, the lower the high-level voltage of the first scan signal S2N in the hold frame Thold, the larger its flicker value, indicating that the brightness change is more obvious and the flicker phenomenon is more easily perceived by the human eye; conversely, the higher the high-level voltage of the first scan signal S2N in the hold frame Thold, the smaller its flicker value, indicating that the brightness change is less obvious and the flicker phenomenon is less easily perceived by the human eye. Therefore, in this embodiment of the invention, by appropriately raising the high-level voltage of the first scan signal S2N in the hold frame Thold, a sufficient gate-source voltage difference can be generated between the gate and source of the transistor in the compensation module to ensure effective turn-off, thereby avoiding abnormal screen flickering caused by the compensation module's inability to turn off.

[0068] This invention also provides a method for driving a display panel. Figure 8 This is a flowchart of a display panel driving method provided in an embodiment of the present invention, see reference. Figure 4 and Figure 8Based on the display panel, the driving method of the present application can include:

[0069] S110, the compensation module is controlled by using the first scanning signal; wherein the first scanning signal satisfies: V11

[0070] The driving method is essentially using the first scanning signal S2N which has a high voltage change in the refresh frame Trefresh and the holding frame Thold to control the compensation module 13, and specifically to control the off state of the compensation module 13. As described above, the high voltage of the first scanning signal S2N in the refresh frame Trefresh is lower than that in the holding frame Thold, which not only can avoid the voltage of the middle node of the double-gate transistor in the compensation module 13 from being raised by the capacitive coupling to cause the leakage current in the light-emitting stage tc of the refresh frame Trefresh, preventing the gate voltage of the driving transistor M2 from affecting the luminance of the light-emitting element 20 due to the leakage current of the first transistor M31, but also can avoid the situation that the first transistor M31 and the second transistor M32 cannot be turned off due to the high voltage bias adjustment signal VGMP written to the third node N3 in the bias adjustment stage td of the holding frame Thold, preventing the abnormal screen flashing phenomenon.

[0071] Continuing to refer to Figure 1 For the compensation module in the pixel circuit, the display panel in the embodiment of the present application can be provided with a first shift register circuit 31 and a first high voltage signal line 41, the first shift register circuit 31 is electrically connected with the first high voltage signal line 41; the first high voltage signal line 41 is configured to provide the first high voltage signal VGH1 to the first shift register circuit 31; the voltage of the first high voltage signal VGH1 in the refresh frame Trefresh is less than that in the holding frame Thold. Wherein, the first shift register circuit 31 is electrically connected with the compensation module 13 to provide the first scanning signal S2N to the compensation module 13.

[0072] Specifically, the skilled in the art can know that the scan signal received by the pixel circuit of the display panel is essentially provided by the shift register circuit, and each level of the shift register unit provides the scan signal to each row of pixel circuits to realize the row-by-row scanning process and complete the display of one display frame. Based on this, in the embodiment of the present application, the first scan signal S2N provided to the compensation module 13 needs to switch the high voltage level in the refresh frame Trefresh and the holding frame Thold. The driving chip can provide a variable high voltage signal to the shift register circuit, that is, the first high voltage signal line 41 provides a variable high voltage signal to the first shift register circuit 31, that is, the first high voltage signal VGH1 provided by the first high voltage signal line 41 has a voltage smaller than that in the holding frame Thold. In other words, when the driving chip provides the first high voltage signal VGH1 to the first shift register circuit 31 through the first high voltage signal line 41, it can be designed to output different high voltage signals in the refresh frame Trefresh and the holding frame Thold, so that the first shift register circuit 31 generates a change in the high voltage signal when generating the first scan signal S2N in the refresh frame Trefresh and the holding frame Thold.

[0073] Figure 9 is another pixel circuit driving timing diagram provided by the embodiment of the present application, referring to Figure 4 and Figure 9 Further, in the embodiment of the present application, the data writing module 11 can also be configured to be controlled by the second scan signal SP, and the first scan signal S2N and the second scan signal SP satisfy: V11 = V12 (as shown in Figure 4 ), or V11 < V12 (as shown in Figure 9 ). Wherein, V12 is the high voltage level of the second scan signal SP in the refresh frame Trefresh.

[0074] Wherein, the data writing module 11 includes a third transistor M1, two poles of the third transistor M1 are connected between the data signal input end Vdata and the first pole of the driving transistor M2, and the gate of the third transistor M1 receives the second scan signal SP; the third transistor M1 can also be set as a P-type channel transistor.

[0075] In Figure 4In the shown embodiment, the high voltage V11 of the refresh frame Trefresh of the first scanning signal S2N and the high voltage V12 of the refresh frame Trefresh of the second scanning signal SP are equal, both are exemplified as 7.8V, that is, the compensation module 13 and the data writing module 11 are controlled to be turned off by the same high voltage in the refresh frame Trefresh, without differentiation, and the problem that the compensation module 13 can not be turned off in the holding frame Thold is given priority to be considered, the high voltage V11' of the first scanning signal S2N in the holding frame Thold is set to be higher, exemplified as 8V, so that the transistor in the compensation module 13, especially the second transistor M32, can still have sufficient gate-source voltage difference on the basis of the source writing high voltage signal VGMP in the bias adjustment stage td, and the P-type second transistor M32 can be effectively turned off, so as to avoid the problem of abnormal screen flashing in the holding frame Thold.

[0076] In Figure 9 In the shown embodiment, the high voltage V11 of the refresh frame Trefresh of the first scanning signal S2N (exemplified as 6V) is less than the high voltage V12 of the refresh frame Trefresh of the second scanning signal SP (exemplified as 7.8V), that is, the problem of easy leakage current of the compensation module 13 in the refresh frame Trefresh can be given priority to be considered, the high voltage V11 of the first scanning signal S2N in the refresh frame Trefresh is set to be lower than the high voltage of the second scanning signal SP in the refresh frame Trefresh, that is, on the basis of turning off the compensation module 13 by the relatively lower high voltage, the problem that the transistor in the compensation module 13 causes the potential of the middle node of the double-gate transistor to be raised due to capacitive coupling, resulting in leakage current, is avoided.

[0077] Based on the data writing module being configured to be controlled by the second scanning signal SP to write the data signal or the bias signal, continuing to refer to Figure 8 In the driving method of the embodiment of the present application, the following steps can be further added:

[0078] S120, controlling the data writing module by the second scanning signal; wherein the first scanning signal and the second scanning signal satisfy: V11=V12, or V11

[0079] Figure 10 It is another pixel circuit driving timing diagram provided by the embodiment of the present application, referring to Figure 10 Further, the first scanning signal S2N and the second scanning signal SP satisfy: V11'>V12.

[0080] V11 is exemplarily 6V, V11' is exemplarily 8V, and V12 is exemplarily 7.8V. This embodiment not only considers the problem that the compensation module 13 can not be turned off in the holding frame Thold, but also considers the problem that the compensation module 13 is prone to leakage current in the refresh frame Trefresh. The high voltage V11' of the first scanning signal S2N in the holding frame Thold is set to be higher, and the high voltage V11 of the first scanning signal S2N in the refresh frame Trefresh is set to be lower than the high voltage of the second scanning signal SP in the refresh frame Trefresh, so as to avoid the leakage current of the transistor in the compensation module 13.

[0081] Therefore, in this embodiment, the leakage current of the compensation module 13 can be controlled in the refresh frame Trefresh, and the abnormal opening of the compensation module 13 can be effectively avoided in the holding frame Thold. Thus, the gate potential of the driving transistor M2 in each display frame can be stably driven, the change of the gate potential of the driving transistor M2 can be avoided, the deviation between the luminous brightness of the light emitting element 20 and the target luminous brightness can be avoided, the flicker or abnormal screen flashing can be avoided, and the accuracy and uniformity of the display can be ensured.

[0082] With reference to Figure 4 , Figure 9 and Figure 10 , in the embodiment of the present application, the refresh frame Trefresh can include a data writing stage ta, and the holding frame Thold can include a bias adjustment stage td. The data writing module 11 is configured to be controlled by the second scanning signal SP to provide a data signal Vdata for the driving transistor M2 in the data writing stage ta and to provide a bias adjustment signal VGMP for the driving transistor M2 in the bias adjustment stage td, wherein VGMP≥Vdata.

[0083] As described above, the data writing module 11 is reused as a bias adjustment module in the holding frame Thold. The bias adjustment signal VGMP is written to the data signal input end Vdata in the holding frame Thold, which is used to make the driving transistor M2 in the reverse bias state to compensate for the long time in the forward bias state. In the embodiment of the present application, the bias adjustment signal VGMP is set to be not lower than the data signal Vdata normally written in the refresh frame Trefresh, a high voltage signal can be written to the third node N3 to make the voltage of the third node N3 greater than the voltage of the second node N2, and the bias adjustment signal VGMP can be used to adjust the reverse bias degree of the driving transistor M2, so as to effectively adjust the bias state of the driving transistor M2.

[0084] With reference to Figure 4 and Figure 10Further, the data writing module 11 is configured to write a driving signal to the first electrode of the driving transistor M2, and the maximum value of the driving signal is VGMP; wherein V12>VGMP+1V.

[0085] It can be understood that the third transistor M1 in the data writing module 11 is a P-type transistor, and the second scanning signal SP at the high level voltage in the refresh frame Trefresh is responsible for controlling the data writing module 11 to be turned off. Considering that the data writing module 11 needs to be multiplexed as a bias adjustment module in the holding frame Thold, a high-level bias adjustment signal VGMP is provided to the driving transistor M2, that is, the driving signal written to the data signal input end Vdata of the data writing module 11 is not used for data writing all the time, and it is transformed into the bias adjustment signal VGMP with a larger voltage in the bias adjustment stage td. Based on this, when the data writing module 11 is controlled to be turned off, the high-level voltage written to the gate needs to consider the signal written to the source. Specifically, V12>VGMP+1V is set, that is, the difference between the high-level voltage for controlling the data writing module 11 to be turned off and the highest voltage signal VGMP written to the data signal input end is more than 1V, so as to ensure that the P-type third transistor M1 has a large enough gate-source voltage difference to be turned off. On this basis, the high-level voltage V11’ of the first scanning signal S2N in the holding frame Thold is set to be greater than V12, so as to ensure that the gate of the transistor in the compensation module 13, especially the second transistor M32, has a large enough high-level voltage. Even if the bias adjustment signal VGMP is written to the third node N3 in order to reversely bias the driving transistor M2, the gate-source voltage difference of the second transistor M32 is more than 1V, which is greater than the threshold voltage, so as to ensure that the P-type second transistor M32 is effectively turned off.

[0086] With reference to Figure 4 , Figure 9 and Figure 10 , optionally, the second scanning signal SP also satisfies: V12=V12’; wherein V12’ is the high-level voltage of the second scanning signal SP in the holding frame Thold. At this time, it means that the high-level voltages of the second scanning signal SP in the refresh frame and the holding frame do not need to be set differently. For the third transistor M1 in the data writing module 11, the same high-level voltage in the refresh frame Trefresh and the holding frame Thold can be used to effectively turn off.

[0087] For the voltages of the scanning signals of the conduction compensation module and the data writing module, in the embodiment of the application, the first scanning signal S2N and the second scanning signal SP also satisfy: V22≤V21; wherein V21 is the low-level voltage of the first scanning signal S2N, and V22 is the low-level voltage of the second scanning signal SP.

[0088] The low voltage of the first scanning signal S2N is not higher than the low voltage of the second scanning signal SP, which can ensure that the transistors in the compensation module 13 can have equal or relatively lower gate-source voltage difference, so as to control the first transistor M31 and the second transistor M32 of the P type to be completely turned on, and the data signal is effectively written to the gate of the driving transistor M2.

[0089] Similarly, for the data writing module, the display panel in the embodiment of the application can further be provided with a second shift register circuit 32 and a second high voltage signal line 42, the second shift register circuit 32 is electrically connected with the second high voltage signal line 42; the second high voltage signal line 42 is configured to provide the second shift register circuit 32 with a second high voltage signal VGH2; the voltage of the first high voltage signal VGH1 and the voltage of the second high voltage signal VGH2 are different at least in part of time. The second shift register circuit 32 is electrically connected with the data writing module 11 to provide the data writing module 11 with a second scanning signal SP.

[0090] Specifically, the voltage of the first high voltage signal VGH1 and the voltage of the second high voltage signal VGH2 are different at least in part of time, which means that the voltages are different in the refresh frame Trefresh and / or the holding frame Thold. Specifically, in the embodiment of the application, the second scanning signal SP provided to the data writing module 11 can be set differently from the first scanning signal S2N provided to the compensation module 13, such as the embodiments shown in Figure 4 、 Figure 9 and Figure 10 In the embodiments, the high voltage of the first scanning signal S2N in the holding frame Thold is set to be higher than that of the second scanning signal SP, and / or the high voltage of the first scanning signal S2N in the refresh frame Trefresh is set to be lower than that of the second scanning signal SP, thereby forming a difference with the second scanning signal SP. In the implementation of the differential design, the driving chip can provide the second shift register circuit 32 with the second high voltage signal VGH2 through the second high voltage signal line 42, and the second shift register circuit 32 is designed to output the same high voltage signal in the refresh frame Trefresh and the holding frame Thold, and the high voltage signal is different from the first high voltage signal VGH1 in the refresh frame Trefresh and / or the holding frame Thold, thereby making the second shift register circuit 32 generate the second scanning signal SP in the refresh frame Trefresh and the holding frame Thold.

[0091] It should be noted that the second high-level voltage signal line 42 and the first high-level voltage signal line 41 are responsible for providing different high-level voltage signals to different shift register circuits 32, and these different high-level voltage signals can be provided by the driver chip. Therefore, the second high-level voltage signal line 42 and the first high-level voltage signal line 41 can be connected to different high-level voltage signal output pins of the driver chip to obtain different high-level voltage signals.

[0092] In addition, such as Figure 1 As shown, the first shift register circuit 31 and the second shift register circuit 32 are respectively disposed on opposite sides of the display area AA of the display panel. The fact that the first shift register circuit 31 or the second shift register circuit 32 is disposed only on the same side of the display area AA is merely an example of the present invention. Those skilled in the art can, according to actual needs, simultaneously provide the first shift register circuit 31 on both sides of the display area AA, or simultaneously provide the second shift register circuit 32 on both sides of the display area AA, or simultaneously provide the first shift register circuit 31 and the second shift register circuit 32 on the same side of the display area AA. No limitation is imposed here.

[0093] Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 12 yes Figure 11 The timing diagrams of partial signals in different zones of the display panel shown are for reference. Figure 11 and Figure 12 In an optional embodiment, the display panel may include a first partition AA1 and a second partition AA2; during the same display time, the proportion of refresh frames Trefresh during the operation of the pixel circuit of the first partition AA1 is higher than the proportion of refresh frames Trefresh during the operation of the pixel circuit of the second partition AA2; the first scan signal S2N corresponding to the compensation module 13 of the pixel circuit 10 of the first partition AA1 and the second partition AA2 satisfies: V11_1 > V11_2; where V11_1 is the high-level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the first partition AA1 in the refresh frame Trefresh, and V11_2 is the high-level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the second partition AA2 in the refresh frame Trefresh.

[0094] As described above, the display panel can set high refresh mode and low refresh mode according to refresh frequency, and based on the same principle, different refresh frequencies can be further controlled in different areas of the display panel, that is, the function of partitioning and frequency dividing is realized. In the embodiment of the present application, the display panel is divided into a first partition AA1 and a second partition AA2, and the proportion of refresh frame Trefresh in the same time is different, that is, the two partitions adopt different refresh frequencies. The proportion of refresh frame Trefresh of the first partition AA1 is higher, that is, the first partition AA1 is a high refresh area, and the second partition AA2 is a low refresh area. For the low frequency area with lower refresh frequency and longer time in the state of maintaining the brightness of refresh frame Trefresh, when the compensation module 13 causes slight changes in brightness due to leakage, it will also be accumulated because of the longer maintenance time, and the human eye is more likely to perceive it. Based on this, in the present embodiment, the high voltage V11_2 of the first scan signal S2N of the second partition AA2 in the refresh frame Trefresh is relatively lower than the high voltage V11_1 of the first scan signal S2N of the first partition AA1 in the refresh frame Trefresh, that is, the transistor gate in the compensation module 13 receives a relatively lower high voltage for shutdown control, thereby the compensation module 13 of the low frequency area can be relatively more effectively reduced to avoid the human eye from perceiving the brightness change caused by the leakage problem.

[0095] For the driving of other modules in the pixel circuit, the present embodiment also provides specific implementation manners, which will be further described below with reference to Figure 2 、 Figure 4 、 Figure 9 and Figure 10 .

[0096] Optionally, the gate reset module 14 is configured to be controlled by a third scan signal S1N; the first scan signal S2N and the third scan signal S1N satisfy: V11=V13, and / or V21=V23; wherein V11 is the high voltage of the first scan signal S2N in the refresh frame Trefresh, V13 is the high voltage of the third scan signal S1N in the refresh frame Trefresh, V21 is the low voltage of the first scan signal S2N in the refresh frame Trefresh, and V23 is the low voltage of the third scan signal S1N in the refresh frame Trefresh.

[0097] Specifically, the gate reset module 14 can include a fourth transistor M41 and a fifth transistor M42; the fourth transistor M41 and the fifth transistor M42 are connected in series between the gate of the driving transistor M2 and the gate reset signal input end Vref1, and the gates of the fourth transistor M41 and the fifth transistor M42 receive the third scan signal S1N; the fourth transistor M41 and the fifth transistor M42 are P-type channel transistors.

[0098] The embodiment indicates that the first scanning signal S2N driving the compensation module 13 and the third scanning signal S1N driving the gate reset module 14 have the same high voltage state in the refresh frame Trefresh, i.e., have the same high voltage and are lower than the high voltage in the holding frame Thold, so as to avoid the leakage current of the gate reset module 14 in the refresh frame Trefresh due to the capacitive coupling, and avoid the problem of abnormal light emission of the light emitting element 20 caused by the leakage current of the gate reset module 14.

[0099] Further, the first scanning signal and the third scanning signal also satisfy: V11’=V13’; wherein V13’ is the high voltage of the third scanning signal in the holding frame.

[0100] Similarly, the embodiment indicates that the first scanning signal S2N driving the compensation module 11 and the third scanning signal S1N driving the gate reset module 14 have the same high voltage state in the holding frame Thold, i.e., have the same high voltage and are higher than the high voltage in the refresh frame Trefresh, so as to ensure the effective turn-off of the gate reset module 14 in the holding frame Thold.

[0101] In addition, it needs to be supplemented that, in order to avoid the influence of the leakage current of the gate reset module 14 on the luminance, the gate reset module can also be designed as a single transistor, i.e., not designed as a double-gate transistor, so that in the holding frame Thold, even if the third scanning signal S1N has a relatively high high voltage, the high voltage of the middle node will not be lifted due to the capacitive coupling between the gate and the middle node of the double-gate transistor, and the leakage current problem of the gate reset module 14 in the holding frame Thold can be prevented.

[0102] Figure 13 is another structure schematic diagram of a display panel provided by the embodiment of the present application, referring to Figure 13 For the above-mentioned gate reset module, since the first scanning signal S2N driving the compensation module 13 and the third scanning signal S1N driving the gate reset module 14 can have the same high voltage state in the refresh frame Trefresh and the holding frame Thold, the first shift register circuit 31 in the display panel can also be electrically connected with the gate reset module 14 to provide the third scanning signal S1N to the gate reset module 14.

[0103] In this embodiment, the first scan signal S2N driving the compensation module 13 and the third scan signal S1N driving the gate reset module 14 are set to have the same high voltage state in the refresh frame Trefresh and the holding frame Thold, and the same shift register circuit, i.e., the first shift register circuit 31, can be used to provide the first scan signal S2N and the third scan signal S1N. It can be understood that, since each shift register unit can output a plurality of first scan signals S2N with a fixed delay, the first scan signal S2N of other rows can be multiplexed as the third scan signal S1N of the current row for controlling the gate reset module 14 of the current row, so that a separate shift register circuit for the gate reset module 14 is not needed, the number of shift register circuits is greatly reduced, the area of the non-display area where the shift register circuits are located is reduced, and the narrow frame design is facilitated.

[0104] Optionally, the anode reset module 15 is configured to be controlled by the second scan signal SP.

[0105] Specifically, the anode reset module 15 can include a sixth transistor M5, two poles of the sixth transistor M5 are connected between the anode reset signal end Vref2 and the anode of the light emitting element 20, and the gate of the sixth transistor M5 receives the second scan signal SP; the sixth transistor M5 is a P-type channel transistor.

[0106] It can be understood that the anode reset module 15 has the function of resetting the anode of the light emitting element 20, and before the light emitting stage tc of each display frame, by resetting the anode of the light emitting element 20, i.e., writing a fixed anode reset signal to the anode of the light emitting element 20, the voltage state of the anode of the light emitting element 20 in the previous display frame can be avoided, and the light emitting brightness of the light emitting element 20 in the current display frame can be prevented from being affected by the previous display frame.

[0107] In this embodiment, the anode reset module 15 is configured to be controlled by the second scan signal SP, i.e., the data writing module 11 and the anode reset module 15 both use the second scan signal SP to control the switch, and it can also be understood that in the data writing stage tb, the data writing module 11 is turned on for data signal writing, and at the same time, the anode reset module 15 is also turned on for anode reset of the light emitting element 20, and the data writing stage tb is also the anode reset stage.

[0108] For the anode reset module, since the data writing module 11 and the anode reset module 15 can control the switch through the second scan signal SP, the second shift register circuit 32 and the second high-level voltage signal line 42 can also be arranged for the anode reset module 15 in the display panel, the second shift register circuit 32 is electrically connected with the second high-level voltage signal line 42; the second high-level voltage signal line 42 is configured to provide the second high-level voltage signal VGH2 to the second shift register circuit 32; the voltage of the first high-level voltage signal VGH1 and the voltage of the second high-level voltage signal VGH2 are different at least in part of the time. Wherein, the second shift register circuit 32 is electrically connected with the data writing module 11 and the anode reset module 15 at the same time, to provide the second scan signal SP to the data writing module 11 and the anode reset module 15. Thus, it is also not necessary to separately arrange the shift register circuit for the anode reset module 15, which greatly reduces the number of shift register circuits and the area of the non-display area where the shift register circuit is located, and helps to realize the narrow frame design.

[0109] Optionally, the first light emitting control unit 161 and the second light emitting control unit 162 are configured to be controlled by the first light emitting control signal Emit; the second scan signal SP and the first light emitting control signal Emit satisfy: V12=V14, and / or, V22=V24; wherein, V14 is the high-level voltage of the first light emitting control signal Emit, V22 is the high-level voltage of the second scan signal SP in the refresh frame, and V24 is the low-level voltage of the first light emitting control signal Emit.

[0110] Specifically, the first light emitting control unit 161 includes the seventh transistor M61, and the second light emitting control unit 162 includes the eighth transistor M62; two poles of the seventh transistor M61 are connected between the first power supply signal end PVDD and the first pole of the driving transistor M2; two poles of the eighth transistor M62 are connected between the second pole of the driving transistor M2 and the anode of the light emitting element 20; the gate of the seventh transistor M61 and the gate of the eighth transistor M62 receive the first light emitting control signal Emit; the seventh transistor M61 and the eighth transistor M62 are P-type channel transistors.

[0111] This embodiment indicates that the first light emitting control signal Emit driving the light emitting control module and the second scan signal SP driving the data writing module 11 have the same level state, which can control the off and on of the corresponding transistors according to the normal high-level voltage and low-level voltage.

[0112] For the anode reset module, Figure 14 is another structure schematic diagram of a display panel provided by the embodiment of the present application, referring to Figure 14In the embodiment of the present application, the display panel further comprises a third shift register circuit 33 and a third high-level voltage signal line 43, the light-emitting control module 16 is connected with the third shift register circuit 33; the third shift register circuit 33 is electrically connected with the third high-level voltage signal line 43; and the second high-level voltage signal line 42 is electrically connected with the third high-level voltage signal line 43.

[0113] Since the first light-emitting control signal Emit for driving the light-emitting control module and the second scanning signal SP for driving the data writing module 11 can have the same level state, the shift register circuits respectively arranged for the light-emitting control module 16 and the data writing module 11 can adopt the same high-level voltage, that is, the third high-level voltage signal line 43 corresponding to the third shift register circuit 33 connected with the light-emitting control module 16 can be electrically connected with the second high-level voltage signal line 42 corresponding to the second shift register circuit 32 connected with the data writing module 11, so as to receive the same high-level voltage signal VGH2.

[0114] In other embodiments of the present application, a separate shift register circuit can also be arranged for the gate reset module to improve the driving capability. Specifically, Figure 15 is a structural schematic diagram of still another display panel provided by the embodiment of the present application, which continues to refer to Figure 15 The display panel can further comprise a fourth shift register circuit 34 and a fourth high-level voltage signal line 44, the fourth shift register circuit 34 is electrically connected with the gate reset module 14, the fourth shift register circuit 34 is electrically connected with the fourth high-level voltage signal line 44, and the first high-level voltage signal line 41 is electrically connected with the fourth high-level voltage signal line 44.

[0115] As can be known from the foregoing, since the first scanning signal S2N for driving the compensation module 13 and the third scanning signal S1N for driving the gate reset module 14 can be arranged to have the same high-level voltage state in the refresh frame Trefresh and the holding frame Thold, the shift register circuits respectively arranged for the compensation module 13 and the gate reset module 14 can adopt the same high-level voltage, that is, the fourth high-level voltage signal line 44 corresponding to the fourth shift register circuit 34 connected with the gate reset module 14 can be electrically connected with the first high-level voltage signal line 41 corresponding to the first shift register circuit 31 connected with the compensation module 13, so as to receive the same high-level voltage signal VGH1.

[0116] Figure 16 is a driving timing diagram of still another pixel circuit provided by the embodiment of the present application, which continues to refer to Figure 2 、 Figure 9 、 Figure 10 and Figure 16In another embodiment of the present application, the compensation module 13 is also optionally controlled by a first scan signal S2N; the data writing module 11 is controlled by a second scan signal SP; the first scan signal S2N and the second scan signal SP satisfy: V11

[0117] As can be seen from the foregoing, the high voltage V11 of the first scan signal S2N in the refresh frame Trefresh (an example is 6V) is lower than the high voltage V12 of the second scan signal SP in the refresh frame Trefresh (an example is 7.8V), which means that the problem of leakage current in the compensation module 13 in the refresh frame Trefresh can be given priority, and the high voltage V11 of the first scan signal S2N in the refresh frame Trefresh is set to be lower than the high voltage of the second scan signal SP in the refresh frame Trefresh, that is, on the basis of turning off the compensation module 13 by using a relatively lower high voltage, the problem of leakage current caused by the capacitor coupling to raise the potential of the middle node of the double-gate transistor in the compensation module 13 is avoided.

[0118] It should be noted that, as Figure 9 , Figure 10 and Figure 16 mentioned above, for the gate reset module 14 controlled by the third scan signal S1N, the third scan signal S1N can have the same high voltage state as the first scan signal S2N, that is, as shown in the embodiments of Figure 9 and Figure 10 , or can be reasonably designed according to the influence of the gate reset module 14 on the gate of the driving transistor M2, for example, as shown in the embodiment of Figure 16 , which is not limited here.

[0119] Continuing to refer to Figure 9 and Figure 10 ,V11' can be 7.8V or 8V. As shown in Figure 10 , when V11' > V12, that is, the high voltage V11 of the first scan signal S2N in the refresh frame Trefresh is set to be lower than the high voltage of the second scan signal SP in the refresh frame Trefresh, the problem of leakage current in the compensation module 13 in the refresh frame Trefresh is solved, and at the same time, the high voltage V11' of the first scan signal S2N in the holding frame Thold is set to be higher, which avoids the problem that the compensation module 13 can not be turned off in the holding frame Thold.

[0120] Continuing to refer toFigure 11 and Figure 12 , based on Figure 9 , Figure 10 or Figure 16 the driving timing scheme shown in the above table, in the display panel of the embodiment of the present application, the first scan signal S2N corresponding to the compensation module 13 of the pixel circuit 10 of the first sub-area AA1 and the second sub-area AA2 can also satisfy: V11_1 > V11_2; wherein V11_1 is the high level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the first sub-area AA1 in the refresh frame Trefresh, and V11_2 is the high level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the second sub-area AA2 in the refresh frame Trefresh.

[0121] In the embodiment, the high level voltage V11_2 of the first scan signal S2N of the second sub-area AA2 in the refresh frame Trefresh is lower, so that the transistor gate in the compensation module 13 receives a relatively lower high level voltage for off control, thereby the compensation module 13 in the low frequency area can be controlled to relatively more effectively reduce the leakage current, and the brightness change caused by the leakage current problem can be avoided to be perceived by the human eye.

[0122] Based on the same inventive concept, the embodiment of the present application also provides a display device. Figure 17 A structural schematic diagram of a display device provided by the embodiment of the present application is shown in Figure 17 The display device includes the display panel 1 provided by any embodiment of the present application, so that the display device provided by the embodiment of the present application has the beneficial effects of the display panel provided by the embodiment of the present application, which will not be described here. For example, the display device can be a mobile phone, a computer, a smart wearable device (for example, a smart watch), a vehicle-mounted display device, and an electronic device, which is not limited by the embodiment of the present application.

[0123] It should be noted that the above is only the preferred embodiment of the present application and the technical principle applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments, mutual combinations and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The pixel circuit comprises a data writing module, a driving module and a compensation module. The driving module comprises a driving transistor. The data writing module is connected between a data signal input end and a first electrode of the driving transistor. The compensation module is connected between a gate electrode and a second electrode of the driving transistor. The picture display process of the display panel comprises display frames, and the display frames comprise refresh frames and holding frames. The compensation module is configured to be controlled by a first scan signal; the first scan signal satisfies: V11 The data writing module is configured to be controlled by a second scan signal; the first scan signal and the second scan signal satisfy: V11 The first scan signal and the second scan signal satisfy: V11' 2. The display panel of claim 1, wherein, The data writing module is configured to write a driving signal to the first electrode of the driving transistor, and the maximum value of the driving signal is VGMP; 3. The display panel of claim 1, wherein, V12> VGMP + 1V. The display panel comprises a first sub-region and a second sub-region; in the same time, the proportion of the refresh frames in the working process of the pixel circuit of the first sub-region is higher than that in the working process of the pixel circuit of the second sub-region.

4. The display panel of claim 1, wherein, The first scan signal corresponding to the compensation module of the pixel circuit of the first sub-region and the second sub-region satisfies: V11_1> V11_2; V11_1 is the high level voltage of the first scan signal corresponding to the compensation module in the pixel circuit of the first sub-region in the refresh frame, and V11_2 is the high level voltage of the first scan signal corresponding to the compensation module in the pixel circuit of the second sub-region in the refresh frame. The second scan signal also satisfies: V12 = V12'; 5. The display panel of claim 1, wherein, The first scan signal and the second scan signal also satisfy: V22 6. The display panel of claim 1, wherein, V21 is the low level voltage of the first scan signal, and V22 is the low level voltage of the second scan signal. The compensation module comprises a first transistor and a second transistor, which are connected in series between the gate electrode and the second electrode of the driving transistor in sequence, and the gate electrodes of the first transistor and the second transistor receive the first scan signal.

7. The display panel of claim 1, wherein, The data writing module comprises a third transistor, two electrodes of the third transistor are connected between the data signal input end and the first electrode of the driving transistor, and the gate electrode of the third transistor receives the second scan signal. The first transistor, the second transistor and the third transistor are all P-type channel transistors. The pixel circuit further comprises a gate reset module; the gate reset module is connected between a gate reset signal end and the gate electrode of the driving transistor.

8. The display panel of claim 1, wherein, ​ The gate reset module is configured to be controlled by a third scan signal. The first scan signal and the third scan signal satisfy: V11=V13, and / or, V21=V23. V11 is a high voltage of the first scan signal in the refresh frame, V13 is a high voltage of the third scan signal in the refresh frame, V21 is a low voltage of the first scan signal in the refresh frame, and V23 is a low voltage of the third scan signal in the refresh frame.

9. The display panel of claim 8, wherein, The first scan signal and the third scan signal also satisfy: V11'=V13'. V13' is a high voltage of the third scan signal in the holding frame.

10. The display panel of claim 8, wherein, The gate reset module comprises a fourth transistor and a fifth transistor. The fourth transistor and the fifth transistor are connected in series between the gate of the driving transistor and a gate reset signal input end, and the gates of the fourth transistor and the fifth transistor receive the third scan signal. The fourth transistor and the fifth transistor are P-type channel transistors.

11. The display panel of claim 1, wherein, The pixel circuit further comprises an anode reset module connected between an anode reset signal end and an anode of the light emitting element. The anode reset module is configured to be controlled by the second scan signal.

12. The display panel of claim 11, wherein, The anode reset module comprises a sixth transistor connected between the anode reset signal end and the anode of the light emitting element, and the gate of the sixth transistor receives the second scan signal. The sixth transistor is a P-type channel transistor.

13. The display panel of claim 1 or 2, wherein, The pixel circuit further comprises a light emitting control module; the light emitting control module comprises a first light emitting control unit and a second light emitting control unit; the first light emitting control unit, the driving module, the second light emitting control unit, and the light emitting element are connected in series between a first power signal end and a second power signal end. The first light emitting control unit and the second light emitting control unit are configured to be controlled by a first light emitting control signal. The second scan signal and the first light emitting control signal satisfy: V12=V14, and / or, V22=V24. V14 is a high voltage of the first light emitting control signal, V22 is a high voltage of the second scan signal in the refresh frame, and V24 is a low voltage of the first light emitting control signal.

14. The display panel of claim 13, wherein The first light emitting control unit comprises a seventh transistor, and the second light emitting control unit comprises an eighth transistor. The two poles of the seventh transistor are connected between the first power signal end and the first pole of the driving transistor, and the two poles of the eighth transistor are connected between the second pole of the driving transistor and the anode of the light emitting element. The gates of the seventh transistor and the eighth transistor receive the first light emitting control signal. The seventh transistor and the eighth transistor are P-type channel transistors.

15. The display panel of claim 1, wherein, The refresh frame comprises a data writing stage, and the holding frame comprises a bias adjusting stage. The data writing module is configured to be controlled by a second scanning signal, to provide a data signal Vdata for the driving transistor in the data writing stage, and to provide a bias adjustment signal VGMP for the driving transistor in the bias adjustment stage, wherein VGMP≥Vdata.

16. The display panel of claim 1, wherein, The display panel further comprises a first shift register circuit and a first high-level voltage signal line, and the first shift register circuit is electrically connected with the first high-level voltage signal line. The first high-level voltage signal line is configured to provide a first high-level voltage signal for the first shift register circuit. The voltage of the first high-level voltage signal in the refresh frame is less than that in the holding frame; the first shift register circuit is electrically connected with the compensation module.

17. The display panel of claim 16, wherein, The display panel further comprises a second shift register circuit and a second high-level voltage signal line, and the second shift register circuit is electrically connected with the second high-level voltage signal line. The second high-level voltage signal line is configured to provide a second high-level voltage signal for the second shift register circuit; the voltage of the first high-level voltage signal is different from that of the second high-level voltage signal at least in part of time; and the second shift register circuit is electrically connected with the data writing module.

18. The display panel of claim 17, wherein, The pixel circuit further comprises a gate reset module, an anode reset module and a light emitting control module. The gate reset module is electrically connected with the first shift register circuit, and the anode reset module is electrically connected with the second shift register circuit. The display panel further comprises a third shift register circuit and a third high-level voltage signal line, and the light emitting control module is connected with the third shift register circuit. The third shift register circuit is electrically connected with the third high-level voltage signal line; and the second high-level voltage signal line is electrically connected with the third high-level voltage signal line.

19. The display panel of claim 17, wherein, The pixel circuit further comprises a gate reset module, an anode reset module and a light emitting control module. The display panel further comprises a third shift register circuit, a fourth shift register circuit, a third high-level voltage signal line and a fourth high-level voltage signal line; the anode reset module is electrically connected with the second shift register circuit, the third shift register circuit is electrically connected with the light emitting control module, and the fourth shift register circuit is electrically connected with the gate reset module. The third shift register circuit is electrically connected with the third high-level voltage signal line; the second high-level voltage signal line is electrically connected with the third high-level voltage signal line. The fourth shift register circuit is electrically connected with the fourth high-level voltage signal line; and the first high-level voltage signal line is electrically connected with the fourth high-level voltage signal line.

20. A display panel comprising: The display panel comprises a pixel circuit and a light emitting element. The pixel circuit comprises a data writing module, a driving module and a compensation module. The driving module comprises a driving transistor. The data writing module is connected between a data signal input end and a first electrode of the driving transistor. The compensation module is connected between a gate electrode and a second electrode of the driving transistor. The picture display process of the display panel comprises a display frame, and the display frame comprises a refresh frame. The display panel comprises a first sub-region and a second sub-region; in the same time, the proportion of the refresh frame in the working process of the pixel circuit of the first sub-region is higher than the proportion of the refresh frame in the working process of the pixel circuit of the second sub-region; The compensation module is configured to be controlled by a first scan signal; the data writing module is configured to be controlled by a second scan signal; The first scan signal and the second scan signal satisfy: V11 V11 is the high voltage of the first scan signal in the refresh frame, and V12 is the high voltage of the second scan signal in the refresh frame; The first scan signal corresponding to the compensation module of the pixel circuit of the first sub-region and the second sub-region satisfies: V11_1>V11_2; V11_1 is the high voltage of the first scan signal corresponding to the compensation module in the pixel circuit of the first sub-region in the refresh frame, and V11_2 is the high voltage of the first scan signal corresponding to the compensation module in the pixel circuit of the second sub-region in the refresh frame.

21. A driving method of a display panel, comprising: The display panel comprises a pixel circuit and a light emitting element; The pixel circuit comprises a data writing module, a driving module and a compensation module; The driving module comprises a driving transistor; The data writing module is connected between a data signal input end and a first electrode of the driving transistor; The compensation module is connected between a gate electrode and a second electrode of the driving transistor; The picture display process of the display panel comprises a plurality of display frames, and the plurality of display frames comprise a refresh frame and a holding frame; The driving method of the display panel comprises: controlling the compensation module by using a first scan signal; wherein the first scan signal satisfies: V11 The driving method of the display panel further comprises: controlling the data writing module by using a second scan signal; wherein the first scan signal and the second scan signal satisfy: V11 22. The driving method according to claim 21, wherein The first scan signal and the second scan signal further satisfy: V11 23. A display device comprising: The display panel comprises a display panel as claimed in any one of claims 1-20.

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