Preparation method of energetic self-destruct chip, energetic self-destruct chip and application thereof

Abstract

The present application relates to the technical field, and more specifically, to a method for preparing an energetic self-destructing chip, an energetic self-destructing chip and its application. The method for preparing the energetic self-destructing chip comprises: providing a base and a chip body, the base having a first surface and a second surface relative to each other; forming a sink groove on the first surface; forming a first energetic material layer in the sink groove; forming a semiconductor bridge on the second surface, the heating part of the semiconductor bridge being opposite to the position of the first sink hole, the semiconductor bridge being used to release heat when powered on to detonate the first energetic material layer; and fitting and fixing the first surface to the chip body. The energetic self-destructing chip prepared according to the above scheme can improve the problems of difficult board-level integrated design, long excitation and detonation response time and high energy consumption of existing energetic self-destructing devices.

Description

Technical Field

[0001] The present application relates to the technical field, and in particular to a method for preparing an energetic self-destruct chip, an energetic self-destruct chip and applications. Background Art

[0002] Energetic self-destruct devices (chips) can physically destroy chips that store important information, which is the most feasible and thorough way to ensure information security. Common chip physical self-destruction methods usually use energetic materials to physically destroy chips.

[0003] At present, common energetic self-destruction devices are mainly formed by stacking discrete chips, energetic materials (including bases) and electrothermal excited semiconductor bridges (including bases) in sequence. When the electrothermal excited semiconductor bridge is powered on, it can release heat and detonate the energetic materials to achieve physical self-destruction of the chip. However, this type of energetic self-destruction device is relatively thick, which is not conducive to the design of board-level integrated systems. Moreover, the energetic material has a long response time from the beginning of heating to the excitation and detonation, and the energy consumption is relatively high. Summary of the invention

[0004] The embodiments of the present application at least provide a method for preparing an energetic self-destruct chip, an energetic self-destruct chip and applications, which can improve the problems of difficult board-level integrated design, long excitation and detonation response time and high energy consumption of existing energetic self-destruct devices.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing an energetic self-destruct chip, comprising:

[0006] Providing a base and a chip body, the base having a first surface and a second surface opposite to each other;

[0007] forming a sink groove on the first surface and forming a first sink hole on the bottom surface of the sink groove;

[0008] forming a first energetic material layer in the sink groove and the first sink hole;

[0009] forming a semiconductor bridge on the second surface, the semiconductor bridge being used for releasing heat when powered on to detonate the first energetic material layer;

[0010] The first surface is attached and fixed to the chip body.

[0011] As a preferred solution of an embodiment of the present application, the first energetic material layer is formed by ultrasonic immersion filling.

[0012] As a preferred solution of an embodiment of the present application, the parameters of the ultrasonic immersion filling include: a filling time of 30 to 60 minutes and a particle size of the energetic material of 20 to 50 um.

[0013] As a preferred solution of the embodiment of the present application, the semiconductor bridge is formed by coating and mask etching.

[0014] As a preferred solution of the embodiment of the present application, the forming of the semiconductor bridge on the second surface includes:

[0015] A heating portion of the semiconductor bridge is formed on the second surface, and the heating portion of the semiconductor bridge is opposite to the first countersunk hole.

[0016] As a preferred solution of the embodiment of the present application, the step of forming the heating portion of the semiconductor bridge on the second surface includes:

[0017] forming a conductive layer on the second surface;

[0018] A heating electrode is formed on the surface of the conductive layer. The heating electrode is opposite to the first countersunk hole, and the resistance of the heating electrode is greater than the resistance of the conductive layer.

[0019] As a preferred solution of the embodiment of the present application, before forming the semiconductor bridge on the second surface, the method further includes:

[0020] A second countersunk hole is formed by etching the second surface. The second countersunk hole is opposite to the first countersunk hole and is used to form a heating portion of the semiconductor bridge.

[0021] As a preferred solution of the embodiment of the present application, the method further includes:

[0022] A second energetic material layer is formed in the second countersunk hole and on the surface of the heating electrode.

[0023] In a second aspect, an embodiment of the present application further provides an energetic self-destruct chip, which is prepared using the method for preparing an energetic self-destruct chip as described in any one of the first aspects.

[0024] In a third aspect, an embodiment of the present application further provides an application of the energetic self-destruct chip as described in the second aspect in a storage device.

[0025] The above technical solution of the present application has the following beneficial technical effects:

[0026] The energetic self-destruct chip of the embodiment of the present application sets the first energetic material layer in the sink groove and the sink hole, so that the distance between the first energetic material layer and the semiconductor bridge is reduced, which can shorten the excitation and detonation response time of the energetic self-destruct device and reduce energy consumption. In addition, since the first energetic material layer and the semiconductor bridge share a common base, compared with the structure in the prior art where the semiconductor bridge and the energetic material are separate, the energetic self-destruct device can save at least one base, which can make the structure of the energetic self-destruct device more compact, the overall device thickness is smaller, and the board-level system-level design is more convenient. In other words, the energetic self-destruct device of the embodiment of the present application can improve the problems of difficult board-level integrated design, long excitation and detonation response time, and high energy consumption of existing energetic self-destruct devices.

[0027] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solutions of the present application. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic diagram of the structure of an energetic self-destruct chip provided in an embodiment of the present application is shown;

[0030] Figures 2 to 7 The invention shows a preparation process of an energetic self-destruct chip provided in an embodiment of the present application;

[0031] Reference numerals:

[0032] 1. Chip body; 2. Energetic self-destruct device; 21. Base; 211. Sink; 212. First sink hole; 213. Second sink hole; 22. First energetic material layer; 23. Semiconductor bridge; 231. Heating electrode; 232. Conductive layer; 24. Second energetic material layer; 3. Packaging structure. DETAILED DESCRIPTION

[0033] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application.

[0034] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0035] The term "first" or "second" in the specification and claims of this application may include one or more of the features explicitly or implicitly. In the description of this application, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0036] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0037] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] refer to Figure 1 An embodiment of the present application provides an energetic self-destruct chip, including a chip body 1 and an energetic self-destruct device 2. The energetic self-destruct device 2 can physically destroy the chip body 1 when being activated.

[0039] Specifically, the energetic self-destruct device 2 includes a base 21, a first energetic material layer 22 and a semiconductor bridge 23. The base 21 has a first surface attached to the chip body 1 and a second surface away from the chip body 1. The first surface is provided with a sink 211 and a sink hole located at the bottom of the sink 211. The first energetic material layer 22 is formed in the sink 211 and the sink hole. The semiconductor bridge 23 is formed on the second surface. When used, the semiconductor bridge 23 can be powered on to release heat to detonate the first energetic material layer 22, thereby realizing the self-destruction of the chip.

[0040] According to the above scheme, the first energetic material layer 22 is arranged in the sink groove 211 and the sink hole, so that the distance between the first energetic material layer 22 and the semiconductor bridge 23 is reduced, which can shorten the excitation and detonation response time of the energetic self-destruction device 2 and reduce energy consumption. In addition, since the first energetic material layer 22 and the semiconductor bridge 23 share a base 21, compared with the structure in which the semiconductor bridge 23 and the energetic material are separated in the prior art, the energetic self-destruction device 2 can save at least one base 21, which can make the energetic self-destruction device 2 more compact, the overall device thickness is smaller, and the board-level system-level design is more convenient. In other words, the energetic self-destruction device 2 of the embodiment of the present application can improve the problems of the existing energetic self-destruction device 2, such as the difficulty of board-level integrated design, the long excitation and detonation response time, and the high energy consumption.

[0041] Optionally, the base 21 is a composite silicon base 21, which may be a single crystal silicon wafer with a thickness of 300-500 um or a silicon wafer with an oxide layer structure on the surface, etc. This embodiment of the application does not impose any limitation on this.

[0042] Optionally, the first countersunk hole 212 may be a round hole, a square hole, a slit-shaped structure, etc. In this embodiment, the first countersunk hole 212 is preferably a round hole with a hole depth of 100 to 300 μm. In specific configuration, the first countersunk holes 212 may be evenly distributed on the bottom surface of the sink 211 or may be regionally distributed, depending on actual application requirements.

[0043] Optionally, the energetic material in the energetic material layer may be explosives, incendiary agents, chemical reagents, thermosensitive materials, electromagnetic pulse materials, etc. In this embodiment, the energetic material is an incendiary agent, such as aluminum powder, magnesium powder, or titanium powder, etc. This embodiment of the application does not impose any limitation on this.

[0044] Optionally, the semiconductor bridge 23 is composed of a multi-layer metal structure, and the metal used may include gold, copper, titanium, tungsten, etc. This embodiment of the present application does not impose any limitation on this.

[0045] Optionally, the semiconductor bridge 23 includes a heating part and a conductive part, the heating part and the conductive part are connected to each other, the heating part is opposite to the first countersunk hole 212, and the resistance of the heating part is greater than the resistance of the conductive part. When power is turned on, the heating part can be quickly heated, and the energetic material in the first countersunk hole 212 can be quickly heated, so that the response speed of the detonation excitation can be improved. In this regard, the embodiment of the present application does not make any limitation.

[0046] Optionally, a second countersunk hole 213 is provided on the second surface of the base 21, and the second countersunk hole 213 is opposite to the first countersunk hole 212, and the second countersunk hole 213 is used to set the heating part of the semiconductor bridge 23. In this way, the distance between the heating part of the semiconductor bridge 23 and the first energetic material layer 22 can be further shortened, thereby further improving the response speed of the detonation excitation. In this regard, the embodiment of the present application does not make any limitation.

[0047] Optionally, the second countersunk hole 213 may be a round hole, a square hole, a slit-shaped structure, etc. In this embodiment, the second countersunk hole 213 is preferably a round hole with a hole depth of 50 to 100 um. In specific settings, the second countersunk holes 213 may be evenly distributed on the second surface or regionally distributed, depending on actual application requirements.

[0048] Optionally, a second energetic material layer 24 is further provided in the second counterbore 213, and the second energetic material layer 24 is in direct contact with the heating portion of the semiconductor bridge 23. In specific use, the heating portion of the semiconductor bridge 23 can quickly generate heat to detonate the second energetic material layer 24 in direct contact with it, instantly releasing a large amount of energy, and then detonating the first energetic material layer 22. Compared with simply using the semiconductor bridge 23 to detonate the first energetic material layer 22, this can greatly shorten the response time of the detonation excitation and reduce energy consumption. In this regard, the embodiments of the present application do not make any limitation.

[0049] The energetic self-destruct chip of the embodiment of the present application has an integrated structure design of the energetic self-destruct structure and the electrothermal excitation structure through a base 21, which greatly improves the problems of difficult board-level integrated design of the energetic self-destruct device 2, long excitation and detonation response time, and high energy consumption.

[0050] refer to Figures 2 to 7 The method for preparing the energetic self-destruct chip of the embodiment of the present application comprises:

[0051] Step S100 : providing a base 21 and a chip body 1 , wherein the base 21 has a first surface and a second surface opposite to each other.

[0052] Step S200 , forming a sink groove 211 on the first surface and forming a first sink hole 212 on the bottom surface of the sink groove 211 .

[0053] Step S300 , forming a first energetic material layer 22 in the sink groove 211 and the first sink hole 212 .

[0054] Step S400 , forming a semiconductor bridge 23 on the second surface, the semiconductor bridge 23 is used to release heat when powered to detonate the first energetic material layer 22 .

[0055] Step S500 , attaching and fixing the first surface to the chip body 1 .

[0056] According to the above scheme, the energetic self-destruct chip is prepared, and its first energetic material layer 22 is located in the sink groove 211 and the sink hole, so that the distance between the first energetic material layer 22 and the semiconductor bridge 23 is reduced, which can shorten the excitation and detonation response time of the energetic self-destruct device 2 and reduce energy consumption. In addition, since the first energetic material layer 22 and the semiconductor bridge 23 share a base 21, compared with the structure in which the semiconductor bridge 23 and the energetic material are separated in the prior art, the energetic self-destruct device 2 can save at least one base 21, which can make the energetic self-destruct device 2 more compact, the overall device thickness is smaller, and the board-level system-level design is more convenient. Therefore, according to the above scheme, the problems of difficult board-level integrated design, long excitation and detonation response time and high energy consumption of the existing energetic self-destruct device 2 can be improved.

[0057] In step S100 , the base 21 is a composite silicon base 21 , which may be a single crystal silicon wafer with a thickness of 300-500 um or a silicon wafer with an oxide layer structure on the surface.

[0058] In step S200, the sink groove 211 and the first sink hole 212 are used to accommodate the energetic material, wherein the first sink hole 212 is formed by extending the bottom surface of the sink groove 211 toward the second surface, which can not only increase the capacity of the energetic material, but also shorten the distance between the energetic material and the semiconductor bridge 23, which is beneficial to shorten the excitation and detonation response time of the energetic self-destruct device 2 and reduce energy consumption.

[0059] Optionally, the sink groove 211 and the first sink hole 212 may be formed by an etching process.

[0060] For example, the method of forming the sink groove 211 and the first sink hole 212 includes:

[0061] 1. Use industrial standard wet cleaning process to clean silicon wafers;

[0062] 2. Based on the structural design requirements, use photolithography to define the etching pattern area;

[0063] 3. TMAH vapor etching. The operation process mainly includes the following steps:

[0064] a) placing the sample with the patterned mask on the wafer holder with the surface to be etched facing downward;

[0065] b) Set up the vapor etching equipment, turn on the pressure sensor, temperature sensor, heater, rotating motor and cooling water pump and start timing;

[0066] c) According to the hole depth design requirements, the etching equipment is turned off after a certain period of stable etching;

[0067] d) After the preparation is completed, the sample is taken out and tested using a confocal microscope.

[0068] Optionally, the first countersunk hole 212 may be a round hole, a square hole, a slit-shaped structure, etc. In this embodiment, the first countersunk hole 212 is preferably a round hole with a hole depth of 100 to 300 μm. In specific configuration, the first countersunk holes 212 may be evenly distributed on the bottom surface of the sink 211 or may be regionally distributed, depending on actual application requirements.

[0069] In step S300, the energetic material in the energetic material layer may be explosives, combustion agents, chemical reaction agents, heat-sensitive materials, electromagnetic pulse materials, etc. In this embodiment, the energetic material is a combustion agent, such as aluminum powder, magnesium powder or titanium powder.

[0070] Optionally, a process combining an immersion filling process and ultrasonic technology can be used to form the first energetic material layer 22. It should be understood that in a specific implementation, the filling effect of the first energetic material layer 22 is closely related to process parameters (such as the temperature of the immersion liquid, the immersion time, the frequency of the ultrasonic wave, etc.), the aperture of the first countersunk hole 212, and the particle size of the energetic material. Therefore, by controlling the process parameters, the aperture of the first countersunk hole 212, and the particle size of the energetic material, the filling effect of the first energetic material layer 22 can be controlled. In this embodiment, the particle size of the energetic material is 20um~50um, the aperture of the first countersunk hole 212 is 100~500um, and the ultrasonic immersion filling time is 30~60min, which can achieve a better filling effect. In this regard, the embodiment of the present application does not make any limitation. In other embodiments, the first energetic material layer 22 can also be formed by an immersion filling process alone, or the first energetic material layer 22 can be formed by a screen printing process.

[0071] In step S400 , the semiconductor bridge 23 is composed of a multi-layer metal structure, and the metal used may include gold, copper, titanium, tungsten, etc.

[0072] Optionally, in the process of forming the semiconductor bridge 23 on the second surface, the process includes: forming a heating portion of the semiconductor bridge 23 on the second surface, and the heating portion of the semiconductor bridge 23 is opposite to the first countersunk hole 212. Specifically, the semiconductor bridge 23 includes a heating portion and a conductive portion, the heating portion and the conductive portion are connected to each other, the resistance of the heating portion is greater than the resistance of the conductive portion, and the heating portion can be quickly heated when power is turned on. Therefore, by positioning the heating portion of the semiconductor bridge 23 opposite to the first countersunk hole 212, the energetic material located in the first countersunk hole 212 can be quickly heated, thereby facilitating the improvement of the response speed of the detonation excitation. In this regard, the embodiments of the present application do not impose any limitation.

[0073] Optionally, the heating portion of the semiconductor bridge 23 is formed on the second surface, including: forming a conductive layer 232 on the second surface; forming a heating electrode 231 on the surface of the conductive layer 232, the heating electrode 231 is opposite to the first countersunk hole 212, and the resistance of the heating electrode 231 is greater than the resistance of the conductive layer 232. Among them, the conductive layer 232 is the conductive portion of the semiconductor bridge 23, and the heating electrode 231 is the heating portion of the semiconductor bridge 23. It should be understood that in a specific setting, the conductive layer 232 can be composed of multiple layers of low-impedance metal. In this regard, the embodiment of the present application does not make any limitation.

[0074] Optionally, a coating process and a mask etching process may be combined to form the semiconductor bridge 23. The coating and mask etching processes are understandable to process technicians and will not be described in detail here.

[0075] Optionally, before forming the semiconductor bridge 23 on the second surface, the method further includes: etching a second countersunk hole 213 on the second surface, the second countersunk hole 213 and the first countersunk hole 212 are located opposite to each other, and the second countersunk hole 213 is used to form a heating portion of the semiconductor bridge 23. In this way, the distance between the heating portion of the semiconductor bridge 23 and the first energetic material layer 22 can be further shortened, thereby further improving the response speed of the detonation excitation. This embodiment of the present application does not make any limitation to this.

[0076] It should be noted that the second countersunk hole 213 may have one or more heating parts of the semiconductor bridge 23. Of course, when there are multiple second countersunk holes 213, the heating parts of the semiconductor bridge 23 may not be provided in individual second countersunk holes 213. Even according to actual needs, the structures of the heating parts in the second countersunk holes 213 may be consistent with each other or inconsistent with each other.

[0077] Optionally, the second countersunk hole 213 may be a round hole, a square hole, a slit-shaped structure, etc. In this embodiment, the second countersunk hole 213 is preferably a round hole with a hole depth of 50 to 100 um. In specific settings, the second countersunk holes 213 may be evenly distributed on the second surface or regionally distributed, depending on actual application requirements.

[0078] Optionally, after forming the semiconductor bridge 23 on the second surface, the method further includes: forming a second energetic material layer 24 in the second sink 211 and on the surface of the heating electrode 231. That is, the second energetic material layer 24 is in direct contact with the heating electrode 231. In specific use, the heating portion of the semiconductor bridge 23 can quickly generate heat to detonate the second energetic material layer 24 in direct contact with it, instantly releasing a large amount of energy, and then detonating the first energetic material layer 22. Compared with simply using the semiconductor bridge 23 to detonate the first energetic material layer 22, this can greatly shorten the response time of the detonation excitation and reduce energy consumption. In this regard, the embodiments of the present application do not make any limitation.

[0079] Optionally, the process of forming the second energetic material layer 24 and the process of forming the first energetic material layer 22 can be completed simultaneously. That is, after the semiconductor bridge 23 is formed on the second surface, the first energetic material layer 22 and the second energetic material layer 24 are formed on both sides of the base 21 at the same time. In this way, the preparation time can be shortened, which is conducive to improving production efficiency. In this regard, the embodiment of the present application does not make any limitation. In other embodiments, the process of forming the second energetic material layer 24 and the process of forming the first energetic material layer 22 can also be completed successively.

[0080] In step 500, the first surface and the chip body 1 are bonded and fixed, which actually means that the chip body 1 and the energetic self-destruction device 2 are integrated to form an energetic self-destruction chip. In the bonded state, the first energetic material layer 22 and the chip body 1 are bonded.

[0081] Optionally, the chip body 1 and the energetic self-destruct device 2 may be bonded together first, and then the packaging structure 3 may be mounted on the chip body 1 and the energetic self-destruct device 2 to fix the two to form an energetic self-destruct chip. This embodiment of the present application does not impose any limitation on this. In other embodiments, the chip body 1 and the energetic self-destruct device 2 may also be bonded and fixed by adhesive to form an energetic self-destruct chip.

[0082] The energetic self-destruct chip prepared according to the above method has an integrated structure design of the energetic self-destruct structure and the electrothermal excitation structure through a base 21, which greatly improves the problems of difficult board-level integrated design of the energetic self-destruct device 2, long excitation and detonation response time, and high energy consumption.

[0083] The embodiment of the present application also provides an application of an energetic self-destruct chip in a storage device. The energetic self-destruct structure and the electrothermal excitation structure of the energetic self-destruct chip are integrated into a base 21, which greatly improves the problems of difficult board-level integrated design of the energetic self-destruct device 2, long excitation and detonation response time, and high energy consumption.

[0084] One or more embodiments of this specification are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of this application.

[0085] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing an energetic self-destructive chip, characterized in that: include: Providing a base and a chip body, the base having a first surface and a second surface opposite to each other; forming a sink groove on the first surface and forming a first sink hole on the bottom surface of the sink groove; forming a first energetic material layer in the sink groove and the first sink hole; forming a semiconductor bridge on the second surface, the semiconductor bridge being used for releasing heat when powered on to detonate the first energetic material layer; Fixing the first surface to the chip body; The forming of a semiconductor bridge on the second surface comprises: forming a heating portion of the semiconductor bridge on the second surface, wherein the heating portion of the semiconductor bridge is opposite to the first countersunk hole; The step of forming the heating portion of the semiconductor bridge on the second surface comprises: forming a conductive layer on the second surface; A heating electrode is formed on the surface of the conductive layer, the heating electrode is opposite to the first countersunk hole, and the resistance of the heating electrode is greater than the resistance of the conductive layer; Before forming the semiconductor bridge on the second surface, the method further comprises: A second countersunk hole is formed by etching the second surface. The second countersunk hole is opposite to the first countersunk hole and is used to form a heating portion of the semiconductor bridge.

2. The method according to claim 1, characterized in that The first energetic material layer is formed by ultrasonic immersion filling.

3. The method according to claim 2, characterized in that The parameters of the ultrasonic immersion filling include: a filling time of 30 to 60 minutes and a particle size of the energetic material of 20 to 50 um.

4. The method according to claim 1, characterized in that: The semiconductor bridge is formed by film coating and mask etching.

5. The method according to claim 1, characterized in that The method further comprises: A second energetic material layer is formed in the second countersunk hole and on the surface of the heating electrode.

6. An energetic self-destructive chip, characterized in that: The chip is prepared by the method for preparing the energetic self-destructive chip according to any one of claims 1 to 5.

7. Use of the energetic self-destruct chip as claimed in claim 6 in a storage device.

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