Phase shift circuit, step-down switching converter group and converter chip

Abstract

The invention relates to the technical field of electronic circuits, and discloses a phase shift circuit, a step-down switching converter group and a converter chip. The phase-shifting circuit comprises a time-delay phase-shifting module which comprises a plurality of time-delay phase-shifting units; an input end of the decoder is connected with different input voltage signals, and a plurality of output ends of the decoder are respectively connected with control ends of the plurality of delay phase shift units; the positive input end and the negative input end of the comparator are respectively connected with the output end of the delay phase shift module and reference voltage; the R end of the trigger is connected with a clock signal, the output end of the trigger is connected with the input end of the delay phase-shifting module, the S end of the trigger is connected with the output end of the comparator, and the decoder is used for responding to a specific input voltage signal to control the corresponding delay phase-shifting unit to be switched on so as to output the clock signal after phase shifting through the comparator. According to the invention, phase shifting can be effectively carried out on the clock, multi-phase operation is carried out in a multi-phase manner, enough load current required by engineering application can be provided, inductive current ripples can be offset, and output voltage ripples are smaller.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a phase shift circuit, a buck-type switching converter group and a converter chip. Background Art

[0002] Since the advent of electronic products, step-down switching converters have been widely used in battery-powered fields such as various communication devices, portable electronic devices, microprocessors, and automotive electronics. As a result, the design requirements for step-down converters have become more and more diverse, one of which is the power supply for driverless cars. The processor inside the driverless car needs to perform a large amount of calculations and processing on the driving environment information in a short time to ensure the safe driving of the car, which requires the power supply system to provide a large current and respond to changes in load current in a short time.

[0003] However, in the conventional buck switching converter chip, the same-phase operation is performed with a single phase and insufficient load current supply may occur. Summary of the invention

[0004] The object of the present invention is to provide a phase-shifting circuit, a step-down switching converter group and a converter chip, which can effectively shift the phase of the clock, perform multi-phase operation with multiple phases, provide sufficient load current required for engineering applications, and offset the inductor current ripple, so that the output voltage ripple is smaller.

[0005] In order to achieve the above-mentioned purpose, the first aspect of the present invention provides a phase shift circuit, which includes: a delayed phase shift module, including multiple delayed phase shift units; a decoder, the input end of the decoder is connected to different input voltage signals, and the multiple output ends of the decoder are respectively connected to the control ends of the multiple delayed phase shift units; a first comparator, the positive input end of the first comparator is connected to the output end of the delayed phase shift module, and the negative input end of the first comparator is connected to a first reference voltage; a first trigger, the R input end of the first trigger is connected to a clock signal, the output end of the first trigger is connected to the input end of the delayed phase shift module, and the S input end of the first trigger is connected to the output end of the first comparator, wherein the decoder is used to control the corresponding delayed phase shift unit among the multiple delayed phase shift units to be turned on in response to a specific input voltage signal, so as to output the phase-shifted clock signal through the first comparator.

[0006] Preferably, the multiple time-delay phase-shift units include: a shared complementary MOS tube; multiple parallel capacitor circuits, the capacitor circuit includes a capacitor and a switch unit, and one end of the capacitor circuit is connected to the drain of the complementary MOS tube; the multiple output ends of the decoder are respectively connected to the control ends of the switch units in the multiple parallel capacitor circuits; the positive input end of the first comparator is connected to the drain of the complementary MOS tube; and the output end of the first trigger is connected to the gate of the complementary MOS tube, wherein the decoder is used to control the switch unit on one of the multiple parallel capacitor circuits to close in response to the specific input voltage signal to turn on the corresponding capacitor circuit.

[0007] Preferably, the complementary MOS tube includes a PMOS tube and an NMOS tube, and the plurality of time-delay phase-shift units further include: a common current source, the current source is connected to the source of the PMOS tube, and the source of the NMOS tube is grounded.

[0008] Preferably, the decoder comprises: n second comparators, wherein the negative input terminals of the n second comparators are respectively connected to n input voltage signals, and the positive input terminals of the n second comparators are connected to each other; and n logic gate combinations, wherein the i-th logic gate combination comprises ni NOT gates and 1 AND gate, wherein the number of input terminals of the AND gate is n, and the output terminals of the 1st to ith second comparators are directly connected to the 1st to ith input terminals of the AND gate, and the i+1th to nth input terminals are connected to the i+1th to nth input terminals of the AND gate through corresponding NOT gates.

[0009] Through the above technical scheme, the present invention creatively sets a time-delay phase-shift module, a decoder, a first comparator and a first trigger in the phase-shift circuit, wherein the input end of the decoder is connected to different input voltage signals, and the multiple output ends of the decoder are respectively connected to the control ends of multiple time-delay phase-shift units in the time-delay phase-shift module; the positive input end of the first comparator is connected to the output end of the time-delay phase-shift module, and the negative input end of the first comparator is connected to the first reference voltage; the R input end of the first trigger is connected to the clock signal, the output end of the first trigger is connected to the input end of the time-delay phase-shift module, and the S input end of the first trigger is connected to the output end of the first comparator, wherein the decoder is used to control the corresponding time-delay phase-shift unit in the multiple time-delay phase-shift units to be turned on in response to a specific input voltage signal, so as to output the phase-shifted clock signal through the first comparator. Therefore, the present invention can effectively shift the phase of the clock through a simple circuit design.

[0010] The second aspect of the present invention provides a step-down switching converter group in a peak current mode, the step-down switching converter group comprising: N step-down switching converters connected in parallel, N being an integer greater than 1, wherein the step-down switching converter comprises: a main circuit; a pulse modulation control circuit, an input end of the pulse modulation control circuit being connected to a voltage feedback point externally connected to an output end of the main circuit; a loop control circuit, an output end of the loop control circuit being connected to the gates of an upper power tube and a lower power tube of the main circuit; and the phase shift circuit, a clock input end of the phase shift circuit The input end is connected to the first input end of the loop control circuit, the output end of the pulse modulation control circuit is connected to the second input end of the loop control circuit, wherein the phase shift angle of the phase shift circuit is 360° / N, wherein the clock output end of the phase shift circuit in the first of any two adjacent buck-type switching converters is connected to the clock input end of the phase shift circuit in the second, wherein the first buck-type switching converter further includes: an oscillator circuit, wherein the clock signal output end of the oscillator circuit is connected to the first input end of the loop control circuit, for generating an initial clock signal.

[0011] Preferably, the pulse modulation control circuit includes: an error amplifier, a negative input terminal of the error amplifier is connected to the voltage feedback point, and a positive input terminal of the error amplifier is connected to the target feedback voltage; a PWM comparator, a positive input terminal of the PWM comparator is connected to the output terminal of CCVS of the main circuit, and the output terminal of the PWM comparator is connected to the second input terminal of the loop control circuit.

[0012] Preferably, another positive input terminal of the PWM comparator is connected to the ramp signal output terminal of the oscillator circuit.

[0013] Preferably, the N step-down switching converters connected in parallel have the same structure, and the step-down switching converter further comprises: a switch module, comprising a switch unit and a switch control circuit, the clock output end of the oscillator circuit is connected to the first input end of the loop control circuit via the switch unit, and the corresponding switch unit is controlled to be closed by the switch control circuit in the first step-down switching converter; and the corresponding switch units are controlled to be opened by the switch control circuits in other step-down switching converters.

[0014] Preferably, the switch control circuit comprises: a third comparator, a positive input terminal of the third comparator is connected to the selection signal, a negative input terminal of the third comparator is connected to the second reference voltage, and an output terminal of the third comparator is connected to the control terminal of the switch unit.

[0015] Preferably, the loop control circuit comprises a second trigger, the first input terminal is an S input terminal, and the second input terminal is an R input terminal.

[0016] Through the above technical scheme, the present invention creatively introduces a phase shift circuit with adjustable phase shift angle into a buck switching converter, sets an oscillator circuit in the first buck switching converter to generate its own clock signal, combines the pulse signal generated by the pulse modulation control circuit to control the fixed conduction time of the upper power tube, and connects multiple buck switching converters in parallel. Therefore, the present invention can perform multi-phase operation in multiple phases, can provide sufficient load current required for engineering applications, and the inductor current ripple can be offset, and the output voltage ripple is smaller.

[0017] A third aspect of the present invention provides a converter chip, the converter chip comprising: the buck-type switching converter group in the peak current mode; and a selection switch for selecting the first to kth buck-type switching converters from the N buck-type switching converters connected in parallel in the buck-type switching converter group, wherein 1 <k≤N。

[0018] Through the above technical scheme, the present invention creatively uses the phase shifting circuit for multiple chips in parallel to form a variety of phase shifting options, so that the inductor current ripple can be offset when multiple chips are connected in parallel, the output voltage ripple is smaller, and sufficient load current required for engineering applications can be provided.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0021] Figure 1 is a structural schematic diagram of a phase shift circuit provided by an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of the structure of a decoder provided by an embodiment of the present invention;

[0023] Figure 3A is a schematic structural diagram of a buck switching converter in peak current mode provided by an embodiment of the present invention;

[0024] Figure 3B is a schematic structural diagram of a buck switching converter in peak current mode provided by an embodiment of the present invention;

[0025] Figure 4is a clock phase shift diagram of four converters connected in parallel provided by an embodiment of the present invention; and

[0026] Figure 5 It is a schematic diagram of the structure of four converters connected in parallel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0028] Figure 1 1 is a schematic diagram of the structure of a phase shift circuit provided by an embodiment of the present invention. Figure 1 As shown, the phase shift circuit 10 includes: a delay phase shift module 1, including multiple delay phase shift units (for example, delay phase shift units 1-1, 1-2, 1-3, ... 1-n); a decoder 2, the input end of the decoder 2 is connected to different input voltage signals, and the multiple output ends of the decoder 2 are respectively connected to the control ends of the multiple delay phase shift units; a first comparator 3, the positive input end of the first comparator 3 is connected to the output end of the delay phase shift module 1, and the negative input end of the first comparator 3 is connected to a first reference voltage; a first trigger 4, the R input end of the first trigger 4 is connected to a clock signal (for example, CLK_IN), the output end of the first trigger 4 is connected to the input end of the delay phase shift module 1, and the S input end of the first trigger 4 is connected to the output end of the first comparator 3.

[0029] The decoder 2 is used for controlling the corresponding time delay phase shift unit among the plurality of time delay phase shift units to be turned on in response to a specific input voltage signal, so as to output a phase-shifted clock signal through the first comparator 3 .

[0030] like Figure 1 As shown, the phase shift circuit has three pins, namely PHMODE, CLK_IN and CLK_OUT. The PHMODE pin is connected to the input of the decoder 2 for accessing different input voltage signals. The output of the decoder 2 is connected to the control end of each delay phase shift unit (for example, the control end of the voltage-controlled switch). The truth table of the decoder 2 is shown in Table 1 below. Different input PHMODE signals correspond to different delay phase shift units (for example, different capacitors), thereby making different phase shift selections. When the PHMODE pin is connected to an input voltage signal greater than V1 and less than V2, greater than V2 and less than V3, greater than V3 and less than V4, etc., a phase difference of 180 degrees, 120 degrees, and 90 degrees (between CLK_IN and CLK_OUT) will be generated accordingly, which corresponds to a 2-phase, 3-phase or 4-phase working mode.

[0031] For example, when the PHMODE signal of input is V1, the corresponding D1 outputs a high level to select the time-delay phase-shift unit 1-1. For example, due to the different capacitance of each time-delay phase-shift unit, the capacitance charging time is different, thereby causing different delay times to the clock pulse signal, thereby the clock pulse signal is phase-shifted. The output Q signal of the first trigger 4 is connected to the input end of the time-delay phase-shift module to control the capacitance charging and discharging of the time-delay phase-shift unit. The time-delay capacitor is connected to the positive input end of the first comparator 3, the CLK_IN signal is connected to the R input end of the first trigger 4 (for controlling the capacitance charging), the output of the first comparator 3 is connected to the S input end of the first trigger 4 (for controlling the capacitance discharging), and the output of the final first comparator 3 is connected to the CLK_OUT pin to complete the phase shift.

[0032] Table 1 Decoder truth table

[0033] A1 A2 A3 A4 … An D1D2D3D4…Dn 1 0 0 0 … 0 1000…0 1 1 0 0 … 0 1100…0 1 1 0 0 … 0 1110…0 1 1 0 0 … 0 1111…0 1 1 0 0 … 0 1111…0 1 1 0 0 … 0 1111…1

[0034] The phase shift circuit is used to shift the phase of the input clock so that the converter can operate in multiple phases, thereby avoiding the situation where the load current is insufficient. Multiple phases need to be cascaded to provide the load current required for engineering applications.

[0035] like Figure 1 As shown, the multiple time-delay phase-shift units include: a shared complementary MOS tube; multiple parallel capacitor circuits, the capacitor circuit includes a capacitor and a switch unit (for example, the first capacitor circuit includes a capacitor C1 and a switch S1; the second capacitor circuit includes a capacitor C2 and a switch S2; the third capacitor circuit includes a capacitor C3 and a switch S3... and so on), and one end of the capacitor circuit is connected to the drain of the complementary MOS tube; the multiple output ends of the decoder 2 are respectively connected to the control ends of the switch units (for example, switches S1, S2, S3...) in the multiple parallel capacitor circuits; the positive input end of the first comparator 3 is connected to the drain of the complementary MOS tube; and the output end of the first trigger 4 is connected to the gate of the complementary MOS tube.

[0036] The decoder 2 is used for controlling the switch unit on one of the plurality of parallel capacitor circuits to close in response to the specific input voltage signal, so as to turn on the corresponding capacitor circuit.

[0037] The complementary MOS transistors include PMOS transistors and NMOS transistors. The plurality of delay phase shift units also include: a common current source I REF , the current source I REF The source of the PMOS tube is connected to the ground.

[0038] The PHMODE pin is connected to the input of decoder 2 for accessing different input voltage signals, and the output of decoder 2 is connected to the control end of each voltage-controlled switch. The truth table of decoder 2 is shown in Table 1, and different input PHMODE signals correspond to different capacitors, thereby performing different phase shift selections. For example, when the input PHMODE signal is V1, D1 outputs a high level corresponding to select capacitor C1, and each capacitor is different, so the capacitor charging time is different, thereby causing different delay times to the clock pulse signal, thereby performing phase shift on the clock pulse signal. The output Q signal of the first trigger 4 is connected to the gates of the two MOS tubes to control the charging and discharging of the capacitor. The delay capacitor is connected to the positive input of the first comparator 3, the CLK_IN signal is connected to the R input of the first trigger 4 (used to control the charging of the capacitor), the output of the first comparator 3 is connected to the S input of the first trigger 4 (used to control the discharging of the capacitor), and finally the output of the first comparator 3 is connected to the CLK_OUT pin to complete the phase shift.

[0039] like Figure 1 As shown, the clock input CLK_IN is connected to the R input terminal of the first trigger 4, and the closing of the switch S3 (for example, a voltage-controlled switch) is determined by the voltage signal of the PHMODE pin. When the voltage signal input to the PHMODE pin is greater than V3 and less than the voltage of V4, the D3 signal shown in the truth table 1 will output a high level. At this time, the switch S3 of the capacitor C3 will be selected to be closed and turned on, thereby shifting the clock signal by 90°.

[0040] In one embodiment, the decoder 2 comprises: n second comparators, wherein the negative input terminals of the n second comparators are respectively connected to n input voltage signals, and the positive input terminals of the n second comparators are connected to each other; and n logic gate combinations, such as Figure 2 shown.

[0041] The i-th logic gate combination includes ni NOT gates and 1 AND gate, wherein the number of input terminals of the AND gate is n, the output terminals of the 1st to ith second comparators are directly connected to the 1st to ith input terminals of the AND gate, and the i+1st to nth input terminals are connected to the i+1st to nth input terminals of the AND gate through corresponding NOT gates, such as Figure 2 As shown. Where i≤n, and both are positive integers.

[0042] In summary, the present invention creatively sets a time-delay phase-shift module, a decoder, a first comparator and a first trigger in a phase-shift circuit, wherein the input end of the decoder is connected to different input voltage signals, and the multiple output ends of the decoder are respectively connected to the control ends of multiple time-delay phase-shift units in the time-delay phase-shift module; the positive input end of the first comparator is connected to the output end of the time-delay phase-shift module, and the negative input end of the first comparator is connected to a first reference voltage; the R input end of the first trigger is connected to a clock signal, the output end of the first trigger is connected to the input end of the time-delay phase-shift module, and the S input end of the first trigger is connected to the output end of the first comparator, wherein the decoder is used to control the corresponding time-delay phase-shift unit in the multiple time-delay phase-shift units to be turned on in response to a specific input voltage signal, so as to output the phase-shifted clock signal through the first comparator. Therefore, the present invention can effectively shift the phase of the clock through a simple circuit design.

[0043] An embodiment of the present invention provides a buck-type switching converter group in peak current mode, the buck-type switching converter group comprising: N buck-type switching converters 100 connected in parallel, such as Figure 3A or Figure 3B As shown, N is an integer greater than 1. For example, the buck switching converter group includes four buck switching converters 100 connected in parallel, such as Figure 5 shown.

[0044] like Figure 3A As shown, the step-down switching converter 100 includes: a main circuit 20; a pulse modulation control circuit 40, wherein an input terminal of the pulse modulation control circuit 40 is connected to a voltage feedback point FB externally connected to the output terminal of the main circuit 20; a loop control circuit 30, wherein the output terminal of the loop control circuit 30 is connected to the gates of the upper power tube M1 and the lower power tube M2 of the main circuit 20; and the phase shift circuit 10, wherein the clock input terminal of the phase shift circuit 10 is connected to the first input terminal of the loop control circuit 30, and the output terminal of the pulse modulation control circuit 40 is connected to the second input terminal of the loop control circuit 30. The phase shift angle of the phase shift circuit 10 is 360° / N. Figure 5 As shown, four buck switching converters 100 are connected in parallel, and the phase shift angle of the phase shift circuit is adjusted to 90°.

[0045] Wherein, the clock output end of the phase shift circuit in the first of any two adjacent buck-type switching converters is connected to the clock input end of the phase shift circuit in the second one.

[0046] like Figure 5As shown, for four parallel buck-type switching converters, the clock output terminal CLK_OUT of the phase-shift circuit in the first buck-type switching converter is connected to the clock input terminal CLK_IN of the phase-shift circuit in the second buck-type switching converter; the clock output terminal CLK_OUT of the phase-shift circuit in the second buck-type switching converter is connected to the clock input terminal CLK_IN of the phase-shift circuit in the third buck-type switching converter, and the connection conditions of the clock outputs and inputs of the other two adjacent converters are similar.

[0047] like Figure 3B As shown, the first step-down switching converter further includes: an oscillator circuit 50, wherein a clock signal output terminal of the oscillator circuit 50 is connected to a first input terminal of the loop control circuit 30 for generating an initial clock signal.

[0048] Specifically, each buck switching converter includes: a main circuit 20; a pulse modulation control circuit 40; a loop control circuit 30; and a phase shift circuit 10. The main circuit 20 is used to convert the high voltage provided by the DC source into a low DC voltage required for normal operation of the electrical equipment. The pulse modulation control circuit 40 uses voltage and current feedback closed-loop control to adjust the duty cycle according to the output feedback voltage of the buck switching converter to maintain the stability of the output voltage. In addition, Figure 3B As shown, the first buck switching converter further includes: an oscillator circuit 50. The loop control circuit 30 is used to output a control signal according to the signal generated by the pulse modulation control circuit 40 and the initial clock signal generated by the oscillator circuit 50 to trigger the on or off of the upper and lower power tubes.

[0049] Figure 4 Shown are the clock signals of four step-down switching converters 100 connected in parallel, CLK1 (a clock signal without phase shift), CLK2 (a clock signal with a 90° phase shift relative to CLK1), CLK3 (a clock signal with a 90° phase shift relative to CLK2), and CLK4 (a clock signal with a 90° phase shift relative to CLK3).

[0050] In various embodiments, the loop control circuit 30 includes a second flip-flop, the first input terminal is an S input terminal, and the second input terminal is an R input terminal.

[0051] Specifically, the step-down switching converter 100 includes: a main circuit 20; a second trigger, the output end of which is connected to the gates of the upper power tube M1 and the lower power tube M2 of the main circuit 20; and the phase shift circuit 10, the clock input end of the phase shift circuit 10 is connected to the S input end of the second trigger, and the output end of the pulse modulation control circuit 40 is connected to the R input end of the second trigger. The phase shift angle of the phase shift circuit 10 is 360° / N. Figure 5 As shown, four buck switching converters 100 are connected in parallel, and the phase shift angle of the phase shift circuit is adjusted to 90°.

[0052] like Figure 3A As shown, the main circuit 20 includes: the upper power tube M1; the lower power tube M2; CCVS, located between the upper power tube M1 and the lower power tube M2; an inductor L; an output capacitor Cout, the inductor L is connected in series with the output capacitor Cout and in parallel with the lower power tube M2. A first voltage-dividing resistor R1 and a second voltage-dividing resistor R2 connected in series via a voltage feedback point FB are connected in parallel with the output capacitor Cout, wherein the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are output terminals of the main circuit or voltage-dividing resistors external to the converter.

[0053] An external battery pack can be used to provide power VIN for the converter. The power VIN is connected to the source of the upper power tube, and the drain is connected to CCVS to collect the current of the upper power tube. CCVS (which serves as a current sampling module) is a current-controlled voltage source. Through a certain proportional conversion, the current of the upper power tube is converted into a voltage and superimposed with the SLOPE signal generated by the oscillator circuit for slope compensation. The drain connection of the two switching power tubes is SW, and the SW node is connected to the inductor L. The inductor L is connected in parallel with the resistor R_ESR and the capacitor C_OUT, and then connected in parallel with the external voltage-dividing resistors R1 and R2. The connection point of the voltage-dividing resistors R1 and R2 is the FB node. The feedback voltage to be distributed is selected by the resistance values ​​of the voltage-dividing resistors R1 and R2.

[0054] In one embodiment, the pulse modulation control circuit 40 includes: an error amplifier EA, a negative input terminal of the error amplifier EA is connected to a voltage feedback point FB externally connected to the output terminal of the main circuit 20, and a positive input terminal of the error amplifier EA is connected to a target feedback voltage (e.g., 0.6V); and a PWM comparator, a positive input terminal of the PWM comparator is connected to the output terminal of CCVS of the main circuit 20, and the output terminal of the PWM comparator is connected to the second input terminal of the loop control circuit 30.

[0055] Specifically, the output end of the PWM comparator is connected to the R input end of the second trigger, and the clock signal output end of the oscillator circuit is connected to the S end of the second trigger. The clock signal generated by the oscillator circuit 50 is output as a phase-shifted clock signal CLK_OUT through the phase shift circuit 10, and the clock signal CLK_OUT is used as the input signal CLK_IN of the phase shift circuit of the next buck-type switching converter. Similarly, a multi-phase output signal can be generated through multiple buck-type switching converters. The buck-type switching converter provided by the present invention introduces a clock phase shift circuit, and adopts a multi-phase output staggered method to reduce ripple. This load current balancing technology can solve the problem of local overheating or insufficient output power caused by unbalanced output current, and quickly achieve loop stability.

[0056] In order to perform slope compensation, in this embodiment, the other positive input terminal of the PWM comparator is connected to the ramp signal output terminal of the oscillator circuit 50, such as Figure 3B shown.

[0057] In one embodiment, since it is not clear which one will be the first converter in the converter group when preparing the step-down switching converter, the structures of the various converters can be designed to be the same, and the pulse modulation control circuit and the timing circuit can be turned on or off by configuring certain switching modules.

[0058] Specifically, the N buck-type switching converters connected in parallel have the same structure. Figure 3B As shown, the step-down switching converter further includes: a switch module, including a switch unit S and a switch control circuit, and the clock output end of the oscillator circuit 50 is connected to the first input end of the loop control circuit 30 via the switch unit S.

[0059] Correspondingly, the switch control circuit in the first buck-type switching converter controls the corresponding switch unit S to be closed; and the switch control circuits in other buck-type switching converters control the corresponding switch unit S to be opened.

[0060] That is, for the first buck switching converter in the converter group, the oscillator circuit is turned on by controlling S to be closed; and for the other buck switching converters, the oscillator circuit is turned off by controlling S to be opened.

[0061] like Figure 3B As shown, the switch control circuit includes: a third comparator 60, the positive input terminal of the third comparator 60 is connected to the selection signal SELECT, the negative input terminal of the third comparator 60 is connected to the second reference voltage (for example, 4V), and the output terminal of the third comparator 60 is connected to the control terminal of the switch unit S.

[0062] like Figure 3B As shown, SELECT is a direct input by the user. When a high level (such as a level higher than 4V) is input, the comparator connected to the SELECT pin outputs a high level. The high level signal directly controls the switch state of the switch unit S. At this time, the control S is closed and its own clock signal input is used. When SELECT is grounded, the comparator outputs a low level, the switch unit S is disconnected, and an external clock signal input is used. In other words, SELECT is a direct input by the user, which is used to determine whether the converter selects the clock output signal generated by the previous converter.

[0063] like Figure 3B As shown, the step-down switching converter adopts the peak current mode control method. A reference voltage of 0.6V is connected to the positive terminal of the error amplifier EA (the error amplifier EA contains a compensation circuit of EA), and the negative terminal is connected to the feedback voltage at the voltage feedback point FB connected from the periphery of the converter; the ramp signal (such as SLOPE signal) generated by the oscillator circuit 50 is superimposed with the collected voltage signal of the upper power tube M1 (for slope compensation) and then connected to the positive input terminal of the PWM comparator, and the negative terminal is connected to the output of the error amplifier EA; for the first step-down switching converter, the switch unit S is controlled to close by the SELECT signal, so that the output signal Vc of the PWM comparator and the clock signal (such as CLK signal) output by the oscillator circuit 50 enter the loop control circuit 30, and the clock signal (such as CLK signal) output by the oscillator circuit 50 is phase-shifted accordingly through the phase shift circuit 10, that is, the phase shift circuit 10 can output the clock signal after phase shift (such as CLK_OUT); the output signal of the loop control circuit 30 can be connected to the drive circuit, and the drive circuit drives the upper power tube M1 and the lower power tube M2 to realize the switch step-down effect and output the SW signal.

[0064] The frequency of the clock signal generated by the oscillator circuit 50 is fixed. The phase shift function not only affects the clock, but also reduces the ripple effect of the current. The change of the PWM duty cycle is determined by the rise time and fall time of the positive input signal of the PWM comparator.

[0065] During normal operation, the upper power tube M1 is turned on in each cycle when the oscillator circuit 50 sets the loop control circuit 30 (e.g., trigger) (e.g., S is 1), and is turned off when the PWM comparator resets the loop control circuit 30 (e.g., trigger) (e.g., R is 1). The peak inductor current when the PWM comparator resets the loop control circuit 30 (e.g., trigger) is controlled by the output of the error amplifier EA. When the load current increases, it causes the voltage at the voltage feedback point FB to drop slightly relative to the 0.6V reference voltage, which in turn causes the output voltage of the EA amplifier to increase until the average inductor current matches the new load current. When the upper power tube M1 is turned off, the lower power tube M2 is turned on until the inductor current begins to reverse or the next clock cycle begins. That is, when the signal voltage after slope compensation is lower than the EA amplifier output, the PWM comparator output voltage is low, the switch tube is turned on, and the inductor current rises; when the signal voltage after slope compensation is higher than the EA amplifier output, it is high, the switch tube is turned off, the synchronous rectifier tube is turned on, and the inductor current decreases. When the output voltage (VOUT) is disturbed, for example, the output voltage suddenly drops, the EA amplifier output signal increases, and the time that the slope-compensated signal is lower than the EA amplifier output signal is prolonged, that is, the switch conduction time is prolonged and the duty cycle is increased, thereby modulating the output voltage to a normal state.

[0066] The CLK_IN pin allows the converter to synchronize with an external clock (the output clock of another converter), and the CLK_OUT signal can be connected to the CLK_IN pin of the next converter to adjust the frequency and phase of the entire system.

[0067] The specific principle of the input clock signal being able to shift the phase is: the clock frequency of the buck switching converter is constant, for example, the clock frequency is always maintained at 1MHZ, then the phase can be shifted by using a phase shift circuit to delay the input clock signal. For example, if a 180° phase shift is required, then a phase shift circuit is used to delay the input clock by 500nS (the capacitor size can be set), and the final output clock signal will be connected to the loop control circuit (such as a trigger) in the next cascaded converter, and the clock output by the oscillator circuit inside the next converter is calibrated with the input phase-shifted clock through the phase-locked loop in the loop control circuit to complete the phase shift.

[0068] As a specific solution of the embodiment, four buck switching converters are connected in parallel, and the clock phase difference between each converter is 90°. Figure 5 When the voltage signal input to the PHMODE pin of each converter is adjusted to a voltage greater than V3 and less than V4, the phase shift circuit inside the converter will delay the clock signal by a corresponding time.

[0069] The phase shift circuit provided by the present invention is added to the step-down switching converter, which enables the converter to perform multi-phase operation in multiple phases, thereby avoiding the situation where the load current is insufficient and multiple phases need to be cascaded to provide the load current required for engineering applications.

[0070] Multiphase operation allows multiple converter phases to run while using minimal input and output capacitors. The operating supply voltage range is 20V to 4V, making it suitable for point-of-load power applications with dual, triple or quad lithium-ion battery inputs and 12V or 5V power rails. For applications that require a load current exceeding the maximum output current of a single converter, multiple converters can be cascaded to run out of phase, thereby providing more output current.

[0071] In summary, the present invention creatively introduces a phase shift circuit with adjustable phase shift angle into a buck-type switching converter, sets an oscillator circuit in the first buck-type switching converter to generate its own clock signal, combines the pulse signal generated by the pulse modulation control circuit to control the fixed conduction time of the upper power tube, and connects multiple buck-type switching converters in parallel. Therefore, the present invention can perform multi-phase operation in multiple phases, can provide sufficient load current required for engineering applications, and the inductor current ripple can be offset, and the output voltage ripple is smaller.

[0072] An embodiment of the present invention provides a converter chip, the converter chip comprising: a buck-type switching converter group in the peak current mode; and a selection switch for selecting the first to kth buck-type switching converters from N buck-type switching converters connected in parallel in the buck-type switching converter group, wherein 1 <k≤N。

[0073] Specifically, according to actual needs, the first k buck switching converters can be selected from the N buck switching converters connected in parallel by a selection switch to form a k-phase output signal, where k is an integer. When k=4, the phase shift angle of the phase shift circuit is adjusted to 90°.

[0074] In summary, the present invention creatively uses the phase shifting circuit for multiple chips in parallel to form a variety of phase shifting options, so that the inductor current ripple can be offset when multiple chips are connected in parallel, the output voltage ripple is smaller, and sufficient load current required for engineering applications can be provided.

[0075] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0076] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0077] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a single-chip microcomputer, a chip or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0078] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0079] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0080] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A phase shift circuit, characterized in that: The phase shift circuit includes: a time-delay phase shift module, including a plurality of time-delay phase shift units; a decoder, wherein the input end of the decoder is connected to different input voltage signals, and the plurality of output ends of the decoder are respectively connected to the control ends of the plurality of time-delay phase shift units; a first comparator, wherein the positive input end of the first comparator is connected to the output end of the time-delay phase shift module, and the negative input end of the first comparator is connected to a first reference voltage; a first trigger, wherein the R input end of the first trigger is connected to a clock signal, the output end of the first trigger is connected to the input end of the time-delay phase shift module, and the S input end of the first trigger is connected to the output end of the first comparator. The decoder is used for controlling the corresponding time delay phase shift unit among the plurality of time delay phase shift units to be turned on in response to a specific input voltage signal, so as to output a phase-shifted clock signal through the first comparator.

2. The phase shift circuit according to claim 1, characterized in that: The multiple time-delay phase-shift units include: a shared complementary MOS tube; multiple parallel capacitor circuits, the capacitor circuit includes a capacitor and a switch unit, and one end of the capacitor circuit is connected to the drain of the complementary MOS tube; multiple output ends of the decoder are respectively connected to the control ends of the switch units in the multiple parallel capacitor circuits; the positive input end of the first comparator is connected to the drain of the complementary MOS tube; and the output end of the first trigger is connected to the gate of the complementary MOS tube. The decoder is used to control the switch unit on one of the multiple parallel capacitor circuits to close in response to the specific input voltage signal, so as to turn on the corresponding capacitor circuit.

3. The phase shift circuit according to claim 2, characterized in that: The complementary MOS tube includes a PMOS tube and an NMOS tube. The multiple time-delay phase-shift units further include: a common current source, the current source is connected to the source of the PMOS tube, and the source of the NMOS tube is grounded.

4. The phase shift circuit according to claim 1, characterized in that: The decoder comprises: n second comparators, wherein the negative input terminals of the n second comparators are respectively connected to n input voltage signals, and the positive input terminals of the n second comparators are connected to each other; and n logic gate combinations, Among them, the i-th logic gate combination includes ni NOT gates and 1 AND gate, wherein the number of input terminals of the AND gate is n, the output terminals of the 1st to ith second comparators are directly connected to the 1st to ith input terminals of the AND gate, and the i+1th to nth input terminals are connected to the i+1th to nth input terminals of the AND gate through corresponding NOT gates.

5. A step-down switching converter group in peak current mode, characterized in that: The step-down switching converter group includes: N step-down switching converters connected in parallel, where N is an integer greater than 1, Wherein, the step-down switching converter comprises: a main circuit; a pulse modulation control circuit, wherein one input end of the pulse modulation control circuit is connected to a voltage feedback point externally connected to the output end of the main circuit; a loop control circuit, wherein the output end of the loop control circuit is connected to the gates of the upper power tube and the lower power tube of the main circuit; and a phase shift circuit according to any one of claims 1 to 4, wherein the clock input end of the phase shift circuit is connected to the first input end of the loop control circuit, and the output end of the pulse modulation control circuit is connected to the second input end of the loop control circuit, wherein the phase shift angle of the phase shift circuit is 360° / N, The clock output terminal of the phase shift circuit in the first of any two adjacent buck switching converters is connected to the clock input terminal of the phase shift circuit in the second one. The first step-down switching converter further includes: an oscillator circuit, wherein a clock signal output terminal of the oscillator circuit is connected to a first input terminal of the loop control circuit for generating an initial clock signal.

6. The step-down switching converter group according to claim 5, characterized in that: The pulse modulation control circuit includes: an error amplifier, a negative input terminal of the error amplifier is connected to the voltage feedback point, and a positive input terminal of the error amplifier is connected to the target feedback voltage; a PWM comparator, a positive input terminal of the PWM comparator is connected to the output terminal of the CCVS of the main circuit, and the output terminal of the PWM comparator is connected to the second input terminal of the loop control circuit.

7. The step-down switching converter group according to claim 6, characterized in that: Another positive input terminal of the PWM comparator is connected to the ramp signal output terminal of the oscillator circuit.

8. The step-down switching converter group according to claim 5, characterized in that: The N buck-type switching converters connected in parallel have the same structure, and the buck-type switching converters further include: The switch module includes a switch unit and a switch control circuit, wherein the clock output terminal of the oscillator circuit is connected to the first input terminal of the loop control circuit via the switch unit. The corresponding switch unit is controlled to be closed by the switch control circuit in the first buck-type switch converter; and the corresponding switch unit is controlled to be opened by the switch control circuits in other buck-type switch converters.

9. The step-down switching converter group according to claim 8, characterized in that: The switch control circuit includes: a third comparator, a positive input terminal of the third comparator is connected to a selection signal, a negative input terminal of the third comparator is connected to a second reference voltage, and an output terminal of the third comparator is connected to a control terminal of the switch unit.

10. The step-down switching converter group according to claim 5, characterized in that: The loop control circuit includes a second trigger, the first input terminal is an S input terminal, and the second input terminal is an R input terminal.

11. A converter chip, characterized in that: The converter chip comprises: A step-down switching converter group in peak current mode according to any one of claims 5 to 10; and A selection switch is used to select the 1st to kth buck-type switching converters from the N buck-type switching converters connected in parallel in the buck-type switching converter group, wherein 1 <k≤N。

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