Step-down switching converter group and converter chip in fixed on-time mode

Abstract

The invention relates to the technical field of electronic circuits, and discloses a step-down switching converter group and a converter chip in a fixed on-time mode. The converter group comprises N step-down switching converters which are connected in parallel, wherein each converter comprises a main circuit; the output end of the trigger is connected with the grid electrodes of the upper and lower power tubes of the main circuit; the clock input ends of the first phase shift circuit and the second phase shift circuit are respectively connected with the S end and the R end of the trigger, and the phase shift angle of the phase shift circuit is adjusted to 360 degrees / N. The first converter further comprises a pulse modulation control circuit, the first input end and the second input end of the pulse modulation control circuit are respectively connected with the output end and the feedback point of the main circuit, and the output end is connected with the S end; and the input end and the output end of the timing circuit are respectively connected with the output end and the R end of the trigger, and the timing circuit is used for controlling the fixed conduction time of the upper power tube. Multi-phase operation is carried out through multiple phases, enough load current needed by engineering application can be provided, inductive current ripples are offset, and output voltage ripples are smaller.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a buck-type switching converter group and a converter chip in a fixed on-time mode. Background Art

[0002] Since the advent of electronic products, step-down switching converters have been widely used in battery-powered fields such as various communication devices, portable electronic devices, microprocessors, and automotive electronics. As a result, the design requirements for step-down converters have become more and more diverse, one of which is the power supply for driverless cars. The processor inside the driverless car needs to perform a large amount of calculations and processing on the driving environment information in a short time to ensure the safe driving of the car, which requires the power supply system to provide a large current and respond to changes in load current in a short time.

[0003] However, in the conventional buck switching converter chip, the same-phase operation is performed with a single phase and insufficient load current supply may occur. Summary of the invention

[0004] The purpose of the present invention is to provide a step-down switching converter group and converter chip in a fixed on-time mode, which can perform multi-phase operation in multiple phases, can provide sufficient load current required for engineering applications, and the inductor current ripple can be offset, and the output voltage ripple is smaller.

[0005] In order to achieve the above-mentioned object, the present invention provides a buck-type switching converter group in a fixed conduction time mode on one hand, wherein the buck-type switching converter group comprises: N buck-type switching converters connected in parallel, N is an integer greater than 1, wherein the buck-type switching converter comprises: a main circuit; a first trigger, the output end of the first trigger is connected to the gate of the upper power tube and the lower power tube of the main circuit; a first phase shift circuit, the clock input end of the first phase shift circuit is connected to the S input end of the first trigger; and a second phase shift circuit, the clock input end of the second phase shift circuit is connected to the R input end of the first trigger, wherein the phase shift angle of the first phase shift circuit and the second phase shift circuit is adjusted to 360° / N, wherein the first phase shift circuit of any two adjacent buck-type switching converters is connected to the first phase shift circuit of any two adjacent buck-type switching converters. The clock output end of the phase circuit is connected to the clock input end of the first phase shift circuit in the second, and the clock output end of the second phase shift circuit in the first is connected to the clock input end of the second phase shift circuit in the second, wherein the first step-down switching converter also includes: a pulse modulation control circuit, the first input end of the pulse modulation control circuit is connected to the output end of the main circuit, and the second input end of the pulse modulation control circuit is connected to a voltage feedback point externally connected to the output end of the main circuit, and the output end of the pulse modulation control circuit is connected to the S input end of the first trigger; and a timing circuit, the input end of the timing circuit is connected to the output end of the first trigger, and the output end of the timing circuit is connected to the R input end of the first trigger, for controlling the fixed conduction time of the upper power tube.

[0006] Preferably, the first phase shift circuit and the second phase shift circuit include: an adjustable resistor; a first switch module, which turns on the circuit where the adjustable resistor is located in response to a first reference voltage to generate a current in the circuit; a current mirror; a second trigger, wherein the R input end of the second trigger serves as a clock input end; a second switch module, comprising: a first switch unit, a second switch unit and an inverter, wherein the output end of the second trigger is connected to the control end of the second switch unit, and the output end of the second trigger is connected to the control end of the first switch unit via the inverter; a first capacitor, wherein the first capacitor is connected in series with the first switch unit and in parallel with the second switch unit; and a first comparator, wherein the output end of the first comparator serves as a clock output end, the positive input end of the first comparator is connected to one end of the first capacitor, and the negative input end of the first comparator is connected to a second reference voltage, wherein, in response to a clock signal being at a high level, the first switch unit is closed and the second switch unit is opened, and the current charges the first capacitor via the current mirror; in response to the clock signal being at a low level and the voltage of the first capacitor being greater than the second reference voltage, the first switch unit is opened and the second switch unit is closed, and the first capacitor is discharged.

[0007] Preferably, the first switch module includes: an operational amplifier and a PMOS tube, the positive input terminal of the operational amplifier is connected to the first reference voltage, the negative input terminal of the operational amplifier is connected to the source of the PMOS tube and one end of the adjustable resistor, and the output of the operational amplifier is connected to the gate of the PMOS tube.

[0008] Preferably, the current mirror includes a first NMOS tube and a second NMOS tube whose gates are connected, the drain and gate of the first NMOS tube are connected to the drain of the PMOS tube, and the drain of the second NMOS tube is connected to the first capacitor via the first switch unit.

[0009] Preferably, the N step-down switching converters connected in parallel have the same structure, and the step-down switching converter further includes: a third switch module, including a third switch unit, a fourth switch unit and a switch control circuit, the output end of the pulse modulation control circuit is connected to the S input end of the first trigger via the third switch unit, the output end of the timing circuit is connected to the R input end of the first trigger via the fourth switch unit, and the corresponding third switch unit and the fourth switch unit are controlled to be closed by the switch control circuit in the first step-down switching converter; and the corresponding third switch unit and the fourth switch unit are controlled to be disconnected by the switch control circuits in other step-down switching converters.

[0010] Preferably, the switch control circuit includes: a second comparator, the positive input terminal of the second comparator is connected to the selection signal, the negative input terminal of the second comparator is connected to the third reference voltage, and the output terminal of the second comparator is connected to the control terminals of the third switch unit and the fourth switch unit.

[0011] Preferably, the main circuit includes: the upper power tube; the lower power tube; CCVS, located between the upper power tube and the lower power tube; an inductor; and an output capacitor, wherein the inductor is connected in series with the output capacitor and in parallel with the lower power tube.

[0012] Preferably, the pulse modulation control circuit includes: a VCVS, one input terminal of the VCVS is connected to the output terminal of the main circuit, and the other input terminal is connected to the output terminal of the CCVS; an OTA, a negative input terminal of the OTA is connected to the voltage feedback point, and a positive input terminal of the OTA is connected to the target feedback voltage; and a PWM comparator, a positive input terminal of the PWM comparator is connected to the output terminal of the OTA, and a negative input terminal of the PWM comparator is connected to the output terminal of the VCVS, and the output terminal of the PWM comparator is connected to the S input terminal of the first trigger.

[0013] Preferably, the pulse modulation control circuit also includes: a compensation circuit, including: a second capacitor and a third resistor, one end of the second capacitor is connected to the positive input end of the PWM comparator, the other end of the second capacitor is connected to one end of the third resistor, and the other end of the third resistor is grounded.

[0014] Through the above technical scheme, the present invention creatively introduces a phase shift circuit with adjustable phase shift angle into a buck switching converter, and sets a pulse modulation control circuit and a timing circuit in the first buck switching converter to generate its own clock signal, thereby controlling the fixed conduction time of the upper power tube, and connecting multiple buck switching converters in parallel. Therefore, the present invention can perform multi-phase operation in multiple phases, can provide sufficient load current required for engineering applications, and the inductor current ripple can be offset, and the output voltage ripple is smaller.

[0015] A second aspect of the present invention provides a converter chip, the converter chip comprising: a buck-type switching converter group in the fixed on-time mode; and a selection switch for selecting the first to i-th buck-type switching converters from N buck-type switching converters connected in parallel in the buck-type switching converter group, wherein 1 <i≤N。

[0016] Through the above technical scheme, the present invention creatively uses the phase shifting circuit for multiple chips in parallel to form a variety of phase shifting options, so that the inductor current ripple can be offset when multiple chips are connected in parallel, the output voltage ripple is smaller, and sufficient load current required for engineering applications can be provided.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0019] Figure 1A 1 is a schematic structural diagram of a buck switching converter in COT mode provided by an embodiment of the present invention;

[0020] Figure 1B 1 is a schematic structural diagram of a buck switching converter in COT mode provided by an embodiment of the present invention;

[0021] Figure 1C 1 is a schematic structural diagram of a buck switching converter in COT mode provided by an embodiment of the present invention;

[0022] Figure 2 is a structural schematic diagram of a phase shift circuit provided by an embodiment of the present invention;

[0023] Figure 3 is a waveform diagram of an inductor current provided by an embodiment of the present invention;

[0024] Figure 4 It is a connection diagram of two cascaded buck switching converters provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0026] An embodiment of the present invention provides a buck switching converter group in a constant on-time (COT) mode, wherein the buck switching converter group may include: N buck switching converters 100 connected in parallel, such as Figures 1A to 1C As shown, N is an integer greater than 1. For example, the buck switching converter group includes two buck switching converters 100 connected in parallel, such as Figure 4 shown.

[0027] like Figure 1AAs shown, the step-down switching converter 100 includes: a main circuit 10; a first trigger 20, the output end of the first trigger 20 is connected to the gate of the upper power tube M1 and the lower power tube M2 of the main circuit 10; a first phase shift circuit 30, the clock input end S_IN of the first phase shift circuit 30 is connected to the S input end of the first trigger 20; and a second phase shift circuit 40, the clock input end R_IN of the second phase shift circuit 40 is connected to the R input end of the first trigger 20. The phase shift angle between the first phase shift circuit 30 and the second phase shift circuit 40 is adjusted to 360° / N. Figure 4 As shown, two buck switching converters 100 are connected in parallel, and the phase shift angle of the two phase shift circuits is adjusted to 180°. The final inductor current waveform is as follows: Figure 3 shown.

[0028] Among them, the clock output end of the first phase shift circuit in the first of any two adjacent buck switching converters is connected to the clock input end of the first phase shift circuit in the second, and the clock output end of the second phase shift circuit in the first is connected to the clock input end of the second phase shift circuit in the second.

[0029] like Figure 4 As shown, for two parallel buck-type switching converters, the clock output terminal S_OUT of the first phase-shift circuit in the first buck-type switching converter is connected to the clock input terminal S_IN of the first phase-shift circuit in the second buck-type switching converter, and the clock output terminal R_OUT of the second phase-shift circuit in the first buck-type switching converter is connected to the clock input terminal R_IN of the second phase-shift circuit in the second buck-type switching converter.

[0030] like Figure 1B As shown, the first step-down switching converter may also include: a pulse modulation control circuit 50, wherein the first input terminal of the pulse modulation control circuit 50 is connected to the output terminal (output voltage is VOUT) of the main circuit 10, and the second input terminal of the pulse modulation control circuit 50 is connected to the voltage feedback point FB externally connected to the output terminal of the main circuit, and the output terminal of the pulse modulation control circuit 50 is connected to the S input terminal of the first trigger 20; and a timing circuit 60, wherein the input terminal of the timing circuit 60 is connected to the output terminal Q of the first trigger 20, and the output terminal of the timing circuit 60 is connected to the R input terminal of the first trigger, for controlling the fixed conduction time of the upper power tube.

[0031] Specifically, each buck switching converter includes: a main circuit 10; a first trigger 20; a first phase shift circuit 30; and a second phase shift circuit 40. The main circuit 10 is used to convert the high voltage provided by the DC source into a DC low voltage required for normal operation of the electrical equipment. Figure 1B As shown, the first buck-type switching converter also includes: a pulse modulation control circuit 50 and a timing circuit 60 (such as a Ton module). The pulse modulation control circuit 50 adopts voltage and current feedback closed-loop control to adjust the duty cycle according to the output feedback voltage of the buck-type switching converter to maintain the stability of the output voltage. The first trigger 20 is used to output a control signal according to the clock signal (i.e., S signal) generated by the pulse modulation control circuit 50 and the clock signal (i.e., R signal) generated by the timing circuit to trigger the conduction or shutdown of the upper and lower power tubes. In the COT mode, the S signal and the R signal in the first trigger jointly determine the conduction and shutdown time of the upper and lower power tubes.

[0032] The timing circuit 60 (e.g., Ton module) collects the state of M1 (as shown in C_2) to generate a signal to control the opening of the lower power tube M2. The difference between the output feedback voltage FB and the reference voltage of 0.6V is used as the positive terminal of the PWM comparator after passing through the transconductance amplifier, and the difference between the feedback current sampling Vsense and the output voltage Vout is used as the negative terminal of the PWM comparator after passing through the voltage-controlled voltage source (VCVS). The PWM output is the S-terminal input of the first trigger to control the opening of the upper power tube M1.

[0033] As a specific solution of the embodiment, Figure 4 As shown, for example, when two chips are connected in parallel, R_IN is connected to the output signal R_OUT generated by the previous chip, S_IN is connected to the output signal S_OUT generated by the previous chip, and the R_OUT and S_OUT output after the phase shift circuit are connected to the R_IN and S_IN of the next chip, thereby achieving the phase shift of the inductor current. When the two chips are connected in parallel, the chip input voltage range is 4-20V, the frequency range is 800kHz-4MHz, the output voltage is a stable 1.5V, the operating frequency is 1MHz, the single chip output current is 5A, and the output current is 10A after two chips are connected in parallel.

[0034] like Figure 1AAs shown, the main circuit 10 includes: the upper power tube M1; the lower power tube M2; CCVS, located between the upper power tube M1 and the lower power tube M2; an inductor L; and an output capacitor Cout, wherein the inductor L is connected in series with the output capacitor Cout and in parallel with the lower power tube M2. A first voltage-dividing resistor R1 and a second voltage-dividing resistor R2 connected in series via a voltage feedback point FB are connected in parallel with the output capacitor Cout, wherein the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are output terminals of the main circuit or voltage-dividing resistors external to the converter.

[0035] like Figure 1A As shown, the pulse modulation control circuit 50 includes: a VCVS, one input terminal of the VCVS is connected to the output terminal of the main circuit (e.g., VOUT), and the other input terminal is connected to the output terminal of the CCVS (e.g., Vsense); an OTA, a negative input terminal of the OTA is connected to the output terminal of the main circuit or the voltage feedback point FB of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 external to the converter, and a positive input terminal of the OTA is connected to a target feedback voltage (e.g., 0.6V); and a PWM comparator, a positive input terminal of the PWM comparator is connected to the output terminal of the OTA, a negative input terminal of the PWM comparator is connected to the output terminal of the VCVS, and an output terminal of the PWM comparator is connected to the S input terminal of the first trigger.

[0036] This embodiment uses a current-controlled voltage source to output current disturbance information (Vsense). The current of the upper power tube is fed back into the loop through a certain proportion of gain, replacing the ramp generator in the voltage mode and peak current mode. The modulation information does not need to pass through the large capacitor integrator of the error amplifier, so it has great advantages in transient response.

[0037] The clock signal generated by the pulse modulation control circuit 50 passes through the first phase shift circuit 30 to output a phase-shifted clock signal S_OUT, and the clock signal S_OUT serves as the input signal S_IN of the first phase shift circuit of the next buck-type switching converter; similarly, the clock signal generated by the timing circuit 60 passes through the second phase shift circuit 40 to output a phase-shifted clock signal R_OUT, and the clock signal R_OUT serves as the input signal R_IN of the second phase shift circuit of the next buck-type switching converter. Similarly, a multi-phase output signal can be generated through multiple buck-type switching converters. The buck-type switching converter provided by the present invention introduces a clock phase shift circuit, and adopts a multi-phase output staggered method to reduce ripple. This load current balancing technology can solve the problem of local overheating or insufficient output power caused by unbalanced output current, and quickly achieve loop stability.

[0038] When the system starts working, it works as follows: During the off time period, M1 is turned off, M2 is turned on, the energy storage inductor L is discharged, and the inductor current gradually decreases. The inductor current information is also connected to one input end of the pulse modulation control circuit 50 (for example, the voltage-controlled voltage source VCVS) through the current-controlled voltage source CCVS (which serves as a current sampling module), and the output voltage VOUT is connected to the other input end of the VCVS input. The difference between Vsense and VOUT is connected to the negative end of the PWM comparator through the gain of VCVS. The output voltage VOUT (for example, 1.5V) is connected to the feedback voltage of the voltage feedback point FB through the voltage-dividing resistors R1 and R2, and the target voltage 0.6V is connected to the positive input end of the PWM comparator through the gain of the transconductance amplifier (OTA). When the sampled current touches the valley current, the PWM comparator outputs a narrow pulse to flip the drive control signal (that is, the output signal of the first trigger 20) to high, turn off M2, turn on M1, and the off period ends and enters the on period. At this time, the on-time timer (Ton) module collects the M1 state, starts timing, and the inductor current rises. When the timing has passed a fixed time, the timer outputs a narrow pulse, making the control signal low, the system enters the shutdown cycle, and the Ton timer is cleared at the same time, completing a complete control cycle.

[0039] A multi-phase output signal can be generated through multiple step-down switching converters. The step-down switching converter provided by the present invention introduces a clock phase shift circuit, and adopts a multi-phase output interleaving method to reduce ripple. This load current balancing technology can solve the problems of local overheating or insufficient output power caused by unbalanced output current, and quickly achieve loop stability.

[0040] like Figure 1A As shown, the pulse modulation control circuit also includes: a compensation circuit, including: a second capacitor and a third resistor, one end of the second capacitor is connected to the positive input end of the PWM comparator, the other end of the second capacitor is connected to one end of the third resistor, and the other end of the third resistor is grounded.

[0041] Compared with the peak current mode, the COT mode eliminates the need to design a slope compensation module. The compensation value only needs to be designed at the OTA. In the COT mode, the disturbance of the inductor current will only affect the current cycle. The subsequent cycles have no difference from the steady-state waveform except for the shift on the time axis. The situation similar to the peak current mode disturbance increasing cycle by cycle will not occur. It is more stable and the compensation value is also easy to adjust.

[0042] According to the above analysis, each phase is staggered by 360° / N, where N represents the number of phases or the number of converters in parallel. Figure 4As shown, the CLKOUT (such as S_OUT and R_OUT) generated by the first converter should be consistent with the switching frequency generated by the converter itself, and the phase is staggered by 180° and input to the CLKIN (such as S_IN and R_IN) pin of the second converter. Therefore, the Rext at the PHMODE1 and PHMODE2 pins of the first chip is connected to 500kΩ. The resistors of the PHMODE1 and PHMODE2 pins of the second chip are connected to any resistance value. The SELECT pin of the first chip is connected to the input voltage VIN to select its own clock signal to work, and the SELECT pin of the second chip is grounded to select the clock signal provided by the previous chip to work.

[0043] This example uses the multi-master control current sharing method, such as Figure 4 As shown, when two chips are connected in parallel, the FB, SW, Vsense, and Vout pins are all connected.

[0044] In one embodiment, since it is not clear which one will be the first converter in the converter group when preparing the step-down switching converter, the structures of the various converters can be designed to be the same, and the pulse modulation control circuit and the timing circuit can be turned on or off by configuring certain switching modules.

[0045] Specifically, the N buck-type switching converters connected in parallel have the same structure. Figure 1C As shown, the step-down switching converter 100 may further include: a third switch module, including a third switch unit S2, a fourth switch unit S1 and a switch control circuit, the output end of the pulse modulation control circuit 50 is connected to the S input end of the first trigger 20 via the third switch unit S2, and the output end of the timing circuit 60 is connected to the R input end of the first trigger 20 via the fourth switch unit S1.

[0046] Correspondingly, the switch control circuit in the first buck-type switching converter controls the corresponding third switch unit S2 and the fourth switch unit S1 to be closed; and the switch control circuits in other buck-type switching converters control the corresponding third switch unit S2 and the fourth switch unit S1 to be opened.

[0047] That is to say, for the first buck-type switching converter in the converter group, the pulse modulation control circuit 50 and the timing circuit 60 are turned on by controlling S2 and S1 to be closed; and for other buck-type switching converters, the pulse modulation control circuit 50 and the timing circuit 60 are turned off by controlling S2 and S1 to be opened.

[0048] like Figure 1CAs shown, the switch control circuit includes: a second comparator 70, the positive input terminal of the second comparator 70 is connected to the selection signal SELECT, the negative input terminal of the second comparator 70 is connected to a third reference voltage (for example, 4V), and the output terminal of the second comparator 70 is connected to the control terminals of the third switch unit S2 and the fourth switch unit S1.

[0049] like Figure 1C As shown, SELECT is a direct input by the user. When a high level (such as a level higher than 4V) is input, the comparator connected to the SELECT pin outputs a high level (such as signal C_1). The C_1 signal directly controls the switch state of S1 and S2. At this time, S1 and S2 are controlled to be closed, and their own S and R signals are used for input. When SELECT is grounded, the comparator outputs a low level, S1 and S2 are disconnected, and external S and R signals are used for input. In other words, SELECT is a direct input by the user, which is used to determine whether the converter selects the clock output signal generated by the previous converter.

[0050] Specifically, if Figure 1C As shown, the external input voltage provides the internal power supply VIN for the chip. The VIN pin is connected to the drain of the upper power tube M1. The source of M1 is connected to one end of the current-controlled voltage source. The other end of the current-controlled voltage source is connected to the drain of the lower power tube M2, and the SW signal is output. One end of the inductor L is connected to the current-controlled voltage source, and the other end is connected to the feedback voltage-dividing resistors R1 and R2 of the output voltage, and the output capacitor Cout is connected to the load Rload. The feedback voltage FB outputs between the lower end of R1 and the upper end of R2. The output feedback voltage is connected to one end of the transconductance amplifier OTA. The other end of OTA is connected to the reference voltage of 0.6V. The difference between the two is connected to the positive end of the PWM comparator after OTA. One end of R4 is connected to the ground, and the other end is connected to one end of C1. The other end of C1 is connected to the output of OTA. Vsense and the output voltage sampling VOUT are respectively connected to the two input ends of the voltage-controlled voltage source, and the output of the voltage-controlled voltage source is connected to the negative end of the PWM comparator. The output of the PWM comparator is connected to the S input end of the first trigger. The input of the timing circuit (eg, Ton module) collects the on state of M1, and the output is connected to the S input of the first trigger. The output Q of the first trigger is connected to the input of the driving circuit, and the output of the driving circuit is connected to the gates of M1 and M2.

[0051] Therefore, the COT architecture makes the converter design simpler, the components become fewer, the compensation value is easier to adjust, and only less output capacitance is required to meet a given load transient response.

[0052] The specific structure of the phase shift circuit in the above embodiment is described below.

[0053] In one embodiment, if Figure 2 As shown, the first phase shift circuit and the second phase shift circuit include: an adjustable resistor Rext; a first switch module 1, which turns on the circuit where the adjustable resistor Rext is located in response to a first reference voltage to generate a current in the circuit; a current mirror 2; a second trigger 3, the R input end of the second trigger 3 serves as a clock input end; a second switch module, including: a first switch unit S3, a second switch unit S4 and an inverter 4, wherein the output end of the second trigger 3 is connected to the control end of the second switch unit S4, and the output end of the second trigger 3 is connected to the control end of the first switch unit S3 via the inverter 4; a first capacitor C2, the first capacitor C2 is connected in series with the first switch unit S3 and in parallel with the second switch unit S4; and a first comparator 5, the output end of the first comparator 5 serves as a clock output end, the positive input end of the first comparator 5 is connected to one end of the first capacitor C2, and the negative input end of the first comparator 5 is connected to the second reference voltage.

[0054] In which, in response to the clock signal being at a high level, the first switch unit S3 is closed and the second switch unit S4 is opened, and the current charges the first capacitor C2 via the current mirror 2; in response to the clock signal being at a low level and the voltage of the first capacitor C2 being greater than the second reference voltage, the first switch unit S3 is opened and the second switch unit S4 is closed, and the first capacitor C2 is discharged.

[0055] like Figure 2 As shown, Vref1 is a reference voltage, which is connected to the input end of the first switch module 1 to control the circuit where the adjustable resistor is located to be turned on or off through the first switch module 1. The source of the current mirror 2 is connected to VIN, the drain of the current mirror 2 is connected to the upper end of the voltage-controlled switch S1, the other end of S1 is connected to the upper end of C2, and the other end of C2 is grounded. At the same time, the positive input end of the first comparator 5 is connected from the lower end of S1 and the upper end of C2, and the negative input end of the first comparator 5 is connected to the reference voltage Vref2. The first comparator 5 outputs to the pin CLKOUT (which corresponds to R_OUT or S_OUT), and is connected to the S input end of the second trigger 3, and the R input end is connected to CLKIN (which corresponds to R_IN or S_IN). The output end Q of the second trigger 3 is connected to the control end of the voltage-controlled switch S2, and is connected to the input end of the inverter 4. The two ends of S2 are respectively connected to the two ends of C2 to complete the control of the charging and discharging of the capacitor.

[0056] like Figure 2As shown, CLKIN is the system input clock (which corresponds to R_IN or S_IN). When the Rext of the phase shift circuit is determined, the reference voltage Vref1 turns on the first switch module 1. The current value I1 of the circuit where Rext is located is obtained by Vref1 / Rext, and I1 charges the capacitor C through the current mirror; when the voltage across the first capacitor C2 exceeds the reference voltage Vref2, the first comparator 5 outputs a high level to set the S end of the second trigger 3 to 1, and the R end is 0 at this time. The output Q of the second trigger 3 is 1, so that the voltage-controlled switch S2 connected to the two ends of the capacitor is closed, and the control signal is disconnected through the inverter 4, and the first capacitor C2 starts to discharge; when the signal discharged to the R end (that is, the arrival of the system input clock) is 1, Q is cleared, S2 is disconnected, S1 is closed, and I1 continues to charge the first capacitor C2 until the first comparator 5 outputs a high level, at which time the signal is simultaneously output to the S end and CLKOUT of the second trigger 3, and the signal at the S end or CLKOUT is the clock signal after phase shifting, and the phase shift time is the capacitor charging time.

[0057] Specifically, the first switch module 1 includes: an operational amplifier 11 and a PMOS tube M3, the positive input terminal of the operational amplifier 11 is connected to the first reference voltage, the negative input terminal of the operational amplifier 11 is connected to the source of the PMOS tube M3 and one end of the adjustable resistor Rext, and the output of the operational amplifier 11 is connected to the gate of the PMOS tube M3.

[0058] like Figure 2 As shown, the current mirror 2 includes a first NMOS tube M4 and a second NMOS tube M5 whose gates are connected, the drain and gate of the first NMOS tube M4 are connected to the drain of the PMOS tube M3, and the drain of the second NMOS tube M5 is connected to the first capacitor C2 via the first switch unit S3.

[0059] like Figure 2As shown, Vref1 is the reference voltage, which is connected to the positive end of the operational amplifier. The output of the operational amplifier is connected to the gate of M3, the source of M3 is connected to the negative end of the operational amplifier, and the source of M3 is connected to the upper end of Rext. The PHMODE pin is drawn between the source of M3 and Rext, and the other end of Rext is grounded. The drain of M3 is connected to the drain of M4, the source of M4 is connected to VIN, the gate is connected to the gate of M5, and the gate and drain of M4 are connected to form a diode connection. The source of M5 is also connected to VIN, the drain is connected to the upper end of the voltage-controlled switch S1, the other end of S1 is connected to the upper end of C2, and the other end of C2 is grounded. At the same time, the positive input of the comparator is drawn from the lower end of S1 and the upper end of C2, and the negative input of the comparator is connected to the reference voltage Vref2. The comparator outputs to the pin CLKOUT, and is connected to the S input of the second trigger, and the R input is connected to CLKIN. The S / R output terminal Q is connected to the control end of the voltage-controlled switch S2, and is also connected to the input of the inverter. The two ends of S2 are connected to the two ends of C2 respectively to complete the control of capacitor charging and discharging.

[0060] like Figure 2 As shown, CLKIN is the system input clock (which corresponds to R_IN or S_IN). When Rext of the phase shift circuit is determined, the reference voltage Vref1 is output to the gate of M3 after passing through the operational amplifier, so that M3 is turned on. At the same time, the operational amplifier, M3 and Rext form a negative feedback loop to ensure that Vgs of M3 is constant. The current value I1 of M3 is obtained by Vref1 / Rext, and M4 and M5 form a current mirror. I1 charges the capacitor C through the current mirror. When the voltage across the capacitor exceeds the reference voltage Vref2, the comparator outputs a high level to set the S end of the trigger to 1. At this time, the R end is 0, and the trigger output Q is 1, which closes the voltage-controlled switch S2 connected to the capacitor. At the same time, the control signal is disconnected through the inverter, and the capacitor C starts to discharge. When the signal discharged to the R end (that is, the arrival of the system input clock) is 1, Q is cleared, S2 is disconnected, S1 is closed, and I1 continues to charge C until the comparator outputs a high level. At this time, the signal is output to the S end and CLKOUT of the trigger at the same time. The signal at the S end or CLKOUT is the clock signal after phase shifting, and the phase shift time is the capacitor charging time.

[0061] When multiple chips are connected in parallel, the S and R signals of the first chip enter the corresponding phase shift circuit. The user selects the external Rext from the phase selection input PHMODE to directly input the desired phase shift angle. The phase-shifted clock signal is connected to the S_IN and R_IN of the next chip via S_OUT and R_OUT. Repeat the above steps to achieve the phase shift of the two signals. The external Rext of the PHMODE pin of the last chip can take any resistance value. When the phase shift circuit is used for multiple chips in parallel, a variety of phase shift options are formed, so that the inductor current ripple can be offset when multiple chips are connected in parallel, and the output voltage ripple is smaller.

[0062] The phase shift angle achieved by the phase shift circuit is directly determined by Rext, and the specific relationship between the phase shift time t and Rext is: t=CRext, where C is the capacitance of the capacitor in the phase shift circuit, for example, C=1pf. For example, in a three-phase cascade, when the frequency is 1MHz, the inductor current phase shifts by 120°, then t=330ns, and the corresponding Rext=330kΩ. The phase shift angle can be selected from 1° to 180° at any angle, with a wide range of variation, and can be adapted to multiple parallel modes of 2 to 12 phases. The phase shift circuit pins include a clock input CLK_IN, a phase selection input PHMODE, and a phase-shifted output clock CLK_OUT.

[0063] The phase shift circuit is suitable for a system clock with adjustable frequency. In the buck switching converter in the COT mode, the system frequency is 800kHz to 4MHz. The phase shift circuit can work normally when multiple chips are connected in parallel.

[0064] In this embodiment, a phase shift circuit for controlling the output clock phase is added to the buck switching converter chip. The phase shift circuit is simple and easy to control, which can reduce the chip input and input capacitor size, help improve the loop response, and respond faster to the load. When connected in parallel, the inductor current ripple is offset, and the output voltage ripple is smaller.

[0065] The present invention designs a programmable phase shift circuit for parallel application of a step-down switching converter in COT mode, which can effectively shift the phase of the clock signal. The parallel power supply system can share the current stress and realize the N+1 redundant standby function. The multi-phase interleaved parallel connection can offset the inductor current ripple, and the output voltage ripple is smaller. The multi-phase interleaved parallel connection technology is divided into in-phase and out-of-phase operation. In-phase operation refers to the same frequency and phase, and the increment of the inductor current iL in one cycle Tsw is equivalent to the superposition of multiple inductor currents. Out-of-phase operation refers to the same frequency and inconsistent phase, and the increment of the inductor current of multiple converters in one cycle Tsw is partially or completely offset by the inductor current output by multiple chips with inconsistent phases. The phase shift referred to in each embodiment of the invention is out-of-phase operation.

[0066] In summary, the present invention creatively introduces a phase shift circuit with adjustable phase shift angle into a buck switching converter, and sets a pulse modulation control circuit and a timing circuit in the first buck switching converter to generate its own clock signal, thereby controlling the fixed on-time of the upper power tube, and connecting multiple buck switching converters in parallel. Therefore, the present invention can perform multi-phase operation in multiple phases, can provide sufficient load current required for engineering applications, and the inductor current ripple can be offset, and the output voltage ripple is smaller.

[0067] An embodiment of the present invention provides a converter chip, the converter chip comprising: a buck-type switching converter group in the fixed on-time mode; and a selection switch for selecting the first to i-th buck-type switching converters from N buck-type switching converters connected in parallel in the buck-type switching converter group, wherein 1 <i≤N。

[0068] Specifically, according to actual needs, the first i buck switching converters can be selected from the N buck switching converters connected in parallel by selecting the switch to form an output signal of phase i. Where i is an integer. When i=2, the phase shift angle of the phase shift circuit is adjusted to 180°.

[0069] In summary, the present invention creatively uses the phase shifting circuit for multiple chips in parallel to form a variety of phase shifting options, so that the inductor current ripple can be offset when multiple chips are connected in parallel, the output voltage ripple is smaller, and sufficient load current required for engineering applications can be provided.

[0070] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0071] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0072] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a single-chip microcomputer, a chip or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0073] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0074] The present application is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, and the combination of the process and / or box in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0075] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A step-down switching converter group in a fixed on-time mode, characterized in that: The step-down switching converter group includes: N step-down switching converters connected in parallel, where N is an integer greater than 1, The step-down switching converter includes: a main circuit; a first trigger, the output end of which is connected to the gates of the upper power tube and the lower power tube of the main circuit; a first phase shift circuit, the clock input end of which is connected to the S input end of the first trigger; and a second phase shift circuit, the clock input end of which is connected to the R input end of the first trigger, wherein the phase shift angle between the first phase shift circuit and the second phase shift circuit is adjusted to 360° / N. wherein the clock output terminal of the first phase shift circuit in the first of any two adjacent buck switching converters is connected to the clock input terminal of the first phase shift circuit in the second, and the clock output terminal of the second phase shift circuit in the first is connected to the clock input terminal of the second phase shift circuit in the second, Among them, the first step-down switching converter also includes: a pulse modulation control circuit, the first input end of the pulse modulation control circuit is connected to the output end of the main circuit, and the second input end of the pulse modulation control circuit is connected to a voltage feedback point externally connected to the output end of the main circuit, and the output end of the pulse modulation control circuit is connected to the S input end of the first trigger; and a timing circuit, the input end of the timing circuit is connected to the output end of the first trigger, and the output end of the timing circuit is connected to the R input end of the first trigger, which is used to control the fixed conduction time of the upper power tube.

2. The step-down switching converter group according to claim 1, characterized in that: The first phase shift circuit and the second phase shift circuit include: an adjustable resistor; a first switch module, which turns on the circuit where the adjustable resistor is located in response to a first reference voltage to generate a current in the circuit; a current mirror; a second trigger, wherein the R input end of the second trigger serves as a clock input end; a second switch module, including: a first switch unit, a second switch unit and an inverter, wherein the output end of the second trigger is connected to the control end of the second switch unit, and the output end of the second trigger is connected to the control end of the first switch unit via the inverter; a first capacitor, wherein the first capacitor is connected in series with the first switch unit and in parallel with the second switch unit; and a first comparator, wherein the output end of the first comparator serves as a clock output end, the positive input end of the first comparator is connected to one end of the first capacitor, and the negative input end of the first comparator is connected to the second reference voltage, In which, in response to the clock signal being at a high level, the first switch unit is closed and the second switch unit is opened, and the current charges the first capacitor via the current mirror; in response to the clock signal being at a low level and the voltage of the first capacitor being greater than the second reference voltage, the first switch unit is opened and the second switch unit is closed, and the first capacitor is discharged.

3. The step-down switching converter group according to claim 2, characterized in that: The first switch module includes: an operational amplifier and a PMOS tube, the positive input terminal of the operational amplifier is connected to the first reference voltage, the negative input terminal of the operational amplifier is connected to the source of the PMOS tube and one end of the adjustable resistor, and the output of the operational amplifier is connected to the gate of the PMOS tube.

4. The step-down switching converter group according to claim 3, characterized in that: The current mirror includes a first NMOS tube and a second NMOS tube whose gates are connected, the drain and gate of the first NMOS tube are connected to the drain of the PMOS tube, and the drain of the second NMOS tube is connected to the first capacitor via the first switch unit.

5. The step-down switching converter group according to claim 1, characterized in that: The N buck-type switching converters connected in parallel have the same structure, and the buck-type switching converters further include: The third switch module includes a third switch unit, a fourth switch unit and a switch control circuit, wherein the output end of the pulse modulation control circuit is connected to the S input end of the first trigger via the third switch unit, and the output end of the timing circuit is connected to the R input end of the first trigger via the fourth switch unit. The corresponding third switch unit and the fourth switch unit are controlled to be closed by the switch control circuit in the first buck-type switching converter; and the corresponding third switch unit and the fourth switch unit are controlled to be opened by the switch control circuits in other buck-type switching converters.

6. The step-down switching converter group according to claim 5, characterized in that: The switch control circuit includes: a second comparator, a positive input terminal of the second comparator is connected to a selection signal, a negative input terminal of the second comparator is connected to a third reference voltage, and an output terminal of the second comparator is connected to control terminals of the third switch unit and the fourth switch unit.

7. The step-down switching converter group according to claim 1, characterized in that: The main circuit includes: the upper power tube; the lower power tube; a CCVS located between the upper power tube and the lower power tube; an inductor; and an output capacitor, wherein the inductor is connected in series with the output capacitor and in parallel with the lower power tube.

8. The step-down switching converter group according to claim 7, characterized in that: The pulse modulation control circuit includes: a VCVS, one input terminal of the VCVS is connected to the output terminal of the main circuit, and the other input terminal of the VCVS is connected to the output terminal of the CCVS; an OTA, a negative input terminal of the OTA is connected to the voltage feedback point, and a positive input terminal of the OTA is connected to a target feedback voltage; and a PWM comparator, a positive input terminal of the PWM comparator is connected to the output terminal of the OTA, and a negative input terminal of the PWM comparator is connected to the output terminal of the VCVS, and the output terminal of the PWM comparator is connected to the S input terminal of the first trigger.

9. The step-down switching converter group according to claim 8, characterized in that: The pulse modulation control circuit also includes: a compensation circuit, including: a second capacitor and a third resistor, one end of the second capacitor is connected to the positive input end of the PWM comparator, the other end of the second capacitor is connected to one end of the third resistor, and the other end of the third resistor is grounded.

10. A converter chip, characterized in that: The converter chip comprises: A step-down switching converter group in a fixed on-time mode according to any one of claims 1 to 9; and A selection switch is used to select the 1st to the i-th buck-type switching converters from the N buck-type switching converters connected in parallel in the buck-type switching converter group, wherein 1 <i≤N。

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