Display device

Abstract

The present invention relates to a display device. The display device includes: a display panel; a gate driving circuit, which outputs a plurality of gate signals to the display panel, wherein the gate driving circuit includes: a stage portion, including a plurality of first stages and a plurality of second stages respectively subordinate to the plurality of first stages; a branch line portion, including first branch lines respectively electrically connected to the plurality of first stages and second branch lines respectively electrically connected to the plurality of second stages, wherein the first branch lines and the second branch lines extend along a first direction and are arranged along a second direction intersecting the first direction; a line pattern row, including a first pattern row electrically connected to the first branch line and a second pattern row electrically connected to the second branch line; a signal line, facing the line pattern row in the first direction, wherein one of the second branch lines includes a first line portion extending along the first direction and a second line portion extending along the second direction and arranged between the signal line and the line pattern row on a plane.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a display device comprising a gate driving circuit. Background Art

[0002] The display device includes: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines; a gate driving circuit providing gate signals to the gate lines; and a data driving circuit outputting data signals to the data lines.

[0003] Especially, the gate driving circuit includes a plurality of stages for outputting gate signals, and the stages have a form built in the display panel. Summary of the invention

[0004] An object of the present invention is to provide a display device capable of improving driving reliability.

[0005] A display device according to one embodiment for achieving the purpose of the present invention includes: a display panel; a gate driving circuit, which outputs multiple gate signals to the display panel, wherein the gate driving circuit includes: a stage portion, including multiple first stages and multiple second stages respectively subordinate to the multiple first stages; a branch line portion, including first branch lines respectively electrically connected to the multiple first stages and second branch lines respectively electrically connected to the multiple second stages, wherein the first branch lines and the second branch lines extend along a first direction and are arranged along a second direction intersecting the first direction; a line pattern row, including a first pattern row electrically connected to the first branch line and a second pattern row electrically connected to the second branch line; a signal line, facing the line pattern row in the first direction, wherein one of the second branch lines includes a first line portion extending along the first direction and a second line portion extending along the second direction and arranged between the signal line and the line pattern row on a plane.

[0006] According to an embodiment of the present invention, each of the line pattern rows includes a plurality of first line patterns and a plurality of second line patterns arranged alternately with each other along the first direction.

[0007] According to an embodiment of the present invention, each of the first pattern rows is electrically connected to corresponding two first branch lines of the first branch lines, and each of the second pattern rows is electrically connected to corresponding two second branch lines of the second branch lines.

[0008] According to an embodiment of the present invention, the two first branch lines are respectively connected to corresponding two first line patterns among the plurality of first line patterns, and the two second branch lines are respectively connected to corresponding two second line patterns among the plurality of second line patterns.

[0009] According to an embodiment of the present invention, the plurality of first line patterns respectively receive clock signals, and the plurality of second line patterns respectively receive clock inversion signals having a phase opposite to that of the clock signal.

[0010] According to an embodiment of the present invention, the second branch line including the first line portion and the second line portion has a structure connected to a second line pattern that is most adjacent to the signal line among the plurality of second line patterns.

[0011] According to an embodiment of the present invention, one first line pattern among the plurality of first line patterns is arranged between the second line pattern most adjacent to the signal line and the second line portion.

[0012] According to an embodiment of the present invention, the first line pattern arranged between the second line pattern closest to the signal line and the second line portion directly faces the signal line in the first direction and receives a clock signal, and the second line pattern closest to the signal line receives a clock inversion signal having a phase opposite to that of the clock signal.

[0013] According to an embodiment of the present invention, the second line portion overlaps between the second pattern row and the signal line.

[0014] According to an embodiment of the present invention, the second branch line including the first line portion and the second line portion and the signal line are arranged on different layers from each other.

[0015] According to an embodiment of the present invention, each of the remaining second branch lines in the second branch lines does not overlap between the signal line and the line pattern row on the plane.

[0016] According to an embodiment of the present invention, the first branch lines connected to one first pattern row among the first branch lines include a parallel line portion extending along the first direction and a protruding line portion having a shape bent from the parallel line portion.

[0017] According to an embodiment of the present invention, each of the line pattern rows includes a plurality of first line patterns and a plurality of second line patterns that are spaced apart from each other and arranged alternately with each other along the first direction.

[0018] According to an embodiment of the present invention, the first pattern row connected by the first branch line including the parallel line portion and the protruding line portion faces one of the second pattern rows in the second direction, and in the second direction, the protruding line portion faces one of the multiple second line patterns included in the second pattern row facing the first pattern row connected by the first branch line including the parallel line portion and the protruding line portion.

[0019] According to an embodiment of the present invention, in the second direction, the convex line portion is closer to the second line pattern facing the convex line portion than the parallel line portion.

[0020] According to an embodiment of the present invention, the second line pattern facing the protruding line portion is arranged at the outermost side among the second line patterns and is farthest from the signal line.

[0021] A display device according to another embodiment for achieving the purpose of the present invention includes: a display panel; a gate driving circuit, outputting multiple gate signals to the display panel, wherein the gate driving circuit includes: a stage portion, including multiple first stages and multiple second stages respectively subordinate to the multiple first stages; a branch line portion, including first branch lines respectively electrically connected to the multiple first stages and second branch lines respectively electrically connected to the multiple second stages, wherein the first branch lines and the second branch lines extend along a first direction and are arranged along a second direction intersecting the first direction; a line pattern row, including a first pattern row electrically connected to the first branch line and a second pattern row electrically connected to the second branch line, wherein a first branch line of the first branch lines connected to one of the first pattern rows includes a parallel line portion extending along the first direction and a protruding line portion having a shape bent from the parallel line portion.

[0022] According to an embodiment of the present invention, it also includes: a common line, facing the line pattern row in the first direction and receiving a common signal, wherein one of the second branch lines includes a first line portion extending along the first direction and a second line portion extending along the second direction and arranged on a plane between the common line and the line pattern row.

[0023] According to an embodiment of the present invention, the first pattern row connected by the first branch lines including the parallel line portion and the protruding line portion faces one of the second pattern rows in the second direction, and in the second direction, the protruding line portion is closer to the second pattern row facing the first pattern row connected by the first branch lines including the parallel line portion and the protruding line portion than the parallel line portion.

[0024] According to an embodiment of the present invention, each of the line pattern rows includes a plurality of first line patterns and a plurality of second line patterns that are separated from each other and arranged alternately with each other along the first direction, and one of the plurality of second line patterns included in the second pattern row facing the first pattern row connected to the first branch line including the parallel line portion and the protruding line portion faces the protruding line portion, and the second line pattern facing the protruding line portion is arranged at the outermost side of the plurality of second line patterns.

[0025] According to an embodiment of the present invention, a branch line may be arranged between a common line electrically connected to a common electrode and a clock line pattern electrically connected to a stage. By arranging the branch line between the common line and the clock line pattern, the capacitance of the parasitic capacitor arranged between the common electrode and the clock line pattern may be reduced.

[0026] As a result, the capacitance difference between the parasitic capacitor formed between the clock line pattern and the common electrode and the parasitic capacitor formed between the clock inversion line pattern and the common electrode can be reduced. Therefore, the ripple of the common signal applied to the common electrode can be reduced, thereby improving the overall driving reliability of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0028] Figure 2a is a plan view of a display device according to an embodiment of the present invention.

[0029] Figure 2b is a cross-sectional view of a display device according to an embodiment of the present invention.

[0030] Figure 3 is a circuit diagram of a gate driving circuit including a plurality of stages according to an embodiment of the present invention.

[0031] Figure 4 The present invention is a diagram showing a Figure 3 The stages shown provide a diagram of the line portion of the gate control signal.

[0032] Figure 5 is a circuit diagram illustrating a parasitic capacitor between a common electrode and a line pattern row according to an embodiment of the present invention.

[0033] Figure 6 is a timing diagram of common signals according to an embodiment of the present invention.

[0034] Figure 7 FIG. 1 is a diagram showing another embodiment of the present invention. Figure 3 The stages shown provide a diagram of the line portion of the gate control signal.

[0035] Description of Reference Numerals

[0036] 100: Signal control circuit 200: Gate drive circuit

[0037] 300: data driving circuit DS1: first display substrate

[0038] DS2: second display substrate SRC1~SRC16: level

[0039] VL: Common Line

[0040] PG1, PG2, PG4, PG5, PG8: Line pattern

[0041] SL11~SL18、SL21~SL28:branch line

[0042] CL1~CL8: Clock line pattern

[0043] CKL1~CKL8: Clock inversion line pattern DETAILED DESCRIPTION

[0044] In this specification, when a certain component (or region, layer, part, etc.) is mentioned as being "on" another component, "connected" or "combined with" another component, it means that it can be directly arranged on another component or directly connected / combined with another component, or a third component may be arranged between them.

[0045] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, ratio, and size of the components are exaggerated for the purpose of effectively explaining the technical contents.

[0046] “And / or” includes all combinations of more than one that can be defined for the related constituents.

[0047] The terms first, second, etc. may be used to describe a variety of constituent elements, but the constituent elements should not be limited by the terms. The terms are only used to distinguish one constituent element from another constituent element. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. As long as different meanings are not clearly indicated in the context, the singular expression includes the plural expression.

[0048] Furthermore, terms such as “below”, “lower side”, “above”, and “upper side” are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0049] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. Furthermore, terms that are the same as those defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings in the context of the relevant technology, and are explicitly defined herein unless they are interpreted as ideal or excessively formal meanings.

[0050] The terms "including" or "having" should be understood as being used to specify the existence of features, numbers, steps, operations, constituent elements, parts or combinations thereof recorded in the specification, rather than excluding the existence or additional possibility of one or more other features or numbers, steps, operations, constituent elements, parts or combinations thereof.

[0051] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0052] Figure 1 is a perspective view of a display device according to an embodiment of the present invention. Figure 2a is a plan view of a display device according to an embodiment of the present invention. Figure 2b is a cross-sectional view of a display device according to an embodiment of the present invention.

[0053] Reference Figure 1 In this specification, a display device DD that can be applied to a mobile phone terminal is exemplarily illustrated. Although not illustrated, an electronic module, a camera module, a power module, etc. installed on a mainboard can be arranged together with the display device DD on a bracket / housing to constitute a mobile phone terminal. The display device DD according to the present invention can be applied to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as tablet computers, car navigation systems, game consoles, smart watches, etc.

[0054] Reference Figure 1 The display device DD can display the image IM through the display surface DD-IS. Figure 1 An icon image is illustrated as an example of an image IM. The display surface DD-IS is parallel to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DD-IS (i.e., the thickness direction of the display device DD) is indicated by the third direction DR3. In this specification, the meaning of "when viewed on a plane or on a plane" may represent the situation observed in the third direction DR3. The front (or upper surface) and back (or lower surface) of each layer or unit described below are distinguished by the third direction DR3. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be converted to another direction (for example, the opposite direction).

[0055] Furthermore, the display surface DD-IS includes a display area DD-DA for displaying an image IM and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA is an area where no image is displayed. However, this is not limited thereto, and the non-display area DD-NDA may be adjacent to one side of the display area DD-DA or may be omitted.

[0056] Reference Figure 2a The display device DD includes a display panel DP, a signal control circuit 100, a gate driving circuit 200, a data driving circuit 300 and a driving circuit board MCB.

[0057] The display panel DP includes a first display substrate DS1 and a second display substrate DS2 facing each other in the third direction DR3. Also, the display panel DP includes a display area DA for displaying an image and a non-display area NDA adjacent to the display area DA. The display area DA and the non-display area NDA of the display panel DP may correspond to Figure 1 The display device DD shown includes a display area DD-DA and a non-display area DD-NDA.

[0058] The display panel DP includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX11 to PXnm. The gate lines GL1 to GLn extend along a first direction DR1 and are arranged along a second direction DR2. The data lines DL1 to DLm extend along a second direction DR2 and are arranged along a first direction DR1. The data lines DL1 to DLm may cross the gate lines GL1 to GLn in an insulated manner. The gate lines GL1 to GLn are connected to a gate driving circuit 200, and the data lines DL1 to DLm are connected to a data driving circuit 300. The pixels PX11 to PXnm are connected to the gate lines GL1 to GLn and the data lines DL1 to DLm.

[0059] Although not shown, a plurality of gate lines GL1 ˜GLn, a plurality of data lines DL1 ˜DLm, and a plurality of pixels PX11 ˜PXnm may be arranged on the first display substrate DS1 .

[0060] The signal control circuit 100 can be mounted on the driving circuit board MCB. The signal control circuit 100 receives image data and control signals from an external graphics control unit (not shown). In response to the control signals, the signal control circuit 100 outputs gate control signals to the gate driving circuit 200 and data control signals to the data driving circuit 300.

[0061] For example, the control signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The vertical synchronization signal is a signal for distinguishing adjacent frame intervals, the horizontal synchronization signal is a signal for distinguishing horizontal intervals (i.e., a row distinction signal), and the data enable signal is at a high level only during the data output interval in order to indicate the segment where data enters.

[0062] The gate driving circuit 200 generates a gate signal based on a gate control signal received from the signal control circuit 100 through the signal line GSL. The gate control signal may include a vertical start signal that starts the operation of the gate driving circuit 200. The gate driving circuit 200 outputs the gate signal to the gate lines respectively. The gate signal may be sequentially output corresponding to each horizontal interval.

[0063] According to an embodiment of the present invention, the gate driver circuit 200 can be formed simultaneously with the pixels PX11 to PXnm through a thin film process. As an example, the gate driver circuit 200 can be mounted on the first display substrate DS1 in the form of an amorphous silicon thin film transistor gate driver circuit (ASG: Amorphous Silicon TFT Gate driver circuit) in the form of overlapping with the non-display area NDA. As another example, the gate driver circuit 200 can be mounted on the first display substrate DS1 in the form of an oxide semiconductor thin film transistor gate driver circuit (OSG: Oxide Semiconductor TFT Gate driver circuit) in the form of overlapping with the non-display area NDA.

[0064] The data driving circuit 300 receives a data control signal and an image signal from the signal control circuit 100. The data driving circuit 300 converts the image signal into a plurality of data voltages in response to the data control signal, and provides the data voltages to the data lines DL1 to DLm. For example, the data control signal may include a horizontal start signal that starts the operation of the data driving circuit 300, an inversion signal that inverts the polarity of the data voltage, and an output indication signal that determines the timing of outputting the data voltage from the data driving circuit 300.

[0065] The data driving circuit 300 may include a driving chip 310 and a flexible circuit board 320 mounted with the driving chip 310. The flexible circuit board 320 electrically connects the driving circuit board MCB with the first display substrate DS1. The plurality of driving chips 310 provide corresponding data signals to corresponding data lines among the plurality of data lines DL1-DLm.

[0066] In addition, although Figure 2aThe data driving circuit 300 of a tape carrier package (TCP) type is exemplarily illustrated, but is not limited thereto. As another example, the data driving circuit 300 may be mounted on the non-display area NDA of the first display substrate DS1 by a chip on glass (COG) method.

[0067] Reference Figure 2b , illustrates a portion of the display panel DP that overlaps with the display area DA. In particular, Figure 2b The display panel DP shown is described as a liquid crystal display panel including a liquid crystal layer LCL. However, the embodiments of the present invention are not limited thereto, and the display panel DP may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods, etc.

[0068] Specifically, the first display substrate DS1 includes a first base layer BS1, a first insulating layer 10, an intermediate insulating layer 20, a second insulating layer 30, a pixel electrode PXE and a thin film transistor TR-F. The thin film transistor TR-F includes a control electrode GEP, a first electrode IE, a second electrode OE and a semiconductor pattern AP.

[0069] A control electrode GEP is disposed on the upper surface of the first base layer BS1 and may include metals such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), or alloys thereof.

[0070] The first base layer BS1 may be a glass substrate or a plastic substrate. A first insulating layer 10 covering the control electrode GEP is arranged on the upper surface of the first base layer BS1. The first insulating layer 10 may include at least one of an inorganic substance and an organic substance. In the present embodiment, the first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc.

[0071] A semiconductor pattern AP overlapping the control electrode GEP is disposed on the first insulating layer 10. The semiconductor pattern AP may include a semiconductor layer SCL and an ohmic contact layer OCL. The semiconductor layer SCL is disposed on the first insulating layer 10, and the ohmic contact layer OCL is disposed on the semiconductor layer SCL.

[0072] The semiconductor layer SCL may include amorphous silicon or polycrystalline silicon. Also, the semiconductor layer SCL may include a metal oxide semiconductor. The ohmic contact layer OCL may include a dopant doped at a higher density than the semiconductor layer. The ohmic contact layer OCL may include two separated parts.

[0073] A first electrode IE and a second electrode OE are arranged on the semiconductor pattern AP. An intermediate insulating layer 20 covering the first electrode IE and the second electrode OE is arranged on the first insulating layer 10. The intermediate insulating layer 20 may include at least one of an inorganic substance and an organic substance. In the present embodiment, the intermediate insulating layer 20 may be an inorganic layer. The intermediate insulating layer 20 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc.

[0074] A pixel electrode PXE is arranged on the second insulating layer 30. The pixel electrode PXE is connected to the second electrode OE through a pixel contact hole TH that penetrates the intermediate insulating layer 20 and the second insulating layer 30. The pixel contact hole TH includes a first through hole TH1 and a second through hole TH2. The first through hole TH1 is defined in the intermediate insulating layer 20 and exposes the second electrode OE. The second through hole TH2 is defined in the second insulating layer 30 and corresponds to the first through hole TH1.

[0075] The second display substrate DS2 includes a second base layer BS2, a third insulating layer 40, and a common electrode CE. The second base layer BS2 may be a glass substrate or a plastic substrate that is substantially the same material as the first base layer BS1. A third insulating layer 40 may be disposed on the lower surface of the second base layer BS2.

[0076] A common electrode CE to which a common voltage is applied is disposed on a lower surface of the third insulating layer 40. The common voltage has a value different from that of the pixel voltage.

[0077] The liquid crystal layer LCL may be disposed between the first display substrate DS1 and the second display substrate DS2. Although not shown, the first display substrate DS1 may further include a first alignment film, and the second display substrate DS2 may further include a second alignment film. The liquid crystal layer LCL may be neatly arranged by the first alignment film and the second alignment film.

[0078] in addition, Figure 2bThe cross section of the pixel PX shown is only an example. The first display substrate DS1 and the second display substrate DS2 may be reversed in the third direction DR3. Furthermore, although a liquid crystal display panel in a vertical alignment (VA) mode is exemplarily described, a liquid crystal display panel in an in-plane switching (IPS) mode, a fringe-field switching (FFS) mode, or a plane to line switching (PLS) mode may be applied in one embodiment of the present invention. For example, the common electrode CE included in the second display substrate DS2 may be included in the first display substrate DS1 via the IPS mode or the PLS mode.

[0079] Figure 3 is a circuit diagram of a gate driving circuit including a plurality of stages according to an embodiment of the present invention.

[0080] Reference Figure 3 The gate driving circuit 200 may include a stage section. The stage section may include a plurality of driving stages and a plurality of dummy stages connected to each other in a dependent manner. The driving stages may be connected to Figure 2a The gate lines GL1 ˜GLn are shown. A plurality of driving stages can output gate signals to the gate lines GL1 ˜GLn respectively.

[0081] Below, through Figure 3 A plurality of stages SRC1 to SRC16 corresponding to the driving stage are exemplarily shown. The structures of the plurality of stages SRC1 to SRC16 may be repeatedly arranged according to the number of gate lines GL1 to GLn. In addition, a dummy stage not shown may also be provided with substantially the same structure as the driving stage.

[0082] Specifically, the stages SRC1 to SRC16 may respectively and sequentially output the first gate signal G1 to the sixteenth gate signal G16. For example, the nth stage may output the nth gate signal to the nth gate line. Here, n is defined as a positive integer. Each of the stages SRC1 to SRC16 includes a first input terminal IN1, a second input terminal IN2, a clock terminal CNj (here, j is a positive integer), a first discharge terminal V1, a second discharge terminal V2, an output terminal OUT, and a carry terminal CR.

[0083] The carry terminal CR of each of the stages SRC1 to SRC16 is electrically connected to the first input terminal IN1 of the subsequent stage. The i-th stage can output the i-th carry signal through the carry terminal CR. Here, i is defined as a positive integer. The first input terminal IN1 of the first stage SRC1 receives the vertical start signal STV output from the signal control circuit 100 to start the drive of the gate drive circuit 200, instead of the carry signal of the previous stage. After the first stage SRC1, the first input terminal IN1 of each of the stages SRC2 to SRC16 receives the carry signal of the previous stage. The first input terminal IN1 of the i-th stage is electrically connected to the carry terminal CR of the i-1-th stage. In addition, this is only an example, and the first input terminal IN1 of the i-th stage can also be electrically connected to the carry terminal of the previous stage, such as the carry terminal of the i-1-th stage, the i-2-th stage, or the i-3-th stage.

[0084] The second input terminal IN2 of the i-th stage is electrically connected to the carry terminal CR of the i+8-th stage, thereby receiving the carry signal of the i+8-th stage. For example, the second input terminal IN2 of the first stage SRC1 receives the carry signal of the ninth stage SRC9, and the second input terminal IN2 of the second stage SRC2 receives the carry signal of the eighth stage (not shown).

[0085] However, it is not limited thereto, and the second input terminal IN2 of the i-th stage may be electrically connected to the carry terminal CR of the i+k-th stage. Here, k may be a positive integer.

[0086] In addition, at least one of the driver stages can receive a carry signal through a dummy stage. That is, the second input terminal IN2 of at least one driver stage can receive a carry signal output from the dummy stage. The dummy stage is sequentially connected to the rear end of the last driver stage in the driver stage. However, the position and number of the dummy stage can be changed according to the design intention of those skilled in the art.

[0087] According to the present invention, the plurality of stages SRC1 to SRC16 may be divided into first stages SRC1 to SRC8 and second stages SRC9 to SRC16. The first stages SRC1 to SRC8 and the second stages SRC9 to SRC16 may be connected to each other in a dependent manner along a first direction DR1. For example, the second stages SRC9 to SRC16 may be continuously arranged in the first stages SRC1 to SRC8.

[0088] The clock terminals CN1 to CN8 of the first stages SRC1 to SRC8 may receive the first to eighth clock signals CK1 to CK8 , respectively. The clock terminals CN9 to CN16 of the second stages SRC9 to SRC16 may receive the first to eighth clock inversion signals CKB1 to CKB8 , respectively.

[0089] According to the present invention, the first stages SRC1 to SRC8 can sequentially output the first to eighth gate signals G1 to G8 through the output terminal OUT in response to the first to eighth clock signals CK1 to CK8. The second stages SRC9 to SRC16 can sequentially output the ninth to sixteenth gate signals G9 to G16 through the output terminal OUT in response to the first to eighth clock inversion signals CKB1 to CKB8. The operation of the first stages SRC1 to SRC8 and the second stages SRC9 to SRC16 can be repeated.

[0090] The phases of the first clock signal CK1 to the eighth clock signal CK8 and the first clock inversion signal CKB1 to the eighth clock inversion signal CKB8 may be opposite to each other. As an example, the phases of the first clock signal CK1 and the first clock inversion signal CKB1 may be opposite to each other. The clock terminal CN1 of the first stage SRC1 among the first stages SRC1 to SRC8 may receive the first clock signal CK1 of a high voltage. In this case, the clock terminal CN9 of the ninth stage SRC9 among the second stages SRC9 to SRC16 receives the first clock inversion signal CKB1 of a low voltage opposite to the phase of the high voltage of the first clock signal CK1. On the contrary, in the case where the clock terminal CN1 of the first stage SRC1 receives the first clock signal CK1 of a low voltage, the clock terminal CN9 of the ninth stage SRC9 is provided with the first clock inversion signal CKB1 of a high voltage opposite to the phase of the low voltage of the first clock signal CK1.

[0091] As another example, the phases of the eighth clock signal CK8 and the eighth clock inversion signal CKB8 may be opposite to each other. The clock terminal CN8 of the eighth stage SRC8 among the first stages SRC1 to SRC8 receives the eighth clock signal CK8 of high voltage, and the clock terminal CN16 of the sixteenth stage SRC16 among the second stages SRC9 to SRC16 receives the eighth clock inversion signal CKB8 of low voltage. On the contrary, when the clock terminal CN8 of the eighth stage SRC8 receives the eighth clock signal CK8 of low voltage, the clock terminal CN16 of the sixteenth stage SRC16 is provided with the eighth clock inversion signal CKB8 of high voltage.

[0092] Furthermore, a first discharge voltage VS1 may be output to a first discharge terminal V1 of each of the stages SRC1 to SRC16, and a second discharge voltage VS2 may be output to a second discharge terminal V2 of each of the stages SRC1 to SRC16. For example, the first discharge voltage VS1 and the second discharge voltage VS2 may be provided at a ground voltage or a level lower than the ground voltage.

[0093] As an example, the voltage level of the first discharge voltage VS1 may be higher than the voltage level of the second discharge voltage VS2. The first discharge voltage VS1 may be set to approximately -10 V to -5 V, and the second discharge voltage VS2 may be set to approximately -16 V to -10 V. As another example, the first discharge voltage VS1 and the second discharge voltage VS2 may have substantially the same voltage level.

[0094] Figure 4 The present invention is a diagram showing a Figure 3 The stages shown provide a diagram of the line portion of the gate control signal. Figure 5 is a circuit diagram illustrating a parasitic capacitor between a common electrode and a line pattern row according to an embodiment of the present invention. Figure 6 is a timing diagram of common signals according to an embodiment of the present invention.

[0095] Reference Figure 4 ,Apart from Figure 3 In addition to the stage portion shown, the gate driving circuit 200 may further include a line portion. According to the present invention, the line portion may include a line pattern portion and a branch line portion.

[0096] The line pattern portion may include a plurality of line pattern rows extending in the first direction DR1 and arranged in the second direction DR2. The branch line portion includes first branch lines SL11 to SL18 electrically connected to the clock terminals CN of the first stages SRC1 to SRC8, respectively, and second branch lines SL21 to SL28 electrically connected to the clock terminals CN of the second stages SRC9 to SRC16, respectively. The first branch lines SL11 to SL18 and the second branch lines SL21 to SL28 may have a shape extending in the first direction DR1 and arranged in the second direction DR2.

[0097] According to the present invention, the line pattern rows may include four first pattern rows connected to the first branch lines SL11 to SL18 and four second pattern rows connected to the second branch lines SL21 to SL28. Figure 4 The diagram shows three first pattern rows PG1, PG2, PG4 and one second pattern row PG5 in the first pattern rows. Figure 4 The diagram shows first branch lines SL11, SL12, SL13, SL14, SL17, and SL18 connected to the three first pattern rows PG1, GP2, and GP4 among the first branch lines SL11~SL18, and shows second branch lines SL21 and SL22 connected to a second pattern row PG5 among the second branch lines SL21~SL28.

[0098] Each of the first pattern rows may include first to eighth clock line patterns CL1 to CL8 and first to eighth clock inversion line patterns CKL1 to CKL8 that are spaced apart from each other and alternately arranged along the first direction DR1. For example, the first clock line pattern CL1, the first clock inversion line pattern CKL1, the second clock line pattern CL2, and the second clock inversion line pattern CKL2 may be sequentially arranged along the first direction DR1. In particular, in the first direction DR1, the outermost two line patterns of each line pattern row may be the first clock line pattern CL1 and the eighth clock inversion line pattern CKL8.

[0099] According to the present invention, two branch lines among the plurality of branch lines can be electrically connected to a corresponding one of the line pattern rows. Specifically, each of the first pattern rows is electrically connected to two corresponding first branch lines among the first branch lines SL11 to SL18. The two first branch lines can be electrically connected to two clock line patterns among the first clock line pattern CL1 to the eighth clock line pattern CL8 included in each of the first pattern rows, respectively.

[0100] As an example, two first branch lines SL11 and SL12 of the first branch lines SL11 to SL18 may have a structure respectively connected to the first clock line pattern CL1 and the second clock line pattern CL2 included in the first pattern row PG1. In fact, the first clock line pattern CL1 and one first branch line SL11 may be formed into an integral shape, and the second clock line pattern CL2 and another first branch line SL12 may be formed into an integral shape. That is, the branch lines and the clock line patterns according to the present invention may be formed using the same material.

[0101] As another example, two second branch lines SL21 and SL22 of the second branch lines SL21-SL28 can be electrically connected to the first clock inversion line pattern CKL1 and the second clock inversion line pattern CKL2 included in the second pattern row PG5, respectively. Similarly, the branch lines and the clock inversion line patterns according to the present invention can be formed of the same material.

[0102] According to the present invention, the first to eighth clock line patterns CL1 to CL8 and the first to eighth clock inversion line patterns CKL1 to CKL8 may have the same Figure 2b The first electrode IE and the second electrode OE of the thin film transistor TR-F shown are made of the same material and are formed through a single process.

[0103] One of the first to eighth clock line patterns CL1 to CL8 included in each of the first pattern rows may receive a clock line pattern through Figure 3One of the first clock signals CK1 to the eighth clock signal CK8 shown. For example, the first clock line pattern CL1 among the first clock line pattern CL1 to the eighth clock line pattern CL8 included in the first pattern row PG1 can receive the first clock signal CK1. The first clock signal CK1 received at the first clock line pattern CL1 can be transferred to the clock terminal CN1 of the first stage (for example, the first stage SRC1) through the first branch line SL11.

[0104] One of the first to eighth clock inversion line patterns CKL1 to CKL8 included in each of the second pattern rows may receive a clock inversion line pattern through Figure 3 One of the first clock inversion signal CKB1 to the eighth clock inversion signal CKB8 shown. For example, the first clock inversion line pattern CKL1 among the first clock inversion line pattern CKL1 to the eighth clock inversion line pattern CKL8 included in the second pattern row PG5 can receive the first clock inversion signal CKB1. The first clock inversion signal CKB1 received at the first clock inversion line pattern CKL1 can be transferred to the clock terminal CN9 of the second stage (for example, the ninth stage SRC9) through the second branch line SL21.

[0105] Figure 2b The display panel DP shown may further include a common line VL arranged adjacent to the line pattern row of the gate driving circuit 200. In this specification, the common line VL may be described as a signal line. The common line VL may be electrically connected to Figure 2b The common electrode CE shown in FIG. 1 is connected to the common electrode CE and transmits a common signal to the common electrode CE. According to the present invention, the common line VL can be arranged at the same Figure 4 The branch lines, clock line patterns, and clock inversion line patterns are on different layers. Figure 2b The control electrode GEP of the thin film transistor TR-F shown is made of the same material and is formed through a single process.

[0106] Specifically, the common line VL has a structure extending in the second direction DR2 and faces the line pattern rows in the first direction DR1 on a plane. In particular, the common line VL may be most adjacent to the first clock line pattern CL1 among the line patterns included in each of the line pattern rows.

[0107] In addition, since the first clock line pattern CL1 is disposed adjacent to the common line VL, the capacitance of the parasitic capacitor formed between the first clock line pattern CL1 and the common line VL may be large, which may cause ripples in the common signal VC supplied to the common electrode CE.

[0108] Specifically, refer to Figure 5, showing a structure in which two clock line patterns CL1, CL2 and two clock inverted line patterns CKL1, CKL2 are alternately arranged. According to the present invention, the clock line patterns CL1, CL2 and the clock inverted line patterns CKL1, CKL2 may be included in the first display substrate DS1 (refer to Figure 2b In this case, each of the clock line patterns CL1, CL2 and the clock inversion line patterns CKL1, CKL2 may be connected to the second display substrate DS2 (refer to Figure 2b ) forms a parasitic capacitor.

[0109] For example, a first parasitic capacitor CP1 is formed between the first clock line pattern CL1 and the common electrode CE, a second parasitic capacitor CP2 is formed between the second clock line pattern CL2 and the common electrode CE, a third parasitic capacitor CP3 is formed between the first clock reverse line pattern CKL1 and the common electrode CE, and a fourth parasitic capacitor CP4 is formed between the second clock reverse line pattern CKL2 and the common electrode CE.

[0110] Furthermore, a parasitic capacitor CPa is formed between the first clock line pattern CL1 and the first clock inversion line pattern CKL1, a parasitic capacitor CPb is formed between the first clock inversion line pattern CKL1 and the second clock line pattern CL2, and a parasitic capacitor CPc is formed between the second clock line pattern CL2 and the second clock inversion line pattern CKL2. In practice, the parasitic capacitors CPa, CPb, CPc may have substantially similar capacitances.

[0111] According to an embodiment of the present invention, one second branch line SL21 of the second branch lines SL21 ˜ SL28 may be arranged between the common line VL and the first clock line pattern CL1 on a plane.

[0112] Specifically, refer again to Figure 4 , one of the second branch lines SL21 to SL28 may be arranged between the common line VL and the first clock line pattern CL1 on a plane. The second branch line SL21 may be connected to the first clock inversion line pattern CKL1 that is closest to the common line VL among the first to eighth clock inversion line patterns CKL1 to CKL8 included in the second pattern row PG5. In addition, the first clock line pattern CL1 may be arranged between the first clock inversion line pattern CKL1 and the common line VL.

[0113] In particular, the second branch line SL21 may overlap between the second pattern row and the common line VL. The remaining second branch lines SL22 ˜ SL28 among the second branch lines SL21 ˜ SL28 may not overlap between the pattern row and the common line VL.

[0114] According to an embodiment of the present invention, the second branch line SL21 includes a first line portion S1 extending along the first direction DR1 and a second line portion S2 extending along the second direction DR2 and arranged between the common line VL and the first clock line pattern CL1. In addition, the second branch line SL21 may further include a third line portion S3 arranged between the first line portion S1 and the first clock inversion line pattern CKL1. The length of the third line portion S3 may be shorter than that of the second line portion S2, and the third line portion S3 extends along the second direction DR2. The second branch line SL21 may be most adjacent to the last first branch line SL18 among the first branch lines SL11 to SL18.

[0115] In particular, the second line portion S2 extending in the second direction DR2 may face the first clock line pattern CL1 included in at least one first pattern row and the first clock line pattern CL1 included in at least one second pattern row in the first direction DR1.

[0116] like Figure 5 As shown, on a plane, the second line portion S2 may be disposed between the first clock line pattern CL1 and the common line VL. The second line portion S2 and the first clock line pattern CL1 may have the same material and be formed through a single process, and the common line VL is disposed on a different layer therefrom.

[0117] In this case, the parasitic capacitor between the first clock line pattern CL1 and the common line VL can be divided into a parasitic capacitor CPsa formed between the second line portion S2 and the first clock line pattern CL1 and a parasitic capacitor CPsb formed between the second line portion S2 and the common line VL. As a result, the first parasitic capacitor CP1 formed between the first clock line pattern CL1 and the common electrode CE can be reduced.

[0118] According to the above, the capacitance difference between the first parasitic capacitor CP1 formed between the first clock line pattern CL1 and the common electrode CE and the third parasitic capacitor CP3 formed between the first clock inversion line pattern CKL1 and the common electrode CE may be reduced.

[0119] like Figure 6 As shown, the phases of the first clock signal CK1 applied to the first clock line pattern CL1 and the first clock inversion signal CKB1 applied to the first clock inversion line pattern CKL1 may be opposite to each other. In particular, as described above, since the difference between the capacitance of the first parasitic capacitor CP1 and the capacitance of the third parasitic capacitor CP3 is reduced, the ripple RP of the common signal VC applied to the common electrode CE may be reduced.

[0120] In other words, since the difference between parasitic capacitance between the first clock signal CK1 applied to the first clock line pattern CL1 and the common signal VC and parasitic capacitance between the first clock reverse signal CKB1 and the common signal VC is reduced, ripples occurring in the common signal VC may be reduced.

[0121] Figure 7 FIG. 1 is a diagram showing another embodiment of the present invention. Figure 3 The stages shown provide a diagram of the line portion of the gate control signal.

[0122] Reference Figure 7 The two first branch lines SL11 and SL12 may be connected to the first pattern row PG1 of the first pattern rows. The first clock line pattern CL1 included in the first pattern row PG1 is connected to one first branch line SL11, and the second clock line pattern CL2 is connected to another first branch line SL12.

[0123] The first pattern row PG1 may face one of the second pattern rows PG8 in the second direction DR2. In particular, the first branch line SL11 includes a parallel line portion SL11a extending in the first direction DR1 and a convex line portion SL11b having a shape bent from the parallel line portion SL11a in the second direction DR2.

[0124] According to an embodiment of the present invention, the protruding line portion SL11b of the first branch line SL11 may face the eighth clock inversion line pattern CKL8 farthest from the common line VL among the first to eighth clock inversion line patterns CKL1 to CKL8 included in one second pattern row PG8. In other words, the protruding line portion SL11b of the first branch line SL11 may be closer to the eighth clock inversion line pattern CKL8 than the parallel line portion SL11a of the first branch line SL11. As a result, the distance between the first branch line SL11 and the eighth clock inversion line pattern CKL8 may be reduced by the protruding line portion SL11b, thereby increasing the load capacitance of the eighth clock inversion line pattern CKL8.

[0125] That is, since the protruding line portion SL11 b of the first branch line SL11 has a structure that is closer to the eighth clock inversion line pattern CKL8 than the parallel line portion SL11 a , the load capacitance of the eighth clock inversion line pattern CKL8 may increase.

[0126] In addition, although through Figure 7 The shape of the protruding line portion SL11 b protruding from the parallel line portion SL11 a of the first branch line SL11 toward the eighth clock inversion line pattern CKL8 is illustrated, but the shape of the protruding line portion SL11 b may be variously modified.

[0127] Embodiments are disclosed in the drawings and the description described above. Although specific terms are used herein, they are used only for the purpose of illustrating the present invention, and are not used to define the meaning or limit the scope of the present invention as recorded in the claims. Therefore, anyone with ordinary knowledge in the technical field can understand that various modifications can be made to the present invention and other equivalent embodiments can be implemented. Therefore, the true technical protection scope of the present invention should be determined according to the technical ideas of the recorded claims.

Claims

1. A display device, comprising: Display panel; as well as A gate driving circuit outputs a plurality of gate signals to the display panel, Wherein, the gate driving circuit comprises: a stage portion, comprising a plurality of first stages and a plurality of second stages respectively subordinate to the plurality of first stages; a branch line portion, comprising first branch lines electrically connected to the plurality of first levels, respectively, and second branch lines electrically connected to the plurality of second levels, respectively, wherein the first branch lines and the second branch lines extend along a first direction and are arranged along a second direction intersecting the first direction; Line pattern rows, including a first pattern row electrically connected to the first branch line and a second pattern row electrically connected to the second branch line; and a signal line facing the line pattern row in the first direction, One of the second branch lines includes a first line portion extending along the first direction and a second line portion extending along the second direction and arranged between the signal line and the line pattern row on a plane.

2. The display device according to claim 1, wherein: Each of the line pattern rows includes a plurality of first line patterns and a plurality of second line patterns that are alternately arranged with each other along the first direction.

3. The display device according to claim 2, wherein: Each of the first pattern rows is electrically connected to corresponding two first branch lines of the first branch lines, Each of the second pattern rows is electrically connected to corresponding two of the second branch lines.

4. The display device according to claim 3, wherein: The two first branch lines are respectively connected to corresponding two first line patterns among the plurality of first line patterns, The two second branch lines are respectively connected to corresponding two second line patterns among the plurality of second line patterns.

5. The display device according to claim 2, wherein: The plurality of first line patterns respectively receive a clock signal, and the plurality of second line patterns respectively receive a clock inversion signal having a phase opposite to that of the clock signal.

6. The display device according to claim 2, wherein: The second branch line including the first line portion and the second line portion has a structure connected to a second line pattern that is most adjacent to the signal line among the plurality of second line patterns.

7. The display device according to claim 6, wherein: One of the plurality of first line patterns is arranged between the second line pattern most adjacent to the signal line and the second line portion.

8. The display device according to claim 7, wherein: the first line pattern disposed between the second line pattern most adjacent to the signal line and the second line portion directly faces the signal line in the first direction and receives a clock signal, The second line pattern most adjacent to the signal line receives a clock inversion signal having a phase opposite to that of the clock signal.

9. The display device according to claim 1, wherein: The second line portion overlaps between the second pattern row and the signal line.

10. The display device according to claim 1, wherein: The second branch line including the first line portion and the second line portion and the signal line are arranged on different layers from each other.

11. The display device according to claim 1, wherein: Each of the remaining second branch lines of the second branch lines does not overlap between the signal line and the line pattern row on the plane.

12. The display device according to claim 1, wherein: A first branch line connected to one first pattern row among the first branch lines includes a parallel line portion extending along the first direction and a protruding line portion having a shape bent from the parallel line portion.

13. The display device according to claim 12, wherein: Each of the line pattern rows includes a plurality of first line patterns and a plurality of second line patterns that are spaced apart from each other and arranged alternately with each other along the first direction.

14. The display device according to claim 13, wherein: The first pattern row connected by the first branch lines including the parallel line portion and the protruding line portion faces one of the second pattern rows in the second direction, In the second direction, the convex line portion faces one of the plurality of second line patterns included in the second pattern row facing the first pattern row to which the first branch lines including the parallel line portion and the convex line portion are connected.

15. The display device according to claim 14, characterized in that: In the second direction, the convex line portion is adjacent to the second line pattern facing the convex line portion more closely than the parallel line portion.

16. The display device according to claim 14, characterized in that: The second line pattern facing the protruding line portion is arranged at the outermost side among the second line patterns and is farthest from the signal line.

17. A display device, comprising: Display panel; as well as A gate driving circuit outputs a plurality of gate signals to the display panel, Wherein, the gate driving circuit comprises: a stage portion, comprising a plurality of first stages and a plurality of second stages respectively subordinate to the plurality of first stages; a branch line portion, comprising first branch lines electrically connected to the plurality of first stages, respectively, and second branch lines electrically connected to the plurality of second stages, respectively, wherein the first branch lines and the second branch lines extend along a first direction and are arranged along a second direction intersecting the first direction; and The line pattern rows include a first pattern row electrically connected to the first branch line and a second pattern row electrically connected to the second branch line. Among the first branch lines, the first branch lines connected to one first pattern row include a parallel line portion extending along the first direction and a protruding line portion having a shape bent from the parallel line portion.

18. The display device according to claim 17, wherein: Also includes: a common line facing the line pattern row in the first direction and receiving a common signal, One of the second branch lines includes a first line portion extending along the first direction and a second line portion extending along the second direction and arranged between the common line and the line pattern row on a plane.

19. The display device according to claim 17, characterized in that: The first pattern row connected by the first branch lines including the parallel line portion and the protruding line portion faces one of the second pattern rows in the second direction, In the second direction, the convex line portion is closer to the second pattern row facing the first pattern row to which the first branch lines including the parallel line portion and the convex line portion are connected than the parallel line portion.

20. The display device according to claim 19, wherein: Each of the line pattern rows includes a plurality of first line patterns and a plurality of second line patterns that are spaced apart from each other and alternately arranged with each other along the first direction, One of the plurality of second line patterns included in the second pattern row facing the first pattern row connected to the first branch line including the parallel line portion and the protruding line portion faces the protruding line portion, The second line pattern facing the convex line portion is arranged at the outermost side of the plurality of second line patterns.

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