Storage device and manufacturing method thereof, and electronic device

Abstract

The present disclosure relates to a memory device and a manufacturing method thereof, and an electronic device. The memory device includes: a memory cell, which is arranged on a substrate, and the memory cell is arranged at intervals in a direction perpendicular to the substrate. The memory cell includes a gate transistor and a resistive switching device; the gate transistor includes a horizontal semiconductor layer extending in a first direction parallel to the substrate, and the resistive switching device includes a horizontal semiconductor layer and a resistive switching layer and an electrode layer arranged in sequence away from the horizontal semiconductor layer in the first direction; a source line extends in a second direction parallel to the substrate, and is arranged at intervals in a third direction perpendicular to the substrate. In the first direction, the source line is arranged on a side of the horizontal semiconductor layer away from the resistive switching layer; a word line is arranged in the third direction to intersect with the horizontal semiconductor layer of the gate transistor arranged in the third direction; and a bit line is arranged in the third direction to connect with the electrode layer of the resistive switching device arranged in the third direction. The memory cell is integrated in the third direction perpendicular to the substrate, so as to improve the integration density of the memory device.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a storage device and a manufacturing method thereof, and an electronic device. Background Art

[0002] According to Moore's Law, the performance of semiconductor memory doubles with every doubling of semiconductor devices in semiconductor memory. In order to improve the performance of semiconductor memory, the feature size of semiconductor devices continues to shrink and the integration continues to increase. However, as semiconductor process nodes continue to shrink, the size of semiconductor memory faces challenges, the manufacturing cost and complexity of semiconductor memory increase, and the performance improvement of semiconductor memory slows down, making it difficult to achieve higher storage density.

[0003] In the field of integrated circuits, the use of the third dimension to integrate semiconductor devices provides a new direction for the continuation of Moore's Law. Summary of the invention

[0004] Based on this, it is necessary to provide a storage device and a manufacturing method thereof, and an electronic device to address the problems in the prior art.

[0005] In order to achieve the above objectives, in a first aspect, the present disclosure provides a storage device, including:

[0006] A memory cell is provided on a substrate, the memory cells are arranged at intervals in a direction perpendicular to the substrate, and the memory cell comprises a gating transistor and a resistive switching device; the gating transistor comprises a horizontal semiconductor layer extending in a first direction parallel to the substrate, and the resistive switching device comprises the horizontal semiconductor layer and a resistive switching layer and an electrode layer sequentially arranged away from the horizontal semiconductor layer in the first direction;

[0007] Source lines extend along a second direction parallel to the substrate, are arranged at intervals along a third direction perpendicular to the substrate, the first direction intersects the second direction, and along the first direction, the source lines are arranged on a side of the horizontal semiconductor layer away from the resistive switching layer;

[0008] A word line is arranged along the third direction, and the word line intersects the horizontal semiconductor layer of the gate transistor arranged along the third direction;

[0009] The bit line is arranged along the third direction, and the bit line is connected to the electrode layer of the resistive switching device arranged along the third direction.

[0010] Optionally, the memory cells arranged along the third direction and the resistive switching layers of the resistive switching devices are connected in sequence.

[0011] Optionally, the resistive layer surrounds a circumference of the electrode layer.

[0012] Optionally, the gate transistor comprises:

[0013] A first source-drain electrode, a semiconductor channel, and a second source-drain electrode, wherein the first source-drain electrode, the semiconductor channel, and the second source-drain electrode are sequentially arranged in the horizontal semiconductor layer in a direction away from the source line;

[0014] A gate dielectric layer is disposed between the word line and the semiconductor channel, and along a plane parallel to the second direction, the gate dielectric layer surrounds the semiconductor channel;

[0015] A gate is disposed along a plane parallel to the second direction, the gate surrounds the gate dielectric layer, and the gate is connected to the word line.

[0016] Optionally, the storage units are arranged along the first direction and the second direction;

[0017] Along the first direction, one side of the bit line is connected to a first storage unit, and the other side is connected to a second storage unit, and the first storage unit and the second storage unit are mirror-symmetric with respect to the bit line.

[0018] Optionally, along the first direction, the first storage unit and the second storage unit located on both sides of the source line share the same source line.

[0019] In a second aspect, the present disclosure provides a method for manufacturing a memory device, comprising:

[0020] providing a substrate on which alternating insulating layers and semiconductor material layers are formed;

[0021] The insulating layer and the semiconductor material layer are patterned alternately, the semiconductor material layer forms a horizontal semiconductor layer and a source line, the horizontal semiconductor layer extends along a first direction, the source line extends along a second direction, the first direction and the second direction are parallel to the substrate, the first direction intersects with the second direction, along the first direction, at least one end of the horizontal semiconductor layer is connected to the source line, and the horizontal semiconductor layer includes a first source and drain electrode, a semiconductor channel, and a second source and drain electrode arranged in sequence away from the source line;

[0022] removing a portion of the insulating layer to expose the semiconductor channel;

[0023] forming a gate dielectric layer to cover the semiconductor channel;

[0024] forming a gate and a word line, wherein the gate covers the gate dielectric layer and forms a gate transistor together with the horizontal semiconductor layer, and the word line is vertically arranged on the substrate along a third direction, intersects with the semiconductor channel of the gate transistor arranged along the third direction, and is connected to the gate of the gate transistor;

[0025] A resistive switching layer and an electrode layer are sequentially formed on a side of the horizontal semiconductor layer away from the source line, wherein the resistive switching layer, the electrode layer and the horizontal semiconductor layer together form a resistive switching device, and the selection transistor and the resistive switching device form a storage unit;

[0026] A bit line extending along the third direction is formed, and the bit line is connected to the electrode layer of the resistive switching devices arranged along the third direction.

[0027] Optionally, a resistive switching layer and an electrode layer are sequentially formed on a side of the horizontal semiconductor layer away from the source line, including:

[0028] A first trench is formed on a side of the second source and drain of the horizontal semiconductor layer away from the source line, wherein the first trench is arranged on the substrate along the third direction;

[0029] forming the resistive switching layer, wherein the resistive switching layer covers the sidewall of the first trench;

[0030] The electrode layer is formed, and the electrode layer covers the inner sidewall of the resistive layer and fills the unfilled area of ​​the first trench.

[0031] Optionally, after forming the horizontal semiconductor layer and the source line, two ends of the horizontal semiconductor layer are respectively connected to the source line along the first direction; the manufacturing method includes:

[0032] Etching the alternating insulating layers and the horizontal semiconductor layers to form first grooves penetrating the alternating insulating layers and the horizontal semiconductor layers, wherein the first grooves divide the horizontal semiconductor layers into first sections and second sections spaced apart along the first direction;

[0033] The first segment is used to form a first memory cell, and the second segment is used to form a second memory cell. The first memory cell and the second memory cell are mirror-symmetric with respect to the bit line.

[0034] In a third aspect, the present disclosure provides an electronic device, comprising the memory device as described in the first aspect, or comprising a memory device manufactured by the method for manufacturing the memory device as described in the second aspect.

[0035] The memory device and its manufacturing method and electronic device disclosed in the present invention have a horizontal semiconductor layer of a gate transistor extending along a first direction. The horizontal arrangement of the gate transistor can reduce the occupied area of ​​the gate transistor and reduce the characteristic size of the gate transistor. The resistive switching device includes a horizontal semiconductor layer, a resistive switching layer and an electrode layer arranged in sequence along the first direction. The gate transistor and the resistive switching device share the horizontal semiconductor layer, which can reduce the characteristic size of the memory cell and improve the integration density of the memory cell. At the same time, a source line extends along a second direction and is connected to a side of the horizontal semiconductor layer away from the resistive switching layer. A word line extends along a third direction and intersects with the horizontal semiconductor layer of the gate transistor. A bit line extends along the third direction and is connected to the electrode layer of the resistive switching device arranged along the third direction. The memory cell can be integrated in the third direction perpendicular to the substrate, thereby improving the integration density of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A top view of a storage device provided in some embodiments of the present application;

[0038] Figure 2 For along Figure 1 Schematic diagram of the cross section along line AA;

[0039] Figure 3 For along Figure 1 Schematic diagram of the cross section of the BB line;

[0040] Figure 4 A top view of a storage device provided in some other embodiments of the present application;

[0041] Figure 5 For along Figure 4 Schematic diagram of the cross section along line AA;

[0042] Figure 6 For along Figure 4 Schematic diagram of the cross section of the BB line;

[0043] Figure 7 A process flow chart of a method for manufacturing a memory device provided in some embodiments of the present application;

[0044] Figure 8 A top view after forming alternating insulating layers and semiconductor material layers on a substrate provided in some embodiments of the present application;

[0045] Fig. 9 For along Figure 8 Schematic diagram of the cross section along line AA;

[0046] Fig.10 For along Figure 8 Schematic diagram of the cross section of the BB line;

[0047] Fig.11 A top view of patterned alternating insulating layers and semiconductor material layers provided in some embodiments of the present application;

[0048] Fig.12 For along Fig.11 Schematic diagram of the cross section along line AA;

[0049] Fig.13 For along Fig.11 Schematic diagram of the cross section of the BB line;

[0050] Fig.14 A top view after forming a first dielectric layer provided in some embodiments of the present application;

[0051] Fig.15 For along Fig.14 Schematic diagram of the cross section along line AA;

[0052] Fig.16 For along Fig.14 Schematic diagram of the cross section of the BB line;

[0053] Fig.17 A top view after the semiconductor channel is exposed provided in some embodiments of the present application;

[0054] Fig.18 For along Fig.17 Schematic diagram of the cross section along line AA;

[0055] Fig.19 For along Fig.17 Schematic diagram of the cross section of the BB line;

[0056] Fig. 20 A top view after forming a gate transistor and a word line provided in some embodiments of the present application;

[0057] Fig.21 For along Fig. 20 Schematic diagram of the cross section along line AA;

[0058] Fig. 22 For along Fig. 20 Schematic diagram of the cross section of the BB line;

[0059] Fig.23 A top view after forming a first groove provided in some embodiments of the present application;

[0060] Fig.24 For along Fig.23 Schematic diagram of the cross section along line AA;

[0061] Fig.25 For along Fig.23 Schematic diagram of the cross section of the BB line;

[0062] Fig.26 A top view after forming a resistive switching device and a bit line provided in some embodiments of the present application;

[0063] Fig. 27 For along Fig.26 Schematic diagram of the cross section along line AA;

[0064] Fig.28 For along Fig.26 Schematic diagram of the cross section along line BB.

[0065] Description of reference numerals:

[0066] 100, memory device; 10, substrate; 20, memory cell; 21, selection transistor; 211, first source and drain; 212, semiconductor channel; 213, second source and drain; 214, gate dielectric layer; 215, gate; 22, resistive device; 221, resistive layer; 222, electrode layer; 30, source line; 40, word line; 50, bit line; 61, insulating layer; 62, semiconductor material layer; 63, horizontal semiconductor layer; 64, etch stop layer; 65, first dielectric layer; 101, first trench; 120, first memory cell; 220, second memory cell. DETAILED DESCRIPTION

[0067] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0069] Resistive random access memory (RRAM) has a simple structure, flexible design, small feature size, fast read and write speed, and is compatible with complementary metal-oxide-semiconductor (CMOS) process. It is considered to be one of the next-generation storage technologies with the greatest integration potential.

[0070] In the related art, the storage array based on RRAM storage cells adopts an architecture integrating a gate transistor and a resistor (One Transistor One Resistor, 1T1R) to solve the problem of RRAM storage cell leakage current. However, in the 1T1R architecture of the related art, the characteristic size of the gate transistor is 6F. 2 , which limits the scalability of RRAM memory cells and makes it difficult to further reduce the feature size of RRAM memory cells. In addition, due to the thermal budget limitation of the CMOS process, the existing 1T1R architecture RRAM memory cells cannot use the third dimension to achieve three-dimensional stacking to further increase the density, which greatly limits the high-density integration of resistive random access memory.

[0071] According to an exemplary embodiment, the present disclosure provides a storage device, referring to Figure 1 , Figure 2 , Figure 3 As shown, combined with reference Fig.26 , Fig. 27 , Fig.28 As shown, the memory device 100 includes a memory cell 20, a source line 30, a word line 40 and a bit line 50; the memory cell 20 is arranged on a substrate 10, and the memory cell 20 is arranged at intervals in a direction perpendicular to the substrate 10, and the memory cell 20 includes a gate transistor 21 and a resistive device 22; the gate transistor 21 includes a horizontal semiconductor layer 63 extending in a first direction X parallel to the substrate 10, and the resistive device 22 includes the horizontal semiconductor layer 63 and a resistive layer 221 and an electrode layer 221 arranged in sequence away from the horizontal semiconductor layer 63 in the first direction X. 22; the source line 30 extends along a second direction Y parallel to the substrate 10, and is arranged at intervals along a third direction Z perpendicular to the substrate 10, the first direction X intersects the second direction Y, and along the first direction X, the source line 30 is arranged on the side of the horizontal semiconductor layer 63 away from the resistive layer 221; the word line 40 is arranged along the third direction Z, and the word line 40 intersects with the horizontal semiconductor layer 63 of the selection transistor 21 arranged along the third direction Z; the bit line 50 is arranged along the third direction Z, and the bit line 50 is connected to the electrode layer 222 of the resistive device 22 arranged along the third direction Z.

[0072] In the memory device 100 of the present embodiment, the horizontal semiconductor layer 63 of the gate transistor 21 extends along the first direction X. The horizontal arrangement of the gate transistor 21 can reduce the occupied area of ​​the gate transistor 21 and reduce the characteristic size of the gate transistor 21. The resistive device 22 includes the horizontal semiconductor layer 63, the resistive layer 221 and the electrode layer 222 arranged in sequence along the first direction X. The gate transistor 21 and the resistive device 22 share the horizontal semiconductor layer 63, which can reduce the characteristic size of the memory cell 20 and improve the integration density of the memory cell 20. At the same time, the source line 30 extends along the second direction Y, and the source line 30 is connected to the side of the horizontal semiconductor layer 63 away from the resistive layer 221. The word line 40 extends along the third direction Z, and the word line 40 intersects with the horizontal semiconductor layer 63 of the gate transistor 21. The bit line 50 extends along the third direction Z, and the bit line 50 is connected to the electrode layer 222 of the resistive device 22 arranged along the third direction Z. The memory cell 20 can be integrated using the third direction Z perpendicular to the substrate 10, thereby improving the integration density of the memory device 100.

[0073] In some embodiments, reference Figure 1 , Figure 2 , Figure 3 As shown, the memory cells 20 arranged along the third direction Z and the resistive switching layers 221 of the resistive switching devices 22 are connected in sequence. There are multiple memory cells 20 arranged along the third direction Z, and the resistive switching layers 221 of the resistive switching devices 22 of the multiple memory cells 20 are connected in sequence, and the resistive switching layer 221 is vertically arranged on the substrate 10 along the third direction Z. The resistive switching layer 221 includes a resistive switching region and a non-resistive switching region arranged in sequence along the third direction Z, and the selection transistor 21 of each memory cell 20 is connected to a resistive switching region accordingly. In this way, it is helpful to reduce the manufacturing difficulty of the memory device 100, reduce the production cost, and improve the product yield.

[0074] In some embodiments, reference Figure 1 , Figure 2 , Figure 3 As shown, the resistive layer 221 surrounds the circumference of the electrode layer 222. In other words, in a plane parallel to the substrate 10, the circumference of the electrode layer 222 is covered by the resistive layer 221. The contact area between the resistive layer 221 and the electrode layer 222 of the resistive device 22 is larger, which can reduce the driving current of the resistive layer 221. The resistive layer 221 can be driven by a smaller driving current to change the resistance value of the resistive layer 221, thereby completing the read and write operations. In this way, the memory cell 20 can have a smaller feature size, which is conducive to the further development of the memory device 100 in the direction of miniaturization and small size.

[0075] It is understood that in some other embodiments, the resistive layer 221 may only cover the side wall of the electrode layer 222 close to the horizontal semiconductor layer 63. Alternatively, the resistive layer 221 may cover a portion of the circumference of the electrode layer 222 parallel to the plane of the substrate 10.

[0076] In some embodiments, reference Figure 1 , Figure 2 , Figure 3 As shown, the selection transistor 21 includes a first source and drain 211, a semiconductor channel 212, a second source and drain 213, a gate dielectric layer 214 and a gate 215; the first source and drain 211, the semiconductor channel 212 and the second source and drain 213 are arranged in sequence on the horizontal semiconductor layer 63 along a direction away from the source line 30; the gate dielectric layer 214 is arranged between the word line 40 and the semiconductor channel 212, and the gate dielectric layer 214 surrounds the semiconductor channel 212 along a plane parallel to the second direction Y; the gate 215 surrounds the gate dielectric layer 214 along a plane parallel to the second direction Y, and the gate 215 is connected to the word line 40.

[0077] In the memory device 100 of the present embodiment, the selection transistor 21 is a horizontal channel ring-gate transistor, and the selection transistor 21 can have a smaller characteristic size, which is beneficial to further reduce the size of the memory cell 20, improve the integration density of the memory cell 20, and improve the utilization rate of the application area of ​​the substrate 10.

[0078] In some embodiments, reference Figure 4 , Figure 5 , Figure 6 As shown, the memory cells 20 are arranged along the first direction X and the second direction Y. That is, the memory cells 20 are arranged in a three-dimensional array on the substrate 10 along the first direction X, the second direction Y, and the third direction Z. The three-dimensional array includes multiple layers of memory cells 20 arranged along the third direction Z, and each layer of memory cells 20 includes multiple rows of memory cells 20 arranged along the first direction X, and multiple columns of memory cells 20 arranged along the second direction Y. In each layer of memory cells 20, the selection transistors 21 of a column of memory cells 20 arranged along the second direction Y share the source line 30.

[0079] The memory device 100 of the present embodiment fully utilizes the application area of ​​the substrate 10 , realizes the three-dimensional integration of the memory cells 20 of the 1S1R architecture, and integrates a three-dimensional array of the memory cells 20 on the substrate 10 .

[0080] In some embodiments, reference Figure 4 , Figure 5 , Figure 6As shown, along the first direction X, one side of the bit line 50 is connected to the first storage unit 120, and the other side is connected to the second storage unit 220, and the first storage unit 120 and the second storage unit 220 are mirror-symmetric about the bit line 50. In this way, the first storage unit 120 and the second storage unit 220 on both sides of the bit line 50 share the same bit line 50, which further improves the integration density of the storage unit 20 and the utilization rate of the application area of ​​the substrate 10. At the same time, it can reduce the difficulty of manufacturing the storage device 100, save manufacturing processes, and help reduce production costs and improve product yields.

[0081] In some embodiments, reference Figure 4 , Figure 5 , Figure 6 As shown, along the first direction X, the first storage unit 120 and the second storage unit 220 located on both sides of the source line 30 share the same source line 30. In each layer of storage units 20, a column of first storage units 120 and a column of second storage units 220 located on both sides of the source line 30 share the same source line 30, which further improves the integration density of the storage unit 20 and improves the utilization rate of the application area of ​​the substrate 10. At the same time, it can reduce the manufacturing difficulty of the storage device 100, save manufacturing processes, and help reduce production costs and improve product yields.

[0082] According to an exemplary embodiment, this embodiment provides a method for manufacturing a memory device, such as Figure 7 As shown, the method for manufacturing a memory device includes the following steps:

[0083] Step S10: providing a substrate, and forming alternating insulating layers and semiconductor material layers on the substrate.

[0084] Step S20: patterning alternating insulating layers and semiconductor material layers, the semiconductor material layers forming horizontal semiconductor layers and source lines, the horizontal semiconductor layer extending along a first direction, the source line extending along a second direction, the first direction and the second direction are parallel to the substrate, the first direction intersects with the second direction, along the first direction, at least one end of the horizontal semiconductor layer is connected to the source line, the horizontal semiconductor layer includes a first source and drain, a semiconductor channel, and a second source and drain arranged in sequence away from the source line.

[0085] Step S30: removing part of the insulating layer to expose the semiconductor channel.

[0086] Step S40: forming a gate dielectric layer to cover the semiconductor channel.

[0087] Step S50: forming a gate and a word line, wherein the gate covers the gate dielectric layer and forms a gate transistor together with the horizontal semiconductor layer, and the word line is vertically arranged on the substrate along a third direction, intersecting with the semiconductor channel of the gate transistor arranged along the third direction, and connected to the gate of the gate transistor.

[0088] Step S60: forming a resistive switching layer and an electrode layer in sequence on a side of the horizontal semiconductor layer away from the source line; the resistive switching layer, the electrode layer and the horizontal semiconductor layer together form a resistive switching device; and the selection transistor and the resistive switching device form a storage unit.

[0089] Step S70: forming a bit line extending along the third direction, wherein the bit line is connected to the electrode layer of the resistive switching devices arranged along the third direction.

[0090] In the manufacturing method of the memory device of the present embodiment, a horizontal semiconductor layer 63 extending along the first direction X is formed to form a horizontally arranged gate transistor 21, so that the characteristic size of the gate transistor 21 can be reduced, and the occupied area of ​​the gate transistor 21 can be reduced. A resistive switching layer 221 and an electrode layer 222 are sequentially formed on a side of the horizontal semiconductor layer 63 away from the source line 30. The resistive switching layer 221 and the electrode layer 222 form a resistive switching device 22 together with the horizontal semiconductor layer 63. The gate transistor 21 and the resistive switching device 22 share the horizontal semiconductor layer 63, so that the storage unit 20 can be reduced. The characteristic size improves the integration density of the storage unit 20. At the same time, the source line 30 formed in this embodiment extends along the second direction Y, the source line 30 is connected to the side of the horizontal semiconductor layer 63 away from the resistive layer 221, the word line 40 extends along the third direction Z, the word line 40 intersects with the horizontal semiconductor layer 63 of the selection transistor 21, the bit line 50 extends along the third direction Z, and the bit line 50 is connected to the electrode layer 222 of the resistive device 22 arranged along the third direction Z. The storage unit 20 can be integrated using the third direction perpendicular to the substrate 10, thereby improving the integration density of the storage device 100.

[0091] Combine the following Figure 8-Figure 28 The steps of the method for manufacturing a memory device are described in detail. Figure 8-Figure 28 Combined with the attached Figure 2-6 , which is a schematic diagram of the structure of a storage device in an exemplary embodiment of the present disclosure during its manufacturing process.

[0092] like Figure 8 , Fig. 9 , Fig.10 As shown, the substrate 10 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC) or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0093] like Figure 8 , Fig. 9 , Fig.10As shown, the insulating layer 61 and the semiconductor material layer 62 may be alternately deposited on the substrate 10 by chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0094] The material of the insulating layer 61 may include at least one of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), or zirconium oxide (ZrO 2 ).

[0095] The semiconductor material layer 62 includes semiconductor materials such as silicon or metal oxide.

[0096] In some embodiments, the material of the semiconductor material layer 62 includes metal oxide. In this way, the process compatibility of the formed gate transistor 21 with the back-end CMOS process can be improved, the thermal budget cost can be reduced, and the product yield can be improved.

[0097] For example, the material of the metal oxide may be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring a low refresh rate of the memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x Iny Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZO x And other materials.

[0098] In some embodiments, Figure 8 , Fig. 9 , Fig.10 As shown, before forming alternating insulating layers 61 and semiconductor material layers 62 on the substrate 10 , an etch stop layer 64 is first deposited on the substrate 10 . The etch stop layer 64 is used to protect the substrate 10 and prevent over-etching from damaging the substrate 10 .

[0099] For example, the material of the etch stop layer 64 may include at least one of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), or zirconium oxide (ZrO 2 ).

[0100] For example, the etch stop layer 64 may be deposited by CVD or ALD.

[0101] like Fig.11 , Fig.12 , Fig.13As shown, the insulating layer 61 and the semiconductor material layer 62 are etched layer by layer from the top layer of the alternating insulating layer 61 and the semiconductor material layer 62 toward the substrate 10, and the etching is stopped after the top surface of the substrate 10 is exposed. Each semiconductor material layer 62 is patterned to form a source line 30 extending along the second direction Y and a horizontal semiconductor layer 63 extending along the first direction X. Along the first direction X, at least one end of the horizontal semiconductor layer 63 is connected to the source line 30, and from the connection end of the horizontal semiconductor layer 63 and the source line 30, the horizontal semiconductor layer 63 includes a first source and drain electrode 211, a semiconductor channel 212, and a second source and drain electrode 213 arranged in sequence along the first direction X. In some embodiments, along the first direction X, the two ends of the horizontal semiconductor layer 63 are respectively connected to the source lines 30 on both sides, and the projections formed by the horizontal semiconductor layer 63 and the source line 30 on the substrate 10 are in a grid shape.

[0102] For example, a dry process may be used to etch the alternating insulating layers 61 and semiconductor material layers 62 .

[0103] First, if Fig.14 , Fig.15 , Fig.16 As shown, CVD is used to deposit a first dielectric layer 65 to fill the areas where the insulating layer 61 and the semiconductor material layer 62 are removed. The first dielectric layer 65 covers the exposed surface of the substrate 10 and fills between the insulating layers 61, between the source lines 30, and between the horizontal semiconductor layers 63 to facilitate subsequent manufacturing processes.

[0104] For example, the material of the first dielectric layer 65 may include at least one of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ) or zirconium oxide (ZrO 2 ).

[0105] Then, a photoresist layer (not shown in the figure) is formed on the first dielectric layer 65 and the alternating insulating layer 61 and semiconductor material layer 62, and the photoresist layer is exposed and developed to form a mask pattern. Fig.17 , Fig.18 , Fig.19 As shown, refer to Figure 1-Figure 6 , the insulating layer 61 and the first dielectric layer 65 are etched according to the mask pattern, and a portion of the insulating layer 61 and the first dielectric layer 65 are removed to expose the semiconductor channel 212, wherein the semiconductor channel 212 is located in the middle area of ​​the horizontal semiconductor layer 63. After the semiconductor channel 212 is exposed, along the first direction X, the first source and drain 211 and the second source and drain 213 located on both sides of the semiconductor channel 212 are still covered by the insulating layer 61, and along the third direction Z, the semiconductor channel 212 of the horizontal semiconductor layer 63 is suspended.

[0106] Reference Fig. 20 , Fig.21 , Fig. 22 As shown, and combined with reference Figure 1-Figure 6 At least one of an in-situ steam generation process (ISSG), an atomic layer deposition process, a plasma vapor deposition process, and a rapid thermal oxidation process (RTO) can be used to form a gate dielectric layer 214 on the exposed surface of the semiconductor channel 212. Along a plane parallel to the second direction Y, the gate dielectric layer 214 surrounds and covers the semiconductor channel 212.

[0107] Illustratively, the material of the gate dielectric layer 214 includes at least one of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ) or zirconium oxide (ZrO 2 ).

[0108] Continue to refer to Fig. 20 , Fig.21 , Fig. 22 As shown, and combined with reference Figure 1-Figure 6 , a conductive material may be deposited by chemical vapor deposition, atomic layer deposition or physical vapor deposition process, the conductive material covers the gate dielectric layer 214 and fills the unfilled area between the semiconductor channels 212, forming the gate 215 of the gate transistor 21, and the word line 40 vertically arranged on the substrate 10 along the third direction Z. In the plane parallel to the second direction Y, the gate 215 of the gate transistor 21 surrounds and covers the gate dielectric layer 214, and the gate 215, the gate dielectric layer 214, the first source and drain 211, the semiconductor channel 212 and the second source and drain 213 formed on the horizontal semiconductor layer 63 together form the gate transistor 21.

[0109] The gate transistor 21 formed in this embodiment is a horizontal channel all-around gate transistor, so that the gate transistor 21 can have a smaller feature size, which is conducive to further reducing the size of the memory cell 20, improving the integration density of the memory cell 20, and improving the utilization rate of the application area of ​​the substrate 10. The word line 40 is connected to the gate 215 of the gate transistor 21 along the third direction Z.

[0110] By way of example, the material of the word line 40 may include at least one of Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, Ir, Ru, ITO, and heavily doped polysilicon.

[0111] In some embodiments, after forming the horizontal semiconductor layer 63 and the source line 30, along the first direction X, both ends of the horizontal semiconductor layer 63 are connected to the source line 30 respectively; and the resistive layer 221 and the electrode layer 222 are sequentially formed on the side of the horizontal semiconductor layer 63 away from the source line 30, including the following steps:

[0112] Reference Fig.23 , Fig.24 , Fig.25 As shown, and combined with reference Figure 1-Figure 6 , the alternating insulating layers 61 and the horizontal semiconductor layers 63 are etched to form an electrode layer 222 that penetrates the alternating insulating layers 61 and the horizontal semiconductor layers 63, and the electrode layer 222 divides the horizontal semiconductor layer 63 into a first segment and a second segment that are spaced apart along the first direction X; wherein the first segment is used to form a first storage unit 120, and the second segment is used to form a second storage unit 220, and the first storage unit 120 and the second storage unit 220 are mirror-symmetric about the bit line 50.

[0113] Reference Fig.26 , Fig. 27 , Fig.28 As shown, and combined with reference Figure 1-Figure 6 , forming a resistive switching layer 221, wherein the resistive switching layer 221 covers the sidewall of the electrode layer 222. The resistive switching layer 221 may be formed by ALD deposition.

[0114] For example, the resistive switching layer 221 may be a single layer or a multi-layer structure. The material of the resistive switching layer 221 includes TaO x 、TiOx、HfO x 、ZrO x 、SiO x 、MgO、AlN x , Gete x 、GeSb、GeTe、SbTe、CuS x ,GeS x 、GeSex、ZnS、AlBO、SrTiO x 、ZrTiO x 、BaTiO x , HfZrO or HfAlO.

[0115] Reference Fig.26 , Fig. 27 , Fig.28 As shown, and combined with reference Figure 1-Figure 6 , forming an electrode layer 222, the electrode layer 222 covers the inner sidewall of the resistive layer 221 and fills the unfilled area of ​​the electrode layer 222. The electrode layer 222 may be formed by ALD or CVD deposition, the electrode layer 222 covers the inner sidewall of the resistive layer 221 and fills the electrode layer 222, and at the same time, a bit line 50 extending along the third direction Z on the substrate 10 is formed.

[0116] In this embodiment, the resistive switching layer 221 and the electrode layer 222 are both vertically arranged on the substrate 10 along the third direction Z. The resistive switching layer 221 includes a resistive switching region and a non-resistive switching region spaced apart along the third direction Z. The horizontal semiconductor layer 63 is connected to the resistive switching region of the resistive switching layer 221. The horizontal semiconductor layer 63 and the connected resistive switching layer 221 and electrode layer 222 form a resistive switching device 22, and the selection transistor 21 and the resistive switching device 22 together form a storage unit 20.

[0117] In this embodiment, by forming the first trench 101, the resistive switching layer 221 and the electrode layer 222 are sequentially formed in the first trench 101, so that in a plane parallel to the substrate 10, the circumference of the electrode layer 222 is covered by the resistive switching layer 221. This makes the contact area between the resistive switching layer 221 and the electrode layer 222 of the resistive switching device 22 larger, and the driving current of the resistive switching layer 221 can be reduced. The resistive switching layer 221 can be driven by a smaller driving current to change the resistance value of the resistive switching layer 221, and the read and write operations are completed. In this way, the memory cell 20 can have a smaller feature size, which is conducive to the further development of the memory device 100 in the direction of miniaturization and small size.

[0118] The manufacturing method of the memory device of the present embodiment forms a horizontal semiconductor layer 63 with both ends connected to the source line 30, forms a first section and a second end of the horizontal semiconductor layer 63 spaced apart along the first direction X by forming a first groove 101, and after forming a bit line 50, forms a first memory cell 120 and a second memory cell 220 with the bit line 50 as the center line and the mirror center on both sides of the bit line 50, and the first memory cell 120 and the second memory cell 220 share the bit line 50. At the same time, the bit line 50 extends along the third direction Z, and a plurality of first memory cells 120 arranged along the third direction Z and a plurality of second memory cells 220 arranged along the third direction Z share the bit line 50. The integration density of the memory cell 20 is further improved, and the utilization rate of the application area of ​​the substrate 10 is improved. At the same time, the manufacturing difficulty of the memory device 100 can be reduced, the manufacturing process can be saved, and it is beneficial to reduce the production cost and improve the product yield.

[0119] The manufacturing method of the memory device of the present embodiment forms the first memory cell 120 and the second memory cell 220 with the bit line 50 as the center line as the mirror center, the first memory cell 120 and the second memory cell 220 are arrayed along the first direction X, and a column of the first memory cells 120 arranged along the second direction Y and a column of the second memory cells 220 arranged along the second direction Y on both sides of the source line 30 share the same source line 30, thereby further improving the integration density of the memory cell 20 and improving the utilization rate of the application area of ​​the substrate 10. At the same time, it can reduce the manufacturing difficulty of the memory device 100, save the manufacturing process, and help reduce the production cost and improve the product yield.

[0120] In some other embodiments, step S60 sequentially forms a resistive switching layer and an electrode layer on a side of the horizontal semiconductor layer away from the source line, including the following steps:

[0121] Step S601: forming a first trench on a side of the second source and drain of the horizontal semiconductor layer away from the source line, wherein the first trench is arranged on the substrate along a third direction.

[0122] Step S602: forming a resistive switching layer, wherein the resistive switching layer covers the sidewall of the first trench.

[0123] Step S603: forming an electrode layer, where the electrode layer covers the inner sidewall of the resistive layer and fills the unfilled area of ​​the first trench.

[0124] This embodiment is not shown in the drawings. In this embodiment, after the horizontal semiconductor layer 63 and the source line 30 are formed, one end of the horizontal semiconductor layer 63 is connected to the source line 30 on one side thereof along the first direction X, and the other end of the horizontal semiconductor layer 63 is spaced from the source line 30 on the other side thereof. In this embodiment, the first dielectric layer 65 on the side of the horizontal semiconductor layer 63 away from the source line 30 is etched until the top surface of the substrate 10 is exposed, forming a first groove 101 penetrating the first dielectric layer 65 along the third direction Z. Then, a resistive switching layer 221 and an electrode layer 222 are sequentially formed in the first groove 101. The resistive switching layer 221 and the electrode layer 222 are formed in the same manner as in the above embodiment, and will not be described in detail herein.

[0125] It should be understood that although Figure 7 The steps in the above-mentioned process steps are shown in sequence according to arrows or step sequence indications, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 7 At least part of the steps in the process described above may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0126] The order of manufacturing the storage unit, word line, bit line and source line in the above embodiments can be arbitrarily changed or combined with each other. Therefore, those skilled in the art can combine and / or change any number of manufacturing processes of the storage unit, word line, bit line and source line without creative work, which should all fall within the protection scope of the embodiments of the present disclosure.

[0127] In some embodiments, an electronic device is provided, including a memory as described in any of the embodiments of the present disclosure. The electronic device is, for example but not limited to, suitable types of electronic products such as consumer electronic products, home electronic products, vehicle-mounted electronic products, and financial terminal products. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc.

[0128] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive memory (ReRAM), magneto-resistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. The database involved in the embodiments provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, data processing logic devices based on quantum computing, etc., but are not limited thereto. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0130] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A storage device, characterized in that: include: A memory cell is provided on a substrate, the memory cells are arranged at intervals in a direction perpendicular to the substrate, and the memory cell comprises a gating transistor and a resistive switching device; the gating transistor comprises a horizontal semiconductor layer extending in a first direction parallel to the substrate, and the resistive switching device comprises the horizontal semiconductor layer and a resistive switching layer and an electrode layer sequentially arranged away from the horizontal semiconductor layer in the first direction; Source lines extend along a second direction parallel to the substrate, are arranged at intervals along a third direction perpendicular to the substrate, the first direction intersects the second direction, and along the first direction, the source lines are arranged on a side of the horizontal semiconductor layer away from the resistive switching layer; A word line is arranged along the third direction, and the word line intersects the horizontal semiconductor layer of the gate transistor arranged along the third direction; The bit line is arranged along the third direction, and the bit line is connected to the electrode layer of the resistive switching device arranged along the third direction.

2. The memory device according to claim 1, wherein: The memory cells arranged along the third direction and the resistive switching layers of the resistive switching devices are connected in sequence.

3. The memory device according to claim 1, wherein: The resistive layer surrounds the circumference of the electrode layer.

4. The memory device according to claim 1, wherein: The gate transistor comprises: A first source-drain electrode, a semiconductor channel, and a second source-drain electrode, wherein the first source-drain electrode, the semiconductor channel, and the second source-drain electrode are sequentially arranged in the horizontal semiconductor layer in a direction away from the source line; A gate dielectric layer is disposed between the word line and the semiconductor channel, and along a plane parallel to the second direction, the gate dielectric layer surrounds the semiconductor channel; A gate is disposed along a plane parallel to the second direction, the gate surrounds the gate dielectric layer, and the gate is connected to the word line.

5. The memory device according to any one of claims 1 to 4, characterized in that: The storage units are arranged along the first direction and the second direction; Along the first direction, one side of the bit line is connected to a first storage unit, and the other side is connected to a second storage unit, and the first storage unit and the second storage unit are mirror-symmetric with respect to the bit line.

6. The memory device according to claim 5, characterized in that Along the first direction, the first storage unit and the second storage unit located at two sides of the source line share the same source line.

7. A method for manufacturing a memory device, characterized in that: include: providing a substrate on which alternating insulating layers and semiconductor material layers are formed; The insulating layer and the semiconductor material layer are patterned alternately, the semiconductor material layer forms a horizontal semiconductor layer and a source line, the horizontal semiconductor layer extends along a first direction, the source line extends along a second direction, the first direction and the second direction are parallel to the substrate, the first direction intersects with the second direction, along the first direction, at least one end of the horizontal semiconductor layer is connected to the source line, and the horizontal semiconductor layer includes a first source and drain electrode, a semiconductor channel, and a second source and drain electrode arranged in sequence away from the source line; removing a portion of the insulating layer to expose the semiconductor channel; forming a gate dielectric layer to cover the semiconductor channel; forming a gate and a word line, wherein the gate covers the gate dielectric layer and forms a gate transistor together with the horizontal semiconductor layer, and the word line is vertically arranged on the substrate along a third direction, intersects with the semiconductor channel of the gate transistor arranged along the third direction, and is connected to the gate of the gate transistor; A resistive switching layer and an electrode layer are sequentially formed on a side of the horizontal semiconductor layer away from the source line, wherein the resistive switching layer, the electrode layer and the horizontal semiconductor layer together form a resistive switching device, and the selection transistor and the resistive switching device form a storage unit; A bit line extending along the third direction is formed, and the bit line is connected to the electrode layer of the resistive switching devices arranged along the third direction.

8. The method for manufacturing a memory device according to claim 7, characterized in that: A resistive switching layer and an electrode layer are sequentially formed on a side of the horizontal semiconductor layer away from the source line, including: A first trench is formed on a side of the second source and drain of the horizontal semiconductor layer away from the source line, wherein the first trench is arranged on the substrate along the third direction; forming the resistive switching layer, wherein the resistive switching layer covers the sidewall of the first trench; The electrode layer is formed, and the electrode layer covers the inner sidewall of the resistive layer and fills the unfilled area of ​​the first trench.

9. The method for manufacturing a memory device according to claim 7, characterized in that: After forming the horizontal semiconductor layer and the source line, along the first direction, two ends of the horizontal semiconductor layer are respectively connected to the source line; the manufacturing method comprises: Etching the alternating insulating layers and the horizontal semiconductor layers to form first grooves penetrating the alternating insulating layers and the horizontal semiconductor layers, wherein the first grooves divide the horizontal semiconductor layers into first sections and second sections spaced apart along the first direction; The first segment is used to form a first memory cell, and the second segment is used to form a second memory cell. The first memory cell and the second memory cell are mirror-symmetric with respect to the bit line.

10. An electronic device, characterized in that: A memory device comprising the memory device according to any one of claims 1 to 6, or a memory device manufactured by the memory device manufacturing method according to any one of claims 7 to 9.

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