Distributed real-time control system and method based on tsn and fpga

Abstract

The application relates to a distributed real-time control system and method based on TSN and FPGA. The system comprises a TSN module, a plurality of data acquisition modules and a plurality of control output modules, the TSN module is used for receiving control instructions sent by a superior processing system and forwarding the control instructions to the data acquisition modules and the control output modules in a pipeline form through a high-speed interface, and is used for receiving acquisition data returned by each data acquisition module and each control output module through the high-speed interface and transmitting the acquisition data to the superior processing system; the data acquisition module is used for acquiring data according to data acquisition messages in the received control instructions and transmitting the acquired data to the TSN module in a pipeline mode; and the control output module is used for performing real-time control on external equipment according to control output messages in the received control instructions and transmitting feedback signals to the TSN module in a pipeline mode. The system can meet the demand of modern industry for efficient and accurate control.

Description

Technical Field

[0001] This application relates to the field of intelligent control technology, and in particular to a distributed real-time control system and method based on TSN and FPGA. Background Technology

[0002] With the development of Industry 4.0 and intelligent manufacturing, fieldbus is increasingly used in industrial network communication. Common fieldbus protocols include EtherCAT, PROFINET, POWERLINK, and CC-Link. To ensure specific real-time requirements and accommodate the different requirements of various industrial network layers, these protocols are modified based on standard Ethernet. This necessitates the deployment of dedicated communication equipment such as gateways, routers, and switches. While traditional Ethernet is widespread, it has limitations in real-time data transmission. Often, when network congestion occurs, it cannot effectively transmit data with real-time requirements.

[0003] In the field of intelligent manufacturing, there is an urgent need for a unified network infrastructure environment that can meet the real-time and deterministic requirements of industrial control systems for data transmission, while also being compatible with traditional Ethernet protocols. Therefore, how to achieve low-latency real-time acquisition and control while being compatible with traditional Ethernet protocols is a technical problem that needs to be solved. Summary of the Invention

[0004] Therefore, it is necessary to provide a distributed real-time control system and method based on TSN and FPGA to address the above-mentioned technical problems.

[0005] A distributed real-time control system based on TSN and FPGA, the system comprising:

[0006] The system comprises a TSN module, multiple data acquisition modules, and multiple control output modules. Each module includes at least one FPGA, which is used to handle signal acquisition, data processing, and forwarding within the module. The modules are connected via a VPX backplane and transmit data in series between the modules through a high-speed interface.

[0007] The TSN module is connected to the upper-level processing system via Ethernet. It is used to receive control commands sent by the upper-level processing system and forward them to the data acquisition module and control output module in a pipeline manner through a high-speed interface. It is also used to receive the acquired data returned by each data acquisition module and each control output module through the high-speed interface and transmit it to the upper-level processing system. The control commands include data acquisition messages, control output messages and configuration management messages.

[0008] The data acquisition module is used to acquire data according to the data acquisition message in the received control command, and transmit the acquired data to the TSN module in a pipeline manner.

[0009] The control output module is used to control external devices in real time according to the control output message in the received control command, and to transmit the feedback signal to the TSN module in a pipeline manner.

[0010] A distributed real-time control method based on TSN and FPGA, the method comprising:

[0011] The TSN module receives control commands sent by the upper-level processing system and forwards them to the data acquisition module and control output module in a pipeline manner through a high-speed interface. It also receives the acquired data returned by each data acquisition module and each control output module through the high-speed interface and transmits it to the upper-level processing system. The control commands include data acquisition messages, control output messages, and configuration management messages.

[0012] The data acquisition module collects data according to the data acquisition message in the received control command, and transmits the collected data to the TSN module in a pipeline manner.

[0013] The control output module is used to control external devices in real time according to the control output message in the received control command, and to transmit feedback signals to the TSN module in a pipeline manner.

[0014] The aforementioned distributed real-time control system and method based on TSN and FPGA achieves real-time data transmission through TSN technology, meeting the high real-time performance requirements of industrial control systems. Furthermore, the system utilizes FPGA for data acquisition and processing, providing parallel processing capabilities and enabling rapid response to the real-time processing demands of large volumes of data. Modules connect to the VPX backplane via high-speed interfaces, employing a pipelined data transmission method, significantly improving data transmission speed and efficiency. This invention enhances real-time performance and reliability while also offering strong flexibility and scalability, meeting the demands of modern industry for efficient and precise control. Attached Figure Description

[0015] Figure 1 This is an application scenario diagram of a distributed real-time control method based on TSN and FPGA in one embodiment;

[0016] Figure 2 This is a schematic diagram of the TSN module in one embodiment;

[0017] Figure 3 This is a schematic diagram of the data acquisition module in one embodiment;

[0018] Figure 4 This is a schematic diagram of the control output module in one embodiment;

[0019] Figure 5This is a flowchart illustrating a distributed real-time control method based on TSN and FPGA in one embodiment;

[0020] Figure 6 This is a schematic diagram of the data processing flow in one embodiment. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] In one embodiment, such as Figure 1 As shown, a distributed real-time control system based on TSN and FPGA is provided, including:

[0023] The system consists of a TSN module, multiple data acquisition modules, and multiple control output modules. Each module includes at least one FPGA, which is used to handle signal acquisition, data processing, and forwarding within the module. The modules are connected via a VPX backplane and transmit data in series between the modules through a high-speed interface.

[0024] The TSN module connects to the upper-level processing system via Ethernet. It is used to receive control commands sent by the upper-level processing system and forward them to the data acquisition module and control output module in a pipeline manner through a high-speed interface. It is also used to receive the acquired data returned by each data acquisition module and each control output module through the high-speed interface and transmit it to the upper-level processing system. The control commands include data acquisition messages, control output messages and configuration management messages.

[0025] The data acquisition module is used to acquire data according to the data acquisition message in the received control command, and transmit the acquired data to the TSN module in a pipeline manner;

[0026] The control output module is used to control external devices in real time according to the control output messages in the received control commands, and to transmit feedback signals to the TSN module in a pipeline manner.

[0027] In the aforementioned distributed real-time control method based on TSN and FPGA, TSN technology enables real-time data transmission, meeting the high real-time performance requirements of industrial control systems. Furthermore, the system utilizes FPGA for data acquisition and processing, providing parallel processing capabilities and enabling rapid response to the real-time processing demands of large volumes of data. Modules connect to the VPX backplane via high-speed interfaces, employing a pipelined data transmission method, significantly improving data transmission speed and efficiency. This invention enhances real-time performance and reliability while also offering strong flexibility and scalability, meeting the demands of modern industry for efficient and precise control.

[0028] In one embodiment, both the data acquisition module and the control output module include a high-speed receiving interface and a high-speed transmitting interface. The high-speed receiving interface is used for bidirectional communication with the connected upstream module, and the high-speed transmitting interface is used for bidirectional communication with the connected downstream module. The data acquisition module and the control output module receive messages from the upstream module through the high-speed receiving interface, process the data, and forward it to the downstream module through the high-speed transmitting interface. When the data is transmitted to the last module of the link, the last module transmits the data back to the TSN module along the same link in reverse, completing the data return.

[0029] like Figure 1 As shown, the data acquisition module is responsible for collecting data from devices such as sensors; the control output module performs real-time control of external devices based on the processing results; the TSN communication and data processing module is responsible for receiving the data collected by the data acquisition module, processing it quickly, and sending the collected data to the upper-level processing system through the TSN network. Simultaneously, it receives control commands sent from the upper-level processing system through the TSN network, parses them, and forwards them to the control output module. Modules are connected via a VPX backplane. The remote host sends (control output, data acquisition, configuration management) messages to the device's TSN module via Ethernet. The TSN module then forwards these messages to the first sub-module through the backplane LVDS interface. Modules are connected in series through the backplane LVDS interface, with messages sequentially passed down to the last module and then back up to the TSN module, which then forwards them back to the remote host. This structural design not only improves the system's real-time performance and reliability but also enhances its flexibility and scalability.

[0030] In one embodiment, each data acquisition module and each control output module uses PPS+ToD and TSN modules for clock synchronization.

[0031] like Figure 1 As shown, the remote host updates the clock to the TSN module via the 802.1AS Ethernet protocol. The TSN module then updates the clocks of all modules through the PPS and ToD interfaces on the backplane. PPS (Pulse Per Second) is a pulse signal used for time synchronization, providing a fixed pulse per second to mark the start of each second. This signal is typically generated by devices such as GPS receivers to ensure the system clock is synchronized with international standard time (such as UTC), achieving high accuracy down to the nanosecond level. ToD (Time of Day) provides current time information (such as hours, minutes, seconds), typically used for time synchronization between devices to ensure clock consistency. ToD signals are usually transmitted via network or other protocols, providing the system's actual time.

[0032] In one embodiment, the FPGA in the TSN module is used to receive data transmitted through the high-speed interface and preprocess it, package the preprocessed data into data packets conforming to the TSN protocol, and send them to the Ethernet interface; it is also used to receive control commands transmitted through the Ethernet interface, parse them, and then transmit them to the high-speed interface.

[0033] like Figure 2 The diagram shows the structure of the TSN module. The TSN module includes an Ethernet communication interface, an LVDS communication interface, an FPGA, and a power management unit. The Ethernet communication interface is used to communicate with external networks or hosts, supporting real-time data transmission using the TSN protocol. The LVDS communication interface is responsible for data transmission with other modules (such as data acquisition modules and control output modules) via a high-speed LVDS interface. The power management unit provides a stable power supply to ensure the normal operation of the entire module. The FPGA is the core processing unit, responsible for data processing and protocol conversion. The TSN module connects to an external TSN network to receive and send data, integrates the TSN protocol stack, supports real-time data transmission, and ensures low latency and high deterministic transmission of data in the network.

[0034] In one embodiment, the FPGA in the TSN module is also used to filter received messages to obtain valid message types. Valid message types include data read / write messages and configuration management messages. Data read / write messages include data acquisition messages and control output messages. The priority of the module configuration messages is identified through the filter. When processing data read / write messages, they are directly forwarded to downstream modules for real-time processing in a pipeline manner. When processing module configuration messages, they are cached in a low-priority queue and forwarded after the high-priority data read / write messages have been sent.

[0035] Specifically, for data acquisition modules, the device's message types are divided into two categories: data read / write messages and module configuration messages. Data read / write messages have the highest priority. When receiving messages, a filter removes other invalid messages of these two categories. Then, the received messages are parsed and forwarded directly to other modules. Other modules receive messages, read or insert data, and forward them sequentially to the next-level module. Finally, the last module uploads the messages back up. Messages are sent to the corresponding priority queue based on their type priority. The time slice for time-aware scheduling is set to 50µs. After each time slice refresh, data read / write messages are transmitted first, followed by module configuration messages. Data read / write messages do not need to be cached in the queue during the refresh cycle; they are sent immediately as soon as data is available. Module configuration messages... The message will be cached in a low-priority queue and sent only after all high-priority messages have been sent. Before sending a configuration message, the sending module calculates the current configuration message sending time. If the sending time will exceed the next refresh time, the sending will be delayed, thus ensuring the real-time performance of the system and low latency of data messages. At the same time, the device sends data redundantly through dual network ports, ensuring that messages can still be sent to the host normally even if one network fails. The TSN communication and data processing module also uses pipelined processing to receive data from other modules, thus ensuring that the latency of the device sending the processed message back to the host after receiving the message sent by the host and forwarding it to each module can be controlled within ±200ns (the refresh time of the host sending read and write messages is consistent with the time slice of the time-aware scheduling).

[0036] In one embodiment, the FPGA of the data acquisition module includes an analog input signal processing unit and a digital input signal processing unit; the digital input signal processing unit is connected to multiple parallel digital signal acquisition channels, and each digital signal acquisition channel acquires digital signals through an optocoupler; the analog input signal processing unit is connected to multiple parallel analog signal acquisition channels.

[0037] like Figure 3 The diagram shows the structure of the data acquisition module, which includes an LVDS communication interface, a multi-channel parallel digital signal acquisition channel, a multi-channel parallel analog signal acquisition channel, an FPGA, and a power management unit.

[0038] Specifically, the multi-channel parallel analog signal acquisition channel uses a high-precision analog-to-digital converter (ADC) to acquire analog signals, supports simultaneous sampling of multiple channels, and meets the requirements for synchronous acquisition of multiple signals. The multi-channel parallel digital signal acquisition channel uses a high-speed optocoupler to acquire external digital signals, supports simultaneous sampling of multiple channels, and thus realizes real-time acquisition, processing and analysis of analog and digital data. The data acquisition module communicates with the TSN communication and data processing module using a high-speed LVDS interface and uses PPS+ToD for clock synchronization (accuracy of ±50ns). Each module contains two LVDS channels, each with one transmit channel and one receive channel. Data is transmitted between modules in a cascade manner. If a downstream module exists, the current module forwards the message through LVDS2. If the current module is the last in the link, it forwards the message through LVDS1. The transmission between modules is similar to a pipeline operation. The data acquisition module does not buffer the messages received from the TSN communication and data processing module. Instead, it reads or inserts data in real time and immediately sends it to the next module through another LVDS channel. The messages do not linger between modules. The last module returns to the TSN communication and data processing module along the cascaded link. Each module has only a few nanoseconds of delay from receiving to sending messages, which greatly improves real-time performance. The clock synchronization method using PPS+ToD ensures the deterministic timing of the acquisition.

[0039] In one embodiment, the FPGA controlling the output module includes an analog output signal processing unit and a digital output signal processing unit; the digital output signal processing unit is connected to multiple parallel digital signal output channels, and each digital signal output channel outputs a digital signal through an optocoupler; the analog output signal processing unit is connected to multiple parallel analog signal output channels.

[0040] like Figure 4 The schematic diagram of the control output module shown includes an LVDS communication interface, multiple parallel digital signal output channels, multiple parallel analog signal output channels, an FPGA, and a power management unit.

[0041] Specifically, the multi-channel parallel analog signal output uses a high-precision digital-to-analog converter (DAC) to output analog signals, supporting simultaneous output from multiple channels. The multi-channel parallel digital signal output uses a high-speed optocoupler to output external digital signals, also supporting simultaneous output from multiple channels. Like the data acquisition module, the control output module communicates via an LVDS interface and synchronizes the clock using PPS+ToD. The message contains a timestamp, and after clock synchronization, the control delay can be controlled within ±100ns, thus achieving real-time control of analog and digital signals in the control system. Since the time slice for time-aware scheduling is set to 50us, and the control frequency is often higher than this refresh frequency, a bilinear interpolation algorithm is used to increase the control frequency and provide refined control output for analog control commands.

[0042] In one embodiment, the system further includes a power supply; the power supply is connected to the power interfaces within the TSN module, the multiple data acquisition modules, and the multiple control output modules; the TSN module, the multiple data acquisition modules, and the multiple control output modules each include a power monitoring submodule; the power monitoring submodule is connected to the FPGA and the power interface within the module, respectively.

[0043] In one embodiment, the high-speed interface is an LVDS high-speed interface.

[0044] In one embodiment, such as Figure 5 As shown, a distributed real-time control method based on TSN and FPGA is provided, including the following steps:

[0045] Step 502: Receive control commands sent by the upper-level processing system through the TSN module and forward them to the data acquisition module and control output module in a pipeline manner through the high-speed interface; receive the acquired data returned by each data acquisition module and each control output module through the high-speed interface and transmit it to the upper-level processing system; the control commands include data acquisition messages, control output messages and configuration management messages;

[0046] Step 504: The data acquisition module acquires data according to the data acquisition message in the received control command, and transmits the acquired data to the TSN module in a pipeline manner.

[0047] Step 506: The control output module is used to control the external device in real time according to the control output message in the received control command, and the feedback signal is transmitted to the TSN module in a pipeline manner.

[0048] In this embodiment, as Figure 6The data processing flowchart shown first illustrates that the data acquisition module acquires analog and digital signals and then sends them to the TSN communication and data processing module via a high-speed LVDS interface. The TSN communication and data processing module uses an FPGA to implement the 802.1AS, 802.1CB, 802.1Qbv, and 802.Qci protocols in TSN, enabling synchronous acquisition and packaging of data from multiple acquisition cards, as well as simultaneous output of control output messages to multiple control cards. Specifically, the TSN communication and data processing module performs preliminary processing on the acquired data, such as filtering, diagnostics, etc., packages the processed data into TSN protocol format, and uploads it to the remote system via a network interface. It also receives TSN protocol format control output messages from the remote system via the network interface and forwards the parsed control output messages to the control output module via the high-speed LVDS interface. The control output module receives the control output messages via the high-speed LVDS interface and outputs analog and digital signals. This system and method are applicable to industrial automation, intelligent manufacturing, and other fields, and have broad market prospects.

[0049] It should be understood that, although Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 5 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0050] For specific limitations on the distributed real-time control method based on TSN and FPGA, please refer to the limitations on the distributed real-time control system based on TSN and FPGA mentioned above, which will not be repeated here.

[0051] The modules in the aforementioned distributed real-time control system based on TSN and FPGA can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the processor in a computer device, or stored in software within the computer device's memory, allowing the processor to invoke and execute the corresponding operations of each module.

[0052] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A TSN and FPGA based distributed real-time control system, characterized in that, The system comprises a TSN module, a plurality of data acquisition modules and a plurality of control output modules, each module comprising at least one FPGA for processing signal acquisition, data processing and forwarding within the module; the modules are connected through a VPX backplane and transmit data in series between the modules through a high-speed interface; The TSN module is connected with a superior processing system through Ethernet, used for receiving control instructions sent by the superior processing system and forwarding the control instructions to the data acquisition modules and the control output modules in a pipeline form through the high-speed interface, and used for receiving acquisition data returned by each data acquisition module and each control output module through the high-speed interface and transmitting the acquisition data to the superior processing system; the control instructions comprise data acquisition messages, control output messages and configuration management messages; The data acquisition module is used for acquiring data according to the data acquisition messages in the received control instructions and transmitting the acquired data to the TSN module in a pipeline manner; The control output module is used for controlling external devices in real time according to the control output messages in the received control instructions and transmitting feedback signals to the TSN module in a pipeline manner; The FPGA in the TSN module is further used for screening the received messages to obtain valid message types, the valid message types comprising data read-write messages and configuration management messages, and the data read-write messages comprising data acquisition messages and control output messages; The priority of the module configuration messages is identified through a filter, the data read-write messages are directly forwarded to downstream modules for real-time processing through a pipeline manner, and the module configuration messages are cached in a low-priority queue and forwarded after the high-priority data read-write messages are sent.

2. The system of claim 1, wherein, The data acquisition module and the control output module each comprise a high-speed receiving interface and a high-speed sending interface, the high-speed receiving interface being used for bidirectional communication with a connected upstream module, and the high-speed sending interface being used for bidirectional communication with a connected downstream module; The data acquisition module and the control output module receive messages from an upstream module through the high-speed receiving interface, process the data and forward the data to a downstream module through the high-speed sending interface, and when the data is transmitted to the last module of the link, the last module reversely transmits the data along the same link back to the TSN module, completing the return of the data.

3. The system of claim 1, wherein, Each data acquisition module and each control output module respectively adopts PPS+ToD to perform clock synchronization with the TSN module.

4. The system of claim 1, wherein, The FPGA in the TSN module is used for receiving data transmitted through the high-speed interface and performing preprocessing, packing the preprocessed data into data packets conforming to the TSN protocol and sending the data packets to an Ethernet interface; and further used for receiving control instructions transmitted through the Ethernet interface, analyzing the control instructions and transmitting the control instructions to the high-speed interface.

5. The system of claim 1, wherein, The FPGA of the data acquisition module comprises an analog input signal processing unit and a digital input signal processing unit; the digital input signal processing unit is connected with a plurality of parallel digital signal acquisition channels, each digital signal acquisition channel acquires a digital signal through an optical coupler; and the analog input signal processing unit is connected with a plurality of parallel analog signal acquisition channels.

6. The system of claim 1, wherein, The FPGA of the control output module comprises an analog output signal processing unit and a digital output signal processing unit; the digital output signal processing unit is connected with a plurality of parallel digital signal output channels, each digital signal output channel outputs a digital signal through an optical coupler; and the analog output signal processing unit is connected with a plurality of parallel analog signal output channels.

7. The system of claim 1, wherein, The system further comprises a power supply, which is connected with the power supply interface in the TSN module, the plurality of data acquisition modules and the plurality of control output modules. The TSN module, the plurality of data acquisition modules and the plurality of control output modules each comprise a power supply monitoring sub-module, which is connected with the FPGA and the power supply interface in the module.

8. The system of claim 1, wherein, The high-speed interface is an LVDS high-speed interface.

9. A method of implementing a TSN and FPGA based distributed real-time control system according to any one of claims 1-8, characterized in that, The method comprises: receiving, by the TSN module, a control instruction sent by a superior processing system and forwarding the control instruction to the data acquisition modules and the control output modules in a pipeline form through a high-speed interface, and receiving acquisition data returned by each data acquisition module and each control output module through the high-speed interface and transmitting the acquisition data to the superior processing system; the control instruction comprises a data acquisition message, a control output message and a configuration management message; acquiring, by the data acquisition module, data according to the data acquisition message in the received control instruction and transmitting the acquired data to the TSN module in a pipeline form; controlling, by the control output module, external equipment in real time according to the control output message in the received control instruction and transmitting a feedback signal to the TSN module in a pipeline form.

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