Start acceleration method and device for CPU core in research and development verification environment

Abstract

The invention relates to the technical field of CPU cores, and provides a starting acceleration method and device of a CPU core in a research and development verification environment, and the device comprises an initialization model, a preassembling device model and a storage model; the storage model is used for storing a program file, so that the performance core can acquire target instruction data from the program file in the storage model and decode the target instruction data when initiating an instruction data request of a non-cache attribute from the front end of the performance core; the initialization model is used for acquiring and decoding the clock-on reset instruction data from the program file in the storage model, and carrying out clock-on reset on the performance core based on the decoded clock-on reset instruction data; the preloader model is used for preloading the program file in the storage model into a cache of the performance core, so that the performance core can acquire target instruction data from the program file in the cache and decode the target instruction data when initiating an instruction data request of a cache attribute from the front end of the performance core. According to the embodiment of the invention, the starting speed of the CPU core in a research and development verification environment can be improved.

Description

Technical Field

[0001] The present invention relates to the field of CPU core technology, and more particularly to a method and device for accelerating the startup of a CPU core in a research and development verification environment. Background Art

[0002] The CPU is the most important component in a computer system, used to control the entire computer to complete the tasks specified by the characteristic program. In the scenario of high-performance CPU development, the CPU hardware system can generally be simply classified into two parts: performance core (CORE) and non-core (UNCORE). The CORE is the main functional part, responsible for scheduling and computing tasks such as instruction fetching, decoding, and execution; the UNCORE includes the control core and various peripherals of the peripheral system on chip (SOC), which are used to manage the CPU power, clock reset, peripheral data transmission, event communication and other functions.

[0003] The CORE boot process (boot up) generally includes the control core startup, peripheral system configuration, and performance core boot and load startup. As the CPU area becomes larger and larger and more and more peripherals need to be managed, and in order to take into account more diverse application scenarios, the industry gradually tends to package the CORE and UNCORE parts separately, so that the same COREDIE can match different peripheral parts, thereby deriving CPUs of different specifications and improving the diversification of the product line. As for the relatively lengthy CPU boot up process, the CORE R&D department can invest more energy in the CORE boot up itself in the early stage, ignoring the configuration and initialization of the peripheral system, thereby improving the early iteration efficiency of the product.

[0004] However, the existing CORE boot up process is generally adapted to the complete CPU, most of which are not concerned in the CORE design stage, but a lot of effort has to be invested in sorting out the specifications of the peripheral UNCORE for adaptability modification, or the boot is delayed due to the progress of the CORE and UNCORE path specification modification. Therefore, how to improve the CPU core boot speed in the R&D verification environment has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of the embodiments of this specification is to provide a method and device for accelerating the startup of a CPU core in a research and development verification environment, so as to improve the startup speed of the CPU core in the research and development verification environment.

[0006] To achieve the above-mentioned purpose, on the one hand, the embodiments of this specification provide a startup acceleration device for a CPU core in a research and development verification environment, including an initialization model, a pre-loader model and a storage model;

[0007] The storage model is used to store program files, so that when the performance core initiates a non-cacheable instruction data request from its front end, the target instruction data can be obtained and decoded from the program files in the storage model;

[0008] The initialization model is used to decode the clock-on reset instruction data obtained from the program file in the storage model, and perform clock-on reset on the performance core based on the decoded clock-on reset instruction data;

[0009] The preloader model is used to preload the program files in the storage model into the cache of the performance core, so that when the performance core initiates an instruction data request with cache attributes from its front end, it can obtain and decode the target instruction data from the program files in the cache.

[0010] The CPU core of the embodiment of this specification obtains and decodes target instruction data from the program file in the storage model in the startup acceleration device in the R&D verification environment, including:

[0011] If the performance core does not define a data interface, the target instruction data is obtained and decoded from the program file in the storage model through the cache and the bypass interface connecting the cache and the storage model in sequence.

[0012] The CPU core of the embodiment of this specification obtains and decodes target instruction data from the program file in the storage model in the startup acceleration device in the R&D verification environment, including:

[0013] If the performance core has defined a data interface, the instruction data request is sent to the data interface after protocol conversion, so as to obtain and decode the target instruction data from the program file in the storage model through the data interface.

[0014] In the startup acceleration device of the CPU core in the R&D verification environment of the embodiment of this specification, the cache of the performance core includes the outermost cache of the performance core.

[0015] In the startup acceleration device of the CPU core in the R&D verification environment of the embodiment of this specification, the initialization model, the preloader model and the storage model are all hardware circuit models defined based on a hardware description language.

[0016] In the startup acceleration device of the CPU core in the embodiment of this specification in the R&D verification environment, the preloader model is pre-built based on the physical structure of the cache.

[0017] On the other hand, the embodiment of this specification also provides a startup acceleration method for a CPU core in a research and development verification environment based on the startup acceleration device, including:

[0018] Move program files to storage model;

[0019] preloading the program files in the storage model into the cache of the performance core;

[0020] Decoding the clock-on reset instruction data obtained from the program file in the storage model, and performing a clock-on reset on the performance core based on the decoded clock-on reset instruction data;

[0021] When the performance core initiates a cache-attributed instruction data request from its front end, the target instruction data is obtained from the program file in the cache and decoded; or,

[0022] When the performance core initiates a non-cacheable instruction data request from its front end, target instruction data is obtained from the program file in the storage model and decoded.

[0023] In the startup acceleration method of the CPU core in the R&D verification environment of the embodiment of this specification, the target instruction data is obtained from the program file in the storage model and decoded, including:

[0024] If the performance core does not define a data interface, the target instruction data is obtained and decoded from the program file in the storage model through the cache and the bypass interface connecting the cache and the storage model in sequence.

[0025] In the startup acceleration method of the CPU core in the R&D verification environment of the embodiment of this specification, the target instruction data is obtained from the program file in the storage model and decoded, including:

[0026] If the performance core has defined a data interface, the instruction data request is sent to the data interface after protocol conversion, so as to obtain and decode the target instruction data from the program file in the storage model through the data interface.

[0027] On the other hand, an embodiment of the present specification further provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein when the computer program is executed by the processor, the instructions of the above method are executed.

[0028] On the other hand, an embodiment of the present specification further provides a computer storage medium on which a computer program is stored. When the computer program is executed by a processor of a computer device, the instructions of the above method are executed.

[0029] On the other hand, an embodiment of the present specification further provides a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor of a computer device, the computer program executes instructions of the above method.

[0030] It can be seen from the technical solutions provided in the above embodiments of this specification that, in the embodiments of this specification, during the research and development verification stage of the performance core (CORE), the non-core part (UNCORE) and the memory (DRAM) in the CPU are replaced by a boot acceleration device of functional abstract simulation, so that the boot up of the CORE can be transformed from dependence on UNCORE and DRAM to dependence on the boot acceleration device of functional abstract simulation, thereby avoiding the impact of the delay in the adaptation of the CORE and UNCORE specifications, and further accelerating the boot up speed of the CORE. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art description. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. In the drawings:

[0032] Figure 1 The schematic diagram of the startup acceleration principle of the CPU core in the R&D verification environment in the prior art is shown;

[0033] Figure 2 A schematic diagram showing the principle of a startup acceleration device for a CPU core in a research and development verification environment in some embodiments of this specification is shown;

[0034] Figure 3 Shows Figure 2 A schematic diagram of the connection relationship between the outermost cache of the performance core and the storage model in the illustrated embodiment;

[0035] Figure 4 A flowchart of a method for accelerating the startup of a CPU core in a research and development verification environment in some embodiments of this specification is shown;

[0036] Figure 5 The structure block diagram of the computer device in some embodiments of the present specification is shown.

[0037] [Description of Reference Numerals]

[0038] 10. Start the acceleration device;

[0039] 11. Storage model;

[0040] 12. Preloader model;

[0041] 13. Initialize the model;

[0042] 14. Bypass interface;

[0043] 15. Data interface;

[0044] 20. Performance core;

[0045] 30. Program files;

[0046] 502. Computer equipment;

[0047] 504, processor;

[0048] 506. Memory;

[0049] 508, driving mechanism;

[0050] 510, input / output interface;

[0051] 512. Input devices;

[0052] 514. Output device;

[0053] 516. Presentation equipment;

[0054] 518. Graphical user interface;

[0055] 520, network interface;

[0056] 522, communication link;

[0057] 524. Communication bus. DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this specification.

[0059] Figure 1The traditional CORE startup process is shown in . In this CORE startup process, the program is moved to the dynamic random access memory (DRAM) in advance, and the control core (ManageProcesser, MP) obtains its own program from DRAM and resets the CORE and the third-level cache (Level 3Cache, L3C). The CORE initiates an instruction data (program) move request from the front end (FrontEnd). The instruction data starts from DRAM and passes through L3C and the second-level cache (Level 2Cache, L2C) to the FrontEnd, and the instruction decoding is completed in the FrontEnd. In addition to initializing the CORE itself, the content of the startup program also includes the initialization of the peripherals in the UNCORE.

[0060] It can be seen that the traditional CORE boot process relies on the normal function and clear specifications of the UNCORE part, and the premise is that the data path connection between the CORE and the UNCORE meets the expected functions. In other words, the existing CORE boot up process needs to adapt to the complete CPU, most of which do not need to be paid attention to during the CORE design stage, but a lot of effort has to be invested in sorting out the specifications of the peripheral UNCORE for adaptability modification, or the startup is delayed due to the progress of modifying the specifications of the communication path between the CORE and the UNCORE. This will affect the CORE boot up progress and the early debugging work.

[0061] In view of this, the embodiments of this specification provide a CPU core startup acceleration device and method in a research and development verification environment to improve the startup speed of the CPU core in the research and development verification environment.

[0062] Figure 2The schematic diagram of the CPU core startup acceleration device in the R&D verification environment in some embodiments of the present specification is shown in the figure; the startup acceleration device 10 is an abstract simulation of the functions of UNCORE and DRAM in the CPU to complete the data and process support in the CORE startup process, thereby avoiding the influence of the UNCORE part on the CORE startup process. The startup acceleration device 10 may include a storage model (MemModel) 11, a preloader model (Preloader) 12 and an initialization model (Init) 13. The storage model 11 is used to store the program file 30, so that when the performance core 20 (i.e., the CORE of the CPU) initiates a non-cachable instruction data request from its front end (FrontEnd), it can obtain the target instruction data (here, the instruction data required for the performance core 20 to start) from the program file (Program) 30 in the storage model 11 and decode it; the initialization model 13 is used to decode the clock reset instruction data obtained from the program file 30 in the storage model 11, and perform clock reset on the performance core 20 based on the decoded clock reset instruction data; the preloader model 12 is used to preload the program file 30 in the storage model 11 into the outermost cache of the performance core 20, so that when the performance core 20 initiates a cacheable instruction data request from its FrontEnd, it can obtain the target instruction data from the program file 30 in the outermost cache and decode it. In this article, FrontEnd represents the functional part of CORE except the outermost cache.

[0063] In the embodiments of this specification, during the R&D verification stage of CORE, UNCORE and DRAM in the CPU are replaced by a boot acceleration device of functional abstract simulation, so that the boot up of CORE can be transformed from dependence on UNCORE and DRAM to dependence on a boot acceleration device of functional abstract simulation (i.e., simple functional abstraction), thereby avoiding the impact of delayed adaptation of CORE and UNCORE specifications (i.e., removing the initialization content of some peripherals of UNCORE from the boot up of CORE, and finally achieving the purpose of completely shielding the impact of UNCORE changes), and thus accelerating the boot up speed of CORE. In this way, a CORE-level fast debugging method is provided for CORE R&D, so that there is no need to invest a lot of energy to adaptably provide clear specifications of UNCORE in the process of R&D verification of CORE adaptation to different UNCOREs.

[0064] In some embodiments of the present specification, the storage model, preloader model and initialization model can all be hardware circuit models defined based on a hardware description language (HDL). For example, in an exemplary embodiment of the present specification, the storage model, preloader model and initialization model can be defined based on Systemverilog language, Verilog language, etc.

[0065] Combination Figure 3 As shown, in some embodiments of the present specification, the storage model 11 in the startup acceleration device 10 can be connected to the outermost cache of the performance core 20 through the bypass interface (bypass interface) 14 and the data interface 15. Among them, the data interface 15 refers to the top-level data communication interface between CORE and UNCORE. In some embodiments of the present specification, when the performance core 20 does not define the data interface 15, the storage model 11 can communicate with the outermost cache of the performance core 20 through the bypass interface 14; in this way, when the data interface 15 of the performance core 20 is not defined, the bypass interface 14 can ensure that the storage model 11 can still work normally. In this case, obtaining the target instruction data from the program file in the storage model 11 and decoding it includes: if the performance core 20 does not define the data interface 15, then the target instruction data can be obtained from the program file in the storage model 11 and decoded through the outermost cache and the bypass interface 14 connecting the outermost cache and the storage model 11 in sequence.

[0066] In some embodiments of the present specification, when the performance core 20 has defined a data interface 15 (for example, defined as a Cbox interface, etc.), the storage model 11 can communicate with the outermost cache of the performance core 20 through the data interface 15 of the performance core 20; in this way, the startup simulation of the explicit UNCORE part can be implemented. In this case, obtaining and decoding the target instruction data from the program file in the storage model 11 includes: if the performance core 20 has defined a data interface 15, the instruction data request can be sent to the data interface 15 after protocol conversion, so as to obtain and decode the target instruction data from the program file in the storage model 11 through the data interface 15.

[0067] In some embodiments of the present specification, a defined data interface 15 may mean that the signal line name, the number of signal lines, and the signal behavior (i.e., the communication protocol) of the data interface 15 have been defined. Correspondingly, an undefined data interface 15 may mean that at least one of the signal line name, the number of signal lines, and the signal behavior of the data interface 15 has not been defined.

[0068] In addition, both the preloader model and the initialization model can communicate with the CORE through a simulated hardware data communication interface (signal line).

[0069] In other embodiments of the present specification, considering that the CPU has multiple architectures (such as x86, ARM, RISC-V, etc.), when the data interface of the CORE is not defined, it is possible for the CORE and UNCORE under different CPU architectures to communicate data through other interfaces with similar functions to the bypass interface. Therefore, in some embodiments of the present specification, when the data interface of the CORE is not defined, the data communication between the CORE and the UNCORE is realized through the bypass interface. This is only used as an illustrative example and should not be understood as the sole limitation on the embodiments of the present specification.

[0070] In some embodiments of the present specification, the preloader model can be pre-built based on the physical structure of the outermost cache of the performance core; when the preloader model pre-loads the program files in the storage model into the outermost cache, the data originally stored in a physical address in the storage model can be directly loaded into the corresponding storage unit position inside the outermost cache, and the mapping position of this physical address in the outermost cache is strongly related to the physical structure of the outermost cache; in this way, the effect of simulating the performance core loading its own outermost cache can be achieved. Therefore, as long as the physical structure of the outermost cache of the CORE is not significantly adjusted, even if the data interface 15 of the CORE is in an undefined state, the FrontEnd of the CORE can still directly hit the outermost cache and obtain the data required for startup from it, thereby saving the time-consuming overhead of the CORE communicating with the outside.

[0071] For example, the preloader model defined based on the SystemVerilog language can specify the value of a specific circuit-level signal at a specified time, that is, the preloader model can complete the mapping from the physical address to the specific circuit level, thereby changing the original "program file is loaded to a specific physical address" to "program file is loaded to the circuit-level signal of the outermost cache (that is, the physical unit of the outermost cache)".

[0072] In some embodiments of the present specification, the initialization model 13 is an abstract simulation of the functions of the MP in the UNCORE, so as to replace the MP in resetting the CORE.

[0073] It should be noted that the outermost cache of the above-mentioned performance core is only used as an exemplary illustration, and the purpose is to enable the startup process of the CPU core in the R&D verification environment to cover as long a communication path as possible. For example, in an exemplary embodiment of the present specification, if the performance core has a first-level cache (L1C) and a second-level cache (L2C), the outermost cache of the performance core is L2C; in another exemplary embodiment of the present specification, if the performance core only has L1C, the outermost cache of the performance core is L1C. Therefore, in the embodiments of the present specification, the outermost cache of the performance core depends on the specific circumstances of the hierarchical or layered architecture of the cache of the performance core.

[0074] In other embodiments of the present specification, according to actual needs, the outermost cache of the above-mentioned performance core can also be replaced by any designated cache of the performance core (not necessarily its outermost cache).

[0075] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0076] Based on the above-mentioned CPU core startup acceleration device in a research and development verification environment, this specification embodiment provides a CPU core startup acceleration method in a research and development verification environment, referring to Figure 4 As shown, in some embodiments of this specification, the startup acceleration method of the CPU core in the R&D verification environment may include the following steps:

[0077] Step 401: Move the program file to the storage model.

[0078] In some embodiments of the present specification, program files can be moved from external storage (such as a hard disk, an optical disk, a USB flash drive, etc.) to the storage model.

[0079] Step 402: preload the program files in the storage model into the outermost cache of the performance core.

[0080] In some embodiments of the present specification, the program files in the storage model can be preloaded into the outermost cache of the performance core through a preloader model, so that the performance core can be obtained on demand during subsequent startup.

[0081] Step 403: decode the clock-on reset instruction data obtained from the program file in the storage model, and perform a clock-on reset on the performance core based on the decoded clock-on reset instruction data.

[0082] In some embodiments of the present specification, the clock reset instruction data obtained from the program file in the storage model can be decoded by the initialization model, and the performance core can be reset based on the decoded clock reset instruction data. The clock reset is a reset operation (such as hardware reset, software reset and power-on reset) on the clock of the performance core.

[0083] Step 404: when the performance core initiates a request for instruction data with cache attributes from its front end, the target instruction data is obtained from the program file in the outermost cache and decoded; or, when the performance core initiates a request for instruction data with non-cache attributes from its front end, the target instruction data is obtained from the program file in the storage model and decoded.

[0084] In some embodiments of the present specification, when the performance core initiates an instruction data request with a non-cacheable attribute (i.e., a non-cacheable attribute) from its front end, obtaining target instruction data from a program file in the storage model and decoding the target instruction data include: if the performance core does not define a data interface, then obtaining the target instruction data from the program file in the storage model and decoding the target instruction data through the outermost cache and a bypass interface connecting the outermost cache and the storage model in sequence.

[0085] In some embodiments of the present specification, when the performance core initiates an instruction data request with a non-cacheable attribute (i.e., a non-cacheable attribute) from its front end, obtaining target instruction data from a program file in the storage model and decoding it also includes: if the performance core has defined a data interface, the instruction data request is sent to the data interface after protocol conversion, so as to obtain the target instruction data from the program file in the storage model through the data interface and decode it.

[0086] In some embodiments of the present specification, when the performance core initiates an instruction data request with a cache attribute (i.e., a cacheable attribute) from its front end, if the target instruction data is not stored in the outermost cache, the target instruction data can be obtained and decoded from the program file in the storage model. That is, if the target instruction data is not stored in the outermost cache, the target instruction data can also be obtained and decoded from the program file in the storage model through the outermost cache and the bypass interface connecting the outermost cache and the storage model.

[0087] Although the process flows described above include multiple operations that occur in a particular order, it should be clearly understood that the processes may include more or fewer operations, which may be performed sequentially or in parallel (eg, using parallel processors or a multi-threaded environment).

[0088] It should be noted that in the embodiments of this specification, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) that may be involved are all information and data that have been authorized and agreed by the user and fully authorized by all parties, that is, the acquisition, transmission, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations.

[0089] The embodiments of this specification also provide a computer device. Figure 5 As shown, in some embodiments of the present specification, the computer device 502 may include one or more processors 504, such as one or more central processing units (CPUs) or graphics processing units (GPUs), and each processing unit may implement one or more hardware threads. The computer device 502 may also include any memory 506, which is used to store any kind of information such as code, settings, data, etc. In a specific embodiment, the computer program on the memory 506 and can be run on the processor 504, when the computer program is run by the processor 504, can execute the instructions of the startup acceleration method of the CPU core in the R&D verification environment described in any of the above embodiments. Non-limiting, for example, the memory 506 may include any one or more combinations of the following: any type of RAM, any type of ROM, flash memory device, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory can represent a fixed or removable component of the computer device 502. In one embodiment, when the processor 504 executes the associated instructions stored in any memory or combination of memories, the computer device 502 can perform any operation of the associated instructions. The computer device 502 also includes one or more drive mechanisms 508 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0090] The computer device 502 may also include an input / output interface 510 (I / O) for receiving various inputs (via input devices 512) and for providing various outputs (via output devices 514). A specific output mechanism may include a presentation device 516 and an associated graphical user interface 518 (GUI). In other embodiments, the input / output interface 510 (I / O), input device 512, and output device 514 may not be included, and the computer device 502 may be used as a computer device in a network. The computer device 502 may also include one or more network interfaces 520 for exchanging data with other devices via one or more communication links 522. One or more communication buses 524 couple the components described above together.

[0091] The communication link 522 may be implemented in any manner, for example, through a local area network, a wide area network (e.g., the Internet), a point-to-point connection, etc., or any combination thereof. The communication link 522 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc. governed by any protocol or combination of protocols.

[0092] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), computer-readable storage media, and computer program products of some embodiments of the present specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processor to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processor generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0093] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processor to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0094] These computer program instructions can also be loaded onto a computer or other programmable data processor so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0095] In a typical configuration, a computer device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0096] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0097] Computer-readable media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computer device. As defined in this specification, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0098] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, the embodiments of this specification may take the form of complete hardware embodiments, complete software embodiments or embodiments combining software and hardware. Moreover, the embodiments of this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0099] The present specification embodiments may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present specification embodiments may also be practiced in distributed computing environments where tasks are performed by remote processors connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0100] It should also be understood that in the embodiments of this specification, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0101] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0102] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of this specification. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0103] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A CPU core startup acceleration device in a research and development verification environment, characterized in that: Includes initialization model, preloader model and storage model; The storage model is used to store program files, so that when the performance core initiates a non-cacheable instruction data request from its front end, the target instruction data can be obtained and decoded from the program files in the storage model; The initialization model is used to decode the clock-on reset instruction data obtained from the program file in the storage model, and perform clock-on reset on the performance core based on the decoded clock-on reset instruction data; The preloader model is used to preload the program files in the storage model into the cache of the performance core, so that when the performance core initiates an instruction data request with cache attributes from its front end, it can obtain and decode the target instruction data from the program files in the cache.

2. The CPU core startup acceleration device in a research and development verification environment as claimed in claim 1, characterized in that: Obtaining target instruction data from a program file in the storage model and decoding the data comprises: If the performance core does not define a data interface, the target instruction data is obtained and decoded from the program file in the storage model through the cache and the bypass interface connecting the cache and the storage model in sequence.

3. The CPU core startup acceleration device in a research and development verification environment as claimed in claim 1, characterized in that: Obtaining target instruction data from a program file in the storage model and decoding the data comprises: If the performance core has defined a data interface, the instruction data request is sent to the data interface after protocol conversion, so as to obtain and decode the target instruction data from the program file in the storage model through the data interface.

4. The CPU core startup acceleration device in a research and development verification environment as claimed in claim 1, characterized in that: The cache of the performance core includes the outermost cache of the performance core.

5. The CPU core startup acceleration device in a research and development verification environment as claimed in claim 1, characterized in that: The initialization model, the preloader model and the storage model are all hardware circuit models defined based on a hardware description language.

6. The CPU core startup acceleration device in a research and development verification environment as claimed in claim 1, characterized in that: The preloader model is pre-built based on the physical structure of the cache.

7. A startup acceleration method for a CPU core in a research and development verification environment based on the startup acceleration device of claim 1, characterized in that: include: Move program files to storage model; preloading the program files in the storage model into the cache of the performance core; Decoding the clock-on reset instruction data obtained from the program file in the storage model, and performing a clock-on reset on the performance core based on the decoded clock-on reset instruction data; When the performance core initiates a request for instruction data with cache attributes from its front end, the target instruction data is obtained from the program file in the cache and decoded; or, When the performance core initiates a non-cacheable instruction data request from its front end, target instruction data is obtained from the program file in the storage model and decoded.

8. The startup acceleration method according to claim 7, characterized in that: Obtaining target instruction data from a program file in the storage model and decoding the data comprises: If the performance core does not define a data interface, the target instruction data is obtained and decoded from the program file in the storage model through the cache and the bypass interface connecting the cache and the storage model in sequence.

9. The startup acceleration method according to claim 7, characterized in that: Obtaining target instruction data from a program file in the storage model and decoding the data comprises: If the performance core has defined a data interface, the instruction data request is sent to the data interface after protocol conversion, so as to obtain and decode the target instruction data from the program file in the storage model through the data interface.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that: When the computer program is executed by the processor, the computer program executes the instructions of the method according to any one of claims 7 to 9.

11. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor of a computer device, the computer program executes the instructions of the method according to any one of claims 7 to 9.

12. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor of a computer device, the computer program executes instructions of the method according to any one of claims 7 to 9.

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