Construction method and device of application performance prediction model and related equipment

Abstract

The invention provides a construction method and device of an application performance prediction model and related equipment. The method comprises the steps of firstly obtaining a first performance bottleneck and a second performance bottleneck corresponding to an application; wherein the first performance bottleneck is the performance bottleneck when the chip operates the application at the first frequency, and the second performance bottleneck is the performance bottleneck when the chip operates the application at the second frequency; and determining a performance prediction model corresponding to the application according to the first performance bottleneck and the second performance bottleneck. Wherein under the condition that the first performance bottleneck and the second performance bottleneck are different, a performance prediction model is determined through a curve fitting method; and determining a performance prediction model through a linear fitting method under the condition that the first performance bottleneck and the second performance bottleneck are the same. According to the method, the performance prediction model for predicting the application performance can be quickly constructed only by acquiring the performance bottlenecks under the two different frequencies, and the efficiency of constructing the performance prediction model is high.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device and related equipment for constructing an application performance prediction model. Background Art

[0002] Dynamic voltage and frequency scaling (DVFS) dynamically adjusts the chip voltage and frequency according to the computing requirements of the application running on the chip. When the application does not require high performance, the voltage and frequency are reduced to reduce power consumption. When the application requires high performance, the voltage and frequency are increased to improve performance, thereby achieving the goal of balancing performance and power consumption. Therefore, in the DVFS scenario, it is necessary to predict the performance of the application when it runs at different frequencies of the chip in order to dynamically adjust the voltage and frequency of the chip. For a given chip, how to predict the performance of the application when it is executed at different frequencies of the chip is a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present application provides a method, apparatus and related equipment for constructing an application performance prediction model, which can quickly construct a prediction model for predicting the performance of an application when running at different frequencies, thereby improving the efficiency of constructing the performance prediction model.

[0004] In the first aspect, the present application provides a method for constructing an application performance prediction model, wherein a computing device first obtains a first performance bottleneck when a chip runs an application at a first frequency and a second performance bottleneck when the chip runs at a second frequency; then, according to whether the first performance bottleneck and the second performance bottleneck are the same, a performance prediction model corresponding to the application is determined. Wherein, when the first performance bottleneck and the second performance bottleneck are not the same, the performance prediction model is determined by a curve fitting method; when the first performance bottleneck and the second performance bottleneck are the same, the performance prediction model is determined by a linear fitting method, wherein the input of the performance prediction model is a frequency, and the output is the number of cycles required for the chip to run the above application at the frequency.

[0005] Through the above method, when it is necessary to predict the performance of an application running at a certain frequency, the computing device only needs to obtain the performance bottleneck when the chip runs the application at two different frequencies, and can quickly build a performance prediction model for predicting application performance, which can improve the efficiency of building a performance prediction model.

[0006] In addition, since the first performance bottleneck and the second performance bottleneck are different, it means that the performance bottleneck of the application will change during the change of the chip frequency. Therefore, during the change of the chip frequency, the change law of the number of cycles required for the chip to run the application at different frequencies will be more complicated. If a function is used to represent the relationship between the number of cycles required to run the application and the frequency, multiple piecewise functions will be involved. Therefore, the curve fitting method is used to determine the performance model, which can improve the accuracy of the performance prediction model. Since the first performance bottleneck and the second performance bottleneck are the same, it means that during the change of the chip frequency, the change law of the number of cycles required for the chip to run the application at different frequencies will be simpler. Therefore, the linear fitting method is used to determine the performance model, which can reduce the amount of calculation and improve the efficiency of building the performance prediction model.

[0007] In a possible implementation, the first frequency is greater than a bandwidth saturation frequency corresponding to the application, and the second frequency is less than a bandwidth saturation frequency corresponding to the application; wherein the bandwidth saturation frequency refers to the bandwidth saturation frequency corresponding to the application when the chip runs the application.

[0008] In a possible implementation, the first frequency is the highest frequency in the test frequency range, and the second frequency is the lowest frequency in the test frequency range. For example, when the test frequency range is the frequency range that the chip can reach, the first frequency is the highest frequency of the chip, and the second frequency is the lowest frequency of the chip. It should be understood that the highest frequency and the lowest frequency of the chip are both theoretical frequencies, and the chip may not be able to reach or maintain the lowest frequency or the highest frequency. Therefore, the first frequency may also be a frequency whose difference with the highest frequency is less than a first threshold, and the second frequency may also be a frequency whose difference with the lowest frequency is less than a second threshold.

[0009] In a possible implementation, the method further includes: determining, according to a performance prediction model, the number of cycles required for the chip to run an application at a third frequency, where the third frequency is any frequency that can be achieved by the chip.

[0010] After obtaining the performance prediction model corresponding to the above application, if you want to predict the number of cycles required for the chip to execute the application at a certain frequency, you can use the frequency as the input of the performance prediction model. The performance prediction model can output the number of cycles required for the chip to run the application at the frequency. The performance of the application predicted by the performance prediction model is highly accurate.

[0011] In a possible implementation, the method further includes: determining a bandwidth saturation frequency corresponding to the application according to the in-core bandwidth of the chip, the out-core bandwidth of the chip, and the number of cores running the application.

[0012] In a possible implementation, the above-mentioned determining a performance prediction model corresponding to the application based on the first performance bottleneck and the second performance bottleneck includes: when the first performance bottleneck and the second performance bottleneck are different, the computing device obtains a first number of cycles used by the chip to run the application at a first frequency and a second number of cycles used by the chip to run the application at a second frequency; and then determines the parameters of the above-mentioned performance prediction model by a curve fitting method according to the first frequency, the first number of cycles, the second frequency, the second number of cycles and the bandwidth saturation frequency corresponding to the application to obtain the performance prediction model.

[0013] When the first performance bottleneck is obtained according to the first frequency, the above-mentioned first cycle number can be obtained. When the second performance bottleneck is obtained according to the second frequency, the above-mentioned second cycle number can be obtained. The bandwidth saturation frequency is related to the parameters of the chip that have been determined. Therefore, when it is necessary to build a performance prediction model, it is only necessary to obtain the relevant parameters of the chip when running the application at two different frequencies to build the above-mentioned performance prediction model, which can improve the efficiency of building the performance prediction model.

[0014] In a possible implementation, the above-mentioned determining a performance prediction model corresponding to the application based on the first performance bottleneck and the second performance bottleneck includes: when the first performance bottleneck and the second performance bottleneck are different, the computing device obtains a first number of cycles used by the chip to run the application at a first frequency and a second number of cycles used by the chip to run the application at a second frequency; and then determines the parameters of the above-mentioned performance prediction model by a linear fitting method based on the first frequency, the first number of cycles, the second frequency, the second number of cycles and the bandwidth saturation frequency corresponding to the application to obtain the performance prediction model.

[0015] In a second aspect, the present application provides an application performance prediction model construction device, which includes: an acquisition module, used to obtain a first performance bottleneck and a second performance bottleneck corresponding to the application; a processing module, used to determine the performance prediction model corresponding to the application based on whether the first performance bottleneck and the second performance bottleneck are the same; wherein, when the first performance bottleneck and the second performance bottleneck are not the same, the performance prediction model is determined by a curve fitting method; when the first performance bottleneck and the second performance bottleneck are the same, the performance prediction model is determined by a linear fitting method, wherein the input of the performance prediction model is a frequency, and the output is the number of cycles required for the chip to run the above-mentioned application at the frequency.

[0016] In a possible implementation, the first frequency is greater than a bandwidth saturation frequency corresponding to the application, and the second frequency is less than a bandwidth saturation frequency corresponding to the application; wherein the bandwidth saturation frequency refers to the bandwidth saturation frequency corresponding to the application when the chip runs the application.

[0017] In a possible implementation, the first frequency is the highest frequency in the test frequency range, and the second frequency is the lowest frequency in the test frequency range. For example, when the test frequency range is the frequency range that the chip can reach, the first frequency is the highest frequency of the chip, and the second frequency is the lowest frequency of the chip. It should be understood that the highest frequency and the lowest frequency of the chip are both theoretical frequencies, and the chip may not be able to reach or maintain the lowest frequency or the highest frequency. Therefore, the first frequency may also be a frequency whose difference with the highest frequency is less than a first threshold, and the second frequency may also be a frequency whose difference with the lowest frequency is less than a second threshold.

[0018] In a possible implementation, the processing module is further used to: determine the number of cycles required for the chip to run an application at a third frequency according to a performance prediction model, where the third frequency is any frequency that can be achieved by the chip.

[0019] After obtaining the performance prediction model corresponding to the above application, if you want to predict the number of cycles required for the chip to execute the application at a certain frequency, you can use the frequency as the input of the performance prediction model, and the performance prediction model can output the number of cycles required for the chip to run the application at this frequency.

[0020] In a possible implementation, the processing module is further used to determine a bandwidth saturation frequency corresponding to the application according to the in-core bandwidth of the chip, the out-core bandwidth of the chip, and the number of cores running the application.

[0021] In a possible implementation, when the processing module determines the performance prediction model corresponding to the application based on the first performance bottleneck and the second performance bottleneck, the processing module is specifically used to: when the first performance bottleneck and the second performance bottleneck are different, the computing device obtains the first number of cycles used by the chip to run the application at the first frequency and the second number of cycles used by the chip to run the application at the second frequency; then, based on the first frequency, the first number of cycles, the second frequency, the second number of cycles and the bandwidth saturation frequency corresponding to the application, determine the parameters of the performance prediction model by a curve fitting method to obtain the performance prediction model.

[0022] In a possible implementation, the processing module determines a performance prediction model corresponding to the application based on the first performance bottleneck and the second performance bottleneck. The processing module is specifically used for: when the first performance bottleneck and the second performance bottleneck are different, the computing device obtains the first number of cycles used by the chip to run the application at the first frequency and the second number of cycles used by the chip to run the application at the second frequency; then, based on the first frequency, the first number of cycles, the second frequency, the second number of cycles and the bandwidth saturation frequency corresponding to the application, the parameters of the performance prediction model are determined by a linear fitting method to obtain the performance prediction model.

[0023] In a third aspect, the present application provides a computing device, which includes a processor and a memory, the memory is used to store instructions, and the processor is used to execute the instructions. When the processor executes the instructions, it implements the method described in the first aspect or any possible implementation method of the first aspect.

[0024] In a fourth aspect, the present application provides a computer program product, which, when executed on a computing device, enables the computing device to execute the method described in the first aspect or any possible implementation of the first aspect.

[0025] In a fifth aspect, the present application provides a computer-readable storage medium, which stores instructions. When the instructions are executed on a computing device, the computing device executes the method described in the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0027] Figure 1 is a schematic diagram of an application performance prediction method provided in an embodiment of the present application;

[0028] Figure 2 It is a flowchart of an application performance prediction method provided in an embodiment of the present application;

[0029] Figure 3 is a schematic diagram of the relationship between the available bandwidth and chip frequency of an application provided in an embodiment of the present application;

[0030] Figure 4 is a schematic diagram of the relationship between the number of cycles and the frequency of a chip provided in an embodiment of the present application;

[0031] Figure 5 is a schematic diagram of an application performance prediction model building device provided in an embodiment of the present application;

[0032] Figure 6 It is a schematic diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0034] Dynamic voltage and frequency scaling (DVFS) is essentially a low-power technology that dynamically adjusts the voltage and frequency of the processor according to the needs of the application running on the device to achieve energy optimization and performance balance. When the application is idle or requires lower computing performance, the frequency and voltage can be reduced to reduce power consumption. When the application requires higher computing performance, the voltage and frequency can be increased to meet the performance requirements.

[0035] During the running of current applications, due to data dependency and other reasons, the computing units of the chip running the application cannot be fully utilized. For example, for memory-bound applications, the computing unit utilization is low. If the chip maintains a high frequency, it will cause energy waste. In this case, the DVFS technology can be used to reduce the frequency and voltage of the chip, thereby reducing power consumption. Therefore, it is necessary to use the DVFS technology to adjust the frequency and voltage of the chip according to the performance of the application.

[0036] The performance of an application can be measured by the number of cycles or runtime required by a chip to run the application. The longer the runtime, the lower the performance of the application, and the shorter the runtime, the higher the performance of the application. Therefore, for an application and a chip running the application, the performance of the application at the current frequency can be measured by predicting the runtime of the application at a frequency.

[0037] This application provides an application performance prediction method, such as Figure 1 As shown, Figure 1 It is a schematic diagram of an application performance prediction method provided in an embodiment of the present application.

[0038] After determining an application and a chip running the application, if the performance of the application when running the application at the third frequency of the chip is to be predicted, the application is first run at the first frequency of the chip to determine the first performance bottleneck corresponding to the first frequency; the application is run at the second frequency of the chip to determine the second performance bottleneck corresponding to the second frequency; and the bandwidth saturation frequency of the application is determined according to the relevant chip parameters of the chip. Among them, the performance bottleneck of the application includes memory bottleneck (memory bound), computing bottleneck (compute bound), etc.; the chip parameters include the chip's out-of-core bandwidth, the chip's in-core bandwidth, and the number of processor cores executing the application. Then, it is determined whether the performance bottlenecks of the application at different frequencies are the same. If the first performance bottleneck and the second performance bottleneck are not the same, the number of cycles required for the application to be executed at the third frequency is determined by the first performance prediction model, the third frequency and the above-mentioned bandwidth saturation frequency; if the first performance bottleneck and the second performance bottleneck are the same, the number of cycles required for the application to be executed at the third frequency is determined by the second performance prediction model, the third frequency and the above-mentioned bandwidth saturation frequency; the running time of the application at the third frequency can be determined by the number of cycles.

[0039] The following is a detailed description of the application performance prediction method provided by the present application in conjunction with the accompanying drawings. Figure 2 As shown, Figure 2 It is a flowchart of an application performance prediction method provided in an embodiment of the present application.

[0040] S201. Obtain a first performance bottleneck and a second performance bottleneck corresponding to an application.

[0041] The first performance bottleneck is the performance bottleneck of the application when the chip runs the application at the first frequency, and the second performance bottleneck is the performance bottleneck of the application when the chip runs the application at the second frequency. Performance bottlenecks include memory bottlenecks and computing bottlenecks, etc.; the first frequency is greater than the second frequency, the first frequency is greater than the bandwidth saturation frequency corresponding to the application, the second frequency is less than the bandwidth saturation frequency corresponding to the application, and the bandwidth saturation frequency corresponding to the application refers to the bandwidth saturation frequency of the application when the chip runs the application.

[0042] In a possible implementation, the first frequency is the highest frequency in the test frequency range, and the second frequency is the lowest frequency in the above test frequency range. For example, when the test frequency range is the frequency range that the chip can reach, that is, when the test frequency range is the lowest frequency to the highest frequency of the chip, the above first frequency can be the highest frequency of the chip, and the second frequency can be the lowest frequency of the chip; for another example, the highest frequency of the chip is 6.0 GHz, but the test frequency range is 1.8 GHz to 3.2 GHz, then the first frequency is 3.2 GHz, and the second frequency is 1.8 GHz, and the embodiment of the present application is not specifically limited. It should be understood that the highest frequency and the lowest frequency of the chip are both theoretical frequencies, and the chip may not necessarily reach or maintain the lowest frequency or the highest frequency, so the first frequency may also be a frequency whose difference with the highest frequency is less than the first threshold, and the second frequency may also be a frequency whose difference with the lowest frequency is less than the second threshold.

[0043] In an embodiment of the present application, after determining the application to be run and the chip running the application, the computing device runs the application once at the first frequency and the second frequency of the chip respectively to obtain the first performance bottleneck and the second performance bottleneck corresponding to the application.

[0044] In one possible implementation, a mapping table between applications, chips, and performance bottlenecks is stored in a computing device, and the mapping table includes performance bottlenecks when different applications are running in different chips. For example, for commonly used applications and chips, the mapping table records the performance bottlenecks of each application at the highest frequency and the performance bottlenecks at the lowest frequency of different chips. When the computing device needs to run an application, the computing device queries the mapping table to determine the first performance bottleneck and the second performance bottleneck corresponding to the application based on the type of chip running the application. If the mapping table does not contain the performance bottleneck information corresponding to the application when it is running in the chip, the computing device runs the application once at the first frequency and the second frequency of the chip respectively to obtain the first performance bottleneck and the second performance bottleneck corresponding to the application.

[0045] In the embodiment of the present application, for a chip including multiple cores, the relationship between the available bandwidth applied at any frequency and the frequency of the chip can be expressed as the following formula 1:

[0046] w(f)=min(w factor ×f×n,w uncore ) (Formula 1)

[0047] Where w(f) is the available bandwidth of the application, f is the frequency of the chip, and w uncore is the chip’s out-of-core bandwidth, w factor is the chip's intra-core bandwidth, and n is the number of cores running the application. The bandwidth saturation frequency corresponding to the application can be determined according to the following formula 2.

[0048]

[0049] Among them, f s It is the bandwidth saturation frequency corresponding to the application when running in this chip.

[0050] S202. Determine a performance prediction model corresponding to the application according to the first performance bottleneck and the second performance bottleneck.

[0051] In the present application embodiment, Figure 3 As shown, Figure 3 is a schematic diagram of the relationship between the available bandwidth and chip frequency of an application provided in an embodiment of the present application. According to the above formula 1 and formula 2, it can be determined that when f≤f s In the case of w(f)=w factor ×f×n, the available bandwidth of the application increases linearly with the chip frequency; when f>f s In the case of w(f)=w uncore , the available bandwidth for the application remains fixed.

[0052] For applications with fixed data size memory access operations, the number of cycles required by the chip during operation Where M is the amount of data. The relationship between the number of cycles required by the chip when running an application and the frequency of the chip satisfies the following formula 3.

[0053]

[0054] That is, when f≤f s In the case of f>f, the number of cycles required by the chip to run the application remains unchanged; s In this case, the chip frequency required to run the application will increase. Figure 4 As shown, Figure 4 This is a schematic diagram of the relationship between the number of cycles and the frequency of a chip provided in an embodiment of the present application.

[0055] The above formula 3 and Figure 4 is the relationship between the number of cycles and the chip frequency when accessing a fixed amount of memory. Formula 3 and Figure 4 In practice, the relationship between the number of cycles required by the chip when running an application and the chip frequency should include two or more piecewise functions, and as the chip frequency increases, the slope of the piecewise function gradually increases. And when the chip is determined, the number of piecewise functions is related to the application.

[0056] Based on the above analysis, in an embodiment of the present application, after the computing device obtains the first performance bottleneck when running the application at a first frequency and the second performance bottleneck when running the application at a second frequency, the computing device determines the performance prediction model corresponding to the application through the following two different methods according to whether the first performance bottleneck and the second performance bottleneck are the same.

[0057] The first one is that when the first performance bottleneck and the second performance bottleneck are the same, it means that the number of cycles of the application at runtime is only affected by one hardware resource. In the process of the chip frequency changing, the change law of the number of cycles required for the chip to run the application at different frequencies will be relatively simple. Therefore, when the chip frequency is greater than the bandwidth saturation frequency corresponding to the application, it is believed that the number of cycles required for the chip to run the application and the chip frequency satisfy a linear relationship. Therefore, the parameters of the performance prediction model can be determined by the linear fitting method, and then the performance prediction model corresponding to the application is obtained. When the first performance bottleneck and the second performance bottleneck are the same, the relationship between the number of cycles C required for the chip to run the application and the chip frequency f satisfies the relationship shown in the following formula 4, that is, the performance prediction model corresponding to the application is formula 4.

[0058]

[0059] Where c2 is the number of cycles required for the chip to run the application at the second frequency; f s is the bandwidth saturation frequency corresponding to the application; a1 and b1 are constants.

[0060] In the embodiment of the present application, the computing device obtains the first number of cycles used by the chip to run the application at the first frequency and the second number of cycles used by the chip to run the application at the second frequency; then, according to the first frequency, the first number of cycles, the second frequency, the second number of cycles, and the bandwidth saturation frequency f corresponding to the application, the computing device obtains the first number of cycles used by the chip to run the application at the first frequency and the second number of cycles used by the chip to run the application at the second frequency; s , the parameters a1 and b1 of the performance prediction model are determined by a linear fitting method, and the performance prediction model corresponding to the application is obtained. Among them, a1 and b1 can be obtained by the following formula 5.

[0061]

[0062] Where f1 is the first frequency, c1 is the number of cycles required when the chip runs the application at the first frequency, that is, the first number of cycles mentioned above; f2 is the second frequency, c2 is the number of cycles required when the chip runs the application at the second frequency, that is, the second number of cycles mentioned above. When the second frequency f2 is less than or equal to the bandwidth saturation frequency f s In this case, f2 in the above formula 5 is equal to f s .

[0063] After determining the parameters a1 and b1 of the performance prediction model according to Formula 5, the determined a1 and b1 are substituted into Formula 4 to obtain the performance prediction model corresponding to the application when the first performance bottleneck and the second performance bottleneck are the same.

[0064] The second type is that when the first performance bottleneck and the second performance bottleneck are different, the performance bottleneck of the application when running at the first frequency and the second frequency of the chip respectively changes, indicating that the hardware resources affecting the operation of the application have changed, and the change pattern of the number of cycles required to run the application at different frequencies will be more complicated. Therefore, when the frequency of the chip is greater than the bandwidth saturation frequency corresponding to the application, the relationship between the number of cycles required for the chip to run the application and the chip frequency may involve multiple segmented functions, so the curve fitting method is used to fit these multiple segmented functions to determine the parameters of the performance prediction model, and then obtain the performance prediction model corresponding to the application. When the first performance bottleneck and the second performance bottleneck are different, the relationship between the number of cycles C required for the chip to run the application and the chip frequency f satisfies the relationship shown in the following formula 6, that is, the performance prediction model corresponding to the application is formula 6.

[0065]

[0066] Among them, a2 and b2 are constants.

[0067] In the embodiment of the present application, the computing device obtains the first number of cycles used by the chip to run the application at the first frequency and the second number of cycles used by the chip to run the application at the second frequency; then, according to the first frequency, the first number of cycles, the second frequency, the second number of cycles, and the bandwidth saturation frequency f corresponding to the application, the computing device obtains the first number of cycles used by the chip to run the application at the first frequency and the second number of cycles used by the chip to run the application at the second frequency; s , the parameters a2 and b2 of the performance prediction model are determined by the curve fitting method, and the performance prediction model corresponding to the application is obtained. Among them, a2 and b2 can be obtained by the following formula 7.

[0068]

[0069] Wherein, the second frequency f2 is less than or equal to the bandwidth saturation frequency f s In this case, f2 in the above formula 7 is equal to f s .

[0070] After determining the parameters a2 and b2 of the performance prediction model according to Formula 7, the determined a2 and b2 are substituted into Formula 6 to obtain the performance prediction model corresponding to the application when the first performance bottleneck and the second performance bottleneck are different.

[0071] The computing device determines whether the first performance bottleneck and the second performance bottleneck are the same. If the first performance bottleneck and the second performance bottleneck are the same, the performance prediction model corresponding to the application is determined by the above formulas 4 and 5; if the first performance bottleneck and the second performance bottleneck are not the same, the performance prediction model corresponding to the application is determined by the above formulas 6 and 7.

[0072] It should be noted that the performance prediction models corresponding to the above formulas 4 and 6 are only used as examples, and the performance prediction model corresponding to the application can also be obtained in other ways. For example, the application can be run at more frequencies to obtain the relationship between multiple groups of cycle numbers and frequencies, and then the performance prediction model corresponding to the application can be obtained by fitting.

[0073] S203. Determine the number of cycles required for the chip to run the application at the third frequency according to the performance prediction model.

[0074] After obtaining the performance prediction model corresponding to the application, if the first performance bottleneck and the second performance bottleneck are the same, the number of cycles C required for the chip to run the application at the third frequency f3 is determined according to the above formula 4. If the third frequency f3 is less than or equal to the bandwidth saturation frequency f s , then the number of cycles C required for the chip to run the above application at the third frequency f3 is C=c2; if the third frequency f3 is greater than the bandwidth saturation frequency f s , then the number of cycles required for the chip to run the above application at the third frequency f3 is C=a1×f3+b1.

[0075] If the first performance bottleneck and the second performance bottleneck are different, the number of cycles C required for the chip to run the application at the third frequency f3 is determined according to the above formula 6. If the third frequency f3 is less than or equal to the bandwidth saturation frequency f s , then the number of cycles C required for the chip to run the above application at the third frequency f3 is C=c2; if the third frequency f3 is greater than the bandwidth saturation frequency f s , then the number of cycles required for the chip to run the above application at the third frequency f3 is C = a2 × f3 2 +b2.

[0076] In a possible implementation, after determining the number of cycles C required for the chip to run the application at the third frequency, the number of cycles C can be converted into the running time t required for the chip to run the application at the third frequency.

[0077] Through the above method, when it is necessary to predict the performance of an application running at a certain frequency, the computing device only needs to obtain the performance bottleneck when the chip runs the application at two different frequencies, and can quickly build a performance prediction model for predicting application performance, which can improve the efficiency of building a performance prediction model.

[0078] In addition, since the first performance bottleneck and the second performance bottleneck are different, it means that the performance bottleneck of the application will change during the change of the chip frequency. Therefore, during the change of the chip frequency, the change law of the number of cycles required for the chip to run the application at different frequencies will be more complicated. If a function is used to represent the relationship between the number of cycles required to run the application and the frequency, multiple piecewise functions will be involved. Therefore, the curve fitting method is used to determine the performance model, which can improve the accuracy of the performance prediction model. Since the first performance bottleneck and the second performance bottleneck are the same, it means that during the change of the chip frequency, the change law of the number of cycles required for the chip to run the application at different frequencies will be simpler. Therefore, the linear fitting method is used to determine the performance model, which can reduce the amount of calculation and improve the efficiency of building the performance prediction model. The performance prediction model built by this method has high accuracy in predicting the performance of the application at different frequencies.

[0079] For the above method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present invention is not limited by the described order of actions. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the present invention. For example, in the case of building a performance prediction model corresponding to an application, it is only necessary to perform the operations described in S201 and S202 above. Other reasonable step combinations that can be thought of by those skilled in the art based on the above description also fall within the scope of protection of the present invention.

[0080] The above describes the method for constructing a performance prediction model of an application provided by the present application and the method for predicting the performance of an application based on the performance prediction model in conjunction with the accompanying drawings. The present application also provides an application performance prediction model construction device, such as Figure 5As shown, the device 500 includes an acquisition module 510 and a processing module 520. The acquisition module 510 is used to acquire the first performance bottleneck and the second performance bottleneck corresponding to the application; the processing module 520 is used to determine the performance prediction model corresponding to the application according to whether the first performance bottleneck and the second performance bottleneck are the same; when the first performance bottleneck and the second performance bottleneck are not the same, the performance prediction model is determined by a curve fitting method; when the first performance bottleneck and the second performance bottleneck are the same, the performance prediction model is determined by a linear fitting method, wherein the input of the performance prediction model is the frequency, and the output is the number of cycles required for the chip to run the above application at the frequency.

[0081] In one possible implementation, the first frequency is greater than the bandwidth saturation frequency corresponding to the application, and the second frequency is less than the bandwidth saturation frequency corresponding to the application; wherein the bandwidth saturation frequency refers to the bandwidth saturation frequency corresponding to the application when the chip runs the application. For example, the first frequency is the highest frequency of the chip, and the second frequency is the lowest frequency of the chip. It should be understood that the highest frequency and the lowest frequency of the chip are both theoretical frequencies, and the chip may not be able to reach or maintain the lowest frequency or the highest frequency. Therefore, the first frequency may also be a frequency whose difference with the highest frequency is less than a first threshold, and the second frequency may also be a frequency whose difference with the lowest frequency is less than a second threshold.

[0082] Specifically, the method for implementing the construction of the performance prediction model of the application and predicting the performance of the application based on the performance prediction model can be found in the above Figure 2 The relevant description in the corresponding method embodiment will not be repeated here.

[0083] The present application also provides a computing device, such as Figure 6 As shown, Figure 6 6 is a schematic diagram of a computing device provided in an embodiment of the present application. The computing device 600 includes one or more processors 610 , a communication interface 620 , and a memory 630 , wherein the one or more processors 610 , the communication interface 620 , and the memory 630 are interconnected via a bus 640 .

[0084] The operations performed by the processor 610 may refer to the above Figure 2The operations in the corresponding method embodiments are not repeated here. The processor 610 can be a central processing unit (CPU), or it can include a CPU and other hardware chips. The above-mentioned hardware chips can be of various types, for example, it can be a graphics processing unit (GPU), a tensor processing unit (TPU), a programmable logic device (PLD), a complex programmable logic device (CPLD), a field programmable gate array (FPGA) or a digital signal processor (DSP). Any one of the chips, the computing device 600 may include one or more of any of the above-mentioned types of hardware chips, or may include multiple types of the above-mentioned hardware chips, which is not specifically limited in the embodiments of the present application.

[0085] The communication interface 620 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface.

[0086] The memory 630 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 630 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0087] The memory 630 may also be used to store program instructions and data, so that the processor 610 calls the program instructions stored in the memory 630 to execute the operation steps implemented by the computing device in the above method embodiment. Figure 6 Show more or fewer components, or have different component configurations.

[0088] The bus 640 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus 640 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0089] Specifically, the specific implementation of various operations performed by the computing device 600 can refer to the specific operations performed by the computing device in the above method embodiment, which will not be repeated here.

[0090] An embodiment of the present application also provides a computer-readable storage medium, in which instructions are stored. When the computer-readable storage medium is executed on a processor, the method steps implemented in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations of the above method embodiment, which will not be repeated here.

[0091] An embodiment of the present application also provides a computer-readable storage medium, in which instructions are stored. When the computer-readable storage medium is executed on a processor, the method steps implemented in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations of the above method embodiment, which will not be repeated here.

[0092] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0093] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium, or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0094] The steps in the method of the embodiment of the present application can be adjusted in order, combined or deleted according to actual needs; the modules in the device of the embodiment of the present application can be divided, combined or deleted according to actual needs.

[0095] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0096] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for constructing an application performance prediction model, characterized in that: include: Obtaining a first performance bottleneck and a second performance bottleneck corresponding to the application; wherein the first performance bottleneck is a performance bottleneck when the chip runs the application at a first frequency, and the second performance bottleneck is a performance bottleneck when the chip runs the application at a second frequency; the performance bottlenecks include a memory bottleneck and a computing bottleneck; According to the first performance bottleneck and the second performance bottleneck, determine a performance prediction model corresponding to the application; wherein, when the first performance bottleneck and the second performance bottleneck are different, determine the performance prediction model by a curve fitting method; when the first performance bottleneck and the second performance bottleneck are the same, determine the performance prediction model by a linear fitting method.

2. The method according to claim 1, characterized in that The first frequency is greater than a bandwidth saturation frequency corresponding to the application when the chip runs the application, and the second frequency is less than the bandwidth saturation frequency.

3. The method according to claim 2, characterized in that Determining a performance prediction model corresponding to the application according to the first performance bottleneck and the second performance bottleneck includes: Acquire a first number of cycles used by the chip to run the application at the first frequency and a second number of cycles used by the chip to run the application at the second frequency; According to the first frequency, the first number of cycles, the second frequency, the second number of cycles and the bandwidth saturation frequency corresponding to the application, the parameters of the performance prediction model are determined by a curve fitting method to obtain the performance prediction model.

4. The method according to claim 2, characterized in that: Determining a performance prediction model corresponding to the application according to the first performance bottleneck and the second performance bottleneck includes: Acquire a first number of cycles used by the chip to run the application at the first frequency and a second number of cycles used by the chip to run the application at the second frequency; According to the first frequency, the first number of cycles, the second frequency, the second number of cycles and the bandwidth saturation frequency corresponding to the application, the parameters of the performance prediction model are determined by a linear fitting method to obtain the performance prediction model.

5. The method according to any one of claims 2 to 4, characterized in that: The method further comprises: A bandwidth saturation frequency corresponding to the application is determined according to the in-core bandwidth of the chip, the out-core bandwidth of the chip, and the number of cores running the application.

6. The method according to any one of claims 1 to 5, characterized in that: The first frequency is the highest frequency in the test frequency range, and the second frequency is the lowest frequency in the test frequency range.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: The number of cycles required for the chip to run the application at a third frequency is determined according to the performance prediction model.

8. A device for constructing an application performance prediction model, characterized in that: include: An acquisition module, configured to acquire a first performance bottleneck and a second performance bottleneck corresponding to an application; wherein the first performance bottleneck is a performance bottleneck when the chip runs the application at a first frequency, and the second performance bottleneck is a performance bottleneck when the chip runs the application at a second frequency; the performance bottlenecks include a memory bottleneck and a computing bottleneck; A processing module is used to determine a performance prediction model corresponding to the application based on the first performance bottleneck and the second performance bottleneck; wherein, when the first performance bottleneck and the second performance bottleneck are different, the performance prediction model is determined by a curve fitting method; when the first performance bottleneck and the second performance bottleneck are the same, the performance prediction model is determined by a linear fitting method.

9. The device according to claim 8, characterized in that The first frequency is greater than a bandwidth saturation frequency corresponding to the application when the chip runs the application, and the second frequency is less than the bandwidth saturation frequency.

10. The device according to claim 9, characterized in that The processing module is specifically used for: Acquire a first number of cycles used by the chip to run the application at the first frequency and a second number of cycles used by the chip to run the application at the second frequency; According to the first frequency, the first number of cycles, the second frequency, the second number of cycles and the bandwidth saturation frequency corresponding to the application, the parameters of the performance prediction model are determined by a curve fitting method to obtain the performance prediction model.

11. The device according to claim 9, characterized in that The processing module is specifically used for: Acquire a first number of cycles used by the chip to run the application at the first frequency and a second number of cycles used by the chip to run the application at the second frequency; According to the first frequency, the first number of cycles, the second frequency, the second number of cycles and the bandwidth saturation frequency corresponding to the application, the parameters of the performance prediction model are determined by a linear fitting method to obtain the performance prediction model.

12. The device according to any one of claims 9 to 11, characterized in that: The processing module is also used for: A bandwidth saturation frequency corresponding to the application is determined according to the in-core bandwidth of the chip, the out-core bandwidth of the chip, and the number of cores running the application.

13. The device according to any one of claims 8 to 12, characterized in that: The first frequency is the highest frequency in the test frequency range, and the second frequency is the lowest frequency in the test frequency range.

14. The device according to any one of claims 8 to 13, characterized in that: The processing module is also used for: The number of cycles required for the chip to run the application at a third frequency is determined according to the performance prediction model.

15. A computing device, characterized in that: The method comprises a processor and a memory, wherein the memory is used to store instructions, and the processor is used to execute the instructions. When the processor executes the instructions, the method according to any one of claims 1 to 7 is implemented.

16. A computer-readable storage medium, characterized in that: The method comprises computer program instructions, and when the computer program instructions are executed by a computing device, the computing device performs the method as claimed in any one of claims 1 to 7.

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