Pixel circuit and display panel

Abstract

The invention discloses a pixel circuit and a display panel, and the pixel circuit comprises a driving transistor, a first transistor, a first light-emitting device, a second transistor and a second light-emitting device, and a second electrode of the driving transistor is directly connected with a first electrode of the first transistor and a first electrode of the second transistor. Compared with a mode that a transistor needs to be connected between the second electrode of the driving transistor and the first transistor and between the second electrode of the driving transistor and the second transistor, the number of used transistors is reduced, so that the structure of the pixel circuit with the peep-proof effect is simplified, and the pixel density is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit and a display panel. Background Art

[0002] In order to achieve the anti-peeping effect of the display panel, a part of the pixel circuits needs to work in the display mode during normal display, while another part of the pixel circuits needs to work in the anti-peeping mode during anti-peeping display.

[0003] However, this requires more transistors to be used in the pixel circuit, resulting in a complex structure. Summary of the invention

[0004] The present application provides a pixel circuit and a display panel to alleviate the technical problem of needing to use a large number of transistors when having an anti-peeping effect.

[0005] In the first aspect, the present application provides a pixel circuit, which includes a driving transistor, a first transistor, a first light-emitting device, a second transistor and a second light-emitting device, wherein the gate of the driving transistor is connected to the storage capacitor, and the first electrode of the driving transistor is connected to the first power line; the first electrode of the first transistor is connected to the second electrode of the driving transistor; the anode of the first light-emitting device is connected to the second electrode of the first transistor, and the cathode of the first light-emitting device is connected to the second power line; the first electrode of the second transistor and the first electrode of the first transistor are both directly connected to the second electrode of the driving transistor; the anode of the second light-emitting device is connected to the second electrode of the second transistor, and the cathode of the second light-emitting device is connected to the second power line; wherein the operating mode of the pixel circuit includes a display mode and an anti-peeping mode, one of the first transistor and the second transistor is turned on in the display mode, and the other of the first transistor and the second transistor is turned on in the anti-peeping mode.

[0006] In a second aspect, the present application provides a display panel, which includes the above-mentioned pixel circuit.

[0007] The pixel circuit and display panel provided in the present application directly connect the first electrode of the first transistor and the first electrode of the second transistor through the second electrode of the driving transistor. Compared with the requirement of connecting a transistor between the second electrode of the driving transistor and the first transistor and the second transistor, the number of transistors used is reduced, thereby simplifying the structure of the pixel circuit with anti-peeping effect, which is conducive to improving pixel density. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0009] Figure 1 It is a structural schematic diagram of a display panel in the related art.

[0010] Figure 2 A first structural schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0011] Figure 3 for Figure 2 A first timing diagram of the pixel circuit shown.

[0012] Figure 4 for Figure 2 A second timing diagram of the pixel circuit shown.

[0013] Figure 5 A second structural schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0014] Figure 6 for Figure 5 A first timing diagram of the pixel circuit shown.

[0015] Figure 7 for Figure 5 A second timing diagram of the pixel circuit shown. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0017] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0018] Figure 1 The structure diagram of the display panel in the related art is shown in FIG. The display panel includes multiple groups of sub-pixels, each group of sub-pixels includes two sub-pixels of the same color, for example, one group of sub-pixels includes two red sub-pixels RP, one group of sub-pixels includes two blue sub-pixels BP, and one group of sub-pixels includes two green sub-pixels GP.

[0019] In the display mode, one of the sub-pixels in each group is displayed, and the other sub-pixels in each group are turned off. In the anti-peeping mode, one of the sub-pixels in each group is turned off, and the other sub-pixels in each group are displayed. In this way, the switching between the display mode and the anti-peeping mode is realized. However, since each sub-pixel corresponds to a pixel circuit, the number of pixel circuits increases.

[0020] The following embodiments of the present application implement switching between the display mode and the anti-peeping mode by configuring two light-emitting devices in the same pixel circuit, which can reduce the number of pixel circuits.

[0021] See also Figures 2 to 7 , this embodiment provides a pixel circuit, such as Figure 2 As shown, the pixel circuit includes a driving transistor T1, a first electrode of the driving transistor T1 is connected to a first node A, a second electrode of the driving transistor T1 is connected to a second node B, and a gate of the driving transistor T1 is connected to a third node Q.

[0022] The first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or when the first electrode is the drain, the second electrode is the source.

[0023] In some other embodiments, the first electrode of the driving transistor T1 is connected to the first power line.

[0024] In some embodiments, the pixel circuit further includes a storage capacitor Cst, a first end of the storage capacitor Cst is connected to the gate of the driving transistor T1, and a second end of the storage capacitor Cst is connected to the first power line. In some other embodiments, the second end of the storage capacitor Cst is connected to the second power line or the second node B.

[0025] In some embodiments, the pixel circuit further includes a first transistor T6, a first light-emitting device D1, a second transistor T8 and a second light-emitting device D2, the first electrode of the first transistor T6 is connected to the second electrode of the driving transistor T1; the anode of the first light-emitting device D1 is connected to the second electrode of the first transistor T6, and the cathode of the first light-emitting device D1 is connected to the second power line; the first electrode of the second transistor T8 and the first electrode of the first transistor T6 are both connected to the second electrode of the driving transistor T1; the anode of the second light-emitting device D2 is connected to the second electrode of the second transistor T8, and the cathode of the second light-emitting device D2 is connected to the second power line.

[0026] It can be understood that the pixel circuit provided in this embodiment directly connects the first electrode of the first transistor T6 and the first electrode of the second transistor T8 through the second electrode of the driving transistor T1. Compared with the need to connect a transistor between the second electrode of the driving transistor T1 and the first transistor T6 and the second transistor T8, the number of transistors used is reduced, thereby simplifying the structure of the pixel circuit with anti-peeping effect, which is conducive to improving pixel density.

[0027] It should be noted that the first light emitting device D1 may be an organic light emitting diode, a micro light emitting diode, a mini light emitting diode or a quantum dot light emitting diode. The second light emitting device D2 may be an organic light emitting diode, a micro light emitting diode, a mini light emitting diode or a quantum dot light emitting diode.

[0028] The operation mode of the pixel circuit includes a display mode and an anti-peeping mode. One of the first transistor T6 and the second transistor T8 is turned on in the display mode, and the other of the first transistor T6 and the second transistor T8 is turned on in the anti-peeping mode.

[0029] For example, the first transistor T6 is turned on in the display mode, so that the first light-emitting device D1 is turned on; the second transistor T8 is turned on in the anti-peeping mode, so that the second light-emitting device D2 is turned on. Alternatively, the first transistor T6 is turned on in the anti-peeping mode, so that the first light-emitting device D1 is turned on; the second transistor T8 is turned on in the display mode, so that the second light-emitting device D2 is turned on.

[0030] The first power line is used to transmit a first power signal VDD, and the second power line is used to transmit a second power signal VSS. The potential of the first power signal VDD is higher than that of the second power signal VSS.

[0031] In some embodiments, the channel type of the first transistor T6 is the same as the channel type of the second transistor T8; the gate of the first transistor T6 is connected to the first control line, and the gate of the second transistor T8 is connected to the second control line. The first control line is used to transmit the first control signal EM2, and the second control line is used to transmit the second control signal EM3. One of the first control signal EM2 and the second control signal EM3 is at a high level in the display mode, and the other of the first control signal EM2 and the second control signal EM3 is at a low level in the display mode.

[0032] This allows the first transistor T6 and the second transistor T8 to be turned on in time-sharing mode or anti-peeping mode instead of being turned on at the same time, thereby achieving the functions of normal display and anti-peeping display.

[0033] In some embodiments, the pixel circuit further includes an initialization transistor T7, a first electrode of the initialization transistor T7 is connected to the first initialization line, a gate of the initialization transistor T7 is connected to the reset line, and a second electrode of the initialization transistor T7 is connected to the first electrode of the first transistor T6, the first electrode of the second transistor T8, and the second electrode of the driving transistor T1.

[0034] It should be noted that the reset line is used to transmit the reset control signal RST, the first initialization line is used to transmit the first initialization signal VI_ANO, and the initialization transistor T7 is used to initialize the potential of the second node B to the potential of the first initialization signal VI_ANO according to the reset control signal RST.

[0035] In some embodiments, the pixel circuit further includes a light emitting control transistor T5, a first electrode of the light emitting control transistor T5 is connected to the first power line, a second electrode of the light emitting control transistor T5 is connected to the first electrode of the driving transistor T1, and a gate of the light emitting control transistor T5 is connected to the light emitting control line.

[0036] It should be noted that the light emitting control line is used to transmit the light emitting control signal EM1, and the light emitting control transistor T5 is used to control the connection state between the first power line and the first node A according to the light emitting control signal EM1. In other embodiments, the light emitting control transistor T5 can also be omitted, so that the first electrode of the driving transistor T1 is connected to the first power line.

[0037] In some embodiments, the pixel circuit further includes a write transistor T2, a first electrode of the write transistor T2 is connected to the data line, a second electrode of the write transistor T2 is connected to the first electrode of the drive transistor T1, and a gate of the write transistor T2 is connected to the scan line.

[0038] It should be noted that the data line is used to transmit the data signal DS, and the scan line is used to transmit the scan signal SCAN. The write transistor T2 is used to control the writing of the data signal DS according to the scan signal SCAN. In some other embodiments, the second electrode of the write transistor T2 can also be selectively connected to the second electrode of the drive transistor T1.

[0039] In some embodiments, the pixel circuit further includes a first compensation transistor T31 and a second compensation transistor T32, a first electrode of the first compensation transistor T31 is connected to a gate of the driving transistor T1, a second electrode of the first compensation transistor T31 is connected to a first electrode of the second compensation transistor T32, a second electrode of the second compensation transistor T32 is connected to a second electrode of the driving transistor T1, and a gate of the first compensation transistor T31 is connected to a gate of the second compensation transistor T32 and a scan line.

[0040] It should be noted that the first compensation transistor T31 and the second compensation transistor T32 can control the connection state between the second node B and the third node Q according to the scan signal SCAN. The first compensation transistor T31 and the second compensation transistor T32 can both be P-channel transistors, which can improve the dynamic performance of the pixel circuit and reduce the leakage current of the gate of the driving transistor T1.

[0041] In some embodiments, the pixel circuit further includes a first reset transistor T42 and a second reset transistor T41, the first electrode of the first reset transistor T42 is connected to the gate of the driving transistor T1, and the gate of the first reset transistor T42 is connected to the gate of the initialization transistor T7; the first electrode of the second reset transistor T41 is connected to the second electrode of the first reset transistor T42, the second electrode of the second reset transistor T41 is connected to the second initialization line, and the gate of the second reset transistor T41 is connected to the gate of the first reset transistor T42.

[0042] It should be noted that the second initialization line is used to transmit the second initialization signal VI_GATE. The first reset transistor T42 and the second reset transistor T41 are both P-channel transistors, which can not only improve the dynamic performance of the pixel circuit, but also reduce the leakage current of the gate of the driving transistor T1. The first reset transistor T42 and the second reset transistor T41 share the reset line with the initialization transistor T7, which can reduce the number of signal lines required for the pixel circuit.

[0043] In some of the embodiments, at least one of the driving transistor T1, the writing transistor T2, the light emitting control transistor T5, the initialization transistor T7, the first transistor T6, the second transistor T8, the first compensation transistor T31, the second compensation transistor T32, the first reset transistor T42 and the second reset transistor T41 may be an N-channel transistor, such as a low-temperature polysilicon thin film transistor or an indium gallium zinc oxide thin film transistor.

[0044] In some of the embodiments, at least one of the driving transistor T1, the writing transistor T2, the light emitting control transistor T5, the initialization transistor T7, the first transistor T6, the second transistor T8, the first compensation transistor T31, the second compensation transistor T32, the first reset transistor T42 and the second reset transistor T41 can be a P-channel transistor, such as a low-temperature polysilicon thin film transistor or an indium gallium zinc oxide thin film transistor.

[0045] like Figure 3 As shown, taking the case where all transistors in the pixel circuit are P-channel transistors as an example, the first control signal EM2 is a pulse signal, and the second control signal EM3 is a high-potential constant voltage signal. The working stages of the pixel circuit include:

[0046] Initialization stage, i.e., P1: the light control signal EM1 is at a high potential, and the light control transistor T5 is in a cut-off state; the reset control signal RST is at a low potential, and the initialization transistor T7 is in a conducting state; the first control signal EM2 is at a low potential, and the first transistor T6 is in a conducting state; the second control signal EM3 is at a high potential, and the second transistor T8 is in a cut-off state. The first initialization signal VI_ANO can be initialized by initializing the transistor T7 and the first transistor T6 as the anode potential of the first light emitting device D1.

[0047] Writing stage, i.e., P2: the light-emitting control signal EM1 is at a high potential, and the light-emitting control transistor T5 is in the off state; the reset control signal RST is at a high potential, and the initialization transistor T7 is in the off state; the first control signal EM2 and the second control signal EM3 are both at a high potential, and the first transistor T6 and the second transistor T8 are both in the off state. The scanning signal SCAN is at a low potential, and the writing transistor T2, the first compensation transistor T31, and the second compensation transistor T32 are all in the on state. The data signal DS is sequentially written to the storage capacitor Cst via the writing transistor T2, the driving transistor T1, the second compensation transistor T32, and the first compensation transistor T31.

[0048] Display mode is P31: the light-emitting control signal EM1 is at a low potential, and the light-emitting control transistor T5 is in the on state; the first control signal EM2 is at a low potential, the first transistor T6 is turned on, the first light-emitting device D1 emits light, and normal display is performed; the second control signal EM3 is at a high potential, and the second transistor T8 is in the off state.

[0049] like Figure 4 As shown, Figure 3 The difference is that the first control signal EM2 is a high-potential constant voltage signal, and the second control signal EM3 is a pulse signal, that is, the waveform of the first control signal EM2 and the waveform of the second control signal EM3 are interchanged. The working stages of the pixel circuit include:

[0050] Initialization stage, i.e., P1: the light control signal EM1 is at a high potential, and the light control transistor T5 is in a cut-off state; the reset control signal RST is at a low potential, and the initialization transistor T7 is in a conduction state; the first control signal EM2 is at a high potential, and the first transistor T6 is in a cut-off state; the second control signal EM3 is at a low potential, and the second transistor T8 is in a conduction state. The first initialization signal VI_ANO can initialize the anode potential of the second light emitting device D2 by initializing the transistors T7 and T8.

[0051] Writing stage, i.e., P2: the light-emitting control signal EM1 is at a high potential, and the light-emitting control transistor T5 is in the off state; the reset control signal RST is at a high potential, and the initialization transistor T7 is in the off state; the first control signal EM2 and the second control signal EM3 are both at a high potential, and the first transistor T6 and the second transistor T8 are both in the off state. The scanning signal SCAN is at a low potential, and the writing transistor T2, the first compensation transistor T31, and the second compensation transistor T32 are all in the on state. The data signal DS is sequentially written to the storage capacitor Cst via the writing transistor T2, the driving transistor T1, the second compensation transistor T32, and the first compensation transistor T31.

[0052] The anti-peeping mode is P32: the light-emitting control signal EM1 is at a low potential, and the light-emitting control transistor T5 is in the on state; the first control signal EM2 is at a high potential, and the first transistor T6 is cut off; the second control signal EM3 is at a low potential, and the second transistor T8 is in the on state, and the second light-emitting device D2 emits light for anti-peeping display.

[0053] Figure 5 A second structural diagram of a pixel circuit provided in an embodiment of the present application. Figure 2 The difference is that the second electrode of the initialization transistor T7 is connected to the second electrode of the second transistor T8. In other embodiments, the second electrode of the initialization transistor T7 can also be connected to the second electrode of the first transistor T6.

[0054] like Figure 6 As shown, taking the case where all transistors in the pixel circuit are P-channel transistors as an example, the working stages of the pixel circuit include:

[0055] Initialization stage, i.e., P1: the light emitting control signal EM1 is at a high potential, and the light emitting control transistor T5 is in a cut-off state; the reset control signal RST, the first control signal EM2, and the second control signal EM3 are all at a low potential, and the initialization transistor T7, the first transistor T6, and the second transistor T8 are all in a conducting state. The first initialization signal VI_ANO can initialize the anode potential of the second light emitting device D2 through the initialization transistor T7, and initialize the anode potential of the first light emitting device D1 through the first transistor T6 and the second transistor T8.

[0056] Writing stage, i.e., P2: the light-emitting control signal EM1 is at a high potential, and the light-emitting control transistor T5 is in the off state; the reset control signal RST, the first control signal EM2, and the second control signal EM3 are all at a high potential, and the initialization transistor T7, the first transistor T6, and the second transistor T8 are all in the off state. The scanning signal SCAN is at a low potential, and the writing transistor T2, the first compensation transistor T31, and the second compensation transistor T32 are all in the on state. The data signal DS is sequentially written to the storage capacitor Cst via the writing transistor T2, the driving transistor T1, the second compensation transistor T32, and the first compensation transistor T31.

[0057] The display mode is P31: the light-emitting control signal EM1 is at a low potential, and the light-emitting control transistor T5 is in the on state; the reset control signal RST is at a high potential, and the initialization transistor T7 is cut off; the first control signal EM2 is at a high potential, the first transistor T6 is cut off, and the first light-emitting device D1 does not emit light; the second control signal EM3 is at a low potential, the second transistor T8 is in the on state, and the second light-emitting device D2 emits light for normal display.

[0058] like Figure 7 As shown, Figure 6 The difference is that the waveform of the first control signal EM2 and the waveform of the second control signal EM3 are interchanged. The working phases of the pixel circuit include:

[0059] Initialization stage, i.e., P1: the light control signal EM1 is at a high potential, and the light control transistor T5 is in a cut-off state; the reset control signal RST is at a low potential, and the initialization transistor T7 is in a conduction state; the first control signal EM2 is at a high potential, and the first transistor T6 is in a cut-off state; the second control signal EM3 is at a low potential, and the second transistor T8 is in a conduction state. The first initialization signal VI_ANO can initialize the anode potential of the second light emitting device D2 by initializing the transistors T7 and T8.

[0060] Writing stage, i.e., P2: the light-emitting control signal EM1 is at a high potential, and the light-emitting control transistor T5 is in the off state; the reset control signal RST is at a high potential, and the initialization transistor T7 is in the off state; the first control signal EM2 and the second control signal EM3 are both at a high potential, and the first transistor T6 and the second transistor T8 are both in the off state. The scanning signal SCAN is at a low potential, and the writing transistor T2, the first compensation transistor T31, and the second compensation transistor T32 are all in the on state. The data signal DS is sequentially written to the storage capacitor Cst via the writing transistor T2, the driving transistor T1, the second compensation transistor T32, and the first compensation transistor T31.

[0061] The anti-peeping mode is P32: the light-emitting control signal EM1 is at a low potential, and the light-emitting control transistor T5 is in the on state; the reset control signal RST is at a high potential, and the initialization transistor T7 is cut off; the first control signal EM2 is at a low potential, the first transistor T6 is turned on, and the first light-emitting device D1 emits light for anti-peeping display; the second control signal EM3 is at a high potential, the second transistor T8 is in the off state, and the second light-emitting device D2 does not emit light.

[0062] It should be noted that the switching between the display mode and the anti-peeping mode can be within the same frame or between different frames, and there is no specific time limit.

[0063] In some of the embodiments, the present embodiment provides a display panel, which includes the above-mentioned pixel circuit.

[0064] It can be understood that since the display panel provided in this embodiment includes the above-mentioned pixel circuit, it can also directly connect the first electrode of the first transistor T6 and the first electrode of the second transistor T8 through the second electrode of the driving transistor T1. Compared with the need to connect a transistor between the second electrode of the driving transistor T1 and the first transistor T6 and the second transistor T8, the number of transistors used is reduced, thereby simplifying the structure of the pixel circuit with anti-peeping effect, which is conducive to improving the pixel density.

[0065] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0066] The pixel circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel circuit, characterized in that: The pixel circuit comprises: A driving transistor, wherein a gate of the driving transistor is connected to the storage capacitor, and a first electrode of the driving transistor is connected to a first power line; a first transistor, wherein a first electrode of the first transistor is connected to a second electrode of the driving transistor; a first light emitting device, wherein an anode of the first light emitting device is connected to the second electrode of the first transistor, and a cathode of the first light emitting device is connected to a second power line; a second transistor, wherein a first electrode of the second transistor and a first electrode of the first transistor are both directly connected to a second electrode of the driving transistor; a second light emitting device, wherein an anode of the second light emitting device is connected to the second electrode of the second transistor, and a cathode of the second light emitting device is connected to the second power line; The operation mode of the pixel circuit includes a display mode and an anti-peeping mode, one of the first transistor and the second transistor is turned on in the display mode, and the other of the first transistor and the second transistor is turned on in the anti-peeping mode.

2. The pixel circuit according to claim 1, characterized in that: The channel type of the first transistor is the same as the channel type of the second transistor; the gate of the first transistor is connected to a first control signal, and the gate of the second transistor is connected to a second control signal; One of the first control signal and the second control signal is at a high level in the display mode, and the other of the first control signal and the second control signal is at a low level in the display mode.

3. The pixel circuit according to claim 2, characterized in that: The pixel circuit further includes an initialization transistor, a first electrode of the initialization transistor is connected to a first initialization line, a gate of the initialization transistor is connected to a reset line, and a second electrode of the initialization transistor is connected to at least one of the first transistor and the second transistor.

4. The pixel circuit according to claim 3, characterized in that: The second electrode of the initialization transistor is connected to the first electrode of the first transistor, the first electrode of the second transistor, and the second electrode of the driving transistor.

5. The pixel circuit according to claim 4, characterized in that: The working phase of the pixel circuit includes an initialization phase, in which the initialization transistor is in an on state, one of the first transistor and the second transistor is in an on state, and the other of the first transistor and the second transistor is in an off state.

6. The pixel circuit according to claim 5, characterized in that: One of the first control signal and the second control signal is a constant voltage signal, and the other of the first control signal and the second control signal is a pulse signal.

7. The pixel circuit according to claim 3, characterized in that: A second electrode of the initialization transistor is connected to a second electrode of the first transistor or a second electrode of the second transistor.

8. The pixel circuit according to claim 7, characterized in that: The working phase of the pixel circuit includes an initialization phase, during which the initialization transistor, the first transistor, and the second transistor are all in a conducting state.

9. The pixel circuit according to any one of claims 3 to 8, characterized in that: The pixel circuit further includes: a light emitting control transistor, wherein a first electrode of the light emitting control transistor is connected to the first power line, a second electrode of the light emitting control transistor is connected to the first electrode of the driving transistor, and a gate of the light emitting control transistor is connected to a light emitting control line; a first reset transistor, wherein a first electrode of the first reset transistor is connected to a gate of the driving transistor, and a gate of the first reset transistor is connected to a gate of the initialization transistor; a second reset transistor, wherein a first electrode of the second reset transistor is connected to a second electrode of the first reset transistor, a second electrode of the second reset transistor is connected to a second initialization line, and a gate of the second reset transistor is connected to a gate of the first reset transistor; Wherein, the first reset transistor and the second reset transistor are both P-channel transistors.

10. A display panel, characterized in that: The display panel comprises the pixel circuit as described in any one of claims 1-9.

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