Display panel and display device

Abstract

Embodiments of the present application provide a display panel and display device, the display panel including a pixel circuit and a light-emitting device, the pixel circuit being electrically connected to a first electrode of the light-emitting device, the pixel circuit including: a driving transistor configured to generate a light-emitting driving current; and a shunt module electrically connected to a node between the driving transistor and the light-emitting device. The light-emitting device receives a light-emitting driving current of I1, and the light-emitting driving current generated by the driving transistor is I2, where I2 = I1 + ΔI, where ΔI is the light-emitting driving current received by the shunt module. Embodiments of the present application increase the light-emitting driving current generated by the driving transistor, thereby reducing the impact of the threshold bias of the driving transistor on the light-emitting driving current, ensuring the accuracy of the light-emitting device receiving a smaller light-emitting driving current, improving the accuracy of the display panel's luminance at low grayscales, and enhancing the display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] A display panel includes pixel circuits and light-emitting elements. The pixel circuits generate a light-emitting drive current and supply it to the light-emitting devices to emit light. When the light-emitting devices require a low light-emitting drive current, the driver transistors included in the pixel circuits need to generate a low light-emitting drive current. However, the light-emitting drive current generated by the driver transistors is affected to some extent by the threshold bias of the transistors. When the driver transistors generate a high light-emitting drive current, the impact of this threshold bias on the light-emitting drive current is relatively small, and the accuracy of the light-emitting drive current is relatively small. However, when the light-emitting drive current required by the driver transistors is relatively small, the impact of this threshold bias on the low light-emitting drive current becomes significantly larger, and in this case, the accuracy of the light-emitting drive current is significantly affected. It is understandable that when the light-emitting drive current is relatively small, the threshold bias has a greater impact, and the light-emitting device will also experience significant brightness deviations when receiving a light-emitting drive current with a large deviation. This is especially true when the light-emitting devices are connected in series. These devices have a higher luminous efficiency and require a light-emitting drive current that is approximately half that of a standard light-emitting device. Therefore, series light-emitting devices require a higher accuracy of the light-emitting drive current. Summary of the Invention

[0003] In view of this, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel including a pixel circuit and a light-emitting device, wherein the pixel circuit is electrically connected to a first electrode of the light-emitting device, and the pixel circuit includes:

[0005] A driving transistor, the driving transistor is used to generate a light-emitting driving current;

[0006] A shunt module, the shunt module is electrically connected to a node between the driving transistor and the light-emitting device;

[0007] The light-emitting device receives a light-emitting driving current of I1, and the light-emitting driving current generated by the driving transistor is I2. I2=I1+ΔI, where ΔI is the light-emitting driving current received by the shunt module.

[0008] In a second aspect, an embodiment of the present application provides a display device, comprising the display module provided in the first aspect.

[0009] In an embodiment of the present application, a shunt module is electrically connected to a node between a driver transistor and a light-emitting device in a pixel circuit, thereby increasing the light-emitting drive current generated by the driver transistor. This helps reduce the impact of the driver transistor's threshold bias on the light-emitting drive current and improves the accuracy of the light-emitting drive current generated by the driver transistor. Furthermore, the light-emitting drive current required by the shunt module is a relatively stable value. By quantizing the light-emitting drive current using the formula I2 = I1 + ΔI, the accuracy of the light-emitting drive current provided to the light-emitting device is improved, thereby improving the accuracy of the light-emitting brightness of the light-emitting device. Furthermore, the embodiment of the present application helps ensure the accuracy of the light-emitting device receiving a relatively small light-emitting drive current, improves the accuracy of the light-emitting brightness of the display panel at low grayscales, and enhances the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application;

[0012] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0013] Figure 3 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0014] Figure 4 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0015] Figure 5 A schematic structural diagram of a display panel provided in an embodiment of the present application;

[0016] Figure 6 A schematic plan view of a driving transistor provided in an embodiment of the present application;

[0017] Figure 7 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0018] Figure 8 A schematic plan view of a driving transistor provided in an embodiment of the present application;

[0019] Figure 9 A schematic plan view of a driving transistor provided in an embodiment of the present application;

[0020] Figure 10 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0021] Figure 11 A schematic plan view of another driving transistor provided in an embodiment of the present application;

[0022] Figure 12 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0023] Figure 13 A schematic plan view of another driving transistor provided in an embodiment of the present application;

[0024] Figure 14 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0025] Figure 15 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0026] Figure 16 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0027] Figure 17 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0028] Figure 18 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0029] Figure 19 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0030] Figure 20 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0031] Figure 21 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0032] Figure 22 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0033] Figure 23 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0035] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0036] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a," "an," and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0037] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0038] In the description of this specification, it is necessary to understand that the words "substantially", "approximately", "approximately", "about", "roughly", "generally" and the like described in the claims and embodiments of this application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0039] It should be understood that although the terms first, second, etc. may be used to describe nodes, sub-shunt modules, capacitors, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish nodes, sub-shunt modules, capacitors, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first node may also be referred to as the second node, and similarly, the second node may also be referred to as the first node. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0040] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application is shown. Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0041] The embodiment of the present application provides a display panel AA, combined with Figure 1 、 Figure 2 As shown, the display panel AA includes a pixel circuit A10 and a light emitting device B10. The pixel circuit A0 is electrically connected to a first electrode B101 of the light emitting device B10. The pixel circuit A10 includes a driving transistor Md for generating a light emitting driving current.

[0042] Normally, the driving transistor Md receives a data voltage transmitted according to the luminous brightness of the light-emitting device B10, thereby generating a corresponding luminous driving current. However, as mentioned in the background technology, when the driving transistor Md needs to generate a smaller luminous driving current, the threshold voltage of the driving transistor Md has a more significant effect on the magnitude of the generated luminous driving current. On the other hand, when the driving transistor Md generates a larger luminous driving current, the threshold voltage has no significant effect on the magnitude of the generated luminous driving current. In order to reduce the effect of the threshold voltage bias of the driving transistor Md on the generation of a small luminous driving current and improve the accuracy of the generated small luminous driving current, the embodiments of the present application propose the following:

[0043] A shunt module 10 is provided in the pixel circuit A10 and is electrically connected to the node between the driving transistor Md and the light-emitting device B10. In other words, the shunt module 10 is located between the driving transistor Md and the light-emitting device B10. When the light-emitting driving current generated by the driving transistor Md is output from the driving transistor Md, part of the light-emitting driving current can flow to the light-emitting device B10, and part of the light-emitting driving current can flow to the shunt module 10.

[0044] In the process of generating the light-emitting driving current, the light-emitting driving current I2 generated by the driving transistor Md can be set according to the rule that the light-emitting driving current received by the light-emitting device B10 is I1, the light-emitting driving current generated by the driving transistor Md is I2, I2=I1+ΔI, ΔI is the light-emitting driving current received by the shunt module 10.

[0045] During application, the magnitude of the light-emitting drive current ΔI received by the shunt module 10 is measured. When transmitting the data voltage to the driving transistor Md, the light-emitting drive current required by the shunt module 10 is also taken into account. This allows the light-emitting drive current generated by the driving transistor Md after receiving the data voltage to be provided to the shunt module 10 and the light-emitting device B10. In this way, when the light-emitting drive current required by the light-emitting device B10 is relatively small, the addition of the shunt module 10 increases the light-emitting drive current required to be generated by the driving transistor Md, thereby reducing the degree to which the light-emitting drive current generated by the driving transistor Md is affected by the threshold bias.

[0046] In the embodiment of the present application, the node between the driving transistor Md of the pixel circuit A10 and the light-emitting device B10 is electrically connected to the shunt module 10, thereby increasing the light-emitting drive current generated by the driving transistor Md. This helps reduce the impact of the threshold bias of the driving transistor Md on the light-emitting drive current and improves the accuracy of the light-emitting drive current generated by the driving transistor Md. Furthermore, the light-emitting drive current ΔI required by the shunt module 10 is a relatively stable value. By quantizing the light-emitting drive current using the formula I2 = I1 + ΔI, the accuracy of the light-emitting drive current provided to the light-emitting device B10 is improved, thereby improving the accuracy of the light-emitting brightness of the light-emitting device B10. Furthermore, the embodiment of the present application helps ensure the accuracy of the light-emitting drive current received by the light-emitting device B10 at a relatively low light-emitting drive current, improves the accuracy of the light-emitting brightness of the display panel AA at low grayscales, and enhances the display quality of the display panel AA.

[0047] Figure 3 A schematic diagram of another pixel circuit provided in an embodiment of the present application.

[0048] In one embodiment of the present application, Figure 3 As shown, pixel circuit A10 also includes a light-emitting control module 20, which is electrically connected to the driving transistor Md and the light-emitting device B10. One end of the light-emitting control module 20 is connected to the light-emitting driving current generated by the driving transistor Md. When the light-emitting control module 20 is turned on, the light-emitting driving current can be transmitted through the light-emitting control module 20 to the light-emitting device B10, causing the light-emitting device B10 to emit light.

[0049] The pixel circuit A10 further includes a first node N1 , which is located between the driving transistor Md and the light emitting control module 20 , and the light emitting driving current passes through the first node N1 .

[0050] The current shunting module 10 in the pixel circuit A10 includes a first sub-shunting module 10A, which is electrically connected to the first node N1. When the first sub-shunting module 10A is electrically connected to the first node N1, the first sub-shunting module 10A is positioned between the driving transistor Md and the light-emitting device B10, thereby providing a current shunting function.

[0051] In an embodiment of the present application, a shunt module 10 is provided to include a first sub-shunt module 10A, and the first sub-shunt module 10A is electrically connected to the first node N1, which is beneficial for the first sub-shunt module 10A to receive part of the light-emitting driving current before the light-emitting driving current reaches the light-emitting device B10, and is beneficial for realizing a solution in which the driving transistor Md can generate a relatively large light-emitting driving current when the light-emitting device B10 requires a small current to emit light, thereby reducing the influence of the threshold bias on the accuracy of the light-emitting driving current, improving the accuracy of the light-emitting brightness when the light-emitting device B10 receives a small current to emit light, and improving the display effect of the display panel AA.

[0052] In one embodiment of the present application, continue to refer to Figure 3 As shown, the pixel circuit A10 further includes a first reset module 30. The first terminal of the first reset module 30 receives the first reset voltage Vref1, and the second terminal is electrically connected to the first node N1. Optionally, the first reset module 30 is performed after the first sub-dividing module 10A completes the diversion operation and before the next diversion operation.

[0053] As can be seen from the above embodiment, the first sub-dividing module 10 is electrically connected to the first node N1. After the first sub-dividing module 10 receives the light-emitting driving current, the potential of the first node N1 will change. Optionally, the light-emitting driving current that can be received by the first sub-dividing module 10 is a relatively stable value. In this case, after the first sub-dividing module 10 receives the light-emitting driving current and the potential increases, if the potential of the first sub-dividing module 10 is not promptly corrected, the first sub-dividing module 10A may fail to divert the light or the diversion may be inaccurate during the next light-emitting driving current transmission process of the pixel circuit A10, thereby losing the effectiveness of the first sub-dividing module 10A.

[0054] It should be noted that the pixel circuit A10 also includes a threshold voltage compensation module 60, which is used to compensate the threshold voltage of the driving transistor Md to the gate of the driving transistor Md. The threshold voltage compensation module 60 and the first reset module 30 are simultaneously turned on for a period of time before the driving transistor Md generates a light-emitting driving current. At this time, the first reset voltage Vref1 can simultaneously reset the first node N1 electrically connected to the first sub-shunt module 10A and the gate of the driving transistor Md, which is beneficial to ensure the accuracy of the light-emitting driving current generated by the driving transistor Md and the accuracy of the shunt of the first sub-shunt module 10A.

[0055] In an embodiment of the present application, the pixel circuit A10 is further provided with a first reset module 30. The first reset module 30 transmits a first reset voltage Vref1 to the first node N1 after the first sub-shunt module 10 shunts, thereby resetting the first node N1, and further achieving the effect of resetting the input end of the first sub-shunt module 30, which is beneficial to stabilizing the operation of the first sub-shunt module 10A and ensuring the accuracy of the light-emitting drive current received by the first sub-shunt module 10A, thereby facilitating the accuracy of the light-emitting drive current received by the light-emitting device B10.

[0056] Figure 4 A schematic diagram of another pixel circuit provided in an embodiment of the present application.

[0057] In one embodiment of the present application, Figure 4 As shown, the first sub-dividing module 10A includes a first capacitor C1 , and the first capacitor C1 includes a first plate C1A and a second plate C1B.

[0058] In the embodiment of the present application, the first sub-shunt module 10A is provided to include a first capacitor C1, which is conducive to utilizing the charge storage function of the first capacitor C1 to implement the shunt solution of the first sub-shunt module 10A. The capacity of the first capacitor C1 can be limited according to actual use, which is conducive to more flexible and convenient preparation of the first sub-shunt module 10A, thereby improving the applicability of the embodiment of the present application. In addition, the first capacitor C1 includes a first plate C1A and a second plate C1B, and one of the first plate C1A and the second plate C1B is electrically connected to the first node N1 to realize the charging of the first capacitor C1 and complete the shunt of the first sub-shunt module 10A.

[0059] Figure 5 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown in FIG. Figure 6 A schematic plan view of a driving transistor provided in an embodiment of the present application.

[0060] In one embodiment of the present application, Figure 5 、 Figure 6As shown, the first electrode of the driving transistor Md is electrically connected to the first node N1. The display panel AA includes a substrate A20, and the driving transistor Md is located on one side of the substrate A20. The driving transistor Md includes an active layer S1 and a gate G1. The active layer S1 is located on the side of the gate G1 facing the substrate A20. The active layer S1 includes a first portion S1A, a second portion S1B, and a third portion S1C. In a direction perpendicular to the plane of the display panel, the second portion S1B overlaps with the gate G1. Along the extension direction of the active layer S1, the first portion S1A and the third portion S1C are respectively located on opposite sides of the second portion S1B. The first portion S1A and the third portion S1C can serve as the source and drain of the driving transistor Md, respectively. In the embodiment of the present application, the first portion S1A of the active layer S1 is multiplexed as the first electrode of the driving transistor Md. Then, the first portion S1A of the active layer S1 is electrically connected to the first node N1. In the circuit structure, the first node N1 is a part of the first portion S1A, and the potential of the first portion S1A is equal to the potential of the first node N1.

[0061] As can be seen from the above embodiment, the first node N1 is electrically connected to the first capacitor C1. When preparing the first capacitor C1 in the circuit structure, the structure at the first node N1, that is, the first portion S1A of the active layer S1, can be used as one of the plates of the first capacitor C1.

[0062] In the embodiment of this application, combined with Figure 5-Figure 6 As shown, the width of the first portion S1A along the first direction X1 is greater than the width of the third portion S1C along the first direction X1. The first direction X1 is parallel to the plane of the display panel A10 and intersects the extension direction of the active layer S1. In this case, the area of ​​the first portion S1A on the surface parallel to the display panel AA is increased, so that the first portion S1A has a portion extending beyond the active layer S1 in the first direction X1. This facilitates the reuse of the first portion S1A as a plate of the first capacitor C1. It also facilitates the use of the structure of the first capacitor C1 as a component of the drive transistor Md, reducing the structural complexity of the display panel AA and avoiding an increase in the film thickness of the display panel AA.

[0063] Supplementary explanation, combined with Figure 4 、 Figure 6 The driving transistor Md shown has a first electrode electrically connected to the first node N1 , a second electrode electrically connected to the third node N3 , and a gate electrically connected to the fourth node N4 .

[0064] In one embodiment of the present application, continue to refer to Figure 5-Figure 6As shown, in the structure of the display panel AA, the first plate C1A of the first capacitor C1 is located on the side of the gate G1 of the driving transistor Md away from the substrate A20; in the direction perpendicular to the plane where the display panel AA is located, the first plate C1A covers the first part S1A, and the first part S1A is reused as the second plate C1B of the first capacitor C1.

[0065] In the embodiment of the present application, the first portion S1B of the active layer S1 of the driving transistor Md is used as the second plate C1B of the first capacitor C1. As can be seen from the above embodiment, by setting the area of ​​the first portion S1A larger than that of the third portion S1C, the first portion S1A can function as the second plate C1B, thereby improving the charge storage capacity of the first capacitor C1.

[0066] In the embodiment of the present application, the first plate C1A of the first capacitor C1 is located on the side of the gate G1 of the driving transistor Md away from the substrate A20, and in a direction perpendicular to the plane where the display panel AA is located, the first plate C1A covers the first part S1A, which is conducive to having an overlapping portion between the first part S1A and the first plate C1A, thereby forming the first capacitor C1.

[0067] Figure 7 This is a structural diagram of another display panel provided in an embodiment of the present application. Figure 8 A schematic plan view of a driving transistor provided in an embodiment of the present application is shown in FIG. Figure 9 A schematic plan view of a driving transistor provided in an embodiment of the present application.

[0068] like Figure 3-Figure 4 As shown, the pixel circuit A10 includes a storage capacitor Cst, which is electrically connected to the gate G1 of the driving transistor Md and can be used to stabilize the gate potential of the driving transistor Md. Figure 7 、 Figure 8 As shown, in the circuit structure of pixel circuit A10, the gate of the driving transistor Md can be configured to multiplex as one plate of the storage capacitor Cst, and the other plate of the storage capacitor Cst is configured on a side of the gate G1 of the driving transistor Md away from the substrate A20 to form the storage capacitor Cst. Optionally, one plate of the storage capacitor Cst away from the gate G1 is extended and extended to cover the first portion S1A, so that the portion overlapping the first portion S1A serves as the first plate C1A of the first capacitor C1.

[0069] Or, alternatively, as Figure 9 As shown, the first plate C1A of the first capacitor C1 and a plate of the storage capacitor Cst away from the gate G1 may be located in the same film layer, but are not an integrated structure.

[0070] Figure 10This is a structural diagram of another display panel provided in an embodiment of the present application. Figure 11 A schematic plan view of another driving transistor provided in an embodiment of the present application is shown. Figure 12 This is a structural diagram of another display panel provided in an embodiment of the present application. Figure 13 A schematic plan view of another driving transistor provided in an embodiment of the present application.

[0071] In one embodiment of the present application, Figure 10 、 Figure 11 As shown, the first plate C1A of the first capacitor C1 is located on the side of the active layer S1 of the driving transistor Md that faces the substrate A20. In a direction perpendicular to the plane of the display panel AA, the first plate C1A covers the first portion S1A, which serves as the second plate C1B of the first capacitor C1. The first plate C1A overlaps the first portion S1A of the active layer S1 to form the first capacitor C1, completing the fabrication of the first sub-dividing module 10A.

[0072] Combine Figure 10 、 Figure 11 As shown, the first electrode plate C1A of the first capacitor C1 only includes the portion located on the side of the active layer S1 facing the substrate A20, which facilitates the fabrication of the first capacitor C1. Furthermore, the embodiments of the present application provide a feasible solution for fabricating the first capacitor C1, improving the manufacturability of the first capacitor C1 in the display panel AA.

[0073] Or, combined Figure 12-13 As shown, the first plate C1A of the first capacitor C1 includes a portion located on the side of the active layer S1 facing the substrate A20. Another first plate C1A may also be provided on the side of the gate G1 of the drive transistor Md facing away from the substrate A20. For example, the first plate C1A is divided into a first sub-plate C1A1 and a second sub-plate C1A2. Optionally, the first sub-plate C1A1 is located on the side of the first portion S1A of the active layer S1 facing away from the substrate A20, while the second sub-plate C1A2 is located on the side of the first portion S1A of the active layer S1 facing the substrate A20. This forms a first capacitor C1 structure composed of the capacitance between the first sub-plate C1A1 and the first portion S1A, and the capacitance between the second sub-plate C1A2 and the first portion S1A. This helps increase the capacity of the first capacitor C1, paving the way for significantly increasing the light-emitting drive current generated by the drive transistor Md under low current demands, and further reducing the impact of the threshold bias of the drive transistor Md on the accuracy of the light-emitting drive current.

[0074] Figure 14 A schematic diagram of another pixel circuit provided in an embodiment of the present application is shown. Figure 15A schematic diagram of another pixel circuit provided in an embodiment of the present application.

[0075] In one embodiment of the present application, Figure 14 As shown, the pixel circuit A10 further includes a second node N2, which is located between the light-emitting control module 20 and the light-emitting device B10. After the light-emitting control module 20 is turned on, it outputs the received light-emitting driving current to the light-emitting device B10. The second node N2 is located between the light-emitting control module 20 and the light-emitting device B10, and the light-emitting driving current also passes through the second node N2.

[0076] In an embodiment of the present application, a shunt module 10 is provided to include a second sub-shunt module 10B, which is electrically connected to the second node N2. This is advantageous in that when the light-emitting driving current is provided to the light-emitting device B10, the second sub-shunt module 10B can receive part of the light-emitting driving current, thereby achieving the purpose of shunt.

[0077] In the embodiment of the present application, the second sub-dividing module 10B is positioned between the light-emitting device B10 and the light-emitting control module 20, which facilitates the function of the diverting module 10 and provides a feasible technical solution for the embodiment of the present application. Furthermore, the output terminal of the light-emitting control module 20 has fewer electrical connection lines, which reduces the coupling effect of the output terminal of the light-emitting control module 20 on the entire pixel circuit A10. Therefore, positioning the second sub-dividing module 10B at the second node N2 helps reduce the impact of the second sub-dividing module 10B on the operation of the entire pixel circuit A10 and helps prevent the second sub-dividing module 10B from diverting current during the operating phase when the pixel circuit A10 is not transmitting the light-emitting drive current, thereby ensuring the operational stability of the pixel circuit A10.

[0078] In addition, if Figure 15 As shown, the embodiment of the present application provides a shunt module 10 including a first sub-shunt module 10A and a second sub-shunt module 10B. The first sub-shunt module 10A is electrically connected to the first node N1, and the second sub-shunt module 10B is electrically connected to the second node N2. This helps to increase the shunt range of the shunt module 10 and improve the feasibility of the driving transistor Md generating the light-emitting drive current when the light-emitting device B10 receives a small current to emit light. In addition, the shunt ratio of the first sub-shunt module 10A and the second sub-shunt module 10B can be used to more flexibly improve the operating stability of the shunt module 10 and the shunt accuracy, thereby improving the accuracy of the light-emitting drive current received by the light-emitting device 10.

[0079] In one embodiment of the present application, continue to refer to Figure 14 、 Figure 15As shown, the pixel circuit A10 further includes a second reset module 40. A first terminal of the second reset module 40 receives a second reset voltage Vref2, and a second terminal is electrically connected to the second node N2. After the second sub-dividing module 10B electrically connected to the second node N2 performs partial diversion, the potential of the second node N2 changes accordingly. The potential of the second node N2 needs to be corrected, and the storable state of the second sub-dividing module 10B needs to be restored to prepare for the next diversion.

[0080] In the embodiment of the present application, the second node N2 is electrically connected to the second reset module 40. After the second sub-dividing module 10B diverts the current, the second reset module 40 transmits the second reset voltage Vref2 to the second node N2. This facilitates resetting the second node N2 and restoring the state of the second sub-dividing module 10B. This allows the second sub-dividing module 10B to accurately divert the current when the transistor Md is driven to generate the light-emitting drive current next time, thereby ensuring the accuracy of the light-emitting drive current received by the light-emitting device B10 and ensuring the accurate brightness of the light-emitting device B10.

[0081] Figure 16 A schematic diagram of another pixel circuit provided in an embodiment of the present application is shown. Figure 17 A schematic diagram of another pixel circuit provided in an embodiment of the present application.

[0082] In one embodiment of the present application, Figure 16-17 As shown, the second sub-dividing module 10B includes a second capacitor C2, which includes a third plate C2A and a fourth plate C2B. This facilitates utilizing the second capacitor C2 to implement the current diversion function of the second sub-dividing module 10B. One of the third plate C21 and the fourth plate C2B is electrically connected to the second node N2. When the driving transistor Md generates a light-emitting driving current, one of the third plate C1 and the fourth plate C2B receives the charge and stores it in the second capacitor C2.

[0083] Figure 18 A schematic structural diagram of another display panel provided in an embodiment of the present application.

[0084] In one embodiment of the present application, Figure 16-Figure 18 As shown, the display panel AA includes a substrate A20, a pixel circuit A10 is located on one side of the substrate A20, and a light-emitting device B10 is located on a side of the pixel circuit A10 away from the substrate A20. A first insulating layer D1 is included between the pixel circuit A10 and the first electrode of the light-emitting device B10. Optionally, a hole is punched to electrically connect the pixel circuit A10 and the light-emitting device B10. The pixel circuit A10 includes multiple transistors. Figure 18The transistor M1 electrically connected to the light emitting device B10 is only for illustration. Optionally, the light emitting control module 20 includes a transistor M1, and one electrode of the transistor M1 is electrically connected to the first electrode B101 of the light emitting device B10 via a punched hole. Figure 18 As shown, the transistor M1 includes a gate G2 and an active layer S2. The capacitor plate layer MC included on the side of the gate G2 away from the substrate A20 can be used to prepare a plate of a capacitor such as a storage circuit Cst.

[0085] In an embodiment of the present application, in a direction perpendicular to the plane of the display panel AA, the third plate C2A of the second capacitor C2 is located between the first insulating layer D1 and the pixel circuit A10, and the third plate C2A at least partially overlaps with the first pole B101 of the light-emitting device B10. The first pole B101 of the light-emitting device B10 is reused as the fourth plate C2B, which is conducive to the preparation of the second capacitor C2 in the display panel AA. In addition, in the preparation of the second capacitor C2, the third plate C2A is set between the pixel circuit A10 and the first insulating layer D1. The structure shown is that the first insulating layer D1 covers the third plate C2A, and the third plate C2A at least partially overlaps with the first pole B101 of the light-emitting device B10, which is conducive to forming a capacitor structure between the third plate C2A and the first pole B101. At this time, part of the first insulating layer D1 can be used as the dielectric material of the second capacitor C2.

[0086] Since the second node N2 is located between the light control module 20 and the first electrode B101 of the light-emitting device B10, the electrical connection between the second capacitor C2 and the first electrode B101 of the light-emitting device B10 is equivalent to the electrical connection with the second node N2. Reusing the first electrode B101 of the light-emitting device B10 as the fourth electrode plate C2B in the second capacitor C2 facilitates the electrical connection between the second capacitor C2 and the second node N2, reduces the required structure, reduces the structural complexity of the display panel AA, and facilitates the feasibility of making the display panel AA thinner and lighter.

[0087] Figure 19 A schematic structural diagram of another display panel provided in an embodiment of the present application.

[0088] In one embodiment of the present application, Figure 19 As shown, the display panel AA further includes a second insulating layer D2 and a third insulating layer D3. The second insulating layer D2 is located between the first electrode B101 of the light-emitting device B10 and the first insulating layer D1. The third insulating layer D3 is located on the side of the first electrode B101 of the light-emitting device B10 away from the substrate A20.

[0089] The first insulating layer D1 includes a first opening D11. A portion of the second insulating layer D2 and a portion of the first electrode B101 of the light-emitting device B10 are located within the first opening D11. In a direction perpendicular to the plane of the display panel AA, the first opening D11 overlaps a portion of the second opening D31. In a direction perpendicular to the plane of the display panel AA, the third plate C2A of the second capacitor C2 is located between the second insulating layer D2 and the pixel circuit A10. The third plate C2A overlaps the first electrode B101 of the light-emitting device B10 and the first opening D11. The first electrode B101 of the light-emitting device B10 serves as the fourth plate C2B.

[0090] Combine Figure 18 As shown, the third electrode plate C2A can be located between the first insulating layer D1 and the pixel circuit B10. In this case, a portion of the first insulating layer D1 can serve as a dielectric layer between the third electrode plate C2A and the fourth electrode plate C2B. However, if the thickness of the first insulating layer D1 is relatively large, the distance between the third electrode plate C2A and the fourth electrode plate C2B may be relatively large when the first insulating layer D1 is used to form the second capacitor C2. This is not conducive to increasing the capacitance of the prepared second capacitor C2. In addition, when the thickness of the first insulating layer D1 is relatively large, the preparation of the second capacitor C2 to achieve the desired capacitance value usually adopts the method of increasing the electrode area, but this method takes up a large structural space.

[0091] So, if Figure 19 As shown, the embodiment of the present application proposes to open a first opening D11 in the first insulating layer D1 at a position overlapping with the third electrode C2A. Optionally, the first opening D11 does not include the first insulating layer D1 material. At this time, the first opening D11 exposes the third electrode C2A. In order to avoid direct contact between the third electrode C2A and the first pole B101 of the light-emitting device B10, a second insulating layer D2 is prepared between the first insulating layer D1 and the first pole B101 of the light-emitting device B10, so that part of the second insulating layer D2 is located in the first opening D11. Then, when preparing the first pole B101 of the light-emitting device B10, part of the first pole B101 is also prepared in the first opening D11. The first pole B101 of the part of the light-emitting device B10 located in the first opening D11 forms a second capacitor C2 with the third electrode C2A and the second insulating layer D2. During the preparation of the second capacitor C2, the thickness of the second insulating layer D2 can be adjusted according to actual usage requirements. When the thickness of the second insulating layer D2 is relatively small, it is beneficial to increase the capacitance of the second capacitor C2 and reduce the overlapping area of ​​the third plate C2A and the fourth plate C2B, thereby avoiding occupying a large preparation space.

[0092] Furthermore, the third insulating layer D3 includes a second opening D31, and the light-emitting device B10 is located in the second opening D31. The third insulating layer D3 can be used to separate adjacent light-emitting devices B10 in the display panel AA, and one light-emitting device B10 is prepared in one second opening D31. In the embodiment of the present application, when preparing the film layer other than the first pole B101 in the light-emitting device B10, at least part of the film layer is also prepared in the first opening D11. When the first pole B101 of the light-emitting device B10 is prepared in a direction parallel to the display panel AA, it also includes a portion located in the first opening D31, which is beneficial to increase the extension area of ​​the first pole B101, and part of the second opening D31 overlaps with the first opening D11. After the area of ​​the first pole B101 is increased by the first opening D11, it is beneficial to improve the ability of the first pole B101 to provide electrons or holes to the light-emitting device B10, thereby improving the luminous efficiency of the light-emitting device B10.

[0093] In another implementation of the embodiment of the present application, optionally, when the first opening D11 is formed, a portion of the first insulating layer D1 material is reserved according to the capacitance requirement of the second capacitor C2 so that the first opening D11 does not expose the third electrode plate C2A.

[0094] Figure 20 A schematic structural diagram of another display panel provided in an embodiment of the present application.

[0095] In one embodiment of the present application, Figure 20 As shown, the display panel AA also includes a second insulating layer D2 and a third insulating layer D3. The second insulating layer D2 is located between the first pole B101 of the light-emitting device B10 and the first insulating layer D1, and the third insulating layer D3 is located on the side of the first pole B101 of the light-emitting device B10 away from the substrate A20; the first insulating layer D1 includes a first opening D11, and part of the second insulating layer D2 and part of the first pole B101 of the light-emitting device B10 are located in the first opening D11; the third insulating layer D3 includes a second opening D31, and the light-emitting device B10 is located in the second opening D31; along the direction perpendicular to the plane where the display panel AA is located, the first opening D11 and the second opening D31 do not overlap.

[0096] In a direction perpendicular to the plane of the display panel AA, the third plate C2A of the second capacitor C1 is located between the first insulating layer D1 and the pixel circuit B10. The third plate C2A overlaps with the first pole B101 of the light-emitting device B10 and the first opening D11. The first pole B101 of the light-emitting device B10 is reused as the fourth plate C32.

[0097] The above embodiment describes that the preparation of the first opening D11 reduces the thickness of the dielectric layer between the third plate C2A and the fourth plate C2B of the second capacitor C2, thereby facilitating an increase in the capacitance of the second capacitor C2. However, in the present embodiment, the first opening D11 is configured to not overlap with the second opening D31 used to prepare the light-emitting device B10. This facilitates improving the flatness of the first electrode B10 and other film layers such as the light-emitting layer in the light-emitting device B10 during preparation, thereby improving the structural regularity of the prepared light-emitting device B10 and improving the operational stability and uniformity of the light-emitting device B10.

[0098] In an embodiment of the present application, the first pole B101 of the light-emitting device B10 is extended to the position where the first opening D11 is opened. At this time, the portion of the first pole B101 that can serve as the fourth pole plate C2B overlaps with the third pole plate C2A and does not overlap with other film layers of the light-emitting device B10, which is beneficial to improving the structural flatness when preparing the light-emitting device B10 and flexibly adjusting the structure of the second capacitor C2.

[0099] In one embodiment of the present application, a first sub-dividing module 10A is provided to include a first capacitor C1 , and the structure of the first capacitor C1 is the same as that of the second capacitor C2 .

[0100] In the embodiment of the present application, the first capacitor C1 and the second capacitor C2 are arranged to have the same structure. The same structure here means that the overlapping area and distance between the capacitor plates are the same, which is conducive to reducing the difficulty of preparation and improving the uniformity when the first capacitor C1 and the second capacitor C2 are shunted.

[0101] In one embodiment of the present application, continue to refer to 5, Figure 18 As shown, the first sub-dividing module 10A includes a first capacitor C1 , and the structure of the first capacitor C1 is different from that of the second capacitor C2 .

[0102] In the embodiment of the present application, the structures of the first capacitor C1 and the second capacitor C2 are set to be different, which is conducive to flexibly setting the first capacitor C1 and the second capacitor C2 according to the circuit conditions of the first node N1 and the second node N2, adaptively adjusting the capacitance of the first capacitor C1 and the second capacitor C2, and improving the accuracy of diversion.

[0103] Figure 21 A schematic diagram of another pixel circuit provided in an embodiment of the present application.

[0104] In one embodiment of the present application, Figure 21As shown, the pixel circuit B10 also includes a shunt control module 50, which is electrically connected to the node between the shunt module 10 and the driving transistor Md and the light-emitting device B10. The above embodiment mentioned that the node between the driving transistor Md and the light-emitting device B10 includes a first node N1 and a second node N2, and the shunt module 10 can be electrically connected to the first node N1 and / or the second node N2. Optionally, one end of the shunt control module 50 is electrically connected to the first node N1 and the other end is electrically connected to the shunt module 10. Optionally, one end of the shunt control module 50 is electrically connected to the first node N1 and the other end is electrically connected to the shunt module 10. Alternatively, a plurality of shunt control modules 50 are provided in the pixel circuit B10, one of which is electrically connected to the first node N1 and the other is electrically connected to the second node N2.

[0105] The shunt control module 50 is turned on during at least part of the light-emitting phase of the pixel circuit B10 and controls the shunt module 10 to receive part of the light-emitting drive current. The pixel circuit B10 also includes a transistor M2. The gate of the transistor M2 receives a valid signal transmitted by the light-emitting control signal line Emit during the light-emitting phase and turns on. The transistor M2 transmits the power supply voltage PVDD to the driving transistor Md, driving the driving transistor Md to generate a light-emitting drive current. In addition, the pixel circuit B10 also includes a first data voltage writing module 70 and a second data voltage writing module 80. The first data voltage writing module 70 is used to write a first data voltage Vdata to the driving transistor Md before the pixel circuit B10 enters the light-emitting phase. The second data voltage writing module 80 can be used to write a second data voltage Dvh of a compensatory nature to the driving transistor Md when the pixel circuit B10 maintains frame operation. The first data voltage Vdata can be used to regulate the magnitude of the light-emitting drive current generated by the driving transistor Md.

[0106] When the shunt control module 50 is on, some of the light-emitting drive current can be transmitted to the shunt module 10. When the shunt control module 50 is off, the shunt module 10 cannot receive the light-emitting drive current. When the pixel circuit B10 is operating in the light-emitting phase, the driving transistor Md generates a light-emitting drive current. At this time, the light-emitting drive current is output to the light-emitting device B10. At this time, the shunt control module 50 can be turned on to prepare the shunt module 10 for current diversion.

[0107] In an embodiment of the present application, a shunt control module 50 is provided between the shunt module 10 and the node electrically connected thereto, for controlling part of the light-emitting driving current to flow to the shunt module 10, and the shunt control module 50 is provided to be turned on during the light-emitting stage, which is conducive to accurately controlling the operation of the shunt module 10, avoiding the shunt module 10 from shunting at various stages of the operation of the pixel circuit B10, thereby avoiding the shunt module 10 from disrupting the working process of the pixel circuit B10, avoiding interfering with the normal electrical signal transmission of the pixel circuit B10, and improving the working stability of the pixel circuit B10.

[0108] Figure 22 A schematic diagram of another pixel circuit provided in an embodiment of the present application.

[0109] In one embodiment of the present application, Figure 21-22 As shown, pixel circuit B10 includes a light-emission control module 20, which is electrically connected to the driving transistor Md and the light-emitting device B10. The light-emission control module 20 is configured to turn on during the light-emission phase of the pixel circuit B10 and control the light-emitting device B10 to receive at least a portion of the light-emission drive current. During operation of the pixel circuit B10, the light-emission drive current can only be received by the light-emitting device B10 when the light-emission control module 20 is turned on. Optionally, the control terminal of the light-emission control module 20 is also electrically connected to the light-emission control signal line Emit, so that the light-emission control module 20 and the transistor M2 are both turned on during the light-emission phase.

[0110] In the embodiment of the present application, the control terminal 501 of the shunt control module 50 and the control terminal 201 of the light control module 20 are electrically connected to the same control signal line, which helps reduce the number of control signal lines provided in the display panel AA. This also helps ensure that the shunt module 10 also receives the light driving current when the light emitting device B10 receives the light driving current, thereby ensuring the stability of the shunt function of the shunt module 10. In combination with the above, the control signal line electrically connected to the control terminal 501 of the shunt control module 50 and the control terminal 201 of the light control module 20 can be the light control signal line Emit.

[0111] In one embodiment of the present application, the pixel circuit B10 operates in a first mode W1 and a second mode W2. The current shunt control module 50 is turned on in the first mode W1 and is not turned on in the second mode W2. The luminance of the light-emitting device B10 in the first mode W1 is lower than that in the second mode W2. The first mode W1 is the operating process when the light-emitting device B10 needs to receive a small current to emit light. In this case, the luminance is low. When the driving transistor Md generates a small current, the current is significantly affected by the threshold bias. The second mode W2 is the operating process when the light-emitting device B10 needs to receive a large current to emit light. In this case, the luminance is higher.

[0112] In the embodiment of the present application, the shunt control module 50 is set to be turned on in the first mode W1 and not turned on in the second mode W2. This is beneficial to ensure that the shunt module 10 is turned on when the light-emitting device B10 requires a small current. In combination with the control drive transistor Md, a relatively large current can be generated, thereby reducing the impact of the threshold bias on the light-emitting drive current and ensuring the accuracy of the light-emitting drive current received by the light-emitting device B10. Setting the shunt control module 50 to be turned off in the second mode W2 is beneficial to prevent the shunt module 10 from being turned on when not necessary, thereby reducing the power consumption of the pixel circuit A10.

[0113] Figure 23 A schematic diagram of a display device provided in an embodiment of the present application.

[0114] The embodiment of the present application provides a display device AA1, such as Figure 23 As shown, the display device AA1 includes the display panel AA provided in the above embodiment. The display device AA1 can be a device that can be used for display, such as a computer, a television, a mobile phone, etc.

[0115] In display device AA1, the node between the driver transistor Md of pixel circuit A10 and the light-emitting device B10 is electrically connected to a shunt module 10, increasing the light-emitting drive current generated by the driver transistor Md. This helps reduce the impact of the driver transistor Md's threshold bias on the light-emitting drive current and improves the accuracy of the light-emitting drive current generated by the driver transistor Md. Furthermore, the light-emitting drive current ΔI required by the shunt module 10 is a relatively stable value. By quantizing the light-emitting drive current using the formula I2 = I1 + ΔI, the accuracy of the light-emitting drive current provided to the light-emitting device B10 is improved, thereby improving the accuracy of the light-emitting brightness of the light-emitting device B10. Furthermore, embodiments of the present application help ensure the accuracy of the low light-emitting drive current received by the light-emitting device B10, improve the accuracy of the light-emitting brightness of the display panel AA at low grayscales, and enhance the display quality of the display panel AA.

[0116] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The device comprises a pixel circuit and a light-emitting device, wherein the pixel circuit is electrically connected to a first electrode of the light-emitting device, and the pixel circuit comprises: A driving transistor, wherein the driving transistor is used to generate a light-emitting driving current; a light emitting control module, the light emitting control module electrically connecting the driving transistor and the light emitting device; A first node is located between the driving transistor and the light emitting control module; A shunt module, the shunt module being electrically connected to a node between the driving transistor and the light-emitting device; the shunt module comprising a first sub-shunt module, the first sub-shunt module being electrically connected to the first node; the first sub-shunt module comprising a first capacitor, the first capacitor comprising a first plate and a second plate; The light-emitting driving current received by the light-emitting device is I1, the light-emitting driving current generated by the driving transistor is I2, I2=I1+ΔI, ΔI is the light-emitting driving current received by the shunt module; The first electrode of the driving transistor is electrically connected to the first node; the display panel includes a substrate, and the driving transistor is located on one side of the substrate; the driving transistor includes an active layer and a gate, and the active layer is located on the side of the gate facing the substrate, and the active layer includes a first part, a second part, and a third part, and the second part overlaps with the gate along a direction perpendicular to the plane where the display panel is located; along the extension direction of the active layer, the first part and the third part are respectively located on opposite sides of the second part, and the first part is reused as the first electrode of the driving transistor; the width of the first part along the first direction is greater than the width of the third part along the first direction, and the first direction is parallel to the plane where the display panel is located and intersects with the extension direction of the active layer.

2. The display panel according to claim 1, wherein: The pixel circuit further includes a first reset module, wherein a first terminal of the first reset module receives a first reset voltage and a second terminal of the first reset module is electrically connected to the first node.

3. The display panel according to claim 1, wherein: The first electrode plate of the first capacitor is located on the side of the gate of the driving transistor away from the substrate; in a direction perpendicular to the plane where the display panel is located, the first electrode plate covers the first part, and the first part is reused as the second electrode plate of the first capacitor.

4. The display panel according to claim 1 or 3, wherein: The first electrode plate of the first capacitor is located on a side of the active layer of the driving transistor facing the substrate; In a direction perpendicular to the plane where the display panel is located, the first electrode plate covers the first portion, and the first portion is reused as the second electrode plate of the first capacitor.

5. The display panel according to claim 1, wherein: The pixel circuit further includes a second node located between the light emitting control module and the light emitting device; The shunt module includes a second sub-shunt module, and the second sub-shunt module is electrically connected to the second node.

6. The display panel according to claim 5, characterized in that The pixel circuit further includes a second reset module, wherein a first terminal of the second reset module receives a second reset voltage, and a second terminal of the second reset module is electrically connected to the second node.

7. The display panel according to claim 5, wherein: The second sub-dividing module includes a second capacitor, and the second capacitor includes a third electrode plate and a fourth electrode plate.

8. The display panel according to claim 7, wherein: The display panel includes a substrate, the pixel circuit is located on one side of the substrate, and the light emitting device is located on a side of the pixel circuit away from the substrate; a first insulating layer is included between the pixel circuit and the first electrode of the light emitting device; In a direction perpendicular to the plane of the display panel, the third plate of the second capacitor is located between the first insulating layer and the pixel circuit, and the third plate at least partially overlaps with the first pole of the light-emitting device, and the first pole of the light-emitting device is reused as the fourth plate.

9. The display panel according to claim 8, wherein: The display panel further includes a second insulating layer and a third insulating layer, wherein the second insulating layer is located between the first electrode of the light-emitting device and the first insulating layer, and the third insulating layer is located on a side of the first electrode of the light-emitting device away from the substrate; the first insulating layer includes a first opening, and a portion of the second insulating layer and a portion of the first electrode of the light-emitting device are located within the first opening; the third insulating layer includes a second opening, and the light-emitting device is located within the second opening; Along a direction perpendicular to the plane where the display panel is located, the first opening overlaps a portion of the second opening; In a direction perpendicular to the plane of the display panel, the third plate of the second capacitor is located between the second insulating layer and the pixel circuit, the third plate overlaps with the first pole of the light-emitting device and the first opening, and the first pole of the light-emitting device is reused as the fourth plate.

10. The display panel according to claim 8, wherein The display panel further includes a second insulating layer and a third insulating layer, wherein the second insulating layer is located between the first electrode of the light-emitting device and the first insulating layer, and the third insulating layer is located on a side of the first electrode of the light-emitting device away from the substrate; the first insulating layer includes a first opening, and a portion of the second insulating layer and a portion of the first electrode of the light-emitting device are located within the first opening; the third insulating layer includes a second opening, and the light-emitting device is located within the second opening; Along a direction perpendicular to the plane where the display panel is located, the first opening and the second opening do not overlap; In a direction perpendicular to the plane of the display panel, the third plate of the second capacitor is located between the second insulating layer and the pixel circuit, the third plate overlaps with the first pole of the light-emitting device and the first opening, and the first pole of the light-emitting device is reused as the fourth plate.

11. The display panel according to claim 7, wherein: The first sub-dividing module includes a first capacitor, and the structure of the first capacitor is the same as that of the second capacitor.

12. The display panel according to claim 7, wherein: The first sub-dividing module includes a first capacitor, and the structure of the first capacitor is different from that of the second capacitor.

13. The display panel according to claim 1, wherein The pixel circuit also includes a shunt control module, which electrically connects the shunt module to the node between the driving transistor and the light-emitting device; the shunt control module is turned on during at least part of the light-emitting stage of the pixel circuit and controls the shunt module to receive part of the light-emitting driving current.

14. The display panel according to claim 13, wherein: The pixel circuit includes a light emitting control module, the light emitting control module being electrically connected to the driving transistor and the light emitting device; the light emitting control module being configured to be turned on during a light emitting phase of the pixel circuit and to control the light emitting device to receive at least part of the light emitting driving current; The control end of the shunt control module and the control end of the light emitting control module are electrically connected to the same control signal line.

15. The display panel according to claim 13, wherein: The operation of the pixel circuit includes a first mode and a second mode. The shunt control module is turned on in the first mode and not turned on in the second mode. The luminous brightness of the light-emitting device in the first mode is lower than the luminous brightness in the second mode.

16. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 15.

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