Display device

Abstract

The present application provides a display device, comprising multiple rows of pixels and a multi-stage gate drive circuit, wherein a first gate drive subcircuit of the gate drive circuit comprises a first stage transmission circuit and a first output circuit, wherein the first output circuit comprises an eighteenth transistor, a twenty-first transistor, a twenty-second transistor, and a fifth capacitor, wherein one plate of the fifth capacitor is electrically connected to a first control node I, and the other plate is electrically connected to a first or second low-level signal input terminal, wherein in a top view of the gate drive circuit, the first high-level signal line is located on a first side of the first low-level signal line, and the fifth capacitor is located on a second side of the first low-level signal line. Through the above technical solution, the fifth capacitor is prevented from having a coupling effect on the potential of the signal transmitted by the high-level signal input terminal, thereby preventing the potential of the first scanning signal from fluctuating, and improving the display abnormality that occurs at the boundary between different areas when the display device turns on the frequency division display function.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] To provide better display quality and user experience, frequency-splitting display technology is widely used in OLED display panels. Frequency-splitting display technology uses different refresh rates in different areas of the same display panel. For example, a 120Hz refresh rate is used in the area displaying dynamic content, while a 60Hz refresh rate is used in the area displaying static content. This ensures the smoothness of dynamic images while reducing power consumption.

[0003] However, in OLED display panels that use frequency division display technology, when the refresh frequencies of different areas are switched, display anomalies may occur at the boundaries between different areas due to design issues with the gate drive circuit. This display anomaly may affect the display effect and user experience. Summary of the Invention

[0004] An object of the embodiments of the present application is to provide a display device to improve display abnormality occurring at the boundary between different areas when the display device turns on the frequency division display function.

[0005] An embodiment of the present application provides a display device, including a display panel, wherein the display panel includes multiple rows of pixels and multiple levels of gate drive circuits, wherein the first level of the gate drive circuit includes: a first gate drive sub-circuit, the first gate drive sub-circuit includes a first-level transmission circuit and a first output circuit, the first output circuit includes: an eighteenth transistor, the gate of the eighteenth transistor is electrically connected to the first control node I, and the source of the eighteenth transistor is electrically connected to the second control node F of the first-level transmission circuit; a twenty-first transistor, the gate of the twenty-first transistor is electrically connected to the third control node G of the first-level transmission circuit, the source of the twenty-first transistor is electrically connected to the first low-level signal input terminal of the display panel, and the drain of the twenty-first transistor is electrically connected to the second control node F of the first-level transmission circuit. a first scanning signal output terminal of a gate driving sub-circuit electrically connected; a twenty-second transistor, the gate of the twenty-second transistor is electrically connected to the drain of the eighteenth transistor, the source of the twenty-second transistor is electrically connected to the first high-level signal input terminal of the display panel, and the drain of the twenty-second transistor is electrically connected to the first scanning signal output terminal; and a fifth capacitor, one plate of the fifth capacitor is electrically connected to the first control node I, and the other plate of the fifth capacitor is electrically connected to the first low-level signal input terminal; wherein, in a top view of the gate driving circuit, the first high-level signal line is located on a first side of the first low-level signal line, and the fifth capacitor is located on a second side of the first low-level signal line opposite to the first side.

[0006] In the above-mentioned display device, the first output circuit also includes: a nineteenth transistor, the gate of the nineteenth transistor is electrically connected to the node D, the source of the nineteenth transistor is electrically connected to the first high-level signal input terminal, and the drain of the nineteenth transistor is electrically connected to the node H; a twentieth transistor, the gate of the twentieth transistor is electrically connected to the node D, the source of the twentieth transistor is electrically connected to the first control signal input terminal, and the drain of the twentieth transistor is electrically connected to the gate of the eighteenth transistor; and a fourth capacitor, one plate of the fourth capacitor is electrically connected to the node H, and the other plate of the fourth capacitor is electrically connected to the first high-level signal input terminal.

[0007] In the above-mentioned display device, the first-stage transmission circuit includes: a first transistor, the gate of the first transistor is electrically connected to the node C, and the source of the first transistor is electrically connected to the first high-level signal input terminal; a second transistor, the gate of the second transistor is electrically connected to the node E, the source of the second transistor is electrically connected to the first clock signal input terminal, and the drain of the second transistor is electrically connected to the drain of the first transistor; a third transistor, the gate of the third transistor is electrically connected to the second clock signal input terminal, the source of the third transistor is electrically connected to the first-stage transmission signal input terminal, and the drain of the third transistor is electrically connected to the node D; a fourth transistor, the gate of the fourth transistor is electrically connected to the second clock signal input terminal an input terminal, a source of the fourth transistor is electrically connected to the first low-level signal input terminal, and a drain of the fourth transistor is electrically connected to the node C; a fifth transistor, a gate of the fifth transistor is electrically connected to the node D, a source of the fifth transistor is electrically connected to the second clock signal input terminal, and a drain of the fifth transistor is electrically connected to the node C; a sixth transistor, a gate of the sixth transistor is electrically connected to the node B, a source of the sixth transistor is electrically connected to the first clock signal input terminal, and a drain of the sixth transistor is electrically connected to the node A; a seventh transistor, a gate of the seventh transistor is electrically connected to the first clock signal input terminal, and a source of the seventh transistor is electrically connected to the node A an eighth transistor, the gate of the eighth transistor is electrically connected to the node D, the source of the eighth transistor is electrically connected to the first high-level signal input terminal, and the drain of the eighth transistor is electrically connected to the second control node F; a ninth transistor, the gate of the ninth transistor is electrically connected to the third control node G, the source of the ninth transistor is electrically connected to the first low-level signal input terminal, and the drain of the ninth transistor is electrically connected to the first-stage transmission signal output terminal; a tenth transistor, the gate of the tenth transistor is electrically connected to the second control node F, the source of the tenth transistor is electrically connected to the first high-level signal input terminal, and the drain of the tenth transistor is electrically connected to the first-stage transmission signal output terminal an eleventh transistor, the gate of the eleventh transistor being electrically connected to the first low-level signal input terminal, the source of the eleventh transistor being electrically connected to the node C, and the drain of the eleventh transistor being electrically connected to the node B; a twelfth transistor, the gate of the twelfth transistor being electrically connected to the first low-level signal input terminal, the source of the twelfth transistor being electrically connected to the node D, and the drain of the twelfth transistor being electrically connected to the third control node G; a thirteenth transistor, the gate of the thirteenth transistor being electrically connected to the first control signal input terminal, the source of the thirteenth transistor being electrically connected to the first high-level signal input terminal, and the drain of the thirteenth transistor being electrically connected to the node D;a fourteenth transistor, wherein the gate of the fourteenth transistor is electrically connected to the second clock signal input terminal, and the source of the fourteenth transistor is electrically connected to the first-stage transmission signal input terminal; a fifteenth transistor, wherein the gate of the fifteenth transistor is electrically connected to the first low-level signal input terminal, the source of the fifteenth transistor is electrically connected to the drain of the fourteenth transistor, and the drain of the fifteenth transistor is electrically connected to the node E; a sixteenth transistor, wherein the gate of the sixteenth transistor is electrically connected to the node E, the source of the sixteenth transistor is electrically connected to the node E, and the drain of the sixteenth transistor is electrically connected to the third control node G; a seventeenth transistor, wherein the seventeenth transistor The gate of the seventeenth transistor is electrically connected to the second control signal input terminal, the source of the seventeenth transistor is electrically connected to the drain of the seventh transistor, and the drain of the seventeenth transistor is electrically connected to the second control node F; a first capacitor, one plate of the first capacitor is electrically connected to the node E, and the other plate of the first capacitor is electrically connected to the drain of the first transistor; a second capacitor, one plate of the second capacitor is electrically connected to the node A, and the other plate of the second capacitor is electrically connected to the node B; and a third capacitor, one plate of the third capacitor is electrically connected to the second control node F, and the other plate of the third capacitor is electrically connected to the first high-level signal input terminal.

[0008] In the above display device, the first-stage transmission circuit further includes: a sixth capacitor, one plate of the sixth capacitor is electrically connected to the third control node G, and the other plate of the sixth capacitor is electrically connected to the first-stage transmission signal output terminal.

[0009] In the above-mentioned display device, the display panel also includes a second gate driving sub-circuit and a second high-level signal line, the second gate driving sub-circuit is electrically connected to the second high-level signal line, and in the top view of the gate driving circuit, the second high-level signal line is located on the first side of the first low-level signal line.

[0010] An embodiment of the present application further provides a display device, including a display panel, the display panel including multiple rows of pixels and multiple levels of gate drive circuits, wherein the first level of the gate drive circuit includes: a first gate drive sub-circuit, the first gate drive sub-circuit including a first-level transmission circuit and a first output circuit, the first output circuit including: an eighteenth transistor, the gate of the eighteenth transistor being electrically connected to a first control node I, the source of the eighteenth transistor being electrically connected to a second control node F of the first-level transmission circuit; a twenty-first transistor, the gate of the twenty-first transistor being electrically connected to a third control node G of the first-level transmission circuit, the source of the twenty-first transistor being electrically connected to a first low-level signal input terminal of the display panel, and the drain of the twenty-first transistor being electrically connected to a first scan signal output terminal of the first gate drive sub-circuit ; a twenty-second transistor, the gate of the twenty-second transistor is electrically connected to the drain of the eighteenth transistor, the source of the twenty-second transistor is electrically connected to the first high-level signal input terminal of the display panel, and the drain of the twenty-second transistor is electrically connected to the first scanning signal output terminal; and a fifth capacitor, one plate of the fifth capacitor is electrically connected to the first control node I, and the other plate of the fifth capacitor is electrically connected to the second low-level signal input terminal of the display panel; wherein, in the top view of the gate drive circuit, the first high-level signal line is located on a first side of the second low-level signal line, the fifth capacitor is located on a second side of the second low-level signal line opposite to the first side, and the first low-level signal line is located on a side of the first high-level signal line away from the second low-level signal line.

[0011] In the above-mentioned display device, the first output circuit also includes: a nineteenth transistor, the gate of the nineteenth transistor is electrically connected to the node D, the source of the nineteenth transistor is electrically connected to the first high-level signal input terminal, and the drain of the nineteenth transistor is electrically connected to the node H; a twentieth transistor, the gate of the twentieth transistor is electrically connected to the node D, the source of the twentieth transistor is electrically connected to the first control signal input terminal, and the drain of the twentieth transistor is electrically connected to the gate of the eighteenth transistor; and a fourth capacitor, one plate of the fourth capacitor is electrically connected to the node H, and the other plate of the fourth capacitor is electrically connected to the first high-level signal input terminal.

[0012] In the above-mentioned display device, the first gate drive subcircuit also includes a first-level transmission circuit, which includes: a first transistor, the gate of the first transistor is electrically connected to the node C, and the source of the first transistor is electrically connected to the first high-level signal input terminal; a second transistor, the gate of the second transistor is electrically connected to the node E, the source of the second transistor is electrically connected to the first clock signal input terminal, and the drain of the second transistor is electrically connected to the drain of the first transistor; a third transistor, the gate of the third transistor is electrically connected to the second clock signal input terminal, the source of the third transistor is electrically connected to the first-level transmission signal input terminal, and the drain of the third transistor is electrically connected to the node D; a fourth transistor, the fourth a first transistor, a second transistor, a gate electrically connected to the second clock signal input terminal, a source electrically connected to the first low-level signal input terminal, and a drain electrically connected to the node C; a fifth transistor, a gate electrically connected to the node D, a source electrically connected to the second clock signal input terminal, and a drain electrically connected to the node C; a sixth transistor, a gate electrically connected to the node B, a source electrically connected to the first clock signal input terminal, and a drain electrically connected to the node A; a seventh transistor, a gate electrically connected to the first clock signal input terminal, and a drain electrically connected to the node C; a seventh transistor, a gate electrically connected to the first clock signal input terminal, and a drain electrically connected to the node A. a ninth transistor, a gate of the ninth transistor being electrically connected to the third control node G, a source of the ninth transistor being electrically connected to the first low-level signal input terminal, and a drain of the ninth transistor being electrically connected to the first-stage transmission signal output terminal; a tenth transistor, a gate of the tenth transistor being electrically connected to the second control node F, a source of the tenth transistor being electrically connected to the first high-level signal input terminal, and a drain of the tenth transistor being electrically connected to the first-stage transmission signal output terminal. a first transistor electrically connected to the first low-level signal input terminal, a source electrically connected to the node C, and a drain electrically connected to the node B; a second transistor electrically connected to the first low-level signal input terminal, a source electrically connected to the node D, and a drain electrically connected to the third control node G; a third transistor electrically connected to the first control signal input terminal, a source electrically connected to the first high-level signal input terminal, and a drain electrically connected to the node D;a fourteenth transistor, wherein the gate of the fourteenth transistor is electrically connected to the second clock signal input terminal, and the source of the fourteenth transistor is electrically connected to the first-stage transmission signal input terminal; a fifteenth transistor, wherein the gate of the fifteenth transistor is electrically connected to the first low-level signal input terminal, the source of the fifteenth transistor is electrically connected to the drain of the fourteenth transistor, and the drain of the fifteenth transistor is electrically connected to the node E; a sixteenth transistor, wherein the gate of the sixteenth transistor is electrically connected to the node E, the source of the sixteenth transistor is electrically connected to the node E, and the drain of the sixteenth transistor is electrically connected to the third control node G; a seventeenth transistor, wherein the seventeenth transistor The gate of the seventeenth transistor is electrically connected to the second control signal input terminal, the source of the seventeenth transistor is electrically connected to the drain of the seventh transistor, and the drain of the seventeenth transistor is electrically connected to the second control node F; a first capacitor, one plate of the first capacitor is electrically connected to the node E, and the other plate of the first capacitor is electrically connected to the drain of the first transistor; a second capacitor, one plate of the second capacitor is electrically connected to the node A, and the other plate of the second capacitor is electrically connected to the node B; and a third capacitor, one plate of the third capacitor is electrically connected to the second control node F, and the other plate of the third capacitor is electrically connected to the first high-level signal input terminal.

[0013] In the above display device, the first-stage transmission circuit further includes: a sixth capacitor, one plate of the sixth capacitor is electrically connected to the third control node G, and the other plate of the sixth capacitor is electrically connected to the first-stage transmission signal output terminal.

[0014] In the above-mentioned display device, the display panel also includes a second gate driving sub-circuit and a second high-level signal line, the second gate driving sub-circuit is electrically connected to the second high-level signal line and the second low-level signal line, and in the top view of the gate driving circuit, the second high-level signal line is located on the first side of the second low-level signal line, and the second high-level signal line is located between the first low-level signal line and the second low-level signal line.

[0015] In the display device provided in the embodiment of the present application, since one plate of the fifth capacitor in the first output circuit of the first gate driving sub-circuit in the gate driving circuit is electrically connected to the node I of the first output circuit, and the other plate is electrically connected to the first low-level signal input terminal of the first gate driving sub-circuit or the second low-level signal input terminal of the second gate driving sub-circuit, and the first high-level signal input terminal is insulated from the fifth capacitor, when the first control signal input terminal inputs the first control signal to the node I, the fifth capacitor will not have a coupling effect on the potential of the signal transmitted by the first high-level signal input terminal, thereby avoiding the problem of fluctuation of the potential of the signal transmitted by the first high-level signal input terminal due to the coupling effect between the fifth capacitor and the first high-level signal input terminal.

[0016] Furthermore, because the potential of the signal transmitted by the first high-level signal input terminal is not affected by the coupling effect of the fifth capacitor and thus does not fluctuate, and because the first gate driver sub-circuit generates the first scanning signal based on the signals transmitted by the first high-level signal input terminal and the first low-level signal input terminal, the potential of the first scanning signal is also not affected by the coupling effect of the fifth capacitor and thus does not fluctuate. Since the potential of the first scanning signal does not fluctuate, the turning on or off of the third transistor in the pixel driver circuit of the pixel is not affected. The second capacitor electrically connected to the drain of the third transistor does not exert a coupling effect on the gate of the second transistor, which is also electrically connected to the second capacitor, and thus does not affect the turning on or off of the second transistor, thereby avoiding the problem of abnormal data signal writing.

[0017] In addition, since the data signal can be written into the pixel normally, when the display device turns on the frequency division display function, there will be no display abnormality at the boundary between different areas due to abnormal data signal writing, thereby improving the display effect of the display device when the frequency division display function is turned on.

[0018] In addition, since one plate of the fifth capacitor is electrically connected to node I of the first output circuit, and the other plate is electrically connected to the first low-level signal input terminal of the first gate driving sub-circuit or the second low-level signal input terminal of the second gate driving sub-circuit, rather than the first high-level signal input terminal, in the layout of the gate driving circuit, the first low-level signal line of the first gate driving sub-circuit or the second low-level signal line of the second gate driving sub-circuit can be arranged between the whole formed by the first high-level signal line and the second high-level signal line and the fifth capacitor, thereby making the layout of the first high-level signal line and the second high-level signal line more uniform, avoiding the uneven layout of the first high-level signal line and the second high-level signal line caused by the fifth capacitor being electrically connected to the first high-level signal input terminal and occupying the routing space of the first high-level signal line and / or the second high-level signal line, thereby avoiding the uneven load problem caused by the uneven layout of the first high-level signal line and the second high-level signal line, and improving the working stability of the gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of a potential fluctuation phenomenon of a first scanning signal in a conventional display device.

[0020] Figure 2 is a schematic diagram of a display device provided in an embodiment of the present application.

[0021] Figure 3 is a circuit diagram of a pixel in a display device provided in an embodiment of the present application.

[0022] Figure 4 This is a circuit diagram of a first embodiment of a first gate driving sub-circuit in a display device provided in this application.

[0023] Figure 5 This is a layout diagram of a first embodiment of a first gate driving sub-circuit in a display device provided in this application.

[0024] Figure 6 This is a circuit diagram of a second embodiment of the first gate driving sub-circuit in the display device provided by this application.

[0025] Figure 7 This is a layout diagram of a second embodiment of the first gate driving sub-circuit in the display device provided in this application. DETAILED DESCRIPTION

[0026] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0027] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0028] The embodiments of the present application may be combined with each other.

[0029] like Figure 1 As shown, in a conventional display device, when the first control signal inputted by the first control signal input terminal CTRL1 switches from a low potential to a high potential, the scanning signal (such as Nout2) outputted by the multi-stage gate driving circuit <1327> To Nout2 <1338> ) There will be potential fluctuation phenomenon CPL.

[0030] Fluctuations in the potential of the scanning signal can affect the on / off switching of the third transistor Tp3 in the pixel PX, leading to abnormal data signal writing. When the display device uses the frequency division display function, due to the different refresh rates of pixels PX in different areas, the abnormal data signal writing phenomenon is more obvious at the boundary between different areas, resulting in display abnormality.

[0031] The embodiments of the present application aim to provide a display device to solve the above technical problems.

[0032] like Figure 2 As shown, the display device provided by the embodiment of the present application includes a display panel, a timing controller, a source driving circuit and a power management chip. The display panel is an organic light emitting diode display panel.

[0033] The display panel includes a display area and a non-display area. The display area is provided with m×n pixels PX arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange the drive circuit and various signal lines. The display panel also includes a plurality of scan lines SCAN, a plurality of data lines DATA and a gate drive circuit. The plurality of scan lines SCAN extend along a first direction and are arranged along a second direction, and the plurality of data lines DATA extend along a second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate drive circuit is provided in the non-display area and is electrically connected to the plurality of scan lines SCAN. The source drive circuit is electrically connected to the plurality of data lines DATA through a flexible circuit board. The timing controller is electrically connected to the gate drive circuit and the source drive circuit, respectively.

[0034] The display panel includes an organic light-emitting diode array substrate and an encapsulation layer. The organic light-emitting diode array substrate includes a base substrate, a buffer layer disposed on the base substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed within an opening area defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes scan lines SCAN, a gate electrode, etc. The second metal layer includes data lines DATA, a source electrode, a drain electrode, etc. The encapsulation layer is sealed and connected to the organic light-emitting diode array substrate to prevent moisture and oxygen from invading the organic light-emitting layer.

[0035] Each pixel PX includes a pixel driver circuit and an organic light-emitting diode (OLED). The pixel driver circuit includes at least two thin-film transistors and a storage capacitor. One thin-film transistor functions as a switching transistor, with its gate electrically connected to the corresponding scan line and its source electrically connected to the corresponding data line. The other thin-film transistor functions as a driving transistor, with its gate electrically connected to the drain of the switching transistor, its source electrically connected to a first power supply voltage line, and its drain electrically connected to the anode of the organic light-emitting diode (OLED). One end of the storage capacitor is electrically connected to the gate of the driving transistor and the other end is electrically connected to either the source or drain of the driving transistor. The cathode of the organic light-emitting diode (OLED) is electrically connected to a second power supply voltage line. When the scan line outputs a high-voltage scan signal, the switching transistor turns on, and the data signal on the data line is written to the gate of the driving transistor and the storage capacitor through the switching transistor. When the scan line outputs a low-voltage scan signal, the switching transistor turns off, and the storage capacitor maintains the voltage at the gate of the driving transistor. The driving transistor generates a drive current corresponding to the gate voltage, driving the organic light-emitting diode (OLED) to emit light.

[0036] Each gate drive circuit is electrically connected to a scan line. Under the control of the timing controller, the gate drive circuit sequentially outputs scan signals, scanning the pixels PX in the display area row by row. Under the control of the timing controller, the source drive circuit generates and outputs data signals based on the image data. The timing controller is used to receive and process external image data and timing signals, generate control signals, and transmit image data to the source drive circuit. The power management chip is used to provide operating voltages for various parts of the display device, including providing a second power supply voltage VSS to the cathode of the organic light-emitting diode OLED, providing a first power supply voltage VDD to the first power supply voltage line, and providing gate drive voltages VGH / VGL to the gate drive circuit.

[0037] The display device provided by the embodiment of the present application includes a display panel, which includes multiple rows of pixels PX. Each pixel PX includes a pixel driving circuit and a light-emitting device OLED, and the pixel driving circuit is electrically connected to the light-emitting device OLED.

[0038] like Figure 3 As shown, the pixel driving circuit includes a thin film transistor Tp1, a thin film transistor Tp2, a thin film transistor Tp3, a thin film transistor Tp4, a thin film transistor Tp5, a thin film transistor Tp6, a thin film transistor Tp7, a thin film transistor Tp8, a capacitor Cst and a capacitor Cboost.

[0039] Among them, the thin film transistors Tp1 , Tp2 , Tp5 , Tp6 , Tp7 , and Tp8 are P-type thin film transistors, and the thin film transistors Tp3 and Tp4 are N-type thin film transistors.

[0040] The gate of thin-film transistor Tp1 is electrically connected to node Q, the source of thin-film transistor Tp1 is electrically connected to node P, and the drain of thin-film transistor Tp1 is electrically connected to node R. The gate of thin-film transistor Tp2 is electrically connected to the second scan signal input terminal Pscan1, the source of thin-film transistor Tp2 is electrically connected to the data signal input terminal Data, and the drain of thin-film transistor Tp2 is electrically connected to node P. The gate of thin-film transistor Tp3 is electrically connected to the first scan signal input terminal Nscan1 (Nout2), the source of thin-film transistor Tp3 is electrically connected to node R, and the drain of thin-film transistor Tp3 is electrically connected to node Q. The gate of thin-film transistor Tp4 is electrically connected to the third scan signal input terminal Nscan2, the source of thin-film transistor Tp4 is electrically connected to the first reset signal input terminal Vi1, and the drain of thin-film transistor Tp4 is electrically connected to node Q. The gate of thin-film transistor Tp5 is electrically connected to the first emission control signal input terminal EM, the source of thin-film transistor Tp5 is electrically connected to the first power signal input terminal VDD, and the drain of thin-film transistor Tp5 is electrically connected to node P. The gate of thin-film transistor Tp6 is electrically connected to the first emission control signal input terminal EM, the source of thin-film transistor Tp6 is electrically connected to node R, and the drain of thin-film transistor Tp6 is electrically connected to node S. The gate of thin-film transistor Tp7 is electrically connected to the fourth scan signal input terminal Pscan2, the source of thin-film transistor Tp7 is electrically connected to the second reset signal input terminal Vi2, and the drain of thin-film transistor Tp7 is electrically connected to node S. The gate of thin-film transistor Tp8 is electrically connected to the fourth scan signal input terminal Pscan2, the source of thin-film transistor Tp8 is electrically connected to the third reset signal input terminal Vi3, and the drain of thin-film transistor Tp8 is electrically connected to node R. One plate of capacitor Cst is electrically connected to node Q, and the other plate of capacitor Cst is electrically connected to the first power signal input terminal VDD. One plate of capacitor Cboost is electrically connected to node Q, and the other plate of capacitor Cboost is electrically connected to the second scan signal input terminal Pscan1. The anode of light emitting device OLED is electrically connected to node S, and the cathode of light emitting device OLED is electrically connected to the second power signal input terminal VSS.

[0041] The display panel also includes a cascaded multi-stage gate driving circuit. The first-stage gate driving circuit includes a first gate driving sub-circuit and a second gate driving sub-circuit, wherein the first gate driving sub-circuit is used to output a first scanning signal Nscan1 (Nout2), and the second gate driving sub-circuit is used to output a second scanning signal Pscan1. Figure 4 and Figure 6As shown, the first gate driver subcircuit includes a first-stage transmission circuit 401 and a first output circuit 402. The first-stage transmission circuit 401 is electrically connected to the first output circuit 402. The first output circuit 402 is used to output a first scan signal Nscan1 (Nout2) to a row of pixels PX. The first-stage transmission circuit 401 is used to output a stage transmission signal to the first gate driver subcircuit of the gate driver circuit of another stage. The second gate driver subcircuit includes a second-stage transmission circuit and a second output circuit. The second-stage transmission circuit is electrically connected to the second output circuit. The second output circuit is used to output a second scan signal Pscan1 to the row of pixels PX. The second-stage transmission circuit is used to output a stage transmission signal to the second gate driver subcircuit of the gate driver circuit of another stage. The technical solutions of the embodiments of the present application mainly improve the first gate driver subcircuit.

[0042] The first output circuit 402 includes an eighteenth transistor Ts18 , a twentieth transistor Ts20 , a twenty-first transistor Ts21 , and a fifth capacitor C5 .

[0043] The gate of the eighteenth transistor Ts18 is electrically connected to the first control node I, the source of the eighteenth transistor Ts18 is electrically connected to the second control node F of the first-stage transfer circuit 401, and the drain of the eighteenth transistor Ts18 is electrically connected to the node H. The gate of the twenty-first transistor Ts21 is electrically connected to the node G (the third control node) of the first-stage transfer circuit 401, the source of the twenty-first transistor Ts21 is electrically connected to the first low-level signal input terminal VGL1 of the display panel, and the drain of the twenty-first transistor Ts21 is electrically connected to the first scan signal output terminal Nout2 of the first gate drive sub-circuit. The gate of the twenty-second transistor Ts22 is electrically connected to the node H (the drain of the eighteenth transistor Ts18), the source of the twenty-second transistor Ts22 is electrically connected to the first high-level signal input terminal VGH1 of the display panel, and the drain of the twenty-second transistor Ts22 is electrically connected to the first scan signal output terminal Nout2. One plate of the fifth capacitor C5 is electrically connected to the first control node I, and the other plate of the fifth capacitor C5 is electrically connected to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit or the second low-level signal input terminal VGL2 of the display panel (the second low-level signal input terminal VGL2 is electrically connected to the second gate driving sub-circuit).

[0044] The first-stage transmission circuit 401 includes a first transistor Ts1, a second transistor Ts2, a third transistor Ts3, a fourth transistor Ts4, a fifth transistor Ts5, a sixth transistor Ts6, a seventh transistor Ts7, an eighth transistor Ts8, a ninth transistor Ts9, a tenth transistor Ts10, an eleventh transistor Ts11, a twelfth transistor Ts12, a thirteenth transistor Ts13, a fourteenth transistor Ts14, a fifteenth transistor Ts15, a sixteenth transistor Ts16, a seventeenth transistor Ts17, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0045] The gate of the first transistor Ts1 is electrically connected to the node C, and the source of the first transistor Ts1 is electrically connected to the first high-level signal input terminal VGH1. The gate of the second transistor Ts2 is electrically connected to the node E, the source of the second transistor Ts2 is electrically connected to the first clock signal input terminal CK, and the drain of the second transistor Ts2 is electrically connected to the drain of the first transistor Ts1. The gate of the third transistor Ts3 is electrically connected to the second clock signal input terminal XCK, the source of the third transistor Ts3 is electrically connected to the stage transfer signal input terminal Nin, and the drain of the third transistor Ts3 is electrically connected to the node D. The gate of the fourth transistor Ts4 is electrically connected to the second clock signal input terminal XCK, the source of the fourth transistor Ts4 is electrically connected to the first low-level signal input terminal VGL1, and the drain of the fourth transistor Ts4 is electrically connected to the node C. The gate of the fifth transistor Ts5 is electrically connected to the node D, the source of the fifth transistor Ts5 is electrically connected to the second clock signal input terminal XCK, and the drain of the fifth transistor Ts5 is electrically connected to the node C. The gate of the sixth transistor Ts6 is electrically connected to the node B, the source of the sixth transistor Ts6 is electrically connected to the first clock signal input terminal CK, and the drain of the sixth transistor Ts6 is electrically connected to the node A. The gate of the seventh transistor Ts7 is electrically connected to the first clock signal input terminal CK, and the source of the seventh transistor Ts7 is electrically connected to the node A. The gate of the eighth transistor Ts8 is electrically connected to the node D, the source of the eighth transistor Ts8 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the eighth transistor Ts8 is electrically connected to the node F (the second control node). The gate of the ninth transistor Ts9 is electrically connected to the node G (the third control node), the source of the ninth transistor Ts9 is electrically connected to the first low-level signal input terminal VGL1, and the drain of the ninth transistor Ts9 is electrically connected to the first-stage transmission signal output terminal Nout1. The gate of the tenth transistor Ts10 is electrically connected to the node F (the second control node), the source of the tenth transistor Ts10 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the tenth transistor Ts10 is electrically connected to the first-stage transmission signal output terminal Nout1. The gate of the eleventh transistor Ts11 is electrically connected to the first low-level signal input terminal VGL1, the source of the eleventh transistor Ts11 is electrically connected to the node C, and the drain of the eleventh transistor Ts11 is electrically connected to the node B. The gate of the twelfth transistor Ts12 is electrically connected to the first low-level signal input terminal VGL1, the source of the twelfth transistor Ts12 is electrically connected to the node D, and the drain of the twelfth transistor Ts12 is electrically connected to the node G (the third control node). The gate of the thirteenth transistor Ts13 is electrically connected to the first control signal input terminal CTRL1, the source of the thirteenth transistor Ts13 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the thirteenth transistor Ts13 is electrically connected to the node D.The gate of the fourteenth transistor Ts14 is electrically connected to the second clock signal input terminal XCK, and the source of the fourteenth transistor Ts14 is electrically connected to the first-stage transmission signal input terminal Nin. The gate of the fifteenth transistor Ts15 is electrically connected to the first low-level signal input terminal VGL1, the source of the fifteenth transistor Ts15 is electrically connected to the drain of the fourteenth transistor Ts14, and the drain of the fifteenth transistor Ts15 is electrically connected to the node E. The gate of the sixteenth transistor Ts16 is electrically connected to the node E, the source of the sixteenth transistor Ts16 is electrically connected to the node E, and the drain of the sixteenth transistor Ts16 is electrically connected to the node G (the third control node). The gate of the seventeenth transistor Ts17 is electrically connected to the second control signal input terminal CTRL2, the source of the seventeenth transistor Ts17 is electrically connected to the drain of the seventh transistor Ts7, and the drain of the seventeenth transistor Ts17 is electrically connected to the node F (the second control node). One plate of the first capacitor C1 is electrically connected to node E, and the other plate of the first capacitor C1 is electrically connected to the drain of the first transistor Ts1. One plate of the second capacitor C2 is electrically connected to node A, and the other plate of the second capacitor C2 is electrically connected to node B. One plate of the third capacitor C3 is electrically connected to node F (the second control node), and the other plate of the third capacitor C3 is electrically connected to the first high-level signal input terminal VGH1.

[0046] The first output circuit 402 further includes a nineteenth transistor Ts19 , a twentieth transistor Ts20 , and a fourth capacitor C4 .

[0047] The gate of the nineteenth transistor Ts19 is electrically connected to the node D, the source of the nineteenth transistor Ts19 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the nineteenth transistor Ts19 is electrically connected to the node H. The gate of the twentieth transistor Ts20 is electrically connected to the node D, the source of the twentieth transistor Ts20 is electrically connected to the first control signal input terminal CTRL1, and the drain of the twentieth transistor Ts20 is electrically connected to the gate of the eighteenth transistor Ts18. One plate of the fourth capacitor C4 is electrically connected to the node H, and the other plate of the fourth capacitor C4 is electrically connected to the first high-level signal input terminal VGH1.

[0048] In this embodiment, the first transistor Ts1 to the twenty-second transistor Ts22 are all P-type thin film transistors.

[0049] In the technical solution provided by the embodiments of the present application, by electrically connecting one plate of the fifth capacitor C5 to node I (the first control node) of the first output circuit 402 and the other plate to the first low-level signal input terminal VGL1 of the first gate driver sub-circuit or the second low-level signal input terminal VGL2 of the second gate driver sub-circuit, rather than to the first high-level signal input terminal VGH1, the coupling effect of the signal transmitted by the first control signal input terminal CTRL1 on the potential of the signal transmitted by the first high-level signal input terminal VGH1 through the fifth capacitor C5 is avoided. Because the first gate driver sub-circuit generates the first scan signal Nscan1 (Nout2) based on the signals transmitted by the first high-level signal input terminal VGH1 and the first low-level signal input terminal VGL1, if the potential of the signal transmitted by the first high-level signal input terminal VGH1 is not affected by the coupling of the fifth capacitor C5, the potential of the first scan signal Nscan1 (Nout2) will also not be affected by the coupling of the fifth capacitor C5.

[0050] like Figure 5 and Figure 7As shown in the layout of the gate driving circuit, the first high-level signal line VGH1 and the second high-level signal line VGH2 of the display panel are located on a first side of the first low-level signal line VGL1 of the first gate driving sub-circuit, and the fifth capacitor C5 is located on a second side of the first low-level signal line VGL1 opposite to the first side. That is, when the other plate of the fifth capacitor C5 is electrically connected to the first low-level signal line VGL1, the first low-level signal line VGL1 is arranged between the entirety of the first high-level signal line VGH1 and the second high-level signal line VGH2 and the fifth capacitor C5, and the second low-level signal line VGL1 is arranged between the first high-level signal line VGH1 and the second high-level signal line VGH2. The signal line VGL2 is arranged on a side of the whole formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 away from the fifth capacitor C5, or, when the other electrode plate of the fifth capacitor C5 is electrically connected to the second low-level signal line VGL2, the second low-level signal line VGL2 is arranged between the whole formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 and the fifth capacitor C5, and the first low-level signal line VGL1 is arranged on a side of the whole formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 away from the fifth capacitor C5. Since one plate of the fifth capacitor C5 is electrically connected to the node I (the first control node) of the first output circuit 402, and the other plate is electrically connected to the first low-level signal input terminal VGL1 of the first gate driver sub-circuit or the second low-level signal input terminal VGL2 of the second gate driver sub-circuit, rather than to the first high-level signal input terminal VGH1, the uneven layout of the first high-level signal line VGH1 and the second high-level signal line VGH2 caused by the fifth capacitor C5 being electrically connected to the first high-level signal input terminal VGH1 and occupying the routing space of the first high-level signal line VGH1 and / or the second high-level signal line VGH2 is avoided. This further avoids the problem of uneven load on the first high-level signal line VGH1 and the second high-level signal line VGH2 caused by the uneven layout.

[0051] The first-stage transmission circuit 401 further includes a sixth capacitor C6 , one plate of the sixth capacitor C6 is electrically connected to the node G (the third control node), and the other plate of the sixth capacitor C6 is electrically connected to the first-stage transmission signal output terminal Nout1 .

[0052] In this embodiment, by providing a sixth capacitor C6 between the node G (the third control node) and the first-stage signal transmission output terminal Nout1, when the signal at the first-stage signal transmission output terminal Nout1 switches from a high potential to a low potential, the sixth capacitor C6 can pull down the potential of the node G (the third control node), and control the twenty-first transistor Ts21 to turn on through the potential of the node G (the third control node), thereby reducing the voltage of the portion of the output first scanning signal Nscan1 (Nout2) that presents a step-shaped waveform, ensuring the stability of the waveform of the first scanning signal outputted by the first scanning signal output terminal Nout2, and improving the circuit stability when the frequency division display function of the display device is turned on.

[0053] Furthermore, by providing a sixth capacitor C6 in the first-stage transfer circuit 401, the pulse width of the scan signal output by each stage of the gate drive circuit can be effectively controlled, thereby avoiding the prior art problem of the first scan signal's pulse width gradually increasing with the number of stages. This technical solution not only ensures that the scan signal output by each stage of the gate drive circuit has a stable pulse width, but also avoids signal interference between adjacent stages caused by an excessively large pulse width of the first scan signal Nscan1 (Nout2), thereby improving the operational reliability of the gate drive circuit and, in turn, the display quality of the display device.

[0054] The display device provided in the embodiments of the present application can be applied to the field of flexible organic light-emitting diode display technology, and is particularly suitable for display panel products with a frequency division display function.

[0055] A first embodiment of a display device provided in the present application includes a display panel, which is an organic light-emitting diode display panel. The display panel includes multiple rows of pixels and a cascaded multi-stage gate driving circuit, wherein the first-stage gate driving circuit includes a first gate driving sub-circuit and a second gate driving sub-circuit. The first gate driving sub-circuit is used to output a first scanning signal Nscan1 (Nout2) to a row of pixels PX, and the second gate driving sub-circuit is used to output a second scanning signal to the same row of pixels PX.

[0056] The first gate driving sub-circuit includes a first-stage transmission circuit 401 and a first output circuit 402 . The first output circuit 402 is configured to output a first scanning signal Nscan1 (Nout2 ) to a row of pixels PX.

[0057] The first output circuit 402 includes an eighteenth transistor Ts18 , a twenty-first transistor Ts21 , a twenty-second transistor Ts22 , and a fifth capacitor C5 .

[0058] The gate of the eighteenth transistor Ts18 is electrically connected to the first control node I, the source of the eighteenth transistor Ts18 is electrically connected to the second control node F of the first-stage transfer circuit 401, and the drain of the eighteenth transistor Ts18 is electrically connected to the node H.

[0059] The gate of the twenty-first transistor Ts21 is electrically connected to the node G (the third control node) of the first-stage transfer circuit, the source of the twenty-first transistor Ts21 is electrically connected to the first low-level signal input terminal VGL1, and the drain of the twenty-first transistor Ts21 is electrically connected to the first scan signal output terminal of the first gate driving sub-circuit.

[0060] The gate of the twenty-second transistor Ts22 is electrically connected to the node H (the drain of the eighteenth transistor Ts18 ), the source of the twenty-second transistor Ts22 is electrically connected to the first high-level signal input terminal VGH1 of the display panel, and the drain of the twenty-second transistor Ts22 is electrically connected to the first scan signal output terminal.

[0061] One plate of the fifth capacitor C5 is electrically connected to the node I (first control node) of the first output circuit 402 , and the other plate of the fifth capacitor C5 is electrically connected to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit.

[0062] In a top view of the gate driving circuit, the first high level signal line VGH1 is located on a first side of the first low level signal line VGL1 , and the fifth capacitor C5 is located on a second side of the first low level signal line VGL1 opposite to the first side.

[0063] In this embodiment, the first low-level signal line VGL1 of the first gate driving sub-circuit is used to transmit the low-level signal VGL1. The gate driving circuit also includes a first high-level signal line VGH1 and a second high-level signal line VGH2. The first high-level signal line VGH1 and the second high-level signal line VGH2 are used to transmit high-level signals. The first high-level signal line VGH1 is electrically connected to the high-level signal input terminal of the odd-numbered gate driving circuit (including the first high-level signal input terminal VGH1 of the first gate driving sub-circuit and the second high-level signal input terminal VGH2 of the second gate driving sub-circuit), and the second high-level signal line VGH2 is electrically connected to the high-level signal input terminal of the even-numbered gate driving circuit (including the first high-level signal input terminal VGH1 of the first gate driving sub-circuit and the second high-level signal input terminal VGH2 of the second gate driving sub-circuit).

[0064] In this embodiment, the first gate driver sub-circuit has a first low-level signal input terminal VGL1 for receiving a first low-level signal VGL1, and a first high-level signal input terminal VGH1 for receiving a first high-level signal VGH1. The voltage value of the first low-level signal VGL1 may be, for example, -5 volts, and the voltage value of the first high-level signal VGH1 may be, for example, 15 volts.

[0065] The first output circuit 402 further includes a nineteenth transistor Ts19 , a twentieth transistor Ts20 , and a fourth capacitor C4 .

[0066] A gate of the nineteenth transistor Ts19 is electrically connected to the node D, a source of the nineteenth transistor Ts19 is electrically connected to the first high-level signal input terminal VGH1 , and a drain of the nineteenth transistor Ts19 is electrically connected to the node H.

[0067] A gate of the twentieth transistor Ts20 is electrically connected to the node D, a source of the twentieth transistor Ts20 is electrically connected to the first control signal input terminal CTRL1 , and a drain of the twentieth transistor Ts20 is electrically connected to the gate of the eighteenth transistor.

[0068] One plate of the fourth capacitor C4 is electrically connected to the node H, and the other plate of the fourth capacitor C4 is electrically connected to the first high-level signal input terminal VGH1 .

[0069] The first-stage transmission circuit 401 is configured to output a stage transmission signal to the first gate driving sub-circuit of the gate driving circuit of another stage.

[0070] The first-stage transfer circuit 401 includes a first transistor Ts1, a second transistor Ts2, a third transistor Ts3, a fourth transistor Ts4, a fifth transistor Ts5, a sixth transistor Ts6, a seventh transistor Ts7, an eighth transistor Ts8, a ninth transistor Ts9, a tenth transistor Ts10, an eleventh transistor Ts11, a twelfth transistor Ts12, a thirteenth transistor Ts13, a fourteenth transistor Ts14, a fifteenth transistor Ts15, a sixteenth transistor Ts16, a seventeenth transistor Ts17, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0071] A gate of the first transistor Ts1 is electrically connected to the node C, and a source of the first transistor Ts1 is electrically connected to the first high-level signal input terminal VGH1 .

[0072] The gate of the second transistor Ts2 is electrically connected to the node E, the source of the second transistor Ts2 is electrically connected to the first clock signal input terminal CK, and the drain of the second transistor Ts2 is electrically connected to the drain of the first transistor Ts1.

[0073] The gate of the third transistor Ts3 is electrically connected to the second clock signal input terminal XCK, the source of the third transistor Ts3 is electrically connected to the first-stage transmission signal input terminal Nin, and the drain of the third transistor Ts3 is electrically connected to the node D.

[0074] The gate of the fourth transistor Ts4 is electrically connected to the second clock signal input terminal XCK, the source of the fourth transistor 4Ts is electrically connected to the first low level signal input terminal VGL1, and the drain of the fourth transistor Ts4 is electrically connected to the node C.

[0075] A gate of the fifth transistor Ts5 is electrically connected to the node D, a source of the fifth transistor Ts5 is electrically connected to the second clock signal input terminal XCK, and a drain of the fifth transistor Ts5 is electrically connected to the node C.

[0076] A gate of the sixth transistor Ts6 is electrically connected to the node B, a source of the sixth transistor Ts6 is electrically connected to the first clock signal input terminal CK, and a drain of the sixth transistor Ts6 is electrically connected to the node A.

[0077] A gate of the seventh transistor Ts7 is electrically connected to the first clock signal input terminal CK, and a source of the seventh transistor Ts7 is electrically connected to the node A.

[0078] A gate of the eighth transistor Ts8 is electrically connected to the node D, a source of the eighth transistor Ts8 is electrically connected to the first high-level signal input terminal VGH1 , and a drain of the eighth transistor Ts8 is electrically connected to the node F (the second control node).

[0079] The gate of the ninth transistor Ts9 is electrically connected to the node G (the third control node), the source of the ninth transistor Ts9 is electrically connected to the first low-level signal input terminal VGL1, and the drain of the ninth transistor Ts9 is electrically connected to the first-stage signal output terminal Nout1.

[0080] The gate of the tenth transistor Ts10 is electrically connected to the node F (the second control node), the source of the tenth transistor Ts10 is electrically connected to the first high-level signal input terminal VGH1 , and the drain of the tenth transistor Ts10 is electrically connected to the first-stage signal output terminal Nout1 .

[0081] A gate of the eleventh transistor Ts11 is electrically connected to the first low-level signal input terminal VGL1 , a source of the eleventh transistor Ts11 is electrically connected to the node C, and a drain of the eleventh transistor Ts11 is electrically connected to the node B.

[0082] A gate of the twelfth transistor Ts12 is electrically connected to the first low-level signal input terminal VGL1 , a source of the twelfth transistor Ts12 is electrically connected to the node D, and a drain of the twelfth transistor Ts12 is electrically connected to the node G (the third control node).

[0083] A gate of the thirteenth transistor Ts13 is electrically connected to the first control signal input terminal CTRL1 , a source of the thirteenth transistor Ts13 is electrically connected to the first high level signal input terminal VGH1 , and a drain of the thirteenth transistor Ts13 is electrically connected to the node D.

[0084] A gate of the fourteenth transistor Ts14 is electrically connected to the second clock signal input terminal XCK, and a source of the fourteenth transistor Ts14 is electrically connected to the first-stage transmission signal input terminal Nin.

[0085] The gate of the fifteenth transistor Ts15 is electrically connected to the first low-level signal input terminal VGL1 , the source of the fifteenth transistor Ts15 is electrically connected to the drain of the fourteenth transistor Ts14 , and the drain of the fifteenth transistor Ts15 is electrically connected to the node E.

[0086] A gate of the sixteenth transistor Ts16 is electrically connected to the node E, a source of the sixteenth transistor Ts16 is electrically connected to the node E, and a drain of the sixteenth transistor Ts16 is electrically connected to the node G (the third control node).

[0087] The gate of the seventeenth transistor Ts17 is electrically connected to the second control signal input terminal CTRL2 , the source of the seventeenth transistor Ts17 is electrically connected to the drain of the seventh transistor Ts7 , and the drain of the seventeenth transistor Ts17 is electrically connected to the node F (the second control node).

[0088] One plate of the first capacitor C1 is electrically connected to the node E, and the other plate of the first capacitor C1 is electrically connected to the drain of the first transistor Ts1.

[0089] One plate of the second capacitor C2 is electrically connected to the node A, and the other plate of the second capacitor C2 is electrically connected to the node B.

[0090] One plate of the third capacitor C3 is electrically connected to the node F (the second control node), and the other plate of the third capacitor C3 is electrically connected to the first high-level signal input terminal VGH1 .

[0091] Furthermore, the channel width of the ninth transistor Ts9 in the first-stage transmission circuit 401 is greater than or equal to 20 micrometers. Preferably, the channel width of the ninth transistor Ts9 is within a range of 30 to 50 micrometers, and more preferably, the channel width of the ninth transistor Ts9 is 40 micrometers. Increasing the channel width of the ninth transistor Ts9 improves the output capability of the ninth transistor Ts9, thereby further improving the waveform stability of the stage transmission signal outputted by the first-stage transmission signal output terminal Nout1 and improving the circuit stability when the frequency division display function of the display device is enabled.

[0092] The first-stage transmission circuit 401 further includes a sixth capacitor C6 , one plate of the sixth capacitor C6 is electrically connected to the node G (the third control node), and the other plate of the sixth capacitor C6 is electrically connected to the first-stage transmission signal output terminal Nout1 .

[0093] By providing a sixth capacitor C6 between node G (the third control node) and the first-stage transmission signal output terminal Nout1, when the signal at the first-stage transmission signal output terminal Nout1 switches from a high potential to a low potential, the sixth capacitor C6 can pull down the potential of node G (the third control node), thereby reducing the voltage of the portion of the output scanning signal that presents a step-shaped waveform, thereby ensuring the stability of the waveform of the stage transmission signal output by the first-stage transmission signal output terminal Nout1.

[0094] The display panel also includes a second high-level signal line VGH2, which is electrically connected to the second gate driving sub-circuit. In the top view of the gate driving circuit, the first high-level signal line VGH1 and the second high-level signal line VGH2 cross the first gate driving sub-circuit and the second gate driving sub-circuit, and the first low-level signal line VGL1 and the second low-level signal line VGL2 cross the first gate driving sub-circuit and the second gate driving sub-circuit.

[0095] In a top view of the gate driving circuit, the second high level signal line VGH2 is located on a first side of the first low level signal line VGL1 of the first gate driving sub-circuit.

[0096] The line width of any point of the first high-level signal line VGH1 is the same as the line width of any point of the second high-level signal line VGH2, the line width of any point of the first low-level signal line VGL1 is the same as the line width of any point of the second low-level signal line VGL2, and the resistivity of the first high-level signal line VGH1 and the second high-level signal line VGH2 is the same, and the resistivity of the first low-level signal line VGL1 and the second low-level signal line VGL2 is the same, so that the load of each signal line can be more uniform, thereby improving the working stability of the gate drive circuit.

[0097] The second embodiment of the display device provided in this application is similar to the first embodiment, except that:

[0098] One plate of the fifth capacitor C5 is electrically connected to the node I (the first control node) of the first output circuit 402 , and the other plate of the fifth capacitor C5 is electrically connected to the second low-level signal input terminal VGL2 of the display panel.

[0099] In the top view of the gate drive circuit, the first high-level signal line VGH1 is located on a first side of the second low-level signal line VGL2, the fifth capacitor C5 is located on a second side of the second low-level signal line VGL2 opposite to the first side, and the first low-level signal line VGL1 is located on a side of the first high-level signal line VGH1 away from the second low-level signal line VGL2.

[0100] By electrically connecting the other electrode plate of the fifth capacitor C5 to the second low-level signal input terminal VGL2 , it is also possible to avoid the fifth capacitor C5 from causing coupling influence on the potential of the signal transmitted by the first high-level signal input terminal VGH1 .

[0101] The display panel further includes a second high-level signal line VGH2. In a top view of the gate driver circuit, the second high-level signal line VGH2 is located between the second low-level signal line VGL2 and the first low-level signal line VGL1. That is, in a top view of the gate driver circuit, the second low-level signal line VGL2 of the second gate driver sub-circuit is disposed between the entirety of the first high-level signal line VGH1 and the second high-level signal line VGH2 and the fifth capacitor C5, and the first low-level signal line VGL1 is disposed on a side of the entirety of the first high-level signal line VGH1 and the second high-level signal line VGH2 that is away from the fifth capacitor C5.

[0102] In the display device provided in the embodiments of the present application, one plate of the fifth capacitor C5 in the first output circuit 402 of the first gate driving sub-circuit in the gate driving circuit is electrically connected to the node I (first control node) of the first output circuit 402, and the other plate is electrically connected to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit or the second low-level signal input terminal VGL2 of the second gate driving sub-circuit, and the first high-level signal input terminal VGH1 is insulated from the fifth capacitor C5. Therefore, when the first control signal input terminal CTRL1 inputs the first control signal to the node I (first control node), the fifth capacitor C5 does not have a coupling effect on the potential of the signal transmitted by the first high-level signal input terminal VGH1, thereby avoiding the problem of fluctuation in the potential of the signal transmitted by the first high-level signal input terminal VGH1 due to the coupling effect between the fifth capacitor C5 and the first high-level signal input terminal VGH1.

[0103] Furthermore, because the potential of the signal transmitted by the first high-level signal input terminal VGH1 is not affected by the coupling effect of the fifth capacitor C5 and thus does not fluctuate, and because the first gate driver sub-circuit generates the first scan signal Nscan1 (Nout2) based on the signals transmitted by the first high-level signal input terminal VGH1 and the first low-level signal input terminal VGL1, the potential of the first scan signal Nscan1 (Nout2) is also not affected by the coupling effect of the fifth capacitor C5 and thus does not fluctuate. Since the potential of the first scan signal Nscan1 (Nout2) does not fluctuate, the turning on or off of the third transistor in the pixel driver circuit of the pixel PX is not affected. The second capacitor electrically connected to the drain of the third transistor does not couple to the gate of the second transistor, which is also electrically connected to the second capacitor, and thus does not affect the turning on or off of the second transistor, thereby avoiding the problem of abnormal data signal writing.

[0104] In addition, since the data signal can be written into the pixel PX normally, when the display device turns on the frequency division display function, there will be no display abnormality at the boundary between different areas due to abnormal data signal writing, thereby improving the display effect of the display device when the frequency division display function is turned on.

[0105] In addition, since one plate of the fifth capacitor C5 is electrically connected to the node I (the first control node) of the first output circuit 402, and the other plate is electrically connected to the first low-level signal input terminal VGL1 of the first gate driver sub-circuit or the second low-level signal input terminal VGL2 of the second gate driver sub-circuit, rather than being electrically connected to the first high-level signal input terminal VGH1, in the layout of the gate driver circuit, the first low-level signal line VGL1 of the first gate driver sub-circuit or the second low-level signal line VGL2 of the second gate driver sub-circuit can be set in the first high-level signal line VGH1 and the second high-level signal line VGH2. and the fifth capacitor C5, thereby making the layout of the first high-level signal line VGH1 and the second high-level signal line VGH2 more uniform, avoiding the uneven layout of the first high-level signal line VGH1 and the second high-level signal line VGH2 caused by the fifth capacitor C5 being electrically connected to the first high-level signal input terminal VGH1 and occupying the routing space of the first high-level signal line VGH1 and / or the second high-level signal line VGH2, thereby avoiding the uneven load problem caused by the uneven layout of the first high-level signal line VGH1 and the second high-level signal line VGH2, and improving the working stability of the gate drive circuit.

[0106] The above is a detailed introduction to the embodiments of the present application. The contents of this specification should not be understood as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: The display panel includes a plurality of rows of pixels and a multi-stage gate driving circuit, wherein the gate driving circuit at one stage includes: The first gate driving sub-circuit includes a first-stage transmission circuit and a first output circuit, and the first output circuit includes: an eighteenth transistor, wherein a gate of the eighteenth transistor is electrically connected to the first control node I, and a source of the eighteenth transistor is electrically connected to the second control node F of the first-stage transfer circuit; a twenty-first transistor, wherein a gate of the twenty-first transistor is electrically connected to the third control node G of the first-stage transfer circuit, a source of the twenty-first transistor is electrically connected to the first low-level signal input terminal of the display panel, and a drain of the twenty-first transistor is electrically connected to the first scan signal output terminal of the first gate driving sub-circuit; a twenty-second transistor, wherein a gate of the twenty-second transistor is electrically connected to the drain of the eighteenth transistor, a source of the twenty-second transistor is electrically connected to the first high-level signal input terminal of the display panel, and a drain of the twenty-second transistor is electrically connected to the first scan signal output terminal; and a fifth capacitor, one plate of the fifth capacitor being electrically connected to the first control node 1, and another plate of the fifth capacitor being electrically connected to the first low-level signal input terminal; In the top view of the gate driving circuit, the first high-level signal line is located on a first side of the first low-level signal line, and the fifth capacitor is located on a second side of the first low-level signal line opposite to the first side.

2. The display device according to claim 1, wherein The first output circuit further includes: a nineteenth transistor, wherein a gate of the nineteenth transistor is electrically connected to the node D, a source of the nineteenth transistor is electrically connected to the first high-level signal input terminal, and a drain of the nineteenth transistor is electrically connected to the node H; a twentieth transistor, wherein a gate of the twentieth transistor is electrically connected to the node D, a source of the twentieth transistor is electrically connected to the first control signal input terminal, and a drain of the twentieth transistor is electrically connected to the gate of the eighteenth transistor; and A fourth capacitor, one plate of the fourth capacitor is electrically connected to the node H, and the other plate of the fourth capacitor is electrically connected to the first high-level signal input terminal.

3. The display device according to claim 1, wherein The first-stage transmission circuit includes: a first transistor, wherein a gate of the first transistor is electrically connected to the node C, and a source of the first transistor is electrically connected to the first high-level signal input terminal; a second transistor, wherein a gate of the second transistor is electrically connected to the node E, a source of the second transistor is electrically connected to the first clock signal input terminal, and a drain of the second transistor is electrically connected to the drain of the first transistor; a third transistor, wherein a gate of the third transistor is electrically connected to the second clock signal input terminal, a source of the third transistor is electrically connected to the first-stage transmission signal input terminal, and a drain of the third transistor is electrically connected to the node D; a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the second clock signal input terminal, a source of the fourth transistor is electrically connected to the first low-level signal input terminal, and a drain of the fourth transistor is electrically connected to the node C; a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the node D, a source of the fifth transistor is electrically connected to the second clock signal input terminal, and a drain of the fifth transistor is electrically connected to the node C; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the node B, a source of the sixth transistor is electrically connected to the first clock signal input terminal, and a drain of the sixth transistor is electrically connected to the node A; a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the first clock signal input terminal, and a source of the seventh transistor is electrically connected to the node A; an eighth transistor, wherein a gate of the eighth transistor is electrically connected to the node D, a source of the eighth transistor is electrically connected to the first high-level signal input terminal, and a drain of the eighth transistor is electrically connected to the second control node F; a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the third control node G, a source of the ninth transistor is electrically connected to the first low-level signal input terminal, and a drain of the ninth transistor is electrically connected to the first-stage transmission signal output terminal; a tenth transistor, wherein a gate of the tenth transistor is electrically connected to the second control node F, a source of the tenth transistor is electrically connected to the first high-level signal input terminal, and a drain of the tenth transistor is electrically connected to the first-stage transmission signal output terminal; an eleventh transistor, wherein a gate of the eleventh transistor is electrically connected to the first low-level signal input terminal, a source of the eleventh transistor is electrically connected to the node C, and a drain of the eleventh transistor is electrically connected to the node B; a twelfth transistor, wherein a gate of the twelfth transistor is electrically connected to the first low-level signal input terminal, a source of the twelfth transistor is electrically connected to the node D, and a drain of the twelfth transistor is electrically connected to the third control node G; a thirteenth transistor, wherein a gate of the thirteenth transistor is electrically connected to the first control signal input terminal, a source of the thirteenth transistor is electrically connected to the first high-level signal input terminal, and a drain of the thirteenth transistor is electrically connected to the node D; a fourteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to the second clock signal input terminal, and a source of the fourteenth transistor is electrically connected to the first-stage transmission signal input terminal; a fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to the first low-level signal input terminal, a source of the fifteenth transistor is electrically connected to the drain of the fourteenth transistor, and a drain of the fifteenth transistor is electrically connected to the node E; a sixteenth transistor, wherein a gate of the sixteenth transistor is electrically connected to the node E, a source of the sixteenth transistor is electrically connected to the node E, and a drain of the sixteenth transistor is electrically connected to the third control node G; a seventeenth transistor, wherein a gate of the seventeenth transistor is electrically connected to the second control signal input terminal, a source of the seventeenth transistor is electrically connected to the drain of the seventh transistor, and a drain of the seventeenth transistor is electrically connected to the second control node F; a first capacitor, wherein one plate of the first capacitor is electrically connected to the node E, and the other plate of the first capacitor is electrically connected to the drain of the first transistor; a second capacitor, one plate of the second capacitor being electrically connected to the node A, and the other plate of the second capacitor being electrically connected to the node B; and A third capacitor, one plate of the third capacitor is electrically connected to the second control node F, and the other plate of the third capacitor is electrically connected to the first high-level signal input terminal.

4. The display device according to claim 3, wherein: The first-stage transmission circuit further includes: A sixth capacitor, one plate of the sixth capacitor is electrically connected to the third control node G, and the other plate of the sixth capacitor is electrically connected to the first-stage signal output terminal.

5. The display device according to claim 1, wherein The display panel also includes a second gate driving subcircuit and a second high-level signal line, the second gate driving subcircuit is electrically connected to the second high-level signal line, and in a top view of the gate driving circuit, the second high-level signal line is located on a first side of the first low-level signal line.

6. A display device, characterized in that: The display panel includes a plurality of rows of pixels and a multi-stage gate driving circuit, wherein the gate driving circuit at one stage includes: The first gate driving sub-circuit includes a first-stage transmission circuit and a first output circuit, and the first output circuit includes: an eighteenth transistor, wherein a gate of the eighteenth transistor is electrically connected to the first control node I, and a source of the eighteenth transistor is electrically connected to the second control node F of the first-stage transfer circuit; a twenty-first transistor, wherein a gate of the twenty-first transistor is electrically connected to the third control node G of the first-stage transfer circuit, a source of the twenty-first transistor is electrically connected to the first low-level signal input terminal of the display panel, and a drain of the twenty-first transistor is electrically connected to the first scan signal output terminal of the first gate driving sub-circuit; a twenty-second transistor, wherein a gate of the twenty-second transistor is electrically connected to the drain of the eighteenth transistor, a source of the twenty-second transistor is electrically connected to the first high-level signal input terminal of the display panel, and a drain of the twenty-second transistor is electrically connected to the first scan signal output terminal; and a fifth capacitor, one plate of the fifth capacitor being electrically connected to the first control node 1, and another plate of the fifth capacitor being electrically connected to the second low-level signal input terminal of the display panel; In which, in the top view of the gate drive circuit, the first high-level signal line is located on a first side of the second low-level signal line, the fifth capacitor is located on a second side of the second low-level signal line opposite to the first side, and the first low-level signal line is located on a side of the first high-level signal line away from the second low-level signal line.

7. The display device according to claim 6, wherein: The first output circuit further includes: a nineteenth transistor, wherein a gate of the nineteenth transistor is electrically connected to the node D, a source of the nineteenth transistor is electrically connected to the first high-level signal input terminal, and a drain of the nineteenth transistor is electrically connected to the node H; a twentieth transistor, wherein a gate of the twentieth transistor is electrically connected to the node D, a source of the twentieth transistor is electrically connected to the first control signal input terminal, and a drain of the twentieth transistor is electrically connected to the gate of the eighteenth transistor; and A fourth capacitor, one plate of the fourth capacitor is electrically connected to the node H, and the other plate of the fourth capacitor is electrically connected to the first high-level signal input terminal.

8. The display device according to claim 6, wherein: The first gate drive sub-circuit further includes a first-stage transmission circuit, and the first-stage transmission circuit includes: a first transistor, wherein a gate of the first transistor is electrically connected to the node C, and a source of the first transistor is electrically connected to the first high-level signal input terminal; a second transistor, wherein a gate of the second transistor is electrically connected to the node E, a source of the second transistor is electrically connected to the first clock signal input terminal, and a drain of the second transistor is electrically connected to the drain of the first transistor; a third transistor, wherein a gate of the third transistor is electrically connected to the second clock signal input terminal, a source of the third transistor is electrically connected to the first-stage transmission signal input terminal, and a drain of the third transistor is electrically connected to the node D; a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the second clock signal input terminal, a source of the fourth transistor is electrically connected to the first low-level signal input terminal, and a drain of the fourth transistor is electrically connected to the node C; a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the node D, a source of the fifth transistor is electrically connected to the second clock signal input terminal, and a drain of the fifth transistor is electrically connected to the node C; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the node B, a source of the sixth transistor is electrically connected to the first clock signal input terminal, and a drain of the sixth transistor is electrically connected to the node A; a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the first clock signal input terminal, and a source of the seventh transistor is electrically connected to the node A; an eighth transistor, wherein a gate of the eighth transistor is electrically connected to the node D, a source of the eighth transistor is electrically connected to the first high-level signal input terminal, and a drain of the eighth transistor is electrically connected to the second control node F; a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the third control node G, a source of the ninth transistor is electrically connected to the first low-level signal input terminal, and a drain of the ninth transistor is electrically connected to the first-stage transmission signal output terminal; a tenth transistor, wherein a gate of the tenth transistor is electrically connected to the second control node F, a source of the tenth transistor is electrically connected to the first high-level signal input terminal, and a drain of the tenth transistor is electrically connected to the first-stage transmission signal output terminal; an eleventh transistor, wherein a gate of the eleventh transistor is electrically connected to the first low-level signal input terminal, a source of the eleventh transistor is electrically connected to the node C, and a drain of the eleventh transistor is electrically connected to the node B; a twelfth transistor, wherein a gate of the twelfth transistor is electrically connected to the first low-level signal input terminal, a source of the twelfth transistor is electrically connected to the node D, and a drain of the twelfth transistor is electrically connected to the third control node G; a thirteenth transistor, wherein a gate of the thirteenth transistor is electrically connected to the first control signal input terminal, a source of the thirteenth transistor is electrically connected to the first high-level signal input terminal, and a drain of the thirteenth transistor is electrically connected to the node D; a fourteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to the second clock signal input terminal, and a source of the fourteenth transistor is electrically connected to the first-stage transmission signal input terminal; a fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to the first low-level signal input terminal, a source of the fifteenth transistor is electrically connected to the drain of the fourteenth transistor, and a drain of the fifteenth transistor is electrically connected to the node E; a sixteenth transistor, wherein a gate of the sixteenth transistor is electrically connected to the node E, a source of the sixteenth transistor is electrically connected to the node E, and a drain of the sixteenth transistor is electrically connected to the third control node G; a seventeenth transistor, wherein a gate of the seventeenth transistor is electrically connected to the second control signal input terminal, a source of the seventeenth transistor is electrically connected to the drain of the seventh transistor, and a drain of the seventeenth transistor is electrically connected to the second control node F; a first capacitor, wherein one plate of the first capacitor is electrically connected to the node E, and the other plate of the first capacitor is electrically connected to the drain of the first transistor; a second capacitor, one plate of the second capacitor being electrically connected to the node A, and the other plate of the second capacitor being electrically connected to the node B; and A third capacitor, one plate of the third capacitor is electrically connected to the second control node F, and the other plate of the third capacitor is electrically connected to the first high-level signal input terminal.

9. The display device according to claim 8, wherein The first-stage transmission circuit further includes: A sixth capacitor, one plate of the sixth capacitor is electrically connected to the third control node G, and the other plate of the sixth capacitor is electrically connected to the first-stage signal output terminal.

10. The display device according to claim 6, wherein The display panel also includes a second gate drive sub-circuit and a second high-level signal line, the second gate drive sub-circuit is electrically connected to the second high-level signal line and the second low-level signal line, and in a top view of the gate drive circuit, the second high-level signal line is located on a first side of the second low-level signal line, and the second high-level signal line is located between the first low-level signal line and the second low-level signal line.

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