Shift register unit and display panel

Abstract

The invention relates to a shifting register unit and a display panel, and the shifting register unit comprises a node control module which is used for receiving a power signal, a clock signal, a first driving signal and a second driving signal, adjusting the potentials of the first control node and the second control node respectively according to the power supply signal, the clock signal, the first driving signal and the second driving signal; the first output control module is connected with the first control node and used for receiving the first driving signal, and the first output control circuit responds to the node voltage of the first control node and outputs the first driving signal; and the second output control module is connected with the second control node, and is used for receiving the power supply signal and the first driving signal, outputting the first driving signal in response to the high-level node voltage of the second control node, and outputting the power supply signal in response to the low-level node voltage of the second control node. The shift register unit can improve the display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register unit and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) is increasingly used in the display field because of its advantages of active luminescence, viewing angle, fast response, wide color gamut and low power consumption.

[0003] In the existing display panel, the scan signal is output by the shift register unit of the gate driving circuit, but the structure of the existing shift register unit needs to be optimized. Summary of the invention

[0004] Based on this, it is necessary to provide a shift register unit and a display panel to address the above technical problems, which can avoid the problem of two falling edges in the shift register unit when outputting a low-level signal in the related art, and is beneficial to improving the display effect of the display panel.

[0005] In a first aspect, the present application provides a shift register unit, comprising:

[0006] a node control module, configured to receive a power signal, a clock signal, a first drive signal, and a second drive signal, and to adjust the potentials of the first control node and the second control node respectively according to the power signal, the clock signal, the first drive signal, and the second drive signal;

[0007] A first output control module, connected to the first control node, and configured to receive the first drive signal, wherein the first output control circuit outputs the first drive signal in response to a node voltage of the first control node;

[0008] A second output control module is connected to the second control node, and is used to receive the power supply signal and the first drive signal, and is used to respond to the high-level node voltage of the second control node to output the first drive signal, and respond to the low-level node voltage of the second control node to output the power supply signal.

[0009] In one embodiment, the second output control module includes:

[0010] a first output control unit, wherein a first end of the first output control unit is used to receive a first power signal, a second end of the first output control unit is used as an output end of the shift register unit, a control end of the first output control unit is connected to the second control node, the first output control unit is turned on in response to a low-level signal, and transmits the first power signal to the second end of the first output control unit, wherein the first power signal is a high-level signal;

[0011] A second output control unit, wherein the first end of the second output control unit is used to receive the first drive signal, the second end of the second output control unit serves as the output end of the shift register unit, the control end of the second output control unit is connected to the second control node, and the second output control unit is turned on in response to a high-level signal to transmit the first drive signal to the second end of the second output control unit.

[0012] In one embodiment, the first output control unit includes a first transistor, a first electrode of the first transistor is used to receive the first power supply signal, a second electrode of the first transistor serves as an output end of the shift register unit, a gate of the first transistor is connected to the second control node, and the first transistor is turned on in response to a low-level signal to transmit the first power supply signal to the second electrode of the first transistor.

[0013] In one embodiment, the second output control unit includes a second transistor, a first electrode of the second transistor is used to receive the first drive signal, a second electrode of the second transistor serves as the output end of the shift register unit, one of the top gate and the lower gate of the second transistor is connected to the second control node, and the other is used to receive a third power supply signal, the second transistor is used to be turned on when the node voltage of the second control node is at a high level, and transmit the first drive signal to the second electrode of the second transistor, wherein the potential of the third power supply signal is less than the potential of the second power supply signal, and the second power supply signal is a low level signal.

[0014] In one embodiment, the second output control unit includes a second transistor, a first electrode of the second transistor is used to receive the first drive signal, a second electrode of the second transistor serves as the output end of the shift register unit, a gate of the second transistor is connected to the second control node, and the second transistor is used to be turned on when the node voltage of the second control node is at a high level, so as to transmit the first drive signal to the second electrode of the second transistor.

[0015] In one embodiment, the first output control module includes:

[0016] A third output control unit, wherein the first end of the third output control unit is used to receive the first drive signal, the second end of the third output control unit is used as the output end of the shift register unit, the control end of the third output control unit is connected to the first control node, and the third output control unit is turned on in response to a low-level signal to transmit the first drive signal to the second end of the third output control unit.

[0017] In one embodiment, the third output control unit includes:

[0018] A third transistor, wherein a first electrode of the third transistor is used to receive a first driving signal, a second electrode of the third transistor is used as an output end of the shift register unit, a gate of the third transistor is connected to the first control node, and the third transistor is turned on in response to a low level signal.

[0019] In one embodiment, the driving cycle of the shift register unit includes multiple time stages in sequence, wherein the target time stage of the multiple time stages of the first driving signal is high level, and the remaining time stages are low level, so that the shift register unit outputs a high level signal in the target time stage.

[0020] In one embodiment, the node control module includes:

[0021] a front-stage node control circuit, the front-stage node control circuit being used to receive a first power supply signal, a target signal, a first clock signal, a second clock signal and the second drive signal, and to adjust the potentials of a third control node and a fourth control node according to the target signal, the first power supply signal, the first clock signal, the second clock signal and the second drive signal, wherein the target signal is one of the second power supply signal and the first drive signal;

[0022] The post-stage node control circuit is respectively connected to the third control node and the fourth control node, and is used to receive the power supply signal, the second clock signal, the first drive signal and the target signal, and adjust the potential of the first control node and the second control node accordingly according to the power supply signal, the second clock signal, the first drive signal, the target signal and the node voltages of the third control node and the fourth control node.

[0023] In one embodiment, the preceding node control circuit includes:

[0024] a first input unit, the first input unit being used to receive the second drive signal and the first clock signal, and being used to respond to the first clock signal and adjust a node voltage of the third control node according to the second drive signal;

[0025] A second input unit, the second input unit is used to receive the target signal and the first clock signal, and is used to respond to the first clock signal and adjust the node voltage of the fourth control node according to the target signal.

[0026] In one embodiment, the first input unit comprises:

[0027] A fourth transistor, wherein a first electrode of the fourth transistor is used to receive a second driving signal, a second electrode of the fourth transistor is connected to the third control node, and a gate of the fourth transistor is used to receive a first clock signal.

[0028] In one embodiment, the second input unit comprises:

[0029] A fifth transistor, wherein a first electrode of the fifth transistor is used to receive a target signal, a second electrode of the fifth transistor is connected to the fourth control node, and a gate of the fifth transistor is used to receive a first clock signal.

[0030] In one embodiment, the preceding node control circuit further includes:

[0031] A node control unit, wherein the node control unit is connected to the third control node and the fourth control node respectively, and the node control unit is used to respond to the node voltage of the third control node, adjust the node voltage of the fourth control node according to the first clock signal, and is also used to respond to the node voltage of the fourth control node and the second clock signal, and adjust the node voltage of the third control node according to the first power supply signal.

[0032] In one embodiment, the node control unit includes:

[0033] a sixth transistor, wherein a first electrode of the sixth transistor is used to receive a first clock signal, a second electrode of the sixth transistor is connected to the fourth control node, and a gate of the sixth transistor is connected to the third control node;

[0034] a seventh transistor, wherein a first electrode of the seventh transistor is used to receive a first power supply signal, and a gate of the seventh transistor is connected to the fourth control node;

[0035] An eighth transistor, wherein a first electrode of the eighth transistor is connected to a second electrode of the seventh transistor, a gate of the eighth transistor is used to receive a second clock signal, and a second electrode of the eighth transistor is connected to the third control node.

[0036] In one embodiment, the preceding node control circuit further includes:

[0037] a node control unit, the node control unit being connected to the third control node and the fourth control node respectively, the node control unit being configured to respond to a node voltage of the third control node and adjust a node voltage of the fourth control node according to the first clock signal;

[0038] In one embodiment, the node control unit includes:

[0039] a sixth transistor, wherein a first electrode of the sixth transistor is used to receive a first clock signal, a second electrode of the sixth transistor is connected to the fourth control node, and a gate of the sixth transistor is connected to the third control node;

[0040] a seventh transistor, wherein a first electrode of the seventh transistor is used to receive a first power supply signal, and a gate of the seventh transistor is connected to the fourth control node;

[0041] an eighth transistor, wherein a first electrode of the eighth transistor is connected to a second electrode of the seventh transistor, the second electrode of the eighth transistor is used to receive a second clock signal, and a gate of the eighth transistor is connected to the first control node;

[0042] In one embodiment, the shift register unit further includes:

[0043] A first energy storage module, wherein a first end of the first energy storage module is connected to the second electrode of the seventh transistor, and a second end of the first energy storage module is connected to the first control node.

[0044] In one embodiment, the first energy storage module comprises:

[0045] A first energy storage capacitor, wherein a first end of the first energy storage capacitor is connected to the second electrode of the seventh transistor, and a second end of the energy storage capacitor is connected to the first control node.

[0046] In one embodiment, the shift register unit further includes:

[0047] A first energy storage module, wherein a first end of the first energy storage module is used to receive a second clock signal, and a second end of the first energy storage module is connected to the first control node.

[0048] In one embodiment, the first energy storage module comprises:

[0049] A first energy storage capacitor, wherein a first end of the first energy storage capacitor is used to receive a second clock signal, and a second end of the first energy storage capacitor is connected to the first control node.

[0050] In one embodiment, the subsequent node control circuit includes:

[0051] a first control unit, the first control unit being configured to receive a first power supply signal and a first drive signal, the first control unit being configured to adjust the potential of the first control node according to the voltage of the third control node and the first drive signal, and further configured to adjust the potential of the second control node according to the voltage of the third control node and the first power supply signal;

[0052] A second control unit, the second control unit is used to receive a target signal and a second clock signal, and the second control unit is used to adjust the potential of the second control node according to the voltage of the fourth control node, the target signal and the second clock signal.

[0053] In one embodiment, the first control unit comprises:

[0054] a ninth transistor, wherein a first electrode of the ninth transistor is connected to the third control node, a gate of the ninth transistor is used to receive a first driving signal, and a second electrode of the ninth transistor is connected to the first control node;

[0055] A tenth transistor, wherein a first electrode of the tenth transistor is used to receive the first power supply signal, a second electrode of the tenth transistor is connected to the second control node, and a gate of the tenth transistor is connected to the third control node.

[0056] In one embodiment, the second control unit comprises:

[0057] an eleventh transistor, a first electrode of the eleventh transistor being connected to the fourth control node, and a gate of the eleventh transistor being used for receiving the target signal;

[0058] a twelfth transistor, wherein a first electrode of the twelfth transistor is used to receive a second clock signal, a second electrode of the twelfth transistor is connected to the second control node, and a gate of the twelfth transistor is connected to the second electrode of the eleventh transistor;

[0059] A second energy storage capacitor, wherein a first end of the second energy storage capacitor is connected to the gate of the twelfth transistor, and a second end of the second energy storage capacitor is connected to the second control node.

[0060] In one embodiment, the shift register unit further includes:

[0061] a switch module, the switch module being configured to conduct the second control unit and the second control node according to the second control signal;

[0062] A second energy storage module, wherein a first end of the second energy storage module is used to receive the first power supply signal, and a second end of the second energy storage module is connected to the second control node.

[0063] In one embodiment, the switch module comprises:

[0064] A thirteenth transistor, a first electrode of the thirteenth transistor is connected to the output end of the second control unit, a second electrode of the thirteenth transistor is connected to the second control node, and a gate of the thirteenth transistor is used to receive a second clock signal.

[0065] In one embodiment, the second energy storage module comprises:

[0066] A third energy storage capacitor, wherein a first end of the third energy storage capacitor is connected to the first power signal, and a second end of the third energy storage capacitor is connected to the second control node.

[0067] In a second aspect, the present application further provides a display panel, comprising the shift register unit as described in the first aspect.

[0068] The above-mentioned shift register unit includes a node control module, a first output control module and a second output control module; the node control module adjusts the potential of the first control node and the second control node according to the power signal, the clock signal, the first drive signal and the second drive signal respectively, and the first output control module responds to the node voltage of the first control node and outputs the first drive signal; the second output control module responds to the high-level node voltage of the second control node and outputs the first drive signal, and responds to the low-level node voltage of the second control node and outputs the power signal. The node control module adjusts the potential of the first control node and the second control node, and sets a suitable first drive signal, so that the second output control module can respond to the high-level node voltage of the second control node to output a low-level signal. Compared with the shift register unit in the prior art, which uses a P-type transistor to control the output of the low-level signal, the influence of the threshold voltage of the P-type transistor can be avoided in the process of outputting the low-level signal, thereby avoiding the problem of two falling edges when the shift register unit in the related art outputs the low-level signal, which is beneficial to improving the display effect of the display panel. In addition, the first output control module and the second output control module can both output the first drive signal, and the level state of the first drive signal can be made the same as the level state of the power supply signal output by the second output control module during the corresponding time period, so that all row shift register units can simultaneously output the scanning signal of the same level during this stage, so that the shift register unit of the present application can be applied to specific scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0070] Figure 1 A structural block diagram of a shift register unit provided in an embodiment of the present application;

[0071] Figure 2 It is a structural schematic diagram of a shift register unit in the related art;

[0072] Figure 3 A schematic diagram of the structure of a shift register unit provided in an embodiment of the present application;

[0073] Figure 4 A schematic diagram of the structure of another shift register unit provided in an embodiment of the present application;

[0074] Figure 5 A schematic diagram of the structure of another shift register unit provided in an embodiment of the present application;

[0075] Figure 6 A schematic diagram of the structure of another shift register unit provided in an embodiment of the present application;

[0076] Figure 7 for Figure 3 Schematic diagram of the timing of each signal in;

[0077] Figure 8 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0078] Description of reference numerals:

[0079] 10-shift register unit, 11-first output control module, 111-third output control unit, 12-second output control module, 121-first output control unit, 122-second output control unit, 13-node control module, 131-previous node control circuit, 1311-first input unit, 1312-second input unit, 1313-node control unit, 132-next node control circuit, 1321-first control unit, 1322-second control unit, 14-first energy storage module, 15-switch module, 16-second energy storage module. DETAILED DESCRIPTION

[0080] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0082] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0083] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be intervening layers. In addition, it is also understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers. In addition, the same reference numerals always represent the same elements.

[0084] In the following embodiments, when a layer, region, or element is "connected", it can be interpreted that the layer, region, or element is not only directly connected but also connected through other constituent elements placed therebetween. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. can be connected or electrically connected not only directly or directly, but also through another layer, region, element, etc. placed therebetween.

[0085] Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another. It will also be understood that expressions used in the singular include plural expressions unless the expression in the singular has an obviously different meaning in the context.

[0086] When a statement such as "at least one (of)..." is located after a list of elements, it modifies the entire list of elements rather than the individual elements in the list. The term "and / or" as used herein includes any and all combinations of one or more related listed items. As used in the application documents, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0087] Electronic or electrical devices and / or any other related devices or components according to the embodiments of the concepts of the present application described herein (for example, a display device including a display panel and a display panel driver, wherein the display panel driver also includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver, and an emission driver) can be implemented using any appropriate hardware, firmware (such as a dedicated integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices may be processes or threads that run on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using standard storage devices (e.g., such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., such as CD-ROMs, flash drives, etc.). Moreover, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed on one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the concepts of the present application.

[0088] Although exemplary embodiments of display modules and display devices including display modules have been specifically described herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that display modules and display devices including display modules constructed according to the principles of the present application may be implemented in addition to those specifically described herein. The present application is also defined in the claims and their equivalents.

[0089] As described in the background art, in the prior art OLED display panel, the structure of the shift register unit needs to be optimized. The inventors have found that the reason for this problem is that the shift register unit in the related art has two falling edges when outputting a low-level signal.

[0090] Based on the above reasons, Figure 1 As shown, the present application provides a shift register unit 10 , comprising: a node control module 13 , a first output control module 11 and a second output control module 12 .

[0091] The node control module 13 is used to receive the power signal VG, the clock signal ECK, the first drive signal RST and the second drive signal EIN, and adjust the potential of the first control node N1 and the second control node N2 according to the power signal VG, the clock signal ECK, the first drive signal RST and the second drive signal EIN.

[0092] The driving cycle of the shift register unit 10 may include multiple time stages, and at different time stages, the first control node N1 and the second control node N2 are adjusted by the node control module 13. The node control module 13 may include multiple signal transmission paths, and the on and off of the corresponding signal transmission paths are controlled by at least part of the power signal VG, the clock signal ECK, the first drive signal RST, and the second drive signal EIN, so as to transmit the specific signal to the first control node N1 and the second control node N2, and adjust the potential of the first control node N1 and the second control node N2.

[0093] Exemplarily, the node control module 13 may include at least a first signal transmission path and a second signal transmission path. The on-off of the first signal transmission path is controlled by the clock signal ECK and the first drive signal RST. When the first signal transmission path is turned on, the second drive signal EIN is transmitted to the first control node N1 to adjust the potential of the first control node N1. The on-off of the second signal transmission path is controlled by the power supply signal VG and the clock signal ECK. When the second signal transmission path is turned on, the clock signal ECK is transmitted to the second control node N2 to adjust the potential of the second control node N2.

[0094] The first output control module 11 is connected to the first control node N1, and is used to receive the first drive signal RST. The first output control circuit responds to the node voltage of the first control node N1 and outputs the first drive signal RST. When the first output control module 11 is turned on in response to the node voltage of the first control node N1, the level state of the scan signal G-OUT output by the shift register unit 10 corresponds to the level state of the first drive signal RST. Exemplarily, the first output control module 11 can be turned on in response to the low-level node voltage of the first control node N1.

[0095] The second output control module 12 is connected to the second control node N2, and is configured to receive a power signal VG and a first driving signal RST. It is configured to output the first driving signal RST in response to the high-level node voltage of the second control node N2, and output the power signal VG in response to the low-level node voltage of the second control node N2. It can be understood that when the node voltage of the second control node N2 is in the high-level state, the second output control module 12 outputs the first driving signal RST, and when the node voltage of the second control node N2 is in the low-level state, the second output control module 12 outputs the power signal VG.

[0096] Figure 2 It is a schematic structural diagram of a shift register unit 10 in the related art. For example, as Figure 2 shown, the shift register unit in the related art adopts a 12T3C circuit. The 12T3C circuit controls the output of high and low levels through two P-type transistors (M9 and M10). Among them, since the first pole of the P-type transistor M10 receives the low-level power signal VGVGL, and the second pole of M10 is used as the output terminal of the GOA unit, the P-type transistor conducts in response to the low-level signal. Therefore, when the shift register unit 10 outputs a low level VGL, it is restricted. When M10 is turned on to output the VGL voltage, when the potential VGout at the output position of the shift register unit 10 minus the potential VN1 at point N1 is equal to |Vth|, the M10 transistor will turn off, resulting in the output being first VGL + |Vth|. Subsequently, due to the bootstrap effect of the parasitic capacitance of M10, the potential of node N1 will be further pulled down, ensuring that the output reaches VGL. In summary, the 12T3C circuit in the related art will introduce the influence of the threshold voltage of the P-type transistor (conducting in response to the low-potential level signal) during the output process, resulting in a step in the output of the shift register unit 10, affecting the display effect of the display panel.

[0097] In this embodiment, the node control module 13 adjusts the potential of the first control node N1 and the second control node N2, and sets a suitable first drive signal RST, so that the second output control module 12 can respond to the high-level node voltage of the second control node N2 to output a low-level signal. Compared with the prior art shift register unit 10 using a P-type transistor to control the output of a low-level signal, the influence of the threshold voltage of the P-type transistor can be avoided in the process of outputting a low-level signal, thereby avoiding the problem of the shift register unit 10 having two falling edges when outputting a low-level signal in the related art, which is beneficial to improving the display effect of the display panel. In addition, by setting a suitable first drive signal RST, in at least one time stage of the shift register unit 10, the level state of the first drive signal RST can be the same as the level state of the power supply signal VG output by the second output control module 12, then in this time stage, the scan output by the shift register unit 10 will only have one level state, so that the level state of the shift register units 10 of each row in this time stage can be the same, so that the scan signal G-OUT can be applied to a specific scene.

[0098] The shift register unit 10 comprises a node control module 13, a first output control module 11 and a second output control module 12; the node control module 13 adjusts the potentials of the first control node N1 and the second control node N2 respectively according to the power signal VG, the clock signal ECK, the first drive signal RST and the second drive signal EIN; the first output control module 11 responds to the node voltage of the first control node N1 and outputs the first drive signal RST; the second output control module 12 responds to the high-level node voltage of the second control node N2 and outputs the first drive signal RST, and responds to the low-level node voltage of the second control node N2 and outputs the power signal VG. Signal VG, the potential of the first control node N1 and the second control node N2 is adjusted by the node control module 13, and a suitable first drive signal RST is set, so that the second output control module 12 can respond to the high-level node voltage of the second control node N2 to output a low-level signal. Compared with the prior art shift register unit 10 using a P-type transistor to control the output of a low-level signal, the influence of the threshold voltage of the P-type transistor can be avoided in the process of outputting a low-level signal, thereby avoiding the problem of the shift register unit 10 in the related art having two falling edges when outputting a low-level signal, which is beneficial to improving the display effect of the display panel. In addition, the first output control module 11 and the second output control module 12 can both output the first drive signal RST, so that the level state of the first drive signal RST can be made the same as the level state of the power supply signal VG output by the second output control module 12 at the corresponding time stage, so that all row shift register units 10 can simultaneously output the scanning signal G-OUT of the same level at this stage, so that the shift register unit 10 of the present application can be applied to specific scenarios.

[0099] In one embodiment, Figures 3 to 6 As shown, the second output control module 12 includes: a first output control unit 121 and a second output control unit 122 .

[0100] The first end of the first output control unit 121 is used to receive the first power signal VGH, and the second end of the first output control unit 121 serves as the output end of the shift register unit 10. The control end of the first output control unit 121 is connected to the second control node N2. The first output control unit 121 is turned on in response to a low-level signal, and transmits the first power signal VGH to the second end of the first output control unit 121, wherein the first power signal VGH is a high-level signal.

[0101] The first end of the second output control unit 122 is used to receive the first drive signal RST, and the second end of the second output control unit 122 serves as the output end of the shift register unit 10. The control end of the second output control unit 122 is connected to the second control node N2. The second output control unit 122 is turned on in response to a high-level signal and transmits the first drive signal RST to the second end of the second output control unit 122.

[0102] It can be understood that when the voltage of the second control node N2 is at a low level, the first output control unit 121 is turned on in response to the low level signal, and the first power signal VGH is transmitted to the second end of the first output control unit 121. At this stage, the level state corresponding to the scan signal G-OUT is the level state of the first power signal VGH, that is, the high level state. When the voltage of the second control node N2 is at a high level, the second output control unit 122 is turned on in response to the high level signal, and the first drive signal RST is transmitted to the second end of the first output control unit 121. At this stage, the level state corresponding to the scan signal G-OUT is the level state of the first drive signal RST. When the first drive signal RST is in a low level state, the first output control unit 121 is disconnected and the second output control unit 122 is turned on. Therefore, the output signal conflict between the first output control unit 121 and the second output control unit 122 can be avoided, so that the second output control module 12 can output a low level signal. At the same time, the second output control unit 122 is turned on in response to a high level signal and outputs a low level signal. The scanning signal G-OUT output by the shift register unit 10 can achieve a direct jump from a high level to a low level, avoiding the problem of two falling edges in the high and low level jump of the scanning signal G-OUT in the related art.

[0103] In one embodiment, Figures 3 to 6As shown, the first output control unit 121 includes a first transistor T1, the first electrode of the first transistor T1 is used to receive the first power supply signal VGH, the second electrode of the first transistor T1 serves as the output end of the shift register unit 10, the gate of the first transistor T1 is connected to the second control node N2, and the first transistor T1 is turned on in response to a low-level signal to transmit the first power supply signal VGH to the second electrode of the first transistor T1.

[0104] Among them, the first transistor T1 is a P-type transistor, and the P-type transistor has the advantages of high mobility and stable characteristics. Therefore, the first transistor T1 responds to the low-level signal and turns on quickly, and can quickly transmit the first power supply signal VGH to the second electrode of the first transistor T1, thereby realizing the high-level output of the shift register unit 10.

[0105] In one embodiment, Figures 3 to 6 As shown, the second output control unit 122 includes a second transistor T2, a first electrode of the second transistor T2 is used to receive the first drive signal RST, a second electrode of the second transistor T2 serves as the output end of the shift register unit 10, a gate of the second transistor T2 is connected to the second control node N2, and the second transistor T2 is used to be turned on when the node voltage of the second control node N2 is at a high level, and transmit the first drive signal RST to the second electrode of the second transistor T2.

[0106] The second transistor T2 is an N-type transistor.

[0107] It can be understood that the first electrode of the second transistor T2 receives the first drive signal RST, the second electrode of the second transistor T2 serves as the output end of the shift register unit 10, the first electrode of the first transistor T1 receives the first power supply signal VGH, and the second electrode of the first transistor T1 serves as the output end of the shift register unit 10. Then, when the node voltage of the second control node N2 is a low-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the first power supply signal VGH is transmitted to the output end of the shift register unit 10. When the node voltage of the second control node N2 is a high-level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the first drive signal RST is transmitted to the output end of the shift register unit 10. In this stage, when the level state of the first drive signal RST is a low-level state, the signal output by the shift register unit 10 is directly a low-level signal, thereby avoiding the influence of the threshold voltage of the P-type transistor in the process of outputting the low-level signal, thereby avoiding the output of the shift register unit 10 from having steps, thereby improving the display effect of the display panel.

[0108] In another embodiment, the second output control unit 122 includes a second transistor T2, a first electrode of the second transistor T2 is used to receive the first drive signal RST, a second electrode of the second transistor T2 is used as the output end of the shift register unit 10, one of the top gate and the bottom gate of the second transistor T2 is connected to the second control node N2, and the other is used to receive the third power signal VGLL, and the second transistor T2 is used to be turned on when the node voltage of the second control node N2 is at a high level, and transmit the first drive signal RST to the second electrode of the second transistor T2, wherein the potential of the third power signal VGLL is less than the potential of the second power signal VGL, and the second power signal VGL is a low level signal. For ease of description, this embodiment is described by taking the top gate of the second transistor T2 connected to the second control node N2 and the bottom gate of the second transistor T2 used to receive the third power signal VGLL as an example.

[0109] Compared with the above-mentioned embodiment, the second transistor T2 of this embodiment is a top-bottom dual-gate N-type transistor. Similarly, when the node voltage is a high-level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the first drive signal RST is transmitted to the output end of the shift register unit 10. In this stage, when the level state of the first drive signal RST is a low-level state, the signal output by the shift register unit 10 is directly a low-level signal, thereby avoiding the influence of the threshold voltage of the P-type transistor in the process of outputting the low-level signal, thereby avoiding the output of the shift register unit 10 from having steps, and improving the display effect of the display panel. In addition, the bottom gate of the second transistor T2 receives the third power supply signal VGLL, and the potential of the third power supply signal VGLL is less than the potential of the second power supply signal VGL. Therefore, the stability of the second transistor T2 can be improved, and the abnormal opening of the second transistor T2 can be avoided, thereby ensuring the stability of the scanning signal G-OUT output by the shift register.

[0110] In one embodiment, Figures 3 to 6 As shown, the first output control module 11 includes: a third output control unit 111 .

[0111] The first end of the third output control unit 111 is used to receive the first drive signal RST, the second end of the third output control unit 111 is used as the output end of the shift register unit 10, the control end of the third output control unit 111 is connected to the first control node N1, and the third output control unit 111 is turned on in response to a low-level signal, and the first drive signal RST is transmitted to the second end of the third output control unit 111.

[0112] It can be understood that when the node voltage of the first control node N1 is at a low level, the third output control unit 111 is turned on in response to the low level signal, and the first drive signal RST is transmitted to the second end of the third output control unit 111. In this case, the level state of the scan signal G-OUT output by the shift register unit 10 is the level state of the first drive signal RST. In the corresponding time stage, the level state of the first drive signal RST can be made the same as the level state of the power supply signal VG output by the second output control module 12, and in this stage, all row shift register units 10 simultaneously output the scan signal G-OUT of the same level.

[0113] In one embodiment, Figures 3 to 6 As shown, the third output control unit 111 includes: a third transistor T3.

[0114] The first electrode of the third transistor T3 is used to receive the first driving signal RST, the second electrode of the third transistor T3 is used as the output end of the shift register unit 10, the gate of the third transistor T3 is connected to the first control node N1, and the third transistor T3 is turned on in response to a low level signal.

[0115] Wherein, the third transistor T3 is a P-type transistor. When the node voltage of the first control node N1 is at a low level, the third transistor T3 is turned on in response to the low-level signal, the first drive signal RST is transmitted to the second electrode of the third transistor T3, and the level state of the scanning signal G-OUT output by the shift register unit 10 is the level state of the first drive signal RST. Then, in the corresponding time stage, the level state of the first drive signal RST can be made the same as the level state of the power supply signal VG output by the second output control module 12, and in this stage, all row shift register units 10 simultaneously output the scanning signal G-OUT of the same level.

[0116] In one embodiment, the driving cycle of the shift register unit 10 includes multiple time stages in sequence, wherein the target time stage among the multiple time stages of the first driving signal RST is a high level, and the remaining time stages are low levels, so that the shift register unit 10 outputs a high level signal in the target time stage.

[0117] It can be understood that the target time stage among the multiple time stages of the first driving signal RST is high level, and the other time stages are low level, so that the shift register unit 10 of each row can output a high level signal in the target time stage. In other stages, the first driving signal RST can be used as a low level power supply signal VG, so that the shift register unit 10 can output a low level signal.

[0118] Exemplarily, the driving cycle of the shift register unit 10 can include six time stages in sequence, the second time stage of the driving cycle can be the target time stage, and the first driving signal RST is at a low level in the remaining time stages, so that the shift register units 10 of each row output a high level signal in the second time stage of the driving cycle.

[0119] In one embodiment, Figures 3 to 6 As shown, the node control module 13 includes: a front-stage node control circuit 131 and a rear-stage node control circuit 132 .

[0120] The previous node control circuit 131 is used to receive a first power supply signal VGH, a target signal, a first clock signal ECK1, a second clock signal ECK2 and a second drive signal EIN, and adjust the potentials of the third control node N3 and the fourth control node N4 according to the target signal, the first power supply signal VGH, the first clock signal ECK1, the second clock signal ECK2 and the second drive signal EIN, wherein the target signal is one of the second power supply signal VGL and the first drive signal RST.

[0121] It should be noted that, when the target signal is the first drive signal RST, the signal received by the shift register unit 10 does not include the second power signal VGL, and the first drive signal RST is used instead of the second power signal VGL, thereby reducing the number of signals.

[0122] The post-stage node control circuit 132 is respectively connected to the third control node N3 and the fourth control node N4, and is used to receive the power signal VG, the second clock signal ECK2, the first drive signal RST and the target signal, and adjust the potential of the first control node N1 and the second control node N2 accordingly according to the power signal VG, the second clock signal ECK2, the first drive signal RST, the target signal and the node voltages of the third control node N3 and the fourth control node N4.

[0123] It can be understood that the potentials of the third control node N3 and the fourth control node N4 are adjusted according to the target signal, the first power supply signal VGH, the first clock signal ECK1, the second clock signal ECK2 and the second drive signal EIN, so that the potentials of the third control node N3 and the fourth control node N4 are in a predetermined level state during the corresponding time period, so that during the corresponding time period, the post-stage node control circuit 132 can adjust the potentials of the first control node N1 and the second control node N2 according to the node voltage of the third control node N3 and the node voltage of the fourth control node N4, and the potentials of the first control node N1 and the second control node N2 control the level signal output by the shift register, and respectively control the level signal output by the shift register at different time stages, so that the shift register can output the required scanning signal G-OUT.

[0124] In one embodiment, Figures 3 to 6 As shown, the previous node control circuit 131 includes: a first input unit 1311 and a second input unit 1312 .

[0125] The first input unit 1311 is used for receiving the second driving signal EIN and the first clock signal ECK1, and for responding to the first clock signal ECK1 to adjust the node voltage of the third control node N3 according to the second driving signal EIN.

[0126] It can be understood that the first clock signal ECK1 is a signal whose high electrical level state changes regularly. Then, the first clock signal ECK1 is used as the control signal of the first input unit 1311, and the second drive signal EIN can be controlled to be input at an appropriate time stage, and the node voltage of the third control node N3 can be adjusted according to the second drive signal EIN. Exemplarily, in the case where the node voltage of the third control node N3 affects the node potentials of the first control node N1 and the second control node N2, the potentials of the first control node N1 and the second control node N2 can be adjusted according to the node voltage of the third control node N3.

[0127] The second input unit 1312 is used for receiving the target signal and the first clock signal ECK1, and for responding to the first clock signal ECK1 to adjust the node voltage of the fourth control node N4 according to the target signal.

[0128] Similarly, by using the first clock signal ECK1 as the control signal of the second input unit 1312, the target signal input can be controlled at an appropriate time stage, and the node voltage of the fourth control node N4 can be adjusted according to the second drive signal EIN. Exemplarily, in the case where the node voltage of the fourth control node N4 affects the node potential of the second control node N2, the potential of the second control node N2 can be adjusted according to the node voltage of the fourth control node N4.

[0129] In one embodiment, the first input unit 1311 includes: a fourth transistor T4. A first electrode of the fourth transistor T4 is used to receive the second driving signal EIN, a second electrode of the fourth transistor T4 is connected to the third control node N3, and a gate of the fourth transistor T4 is used to receive the first clock signal ECK1.

[0130] The fourth transistor T4 may be a P-type transistor.

[0131] It can be understood that when the gate of the fourth transistor T4 is turned on in response to the first clock signal ECK1, the second drive signal EIN is input to the second drive signal EIN to adjust the node voltage of the third control node N3.

[0132] In one embodiment, the second input unit 1312 includes a fifth transistor T5. A first electrode of the fifth transistor T5 is used to receive the target signal, a second electrode of the fifth transistor T5 is connected to the fourth control node N4, and a gate of the fifth transistor T5 is used to receive the first clock signal ECK1.

[0133] It can be understood that when the gate of the fifth transistor T5 is turned on in response to the first clock signal ECK1, the target signal is input to the second driving signal EIN to adjust the node voltage of the fourth control node N4.

[0134] In one embodiment, Figures 3 to 5 As shown, the front-stage node control circuit 131 further includes: a node control unit 1313 .

[0135] The node control unit 1313 is connected to the third control node N3 and the fourth control node N4, respectively. The node control unit 1313 is used to respond to the node voltage of the third control node N3, and adjust the node voltage of the fourth control node N4 according to the first clock signal ECK1. It is also used to respond to the node voltage of the fourth control node N4 and the second clock signal ECK2, and adjust the node voltage of the third control node N3 according to the first power supply signal VGH.

[0136] It can be understood that the node control unit 1313 responds to the node voltage of the third control node N3, adjusts the node voltage of the fourth control node N4 according to the first clock signal ECK1, and responds to the node voltage of the fourth control node N4 and the second clock signal ECK2, and adjusts the node voltage of the third control node N3 according to the first power signal VGH. Thus, the third control node N3 and the fourth control node N4 can affect each other, and the node voltages of the third control node N3 and the fourth control node N4 can be adjusted through one input signal.

[0137] In one embodiment, Figures 3 to 5 As shown, the node control unit 1313 includes: a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0138] A first electrode of the sixth transistor T6 is used to receive the first clock signal ECK1 , a second electrode of the sixth transistor T6 is connected to the fourth control node N4 , and a gate of the sixth transistor T6 is connected to the third control node N3 .

[0139] The first electrode of the seventh transistor T7 is used to receive the first power signal VGH, and the gate of the seventh transistor T7 is connected to the fourth control node N4. The first electrode of the eighth transistor T8 is connected to the second electrode of the seventh transistor T7, the gate of the eighth transistor T8 is used to receive the second clock signal ECK2, and the second electrode of the eighth transistor T8 is connected to the third control node N3.

[0140] It can be understood that, when the sixth transistor T6 is turned on in response to the node voltage of the third control node N3, the first clock signal ECK1 is input to the fourth control node N4 through the sixth transistor T6, and the node voltage of the fourth control node N4 is adjusted, thereby adjusting the node voltage of the fourth control node N4 based on the node voltage of the third control node N3. When the seventh transistor T7 is turned on in response to the node voltage of the third control node N3, the first power signal VGH is input to the first electrode of the eighth transistor T8, and when the eighth transistor T8 is turned on in response to the second clock signal ECK2, the first power signal VGH is output to the third control node N3, and the node voltage of the third control node N3 is adjusted, thereby adjusting the node voltage of the third control node N3 based on the node voltage of the fourth control node N4.

[0141] In another embodiment, Figure 6 As shown, the front-stage node control circuit 131 further includes: a node control unit 1313 .

[0142] The node control unit 1313 is connected to the third control node N3 and the fourth control node N4 respectively. The node control unit 1313 is used to respond to the node voltage of the third control node N3 and adjust the node voltage of the fourth control node N4 according to the first clock signal ECK1.

[0143] It can be understood that the node control unit 1313 responds to the node voltage of the third control node N3 and adjusts the node voltage of the fourth control node N4 according to the first clock signal ECK1, and can adjust the node voltage of the fourth control node N4 based on the node voltage of the third control node N3.

[0144] In one embodiment, if Figure 6 As shown, the node control unit 1313 includes: a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0145] A first electrode of the sixth transistor T6 is used to receive the first clock signal ECK1 , a second electrode of the sixth transistor T6 is connected to the fourth control node N4 , and a gate of the sixth transistor T6 is connected to the third control node N3 .

[0146] The first electrode of the seventh transistor T7 is used to receive the first power supply signal VGH, and the gate of the seventh transistor T7 is connected to the fourth control node N4; the first electrode of the eighth transistor T8 is connected to the second electrode of the seventh transistor T7, the second electrode of the eighth transistor T8 is used to receive the second clock signal ECK2, and the gate of the eighth transistor T8 is connected to the first control node N1.

[0147] It can be understood that, when the sixth transistor T6 is turned on in response to the node voltage of the third control node N3, the first clock signal ECK1 is input to the fourth control node N4 via the sixth transistor T6, and the node voltage of the fourth control node N4 is adjusted, thereby adjusting the node voltage of the fourth control node N4 based on the node voltage of the third control node N3. When the seventh transistor T7 is turned on in response to the node voltage of the fourth control node N4, the first power signal VGH is input to the second electrode of the seventh transistor T7. When the gate of the eighth transistor T8 is turned on in response to the node voltage of the first control node N1, the second clock signal ECK2 is input to the second electrode of the seventh transistor T7.

[0148] Based on the previous embodiment, in one embodiment, if Figure 6 As shown, the shift register unit 10 further includes: a first energy storage module 14. A first end of the first energy storage module 14 is connected to the second electrode of the seventh transistor T7, and a second end of the first energy storage module 14 is connected to the first control node N1.

[0149] It can be understood that since the first power signal VGH or the second clock signal ECK2 is input to the second electrode of the seventh transistor T7, and the first end of the first energy storage module 14 is connected to the second electrode of the seventh transistor T7, and the second end of the first energy storage module 14 is connected to the first control node N1, by making the first control node N1 at a low level, the second electrode of the seventh transistor T7 is at a high level, so that the first energy storage module 14 has a potential difference. When the first power signal VGH or the second clock signal ECK2 is input to the second electrode of the seventh transistor T7, the voltage of the first control node N1 can be made low or lower than the low level, so as to control the first output control module 11 to output the first drive signal RST at the corresponding stage.

[0150] The first energy storage module 14 includes: a first energy storage capacitor C1 , a first end of the first energy storage capacitor C1 is connected to the second electrode of the fourth transistor T4 , and a second end of the energy storage capacitor is connected to the first control node N1 .

[0151] It can also be understood that the first end of the first energy storage module 14 is connected to the second electrode of the seventh transistor T7, and the second end of the first energy storage module 14 is connected to the first control node N1. When the first control node N1 is at a low level, the second electrode of the seventh transistor T7 is at a high level, so that the first energy storage capacitor C1 has a potential difference. When the first power supply signal VGH or the second clock signal ECK2 is input to the second electrode of the seventh transistor T7, the voltage of the first control node N1 can be made to be a low level or a voltage lower than the low level, so as to control the first output control module 11 to output the first drive signal RST at the corresponding stage.

[0152] In another embodiment, Figures 3 to 5 As shown, the first end of the first energy storage module 14 is used to receive the second clock signal ECK2, and the second end of the first energy storage module 14 is connected to the first control node N1.

[0153] Among them, when the first control node N1 is at a low level, the second end of the first energy storage module 14 is at a high level, so that the first energy storage capacitor C1 has a potential difference, and when the second clock signal ECK2 changes to a low level state, the voltage of the first control node N1 can be changed to a voltage lower than the low level, so that the voltage of the first control node N1 is a low level or a voltage lower than the low level, so as to control the first output control module 11 to output the first drive signal RST in the corresponding stage.

[0154] The first energy storage module 14 includes: a first energy storage capacitor C1 , a first end of the first energy storage capacitor C1 is used to receive the second clock signal ECK2 , and a second end of the first energy storage capacitor C1 is connected to the first control node N1 .

[0155] In one embodiment, Figures 3 to 6 As shown, the subsequent node control circuit 132 includes: a first control unit 1321 and a second control unit 1322 .

[0156] The first control unit 1321 is used to receive the first power signal VGH and the first drive signal RST. The first control unit 1321 is used to adjust the potential of the first control node N1 according to the voltage of the third control node N3 and the first drive signal RST, and is also used to adjust the potential of the second control node N2 according to the voltage of the third control node N3 and the first power signal VGH.

[0157] The second control unit 1322 is used for receiving the target signal and the second clock signal ECK2, and the second control unit 1322 is used for adjusting the potential of the second control node N2 according to the voltage of the fourth control node N4, the target signal and the second clock signal ECK2.

[0158] It can be understood that the first control unit 1321 adjusts the potential of the first control node N1 according to the voltage of the third control node N3 and the first drive signal RST, and adjusts the potential of the second control node N2 according to the voltage of the third control node N3 and the first power signal VGH, so that the potential of the first control node N1 and / or the second control node N2 can be controlled by controlling the voltage of the third control node N3 at the corresponding time stage. Similarly, the second control unit 1322 adjusts the potential of the second control node N2 according to the voltage of the fourth control node N4, the target signal and the second clock signal ECK2, and the potential of the second control node N2 can be controlled by controlling the voltage of the fourth control node N4 at the corresponding time stage.

[0159] In one embodiment, if Figures 3 to 6 As shown, the first control unit 1321 includes: a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 and the tenth transistor T10 may be P-type transistors.

[0160] The first electrode of the ninth transistor T9 is connected to the third control node N3, the gate of the ninth transistor T9 is used to receive the first drive signal RST, and the second electrode of the ninth transistor T9 is connected to the first control node N1. The ninth transistor T9 is used to respond to the first drive signal RST and turn on, and adjust the voltage of the first control node N1 according to the voltage of the third control node N3.

[0161] The first electrode of the tenth transistor T10 is used to receive the first power signal VGH, the second electrode of the tenth transistor T10 is connected to the second control node N2, and the gate of the tenth transistor T10 is connected to the third control node N3. The tenth transistor T10 is used to respond to the voltage of the third control node N3, so that the first power signal VGH is input to the second control node N2, and the potential of the second control node N2 is adjusted.

[0162] In one embodiment, if Figures 3 to 6 As shown, the second control unit 1322 includes: an eleventh transistor T11, a twelfth transistor T12 and a second energy storage capacitor C2.

[0163] The first electrode of the eleventh transistor T11 is connected to the fourth control node N4, and the gate of the eleventh transistor T11 is used to receive the target signal. The first electrode of the twelfth transistor T12 is used to receive the second clock signal ECK2, the second electrode of the twelfth transistor T12 is connected to the second control node N2, and the gate of the twelfth transistor T12 is connected to the second electrode of the eleventh transistor T11. The first end of the second energy storage capacitor C2 is connected to the gate of the twelfth transistor T12, and the second end of the second energy storage capacitor C2 is connected to the second control node N2.

[0164] It can be understood that the eleventh transistor T11 is used to respond to the target signal and turn on, so that the node voltage of the fourth control node N4 is input to the gate of the twelfth transistor T12, thereby controlling the on and off of the twelfth transistor T12. When the twelfth transistor T12 is turned on in response to the node voltage of the fourth control node N4, the second clock signal ECK2 is input to the second control node N2 to adjust the potential of the second control node N2. The first end of the second energy storage capacitor C2 is connected to the gate of the twelfth transistor T12, and the second end of the second energy storage capacitor C2 is connected to the second control node N2. Therefore, based on the characteristics of the second energy storage capacitor C2, the gate potential of the twelfth transistor T12 can be kept stable in the corresponding time stage, thereby ensuring the stable conduction of the twelfth transistor T12.

[0165] In one embodiment, Figure 5 As shown, the shift register unit 10 further includes: a switch module 15 and a second energy storage module 16 .

[0166] The switch module 15 is used to connect the second control unit 1322 and the second control node N2 according to the second clock signal ECK2. The first end of the second energy storage module 16 is used to receive the first power signal VGH, and the second end of the second energy storage module 16 is connected to the second control node N2.

[0167] It can be understood that the switch module 15 conducts the second control unit 1322 and the second control node N2 in response to the second clock signal ECK2, so that the signal output by the second control unit 1322 can adjust the potential of the second control node N2. On this basis, since the first end of the second energy storage module 16 receives the first power signal VGH, the second end of the second energy storage module 16 is connected to the second control node N2, the node voltage of the second control node N2 can be maintained by the second energy storage module 16, so that the line-by-line output signal can be greater than or equal to 1 line time, and the pulse width of the scanning signal G-OUT is increased.

[0168] In one embodiment, if Figure 5 As shown, the switch module 15 includes: a thirteenth transistor. The first electrode of the thirteenth transistor is connected to the output end of the second control unit 1322, the second electrode of the thirteenth transistor is connected to the second control node N2, and the gate of the thirteenth transistor is used to receive the second clock signal ECK2. The thirteenth transistor can be a P-type transistor. The thirteenth transistor conducts the second control unit 1322 and the second control node N2 in response to the second clock signal ECK2, thereby controlling whether the signal output by the second control unit 1322 can be written into the second control node N2, and adjusting the voltage of the second control node N2.

[0169] The second energy storage module 16 includes: a third energy storage capacitor C3. The first end of the third energy storage capacitor C3 is connected to the first power signal VGH, and the second end of the third energy storage capacitor C3 is connected to the second control node N2. Based on the characteristics of the capacitor, the third energy storage capacitor C3 can maintain the node potential of the second control node N2 when there is no external signal input at its second end, so that the line-by-line output signal can be greater than or equal to 1 line time, and the pulse width of the scanning signal G-OUT is increased.

[0170] Based on the above embodiments, Figure 3 and Figure 7As shown, in one example, the present application provides a scanning circuit, including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a first energy storage capacitor C1 and a second energy storage capacitor C2.

[0171] The first electrode of the first transistor T1 is used to receive the first power signal VGH, the second electrode of the first transistor T1 serves as the output end of the shift register unit 10, and the gate of the first transistor T1 is connected to the second control node N2.

[0172] The first electrode of the second transistor T2 is used to receive the first driving signal RST, the second electrode of the second transistor T2 serves as the output end of the shift register unit 10, the top gate of the second transistor T2 is connected to the second control node N2, and the bottom gate of the second transistor T2 is used to receive the third power signal VGLL.

[0173] A first electrode of the third transistor T3 is used to receive the first driving signal RST, a second electrode of the third transistor T3 is used as an output end of the shift register unit 10, and a gate of the third transistor T3 is connected to the first control node N1.

[0174] A first electrode of the fourth transistor T4 is used to receive the second driving signal EIN, a second electrode of the fourth transistor T4 is connected to the third control node N3, and a gate of the fourth transistor T4 is used to receive the first clock signal ECK1.

[0175] A first electrode of the fifth transistor T5 is used to receive the target signal, a second electrode of the fifth transistor T5 is connected to the fourth control node N4, and a gate of the fifth transistor T5 is used to receive the first clock signal ECK1.

[0176] A first electrode of the sixth transistor T6 is used to receive the first clock signal ECK1 , a second electrode of the sixth transistor T6 is connected to the fourth control node N4 , and a gate of the sixth transistor T6 is connected to the third control node N3 .

[0177] A first electrode of the seventh transistor T7 is used to receive the first power signal VGH, and a gate of the seventh transistor T7 is connected to the fourth control node N4.

[0178] A first electrode of the eighth transistor T8 is connected to the second electrode of the seventh transistor T7 , a gate of the eighth transistor T8 is used to receive the second clock signal ECK2 , and a second electrode of the eighth transistor T8 is connected to the third control node N3 .

[0179] A first electrode of the ninth transistor T9 is connected to the third control node N3, a gate of the ninth transistor T9 is used to receive the first drive signal RST, and a second electrode of the ninth transistor T9 is connected to the first control node N1;

[0180] A first electrode of the tenth transistor T10 is used to receive the first power signal VGH, a second electrode of the tenth transistor T10 is connected to the second control node N2, and a gate of the tenth transistor T10 is connected to the third control node N3.

[0181] The eleventh transistor T11, a first electrode of the eleventh transistor T11 is connected to the fourth control node N4, and a gate of the eleventh transistor T11 is used for receiving a target signal.

[0182] The twelfth transistor T12 has a first electrode for receiving the second clock signal ECK2, a second electrode of the twelfth transistor T12 is connected to the second control node N2, and a gate of the twelfth transistor T12 is connected to the second electrode of the eleventh transistor T11.

[0183] A first end of the first energy storage capacitor C1 is used to receive the second clock signal ECK2 , and a second end of the first energy storage capacitor C1 is connected to the first control node N1 .

[0184] A first end of the second energy storage capacitor C2 is connected to the gate of the twelfth transistor T12 , and a second end of the second energy storage capacitor C2 is connected to the second control node N2 .

[0185] The second transistor T2 may be an N-type transistor, and the other transistors may be P-type transistors.

[0186] Exemplarily, as shown in the figure, the driving cycle of the shift register unit 10 includes six time stages t1 to t6 in sequence. In the T2 stage, the first driving signal RST is at a high level, and the first driving signal RST is at a low level in the remaining stages. In the T4 stage, the second driving signal EIN is at a high level, and the second driving signal EIN is at a low level in the remaining stages.

[0187] In the t1 phase, the first drive signal RST is at a low level, the second drive signal EIN is at a low level, the fourth transistor T4 is turned on when the first clock signal ECK1 is at a low level, the ninth transistor T9 is turned on in response to the first drive signal RST, the first energy storage capacitor C1 maintains the node voltage of the first control node N1 at a low level (corresponding to the second clock signal ECK2 being at a high level) or a lower voltage (corresponding to the second clock signal ECK2 being at a low level), the tenth transistor T10 is turned on in response to the node voltage of the first control node N1, the first power signal VGH is input to the second control node N2, the node voltage of the second control node N2 is at a high level, then the third transistor T3 and the second transistor T2 are turned on, the first transistor T1 is turned off, the shift register outputs the first drive signal RST, and the scanning signal G-OUT (corresponding to Figure 7 GOUT1 in the figure is at a low level during the t1 phase.

[0188] In the t2 stage, the first drive signal RST is at a high level, the second drive signal EIN is at a low level, and the ninth transistor T9 is disconnected in response to the first drive signal RST. Due to the action of the first energy storage capacitor C1, the node voltage of the first control node N1 is a low voltage, and no matter what state the node voltage of the second control node N2 is in, the shift register outputs a high level signal, and the scanning signal G-OUT is at a high level in the t2 stage.

[0189] In the stage t3, the first drive signal RST is at a low level, the second drive signal EIN is at a low level, the fourth transistor T4 is turned on when the first clock signal ECK1 is at a low level, the ninth transistor T9 is turned on in response to the first drive signal RST, the first energy storage capacitor C1 maintains the node voltage of the first control node N1 at a low level (corresponding to the second clock signal ECK2 being at a high level) or a lower voltage (corresponding to the second clock signal ECK2 being at a low level), the tenth transistor T10 is turned on in response to the node voltage of the first control node N1, the first power signal VGH is input to the second control node N2, the node voltage of the second control node N2 is at a high level, then the third transistor T3 and the second transistor T2 are turned on, the first transistor T1 is turned off, the shift register outputs the first drive signal RST, and the scanning signal G-OUT is at a low level in the stage t3.

[0190] In the t4 stage, the first drive signal RST is at a low level, the second drive signal EIN is at a high voltage, the first clock signal ECK1 is at a low level, and the second clock signal ECK2 is at a high level, then the first control node N1 is at a high level, the second control node N2 remains at a high level, the second transistor T2 is turned on, the shift register outputs the first drive signal RST, and the scan signal G-OUT is at a low level in the t4 stage.

[0191] In the t5 stage, the first drive signal RST is at a low level, the second drive signal EIN is at a low level, the first clock signal ECK1 is at a high level, and the second clock signal ECK2 is at a low level. Under the action of the first energy storage capacitor C1, the first control node N1 is maintained at a high voltage, and the second control node N2 is coupled to a low voltage by the second clock signal ECK2. The first transistor T1 is turned on, and the shift register outputs the first power supply signal VGH. The scan signal G-OUT is at a high level in the t5 stage.

[0192] In the t6 stage, the first clock signal ECK1 is at a low level and the second clock signal ECK2 is at a high level. In this case, the fourth transistor T4 is turned on, the ninth transistor T9 is turned on in response to the first drive signal RST, the first energy storage capacitor C1 maintains the node voltage of the first control node N1 at a low level, the tenth transistor T10 is turned on in response to the node voltage of the first control node N1, the second control node N2 is at a high level, the shift register outputs the first drive signal RST, and the scan signal G-OUT is at a low level; and when the first clock signal ECK1 is at a high level and the second clock signal ECK2 is at a low level, the node voltage of the first control node N1 is coupled to a level lower than the electrical level by the first energy storage capacitor C1, the ninth transistor T9 and the tenth transistor T10 are both turned on, the first power supply signal VGH is output to the second control node N2, the second control node N2 is still at a high level, the shift register outputs the first drive signal RST, and the scan signal G-OUT is at a low level. Regardless of the level states of the first clock signal ECK1 and the second clock signal ECK2, at stage t6, the shift register outputs the first drive signal RST, and the scanning signal G-OUT is at a low level.

[0193] Based on the same inventive concept, the embodiment of the present application further provides a gate drive circuit (not shown), which includes a plurality of shift register units in the above embodiments. The beneficial effects of the gate drive circuit relative to the related art are the same as the beneficial effects of the shift register units in the above embodiments relative to the related art, and will not be repeated here.

[0194] like Figure 8 As shown, the embodiment of the present application further provides a display panel 100, which includes the shift register unit 10 in the above embodiment. The beneficial effects of the display panel 100 relative to the related art are the same as the beneficial effects of the shift register unit 10 in the above embodiment relative to the related art, which will not be repeated here.

[0195] The embodiment of the present application further provides a display device (not shown), which includes the display panel 100 in the above embodiment.

[0196] It can be understood that the display device in the embodiments of the present application can be an OLED display device, a QLED display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a wearable device, an Internet of Things device, or any other product or component with a display function, and the embodiments disclosed in the present application are not limited to this.

[0197] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0198] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0199] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A shift register unit, characterized in that: include: a node control module, configured to receive a power signal, a clock signal, a first drive signal, and a second drive signal, and to adjust the potentials of the first control node and the second control node respectively according to the power signal, the clock signal, the first drive signal, and the second drive signal; A first output control module, connected to the first control node, and configured to receive the first drive signal, wherein the first output control circuit outputs the first drive signal in response to a node voltage of the first control node; A second output control module is connected to the second control node, and is used to receive the power supply signal and the first drive signal, and is used to respond to the high-level node voltage of the second control node to output the first drive signal, and respond to the low-level node voltage of the second control node to output the power supply signal.

2. The shift register unit according to claim 1, characterized in that: The second output control module comprises: a first output control unit, wherein a first end of the first output control unit is used to receive a first power signal, a second end of the first output control unit is used as an output end of the shift register unit, a control end of the first output control unit is connected to the second control node, the first output control unit is turned on in response to a low-level signal, and transmits the first power signal to the second end of the first output control unit, wherein the first power signal is a high-level signal; a second output control unit, wherein a first end of the second output control unit is used to receive the first drive signal, a second end of the second output control unit serves as an output end of the shift register unit, a control end of the second output control unit is connected to the second control node, and the second output control unit is turned on in response to a high-level signal to transmit the first drive signal to the second end of the second output control unit; Optionally, the first output control unit includes a first transistor, a first electrode of the first transistor is used to receive the first power supply signal, a second electrode of the first transistor serves as an output end of the shift register unit, a gate of the first transistor is connected to the second control node, and the first transistor is turned on in response to a low-level signal to transmit the first power supply signal to the second electrode of the first transistor; Optionally, the second output control unit includes a second transistor, a first electrode of the second transistor is used to receive the first drive signal, a second electrode of the second transistor serves as an output end of the shift register unit, one of a top gate and a lower gate of the second transistor is connected to the second control node, and the other is used to receive a third power supply signal, the second transistor is used to be turned on when the node voltage of the second control node is at a high level, and transmit the first drive signal to the second electrode of the second transistor, wherein the potential of the third power supply signal is less than the potential of the second power supply signal, and the second power supply signal is a low level signal; Optionally, the second output control unit includes a second transistor, a first electrode of the second transistor is used to receive the first drive signal, a second electrode of the second transistor serves as an output end of the shift register unit, a gate of the second transistor is connected to the second control node, and the second transistor is used to be turned on when the node voltage of the second control node is at a high level, so as to transmit the first drive signal to the second electrode of the second transistor; Optionally, the first output control module includes: a third output control unit, wherein a first end of the third output control unit is used to receive the first drive signal, a second end of the third output control unit is used as an output end of the shift register unit, a control end of the third output control unit is connected to the first control node, and the third output control unit is turned on in response to a low-level signal to transmit the first drive signal to the second end of the third output control unit; Optionally, the third output control unit includes: A third transistor, wherein a first electrode of the third transistor is used to receive a first driving signal, a second electrode of the third transistor is used as an output end of the shift register unit, a gate of the third transistor is connected to the first control node, and the third transistor is turned on in response to a low level signal.

3. The shift register unit according to claim 1, characterized in that: The driving cycle of the shift register unit includes multiple time stages in sequence, wherein the target time stage of the first driving signal among the multiple time stages is high level, and the remaining time stages are low level, so that the shift register unit outputs a high level signal in the target time stage.

4. The shift register unit according to claim 1, characterized in that: The node control module includes: a front-stage node control circuit, the front-stage node control circuit being used to receive a first power supply signal, a target signal, a first clock signal, a second clock signal and the second drive signal, and to adjust the potentials of a third control node and a fourth control node according to the target signal, the first power supply signal, the first clock signal, the second clock signal and the second drive signal, wherein the target signal is one of the second power supply signal and the first drive signal; a post-stage node control circuit, connected to the third control node and the fourth control node respectively, configured to receive the power signal, the second clock signal, the first drive signal and the target signal, and correspondingly adjust the potentials of the first control node and the second control node according to the power signal, the second clock signal, the first drive signal, the target signal and the node voltages of the third control node and the fourth control node; Optionally, the preceding node control circuit includes: a first input unit, the first input unit being used to receive the second drive signal and the first clock signal, and being used to respond to the first clock signal and adjust a node voltage of the third control node according to the second drive signal; a second input unit, the second input unit being used to receive the target signal and the first clock signal, and being used to respond to the first clock signal and adjust a node voltage of the fourth control node according to the target signal; Optionally, the first input unit includes: a fourth transistor, wherein a first electrode of the fourth transistor is used to receive a second driving signal, a second electrode of the fourth transistor is connected to the third control node, and a gate of the fourth transistor is used to receive a first clock signal; Optionally, the second input unit includes: A fifth transistor, wherein a first electrode of the fifth transistor is used to receive a target signal, a second electrode of the fifth transistor is connected to the fourth control node, and a gate of the fifth transistor is used to receive a first clock signal.

5. The shift register unit according to claim 4, characterized in that: The front-stage node control circuit also includes: a node control unit, the node control unit being connected to the third control node and the fourth control node respectively, the node control unit being configured to respond to a node voltage of the third control node and adjust a node voltage of the fourth control node according to the first clock signal; Optionally, the node control unit includes: a sixth transistor, wherein a first electrode of the sixth transistor is used to receive a first clock signal, a second electrode of the sixth transistor is connected to the fourth control node, and a gate of the sixth transistor is connected to the third control node; a seventh transistor, wherein a first electrode of the seventh transistor is used to receive a first power supply signal, and a gate of the seventh transistor is connected to the fourth control node; An eighth transistor, wherein a first electrode of the eighth transistor is connected to a second electrode of the seventh transistor, a gate of the eighth transistor is used to receive a second clock signal, and a second electrode of the eighth transistor is connected to the third control node.

6. The shift register unit according to claim 4, characterized in that: The front-stage node control circuit also includes: a node control unit, the node control unit being connected to the third control node and the fourth control node respectively, the node control unit being configured to respond to a node voltage of the third control node and adjust a node voltage of the fourth control node according to the first clock signal; Optionally, the node control unit includes: a sixth transistor, wherein a first electrode of the sixth transistor is used to receive a first clock signal, a second electrode of the sixth transistor is connected to the fourth control node, and a gate of the sixth transistor is connected to the third control node; a seventh transistor, wherein a first electrode of the seventh transistor is used to receive a first power supply signal, and a gate of the seventh transistor is connected to the fourth control node; an eighth transistor, wherein a first electrode of the eighth transistor is connected to a second electrode of the seventh transistor, the second electrode of the eighth transistor is used to receive a second clock signal, and a gate of the eighth transistor is connected to the first control node; Optionally, the shift register unit further includes: a first energy storage module, wherein a first end of the first energy storage module is connected to the second electrode of the seventh transistor, and a second end of the first energy storage module is connected to the first control node; Optionally, the first energy storage module includes: A first energy storage capacitor, wherein a first end of the first energy storage capacitor is connected to the second electrode of the seventh transistor, and a second end of the energy storage capacitor is connected to the first control node.

7. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: A first energy storage module, wherein a first end of the first energy storage module is used to receive a second clock signal, and a second end of the first energy storage module is connected to the first control node; Optionally, the first energy storage module includes: A first energy storage capacitor, wherein a first end of the first energy storage capacitor is used to receive a second clock signal, and a second end of the first energy storage capacitor is connected to the first control node.

8. The shift register unit according to claim 4, characterized in that: The latter node control circuit comprises: a first control unit, the first control unit being configured to receive the first power signal and the first drive signal, the first control unit being configured to adjust the potential of the first control node according to the voltage of the third control node and the first drive signal, and further configured to adjust the potential of the second control node according to the voltage of the third control node and the first power signal; a second control unit, the second control unit being configured to receive the target signal and the second clock signal, and the second control unit being configured to adjust the potential of the second control node according to the voltage of the fourth control node, the target signal and the second clock signal; Optionally, the first control unit includes: a ninth transistor, wherein a first electrode of the ninth transistor is connected to the third control node, a gate of the ninth transistor is used to receive a first driving signal, and a second electrode of the ninth transistor is connected to the first control node; a tenth transistor, wherein a first electrode of the tenth transistor is used to receive the first power signal, a second electrode of the tenth transistor is connected to the second control node, and a gate of the tenth transistor is connected to the third control node; Optionally, the second control unit includes: an eleventh transistor, a first electrode of the eleventh transistor being connected to the fourth control node, and a gate of the eleventh transistor being used for receiving the target signal; a twelfth transistor, wherein a first electrode of the twelfth transistor is used to receive a second clock signal, a second electrode of the twelfth transistor is connected to the second control node, and a gate of the twelfth transistor is connected to the second electrode of the eleventh transistor; A second energy storage capacitor, wherein a first end of the second energy storage capacitor is connected to the gate of the twelfth transistor, and a second end of the second energy storage capacitor is connected to the second control node.

9. The shift register unit according to claim 5, characterized in that: The shift register unit also includes: a switch module, the switch module being configured to conduct the second control unit and the second control node according to the second control signal; a second energy storage module, wherein a first end of the second energy storage module is used to receive the first power signal, and a second end of the second energy storage module is connected to the second control node; Optionally, the switch module includes: a thirteenth transistor, wherein a first electrode of the thirteenth transistor is connected to the output end of the second control unit, a second electrode of the thirteenth transistor is connected to the second control node, and a gate of the thirteenth transistor is used to receive a second clock signal; Optionally, the second energy storage module includes: A third energy storage capacitor, wherein a first end of the third energy storage capacitor is connected to the first power signal, and a second end of the third energy storage capacitor is connected to the second control node.

10. A display panel, characterized in that: The invention comprises a shift register unit as claimed in any one of claims 1 to 9.

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