Encoder, encoding method and chip

Abstract

The invention discloses an encoder, an encoding method and a chip, relates to the technical field of encoding, and aims to overcome the technical defect that a feedback loop in the encoder cannot converge in time sequence under the scene of large-bandwidth and high-parallelism input. The encoder comprises a feed-forward module which is used for receiving data to be encoded at the parallelism degree of n symbols per beat, and calculating a single-beat polynomial corresponding to the current beat in a finite field according to the symbols in the data to be encoded received by the current beat. The feedback module is used for receiving the single-beat polynomial which is output by the feed-forward module and corresponds to the current beat, and performing calculation in a finite field according to the single-beat polynomial which corresponds to the current beat and a first polynomial which represents symbols received by historical beats to obtain a second polynomial, and the second polynomial is used for determining a target polynomial which represents data to be coded; the target polynomial is used for generating a check sequence of the to-be-coded data, so that code words obtained after the to-be-coded data is coded in a forward error correction coding mode are obtained.

Description

Technical Field

[0001] The present application relates to the field of coding technology, and in particular to an encoder, a coding method and a chip. Background Art

[0002] In the scenario of data communication based on Ethernet, in order to ensure the reliability of data transmission, the data sender can use forward error correction (FEC) technology to encode the data to be transmitted. Among them, FEC is an error control technology that can self-correct and recover data when errors occur during data transmission.

[0003] With the development of information technologies such as cloud computing, big data, artificial intelligence, and the Internet of Things, the scale of global data is exploding. In order to improve the transmission efficiency of data, when performing FEC encoding on the data to be transmitted, the encoder receives the symbols of the data to be encoded in parallel to implement FEC encoding on the data to be encoded.

[0004] However, when the degree of parallelism of symbols in the data to be encoded is large when input to the encoder, there is a technical risk that the feedback loop in the current encoder may not be able to converge in timing. Summary of the invention

[0005] The present application provides an encoder, an encoding method and a chip. In the scenario of large bandwidth and high parallel input, the feedback circuit in the encoder will not produce the technical defect of being unable to converge in timing.

[0006] To achieve the above objectives, this application provides the following technical solutions:

[0007] In the first aspect, the present application provides an encoder, including: a feedforward module, which is used to receive data to be encoded with a parallelism of n (n is a positive integer) symbols per beat, and, according to the symbols in the data to be encoded received by the current beat, a single-beat polynomial corresponding to the current beat is calculated in a finite field. Here, the single-beat polynomial represents the symbol received by the feedforward module through one beat. A feedback module is used to receive the single-beat polynomial corresponding to the current beat output by the feedforward module, and calculate a second polynomial in a finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbol received by the historical beat. The second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine the target polynomial representing the data to be encoded. Among them, the target polynomial is used to generate a check sequence of the data to be encoded, and the check sequence of the data to be encoded is used to check and correct the data to be encoded. The codeword obtained after the data to be encoded is encoded in a forward error correction coding method includes the data to be encoded and the check sequence of the data to be encoded. In addition, the aforementioned first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat between the current beats during the process of the feedforward module receiving the data to be encoded.

[0008] When encoding is performed by the encoder provided by the present application, the target polynomial representing the data to be encoded is calculated by the feedforward module and the feedback module in the encoder. In addition, when the encoder calculates the target polynomial representing the data to be encoded by the feedforward module and the feedback module, the feedforward circuit calculates the corresponding single-beat polynomial according to the symbol received per beat, and the feedback module performs at least one iterative calculation on the single-beat polynomial output by the feedforward module, thereby calculating the target polynomial representing the data to be encoded. It can be seen that the feedback module is independent of the number of symbols (i.e., parallelism) of the data to be encoded input to the feedforward module per beat, or is understood as the feedback module being decoupled from the parallelism of the data to be encoded input to the feedforward module. In this way, in a large bandwidth scenario, even if the parallelism of the data to be encoded input to the encoder is large, the amount of calculation of the feedback module will not become longer due to the increase in the parallelism, so that the feedback module will not produce a technical problem that the timing cannot converge.

[0009] In a possible design, the above-mentioned data to be encoded includes K symbols, K is a positive integer. Then when the length of the codeword obtained after the data to be encoded is N after being encoded in a forward error correction coding method, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each of which includes the above-mentioned feedforward module and feedback module. In addition, the NK polynomial evaluation modules are used to calculate NK target polynomials representing the data to be encoded in a finite field through the feedforward module and feedback module in each polynomial evaluation module.

[0010] In another possible design, when the length of the codeword obtained after the data to be encoded is N+ΔN after being encoded in a forward error correction encoding method, the encoder includes N+ΔN-K polynomial evaluation modules, each of which includes the above-mentioned feedforward module and feedback module. In addition, the N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in a finite field through the feedforward module and feedback module in each polynomial evaluation module. Among them, the N+ΔN-K polynomial evaluation modules include the above-mentioned NK polynomial evaluation modules.

[0011] Among them, for the RS(N,K) code type with a codeword length of N and a payload length of K, the error correction capability is (NK) / 2. For the RS(N+ΔN,K) code type with a codeword length of N+ΔN and a payload length of K, the error correction capability is (N+ΔN-K) / 2. Therefore, through the above two possible design methods, the encoder provided by the present application can realize that when encoding RS code types with different error correction capabilities, the polynomial evaluation module in the encoder of the RS code type with higher error correction capability can reuse the polynomial evaluation module in the encoder of the RS code type with lower error correction capability. That is, through the encoder design provided by the present application, it is possible to realize that the encoder of the RS code type with higher error correction capability and the encoder of the RS code type with lower error correction capability share a common (i.e., multiplexed) polynomial evaluation module, thereby being able to achieve a significant saving of circuit area and power consumption in the actual module implementation. Among them, the error correction capability when the encoded codeword length is (N+ΔN) is (N+ΔN-K), and the error correction capability when the encoded codeword length is N is N-K.

[0012] In another possible design, the encoder further includes: a constant coefficient multiplication and addition module, which is used to calculate the check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial. A merging module, which is used to merge the data to be encoded and the check sequence of the data to be encoded to obtain a codeword after the data to be encoded is encoded in a forward error correction encoding method.

[0013] In another possible design, when the codeword length obtained after the above-mentioned data to be encoded by the forward error correction coding method is N, the above-mentioned constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK). When the codeword length after the above-mentioned data to be encoded by the forward error correction coding method is N+ΔN, the above-mentioned constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K). The second coefficient matrix includes the constant first coefficient matrix.

[0014] Through the above possible design mode, the constant coefficient matrix (second constant coefficient matrix) preset in the encoder with high error correction capability in the present application includes the constant coefficient matrix (second constant coefficient matrix) preset in the encoder with low error correction capability. In this way, the encoder with high error correction capability and the encoder with low error correction capability provided by the present application can share the module constructed based on the same coefficient matrix, so that the encoder provided by the embodiment of the present application can not only realize the encoding of forward error correction code patterns with different error correction capabilities, but also save the circuit area and power consumption of the encoder.

[0015] In another possible design, the encoder supports encoding of at least one forward error correction coding code type, and each code type in the at least one forward error correction coding code type has a different error correction capability.

[0016] Through this possible design, the encoder provided in the embodiment of the present application is a fusion encoder that can support forward error correction coding of multiple error correction capability code types.

[0017] In another possible design, when the value of n is greater than a threshold, the feedforward module includes a register, wherein the register is used to control the feedforward module to complete the calculation of a single-beat polynomial through at least two clock cycles.

[0018] Through this possible design, it can be ensured that the feedforward module of the encoder provided by the present application completes the calculation of a single-beat polynomial through at least two clocks. In other words, in a large bandwidth scenario, even if the parallelism of the data to be encoded input to the encoder is large, the encoder provided by the present application can complete forward error correction coding.

[0019] In another possible design, when the length of the codeword obtained after the above-mentioned data to be encoded is encoded in an error correction coding manner is N, and the root of the primitive polynomial of the finite field is α, the first constant coefficient matrix is ​​pre-calculated based on the following formula:

[0020]

[0021] In another possible design, the feedback module is specifically used when the first polynomial is A1, indicating that the polynomial of the symbol received in the current beat is A 2a When the second polynomial A2 is calculated by the following formula: A2 = A1 × (α i ) n +A 2a ; Among them, α i is the root of the generator polynomial in a finite field, and i is an integer in [0, NK-1].

[0022] It can be seen from this possible design that the feedback module in the encoder provided by the present application is independent of the parallelism of the input data to be encoded, that is, the two are decoupled, so the length of the feedback module is fixed and will not become longer due to the increase in the parallelism of the input data to be encoded. Therefore, in the scenario of large bandwidth and high input parallelism, the feedback module in the encoder of the present application will not have the problem of non-convergence in timing.

[0023] In the second aspect, the present application provides a coding method, which is applied to an encoder, and the encoder includes a feedforward module and a feedback module. The method includes: receiving the data to be encoded with a parallelism of n (n is a positive integer) symbols per beat through the feedforward module, and, according to the symbols in the data to be encoded received by the current beat, calculating the single-beat polynomial corresponding to the current beat in a finite field. Here, the single-beat polynomial represents the symbol received by the feedforward module through one beat. The single-beat polynomial corresponding to the current beat output by the feedforward module is received through the feedback module, and the second polynomial is calculated in the finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbol received by the historical beat. Among them, the second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine the target polynomial representing the data to be encoded. The target polynomial is used to generate a check sequence of the data to be encoded, and the check sequence of the data to be encoded is used to check and correct the data to be encoded. The codeword obtained after the data to be encoded is encoded in a forward error correction coding mode includes the data to be encoded and the check sequence of the data to be encoded. In addition, the aforementioned first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat between the current beats in the process of the feedforward module receiving the data to be encoded.

[0024] In another possible design, the data to be encoded includes K symbols, where K is a positive integer. When the length of the codeword obtained after the data to be encoded is N after being encoded in a forward error correction encoding method, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each of which includes the feedforward module and feedback module. In addition, the NK polynomial evaluation modules are used to calculate NK target polynomials representing the data to be encoded in a finite field through the feedforward module and feedback module in each polynomial evaluation module.

[0025] In another possible design, when the codeword length obtained after the above-mentioned data to be encoded is N+ΔN after being encoded in a forward error correction encoding method, the encoder includes N+ΔN-K polynomial evaluation modules, each of which includes a feedforward module and a feedback module. In addition, the N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in a finite field through the feedforward module and the feedback module in each polynomial evaluation module. Among them, the N+ΔN-K polynomial evaluation modules include the above-mentioned NK polynomial evaluation modules.

[0026] In another possible design, the method further includes: when it is determined that the current beat is the K / nth beat of receiving the data to be encoded, the second polynomial is determined as the target polynomial. According to the constant coefficient matrix and the target polynomial, the check sequence of the data to be encoded is calculated. The data to be encoded and the check sequence of the data to be encoded are merged to obtain the codeword of the data to be encoded after being encoded by the forward error correction coding method. Among them, the value of K / n is specifically the value of the quotient of K / n rounded upward. It should be understood that if the current beat is the K / nth beat of the encoder receiving the data to be encoded, it means that the payload of a codeword has been completed. Correspondingly, if the current beat is not the K / nth beat of the encoder receiving the data to be encoded, it means that the payload of a codeword has not yet been completed.

[0027] In another possible design, when the codeword length obtained after the above-mentioned data to be encoded by the forward error correction coding method is N, the above-mentioned constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK). When the codeword length after the above-mentioned data to be encoded by the forward error correction coding method is N+ΔN, the above-mentioned constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K). The second constant coefficient matrix includes the constant first coefficient matrix.

[0028] In another possible design, the encoder supports encoding of at least one forward error correction coding code type, and each code type in the at least one forward error correction coding code type has a different error correction capability.

[0029] In another possible design, when the value of n is greater than a threshold, the method further includes: controlling the feedforward module to complete the calculation of a single-beat polynomial through at least two clock cycles through a register inserted in the feedforward module.

[0030] It should be understood that the description of the beneficial effects of the second aspect and any possible design thereof can refer to the description of the beneficial effects of the first aspect and any possible design thereof, and will not be repeated here.

[0031] In a third aspect, the present application provides an encoding device. In a possible design, the encoding device is used to execute any of the methods provided in the second aspect above. The present application may divide the encoding device into functional modules according to any of the methods provided in the second aspect above. For example, each functional module may be divided according to each function, or two or more functions may be integrated into one processing module. Exemplarily, the present application may divide the malicious domain name determination device into a receiving unit and a computing unit, etc. according to the function. The description of the possible technical solutions and beneficial effects executed by the above-mentioned divided functional modules can refer to the technical solutions provided by the second aspect or its corresponding possible design, and will not be repeated here.

[0032] In a fourth aspect, the present application provides a chip comprising a coding circuit, wherein the coding circuit is used to execute any of the methods provided in the second aspect and any possible design thereof, so as to achieve encoding of the coded data in a forward error correction coding manner.

[0033] In a fifth aspect, the present application provides a computer-readable storage medium, which includes program instructions. When the program instructions are executed on a computer or a processor, the computer or the processor executes any method provided by any possible implementation of the second aspect.

[0034] In a sixth aspect, the present application provides a computer program product, which, when executed on an encoding device, enables any method provided by any possible implementation in the second aspect to be executed.

[0035] In this application, the names of the above encoders, encoding devices, encoding circuits, etc. do not limit the devices or functional modules themselves. In actual implementation, these devices or functional modules may appear with other names. As long as the functions of each device or functional module are similar to those of this application, they fall within the scope of the claims of this application and their equivalent technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of a current encoding circuit;

[0037] Figure 2 It is another current coding circuit schematic diagram;

[0038] Figure 3 An application scenario diagram provided for an embodiment of the present application;

[0039] Figure 4 A schematic diagram of an application of the FEC encoding technology provided in an embodiment of the present application in an Ethernet architecture;

[0040] Figure 5 Another schematic diagram of the application of the FEC encoding technology provided in the embodiment of the present application in the Ethernet architecture;

[0041] Figure 6 A schematic diagram of the architecture of a coding system provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of the structure of a general-purpose computer provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of an encoder provided in an embodiment of the present application;

[0044] Fig. 9A schematic diagram of a circuit structure of a feedforward circuit provided in an embodiment of the present application;

[0045] Fig.10 A schematic diagram of the structure of a feedforward circuit and a feedback circuit provided in an embodiment of the present application;

[0046] Fig.11 A schematic diagram of the structure of an encoder provided in an embodiment of the present application;

[0047] Fig.12 A schematic diagram of another structure of an encoder provided in an embodiment of the present application;

[0048] Fig.13 A schematic diagram of another structure of an encoder provided in an embodiment of the present application;

[0049] Fig.14 A schematic diagram of a feedforward circuit provided in an embodiment of the present application;

[0050] Fig.15 A schematic diagram of the relationship between a set of polynomials representing payloads under different codeword lengths provided in an embodiment of the present application;

[0051] Fig.16 Another schematic diagram of an encoder provided in an embodiment of the present application;

[0052] Fig.17 A schematic diagram of the relationship between constant coefficient sets under different codeword lengths provided in an embodiment of the present application;

[0053] Fig.18 Another schematic diagram of the structure of the encoder provided in the embodiment of the present application;

[0054] Fig.19 A schematic diagram of the structure of an encoder supporting multi-code fusion encoding provided in an embodiment of the present application;

[0055] Fig. 20 A schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

[0056] Fig.21 A schematic diagram of a constant coefficient matrix of the RS (544, 514, 15, 10) code type provided in an embodiment of the present application;

[0057] Fig. 22 A schematic diagram of the structure of an encoding device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to more clearly understand the embodiments of the present application, some terms or technologies involved in the embodiments of the present application are explained below:

[0059] 1) Forward error correction (FEC)

[0060] FEC, also known as forward error correction coding technology, is an error control technology.

[0061] FEC is widely used in communication systems to ensure the accuracy of transmitted data. The basic idea of ​​FEC is to add a check sequence of a certain length to the data to be sent at the transmitting end, so as to obtain the codeword of the data to be sent after FRC encoding. Obviously, the codeword after FRC encoding consists of the data to be sent and the check sequence. After the codeword after FRC encoding is transmitted to the receiving end, if the error in the data is within the correctable range of the check sequence, the receiving end corrects the error according to the check sequence obtained after decoding. In this way, the bit error rate of the data can be reduced and the reliability of the communication system can be improved.

[0062] Common FEC coding types include but are not limited to the following: Reed Solomon code (RS code), Hamming code, linear error correction code (low-density parity-check code), etc.

[0063] Taking RS code as an example, a specific implementation scheme in RS code FEC technology is a linear block cyclic code. RS code can correct both random errors and burst errors, and is usually also recorded as RS FEC.

[0064] Among them, cyclic codes include but are not limited to RS codes, cyclic redundancy check (CRC) codes, forward error correction codes (Bose-Chaudhuri-Hocquenghem codes, BCH), fire codes, etc. The basic unit that constitutes the codeword of the cyclic code is called a symbol. Therefore, the basic unit of RS code encoding calculation and decoding calculation is also a symbol. Usually, a symbol contains m bits, where m is an integer greater than or equal to 1. It should be understood that when m=1, the meaning of the symbol and the bit is the same. As an example, for BCH, CRC code, fire code, etc., m is usually 1. For RS code, m is usually greater than 1. Therefore, the basic unit of a cyclic code can be a bit, such as BCH, CRC, etc., or a symbol, such as RS code, etc.

[0065] Specifically, the length of the RS code word refers to the number of symbols contained in the RS code, usually represented by the letter N. The payload length in the RS code word refers to the number of symbols contained in the payload of an RS code word, usually represented by the letter K. Among them, the payload in the RS code word refers to the original data information protected by the RS code. For example, the payload in the RS code word can be message data to be transmitted in a communication network, etc., but is not limited to this. In addition, the redundant length of the RS code word refers to the number of symbols contained in the check sequence in an RS code word, usually represented by the letter R. Here, the symbols in the check sequence are also called redundant symbols. Obviously, R=NK.

[0066] For ease of description, when the codeword length of the RS code is N and the payload length is K, it can be recorded as RS(N,K) code. For example, the RS code pattern of KR4 is recorded as RS(528,514), indicating that the RS codeword length is 528 and the payload length is 514. For another example, the RS code pattern of KP4 is recorded as RS(544,514), indicating that the RS codeword length is 544 and the codeword information length is 514.

[0067] The error correction capability of the RS code refers to the maximum number of symbols that can be successfully corrected by an RS code word and are allowed to have errors, and is usually represented by T. For RS codes, the error correction capability T = (NK) / 2 (i.e., half of the redundant symbols in the RS code word). For example, for the RS code pattern of KR4, the error correction capability T = (528-514) / 2 = 7, that is, the maximum number of symbols that can be corrected by an RS code word in the RS code pattern of KR4 and are allowed to have errors is 7. For another example, for the RS code pattern of KP4, the error correction capability T = (544-514) / 2 = 15, that is, the maximum number of symbols that can be corrected by an RS code word in the RS code pattern of KP4 and are allowed to have errors is 15.

[0068] In addition, the coding overhead of the FEC code refers to the ratio of the redundancy length in the FEC codeword to the payload length. That is, the coding overhead of the FEC code is ((NK) / K, or R / K.

[0069] The following takes the cyclic code with a codeword length of N and a payload length of K as an example to briefly explain the encoding principle of the cyclic code.

[0070] The payload of length K can be expressed as a polynomial M(x), and M(x) satisfies the following formula (1):

[0071] Formula (1) M(x) = mK -1 ·x K-1 +m K-2 ·x K-2 +…+m1·x+m0

[0072] Here, m represents the value of each symbol in the payload, and x represents the position of each symbol in the payload.

[0073] The preset generating polynomial of the cyclic code in the finite field is denoted as g(x), and g(x) satisfies the following formula (2):

[0074] Formula (2) g(x) = g N-K ·x N-K +g N-K-1 ·x N-K-1 +…+g1·x+g0

[0075] Here, g represents the coefficient of the generator polynomial, and x represents the position of each symbol in the check sequence.

[0076] Based on the polynomials shown in formula (1) and formula (2), the encoding process of the cyclic code can be implemented by dividing M(x) and g(x) to obtain the remainder p(x). Among them, p(x) is the cyclic code codeword check sequence. Therefore, the codeword polynomial of a cyclic code satisfies the following formula (3):

[0077] Formula (3) x N-K M(x) = q(x) g(x) + p(x)

[0078] Here, q(x) is the quotient of M(x) and g(x).

[0079] Furthermore, the codeword polynomial of the cyclic code can be recorded as C(x), and C(x) satisfies the following formula (4):

[0080] Formula (4) C(x) = x N-K ·M(x)+p(x)

[0081] Thus, according to formula (4), the check sequence p(x) in the cyclic code word can be calculated as shown in formula (5). Wherein, MOD is the remainder operation.

[0082] Formula (5) p(x) = (x N-K ·M(x))MODg(x)

[0083] Thus, the check sequence p(x) of the payload data is obtained, and the encoded codeword can be obtained by combining the payload and the check sequence.

[0084] It should be noted that the calculations of polynomials in the above coding principles are all calculations of polynomials in a finite field.

[0085] Among them, the finite field is also called the Galois field, which is a field with only a finite number of elements and can be expressed by GF(2 m ) indicates that the 2 mrepresents an element in a finite field, and m is a positive integer. The addition of polynomials in a finite field is to combine like terms and perform either or operations on the coefficients, such as x 4 +x 4 = 0. Subtraction in a finite field is equal to addition, and there are no negative numbers in a finite field. For example, x 4 –x 4 is equal to x 4 +x 4 , -x 3 It's x 3 .

[0086] Furthermore, the code type of the RS code can also be expressed by RS(N,K,T,m), where N is the code length of the RS codeword, K is the payload length in the RS codeword, T is the error correction capability of the RS code, and m is used to indicate the finite field for RS coding calculation.

[0087] 2) Feedforward circuit, feedback circuit

[0088] In the embodiment of the present application, when in the time domain, the signal output by the circuit at time t1 does not affect the signal output at time t2, the circuit is called a feedforward circuit. When in the time domain, the signal output by the circuit at time t1 affects the signal output at time t2, the circuit is called a feedback circuit. Wherein, time t2 is a certain time after time t1. For example, time t1 is the time before time t2.

[0089] 3) Shoot

[0090] The "beat" described in the embodiment of the present application refers to the rhythm, and the "beat" and "rhythm" in the embodiment of the present application can be replaced with each other.

[0091] Typically, one clock cycle is defined as one tick.

[0092] 4) Parallelism

[0093] The parallelism described in the embodiments of the present application refers to the number of symbols of the data to be encoded that are allowed to be input to the encoder / encoding circuit in parallel in one beat when the data to be encoded is input to the encoder / encoding circuit. For example, when the parallelism of the data to be encoded is n, it means that n symbols of the data to be encoded are allowed to be input to the encoder / encoding circuit in parallel in one beat.

[0094] When the parallelism of the data to be encoded is n and the number of symbols included in the data to be encoded is K, it means that the K symbols of the data to be encoded can be input to the encoder / encoding circuit through K / n beats. The specific value of K / n is the value of the quotient of K / n rounded up. For example, when K is 10 and n is 4, the value of K / n is: the value of the quotient of 10 / 4 (i.e., 2.5) rounded up (i.e., 3).

[0095] In this case, in a scenario where the degree of parallelism of inputting the data to be encoded into the encoder / encoding circuit is n and the number of symbols included in the data to be encoded is K, assuming that K can divide n evenly, then in the first beat, the 1st to nth symbols among the K symbols are allowed to be input into the encoder / encoding circuit in parallel; in the second beat, the (n+1)th to 2nth symbols among the K symbols are allowed to be input into the encoder / encoding circuit in parallel; …; in the [K / n]th beat, the symbols allowed to be input into the encoder / encoding circuit in parallel are the (K-n+1)th to Kth symbols.

[0096] 5) Other terms

[0097] In the embodiments of the present application, the terms "first" and "second" do not indicate an order relationship, but are used to distinguish different objects. The first, second, etc. mentioned in the following documents are also used to distinguish different messages, etc., and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0098] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0099] At present, when FEC encoding is used for transmission data, since the essence of the cyclic code encoding process is the calculation process of polynomial division, the encoding circuit can be implemented as Figure 1 The circuit shown. Figure 1 As shown, taking the cyclic code RS (N, K) code as an example, the circuit 10 can receive K payload symbols serially through K clock cycles. During the input of K payload symbols, the selector points to "1", so that the K payload symbols input to the circuit 10 are output through the selector in sequence through K clock cycles, while entering the circuit 10 and being calculated by the multiplier and adder in the circuit 10. When the K payload symbols are input through K clock cycles, the values ​​stored in the NK registers in the circuit 10 are the symbols of the check sequence. At this time, the selector switches to 0, and the circuit 10 will output the symbols of the check sequence in sequence through NK clock cycles, so that a complete RS code word (including K payload symbols and NK check sequences) can be obtained.

[0100] However, the coding efficiency of inputting the data to be transmitted to the encoder in a serial manner is too low, so when the cyclic code encoding is actually implemented, a parallel input coding architecture is often adopted. That is, multiple payload symbols are input to the encoding circuit at the same time to improve the coding efficiency. As an example, common parallel bit widths are 40 bits, 80 bits, 160 bits, etc. Therefore, when the parallel bit width is 40 bits, 4 payload symbols with a length of 10 bits can be input to the encoding circuit at the same time. When the parallel bit width is 80 bits, 8 payload symbols with a length of 10 bits can be input to the encoding circuit at the same time. When the parallel bit width is 160 bits, 16 payload symbols with a length of 10 bits can be input to the encoding circuit at the same time.

[0101] Existing cyclic codes (such as RS code and BCH code) usually use Figure 1 The circuit structure shown in FIG. 1 is a linear feedback shift register (LFSR) circuit for encoding. Based on this circuit, a parallel encoding calculation circuit can be derived for large bandwidth scenarios. As an example, according to Figure 1 From the circuit structure shown, it can be deduced that when 32 symbols are input into the encoding circuit in parallel, the data calculation in the encoding circuit satisfies the following formula (6):

[0102] Formula (6)

[0103] Among them, REGicurrent represents the current value of the i-th register, and REGinext represents the value of the i-th register in the next clock cycle. Dj represents the j-th data currently input, where i = 1, 2, 3, ..., 14 (i.e., the number of symbols in the check sequence); j = 1, 2, 3, ..., 32 (i.e., the degree of parallelism). G is a 14×14 constant coefficient matrix, which can be expressed as the following matrix (1). H' is a 14×18 constant coefficient matrix, which can be expressed as the following matrix (2).

[0104] Matrix (1)

[0105] Matrix (2)

[0106] In addition, for RS (528, 514) encoding, when the payload is input into the encoding circuit in parallel with 32 symbols, the encoding circuit can be as follows: Figure 2 As shown. Figure 2 As shown, for 32 symbols (including D1 to D32) input into the encoding circuit in one clock cycle, D1 to D18 input Figure 2The circuit 201 shown in FIG. 200 is used to realize the operation of the payload and the constant coefficient matrix H'. D19 to D32 are respectively added to the feedback value of the previous clock cycle and sent to the circuit 202 to realize the operation of the payload and the constant coefficient matrix G. Further, the operation results of the constant coefficient matrix H' of D1 to D18 and the operation results of the constant coefficient matrix G of D19 to D32 are passed through 31 adders (such as through Figure 2 The block 203 shown in FIG. 20 includes 31 adders) to add and output the operation results of D1 to D32. The feedback value of the previous clock cycle refers to the result calculated according to D1 to D32 in the previous clock cycle. In other words, the operation result in one clock cycle is used as the feedback value of the next clock cycle to participate in the operation of the next clock cycle. The loop for obtaining the feedback value can be called a feedback loop.

[0107] It can be seen that for the payload input to the encoder in each clock cycle, the result of the regular coefficient matrix operation needs to be cascaded through n-1 adders (that is, the result of the previous adder is used as the input of the next adder) for addition operation. Among them, n is the number of symbols of the parallel input payload, or called parallelism. Therefore, the length of the feedback loop in the encoder is strongly related to the parallelism of the encoder input payload symbols, that is, the larger the number of symbols of the encoder's parallel input payload, the more addition operations (n-1 addition operations) are performed on the feedback loop in the encoder, that is, the longer the feedback loop in the encoder. In this case, when the number of symbols of the parallel input payload is large, Figure 2 The encoding circuit shown cannot complete n-1 addition operations within one clock cycle, resulting in a technical risk that the feedback loop in the encoder cannot converge in timing.

[0108] In addition, for a variety of FEC code types, such as the two RS FEC code types defined by the 802.3 standard: RS (528, 514) and RS (544, 514), the coefficients of the generating polynomials of these two code types in the finite field are completely different, so it is difficult to share the circuit resources (adder multiplier) for implementing the encoding of these two code types. Referring to Table 1, Table 1 shows the values ​​of the coefficients of the generating polynomials of the RS (528, 514) code type and the RS (544, 514) code type. As shown in Table 1, the 15 (i ∈ [0, 15]) coefficients of the RS (528, 514) code type generating polynomial and the 31 (i ∈ [0, 30]) coefficients of the RS (544, 514) code type generating polynomial are all different. Wherein, i is an integer. It should be understood that the coefficient of the generating polynomial is the coefficient g in the above polynomial (2).

[0109] Table 1

[0110]

[0111]

[0112] Based on this, an embodiment of the present application provides an encoder, which, when encoding, calculates a target polynomial representing the data to be encoded through a feedforward module and a feedback module in the encoder. Wherein, the feedforward front path is used to receive the data to be encoded with a parallelism of n symbols per beat, and calculates a single-beat polynomial corresponding to the current beat in a finite field according to the symbols in the data to be encoded received by the current beat. The feedback module is used to calculate the target polynomial representing the data to be encoded according to the single-beat polynomial corresponding to the current beat received from the feedforward module, and the first polynomial representing the symbols received by the historical beat. In this way, the purpose of decoupling the feedback module in the encoder from the parallelism of the data to be encoded input to the encoder is achieved. That is, even if the number of symbols input to the encoder per beat of the data to be encoded is large, the length of the feedback module will not be lengthened, so that the feedback module will not produce a technical problem that the timing cannot converge.

[0113] The data to be encoded may be data to be transmitted in a communication network, or data to be stored in a storage system (such as a distributed storage system), and is not limited thereto. The single-shot polynomial is used to represent the symbols received by the feedforward module through one shot.

[0114] refer to Figure 3 , Figure 3 An application scenario diagram of an embodiment of the present application is shown. Figure 3 As shown, the payload data to be encoded is input to the encoder provided in the embodiment of the present application with a parallelism of n symbols per beat. Or it is understood that the payload data to be encoded is input to the encoder provided in the embodiment of the present application with a parallelism of n per beat. Thus, the encoder performs forward error correction encoding on the payload data to be encoded, and outputs the encoded codeword of the data to be encoded, which includes the payload and the check sequence, and the payload is the data to be encoded. Furthermore, the encoded codeword can be transmitted or stored. It should be understood that since the feedback module in the encoder provided in the embodiment of the present application does not generate the technical risk that the timing cannot converge, the encoder provided in the embodiment of the present application supports forward error correction encoding of the payload data to be encoded with high parallelism in a large bandwidth scenario.

[0115] Optionally, the process of encoding data by the encoder provided in the embodiment of the present application is generally applied to the media access control (MAC) sublayer and the physical layer (PHY) layer in the Ethernet architecture.

[0116] In an example, refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram showing an application of the FEC encoding technology provided in an embodiment of the present application in an Ethernet architecture. Figure 4 As shown, Figure 4 The figure shows a hierarchical architecture of Ethernet. In the Ethernet architecture, the MAC sublayer, the physical coding sublayer (PCS) sublayer, the physical medium attachment (PMA) sublayer, and the physical medium dependent (PMD) sublayer are divided according to their functions. Among them, PCS, PMA, and PMD constitute the PHY layer. FEC coding technology is applied to Figure 4 The MAC sublayer and PHY layer of the Ethernet architecture shown in Figure 2. For example, CRC encoding is generally used for Figure 4 In the MAC sublayer of the Ethernet architecture shown in the figure, RS coding is generally used for Figure 4 The PCS sublayer in the Ethernet architecture shown is not described in detail.

[0117] In another example, refer to Figure 5 , Figure 5 FIG. 2 shows another application schematic diagram of the FEC encoding technology provided in the embodiment of the present application in the Ethernet architecture. Figure 5 As shown, the standard Ethernet architecture includes an application layer, a presentation layer, a session layer, a transport layer, a network layer, a data link layer, and a physical layer. Among them, the data link layer includes a MAC sublayer and a coordination sublayer. The coordination sublayer is a special sublayer (equivalent to the top layer of the physical layer) responsible for processing the translation or mapping requirements of the MII signaling and the MAC sublayer. The physical layer includes a PCS sublayer, a PMA sublayer, and a PMD sublayer. The FEC encoding technology provided in the embodiment of the present application is applied to the MAC sublayer of the physical layer and the data link layer. For example, the RS encoder provided in the embodiment of the present application can be deployed in Figure 5 The PCS sublayer in the physical layer is shown.

[0118] Optionally, the physical implementation of the above encoder includes but is not limited to: chips, integrated circuits or computing devices or computing equipment with computing processing capabilities. As an example, chips include but are not limited to complex programmable logic devices (CPLD), field programmable gate arrays (FPGA), programmable array logic (PAL) devices, generic array logic (GAL) devices, network cards, microcontroller units (MCU), etc. Integrated circuits include but are not limited to application-specific integrated circuits (ASIC), etc. Computing devices include but are not limited to general-purpose computers, laptops, tablet computers, etc.

[0119] The embodiment of the present application also provides a coding system, which includes a controller and an encoder provided by the embodiment of the present application. The controller is used to control the symbols of the data to be encoded to be input to the encoder in parallel. The encoder performs forward error correction encoding on the encoded data according to the received data to be encoded. The specific process can be referred to the description below and will not be repeated here.

[0120] As an example, refer to Figure 6 , Figure 6 FIG. 6 shows a schematic diagram of a coding system 60 provided in an embodiment of the present application. Figure 6 As shown, the coding system 60 includes a controller 610 and an encoder 620. The controller 610 controls the input of symbols of the data to be coded to the encoder 620 at a parallelism of n symbols per beat, where n is a positive integer. The encoder 620 performs forward error correction coding on the coded data according to the received coded data, and outputs the coded data. The specific process can be referred to the following description and will not be repeated here.

[0121] Optionally, the controller and encoder in the above encoding system can be integrated into one device (such as a serdes chip (serdes is the abbreviation of SERializer / DESerializer)), or integrated into different devices, without limitation. Among them, the device can be a chip, an integrated circuit, or a computing device or computing equipment with computing processing capabilities, etc., without limitation. Among them, the detailed description of "chip, integrated circuit, or computing device or computing equipment with computing processing capabilities" can be referred to the above description and will not be repeated.

[0122] In one example, taking the above encoding system implemented by a general-purpose computer as an example, refer to Figure 7 , Figure 7 FIG. 7 is a schematic diagram showing the structure of a general-purpose computer 70 provided in an embodiment of the present application. Figure 7 As shown, the general purpose computer 70 includes a processor 710, a memory 720, an encoder 730, a network / communication interface 740, and a bus 750. The processor 710, the memory 720, the encoder 730, and the network / communication interface 740 are connected via a bus 750.

[0123] Processor 710 is the control center of general-purpose computer 70, which may be a general-purpose central processing unit (CPU). Processor 710 may also be other general-purpose processors, digital signal processors (digital signal processing, DSP), application-specific integrated circuits (application-specific integrated circuits, ASIC), field-programmable gate arrays (field-programmable gate arrays, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, graphics processing units (graphics processing units, GPU), neural processing units (neural processing units, NPU), tensor processing units (tensor processing units, TPU) or artificial intelligence (artificial intelligent) chips, data processors (data processing units, DPU), etc.

[0124] As an example, the processor 710 includes one or more CPUs, such as Figure 7 CPU 0 and CPU 1 are shown in .

[0125] In addition, the processor 710 is used to implement the controller function in the above encoding system to control the parallel input of the data to be encoded to the encoder.

[0126] The memory 720 is used to store program instructions or data to be accessed by the application process, and the processor 710 can execute the program instructions in the memory 720. As an example, the memory 720 can be used to store data to be encoded and data that has been encoded.

[0127] The memory 720 includes a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. Among them, the volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM) and direct rambus RAM (DR RAM). Non-volatile memory can be storage class memory (SCM), solid state drive (SSD), hard disk drive (HDD), etc. Among them, storage class memory can be, for example, non-volatile memory (NVM), phase-change memory (PCM), persistent memory, etc.

[0128] In a possible implementation, the memory 720 exists independently of the processor 710. The memory 720 is connected to the processor 710 via a bus 750 and is used to store data, instructions or program codes. For example, the processor 710 controls the data to be encoded stored in the memory 720 to be input to the encoder in parallel, and writes the data encoded by the encoder into the memory 720.

[0129] In another possible implementation, the memory 720 and the processor 710 are integrated together.

[0130] The encoder 730 is an encoder in the above encoding system, which is used to perform forward error correction encoding on the received data to be encoded and output the encoded codeword. The detailed description of the encoder can be referred to the following description, which is not repeated here.

[0131] The network / communication interface 740 is used to connect the general-purpose computer 70 with other devices (such as devices for receiving encoded data) through a communication network, and the communication network can be Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. The network / communication interface 740 includes a receiving unit for receiving data / messages and a sending unit for sending data / messages.

[0132] The bus 750 may be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, a high-speed serial computer expansion bus (PCIe), a compute express link (CXL) or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0133] It should be pointed out that Figure 7 The structure shown in the figure does not constitute a limitation on the general-purpose computer 70, except Figure 7 In addition to the components shown, the general purpose computer 70 includes Figure 7 More or fewer components may be shown, or certain components may be combined, or the components may be arranged differently.

[0134] In conjunction with the accompanying drawings, the encoder provided in the embodiment of the present application is described in detail by taking the FEC encoding as RS (N, K) code as an example. Among them, RS (N, K) means that the length of the encoded codeword is N, and the payload length is K. Correspondingly, the length of the check sequence in the encoded codeword is NK. N and K are both integers, and N is greater than K.

[0135] It should be understood that according to the definition of RS(N,K) code, the RS-encoded codeword C(x) satisfies the mathematical constraints of formula (4) above. Therefore, the root α of the generating polynomial in the finite field is i Substituting into formula (4), we can get formula (7), where i∈[0,NK-1].

[0136] Formula (7) C(α i )=(α i ) N-K ·M(α i )+p(α i )=0,i=0,1,2,…,NK-1

[0137] It should also be understood that the polynomial operations described in the embodiments of the present application are all operations of polynomials in a finite field. Based on this, from (α i ) N-K ·M(α i )+p(α i )=0, we can get formula (8):

[0138] Formula (8) p(α i )=(α i ) N-K ·M(α i ) i=0,1,2,…,NK-1

[0139] And from the above, it can be seen that the polynomial p(x) used to obtain the check sequence is the remainder of the division between the polynomial M(x) representing the payload and the generating polynomial g(x). Therefore, based on the polynomials (1) and (2) described above, the polynomial p(x) satisfies the following formula (9).

[0140] Formula (9) p(x) = p0 + p1x + p2x 2 +…+p N-K-1 x N-K-1

[0141] Therefore, the root α of the generating polynomial in the finite field i Substituting formula (9) and combining it with formula (8), we can get the following formula (10): where i∈[0,NK-1].

[0142] Formula 10

[0143] Furthermore, (α 0 ) N-K Moving to the left side of formula (10) and converting the operation into a matrix operation, we can obtain the following formula (11):

[0144] Formula (11)

[0146]

[0147] After matrix operation, formula (11) can be obtained as follows:

[0148] Formula (12)

[0149] Based on formula (12), we introduce the symbols Θ, Φ, and Ω, and when implementing RS(N,K) coding, we use Θ N,K Satisfy formula (13), so that Φ N,K Satisfy formula (14), and make Ω N,K Satisfies formula (15):

[0150] Formula (13)

[0151] Formula (14)

[0152] Formula (15)

[0153] It can be seen that in the RS(N,K) code type, Θ N,K Indicates (NK) 2 The set of constant coefficients, Φ N,K The polynomial set representing the payload in the RS codeword, Ω N,K represents the check sequence in the RS codeword. And, from formula (12), formula (13), formula (14) and formula (15), Θ N,K , Φ N,K and Ω N,K Satisfy Ω N,K =Θ N,K ×Φ N,K Mathematical constraints.

[0154] Therefore, the process of calculating the check sequence in the RS codeword in the RS encoding process can be converted into calculating Θ N,K ×Φ N,K In the specific implementation, the corresponding modules need to implement Θ N,K and Φ N,K Among them, Φ N,K The specific implementation module includes (NK) calculations for the polynomial M(α i ) module (hereinafter referred to as the polynomial evaluation module), i∈[0,NK-1]. N,K Then the calculation (NK) is realized 2 constant coefficient θ j，1 ,θ j，2 ,θj，3 ,…,θ j，N-K , j=1,2,…,NK.

[0155] Among them, M(α i ) is a polynomial representing the payload in a finite field. i is the root of the generator polynomial in a finite field, so α i Substituting into formula (1), we can obtain M(α) that satisfies formula (16) i ):

[0156] Formula (16) M(α i )=m K-1 ·(α i ) K-1 +m K-2 ·(α i ) K-2 +…+m1·(α i )+m0

[0157] Based on this, in the embodiment of the present application, the polynomial M(α i ) is called a polynomial evaluation module. The polynomial evaluation module includes the feedforward module and the feedback module described above. Optionally, the feedforward module and the feedback module can be implemented by hardware circuits, or by a combination of software and hardware circuits, which is not limited. As an example, the feedforward module can be implemented by a feedforward circuit, and the feedback module can be implemented by a feedback circuit.

[0158] For the sake of simplicity, the embodiments of the present application are described below by taking the feedforward module in the encoder as a feedforward circuit and the feedback module in the encoder as a feedback circuit as an example. In this case, the polynomial evaluation module includes the feedforward circuit and the feedback circuit, so in the following, the polynomial evaluation module is referred to as a polynomial evaluation circuit.

[0159] refer to Figure 8 , Figure 8 FIG. 1 is a schematic diagram of an encoder provided in an embodiment of the present application. Figure 8 As shown, the encoder 80 includes a feedforward circuit 810 and a feedback circuit 820 .

[0160] Among them, the feedforward circuit 810 is used to receive the data to be encoded with a parallelism of n symbols per beat. In this way, the feedforward circuit 810 can receive the data to be encoded through K / n beats. Among them, the data to be encoded (i.e., the payload data in the encoded codeword) includes K symbols, n and K are both positive integers, and K is greater than or equal to n. The value of K / n is specifically the value of the quotient of K / n rounded upward. Therefore, the K / nth beat of receiving the data to be encoded is the last beat of receiving K symbols in the data to be encoded.

[0161] It should be understood that when the data to be encoded including K symbols is encoded, the controller in the encoding system controls the data to be encoded to be input into the feedforward circuit 810 of the encoder 81 at n symbols per beat. The detailed description of the controller can refer to the above description and will not be repeated. In response, the feedforward circuit 810 receives the data to be encoded at a parallelism of n symbols per beat, and receives the data to be encoded through K / n beats.

[0162] The feedforward circuit 810 is also used to calculate a single-beat polynomial corresponding to the current beat in a finite field according to the symbols in the data to be encoded received in the current beat. Here, the single-beat polynomial represents the symbols received by the feedforward module through one beat.

[0163] Specifically, the feedforward circuit 810 includes n multipliers, and the n multipliers are used to receive n symbols of the data to be encoded that are input to the feedforward circuit 810 with a parallelism of n. Based on formula (16), it can be seen that the n multipliers are respectively used to multiply the received n symbols by coefficients (α i ) u Then, the multiplication results are summed through n-1 adders, so that a polynomial representing the n symbols input to the feedforward circuit 810 in a single shot can be obtained, which is recorded as a single shot polynomial. Where u∈[0,n-1].

[0164] It should be understood that the operation implemented by the feedforward circuit 810 is an operation in a finite field. i is the root of the generator polynomial used by the feedforward circuit 810 when performing finite field operations, i∈[0,NK-1]. α is the root of the primitive polynomial in the finite field. The finite field is GF(2 10 ) as an example, the primitive polynomial in this finite field is x 10 +x 3 +1, α is the root of the primitive polynomial, so the value of α can be solved based on the primitive polynomial. i The value of can also be calculated.

[0165] Furthermore, according to the K symbols of the data to be encoded input to the feedforward circuit 810 in K / n beats, the feedforward circuit can output K / n single-beat polynomials through K / n beats. That is, the feedforward circuit 810 can calculate in a finite field a polynomial representing the symbol received in each beat (i.e., a single-beat polynomial).

[0166] refer to Fig. 9 , Fig. 9 FIG. 1 shows a schematic diagram of a circuit structure of a feedforward circuit provided in an embodiment of the present application. Fig. 9 As shown, m represents the symbol in the data to be encoded.

[0167] like Fig. 9As shown, in the first beat, the feedforward circuit 810 receives the 1st to nth symbols of the data to be encoded, which are m K-1 、m K-2 ,…,m K-n Among them, m K-1 Through the multiplier and the coefficient (α i ) n-1 Multiplication, m K-2 Through the multiplier and the coefficient (α i ) n-2 Multiply, ..., m K-n Through the multiplier and the coefficient (α i ) 0 Multiply them, and sum the multiplication results of n multipliers through n-1 adders, so as to obtain a single-beat polynomial representing the n symbols of the first beat input, that is, to obtain a single-beat polynomial corresponding to the first beat, denoted as B 1a .

[0168] Similarly, in the second beat, the feedforward circuit 810 receives the n+1th to 2nth symbols of the data to be encoded, which are m K-n-1 、m K-n-2 ,…,m K-2n Among them, m K-n-1 Through the multiplier and the coefficient (α i ) n-1 Multiplication, m K-n-2 Through the multiplier and the coefficient (α i ) n-2 Multiply, ..., m K-2n Through the multiplier and the coefficient (α i ) 0 Multiply them, and sum the multiplication results of the n multipliers through n-1 adders, so as to obtain a single-beat polynomial representing the n symbols of the second beat input, that is, to obtain a single-beat polynomial corresponding to the second beat, denoted as B 2a .

[0169] Similarly, in the K / nth beat, the feedforward circuit 810 receives the [(K / n)-1]×n+1 to (K / n)×n symbols in the data to be encoded, which are m n-1 、m n-2 ,…,m K-(K / n)×n . m K-(K / n)×n That is m0. Among them, m n-1 Through the multiplier and the coefficient (α i ) n-1 Multiplication, m n-2 Through the multiplier and the coefficient (α i ) n-2 Multiply, ..., m0 through the multiplier and the coefficient (α i ) 0Multiply them, and sum the multiplication results of n multipliers through n-1 adders, so as to obtain a single-beat polynomial representing the n symbols of the K / n-th beat input, that is, to obtain a single-beat polynomial corresponding to the K / n-th beat, denoted as B (K / n)a .

[0170] It should be understood that in the process of inputting the data to be encoded with a length of K symbols at a parallelism of n, the K / nth beat is the last beat. When at the K / nth beat, when the number of symbols (recorded as "last beat payload symbols") input to the feedforward circuit 810 in the data to be encoded is less than n, the last beat payload symbol can be set to the low-order symbol of the n symbols input at the K / nth beat, and the bits except for the bits used to set the last beat payload symbol in the n symbols input at the K / nth beat are filled with 0, and n symbols including the last beat payload symbol are input to the encoder.

[0171] Feedback circuit 820 is used to receive the single-beat polynomial corresponding to the current beat output by the feedforward circuit, and calculate the second polynomial in the finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbol received by the historical beat, the second polynomial represents the symbol received from the first beat to the current beat, and the second polynomial is used to determine the polynomial representing the data to be encoded. Here, the first beat refers to the first beat of the feedforward circuit receiving the data to be encoded, and the historical beat is the beat between the current beats in the process of receiving the data to be encoded by the feedforward circuit. As an example, assuming that the current beat is the third beat in the process of receiving the data to be encoded, the historical beat includes the first beat and the second beat of receiving the data to be encoded. As another example, assuming that the current beat is the fifth beat in the process of receiving the data to be encoded, the historical beat includes the first beat, the second beat, the third beat and the fourth beat of receiving the data to be encoded.

[0172] Specifically, the feedback circuit 820 includes an adder and a multiplier. The implementation principle of the feedback circuit 820 is: when the first polynomial is represented by A1, the second polynomial is represented by A2, and the single-shot polynomial representing the symbol received in the current shot is represented by A 2a When , the feedback circuit 820 is used to calculate the second polynomial A2 by the following formula (17):

[0173] Formula (17) A2=A1×(α i ) n +A 2a

[0174] It should be understood that the operation implemented by the feedback circuit 820 is an operation in a finite field. i is the root of the generator polynomial used by the feedback circuit 820 when performing finite field operations, i∈[0,NK-1]. α is the root of the primitive polynomial in the finite field. The process of solving α can refer to the above description and will not be repeated here.

[0175] It should be noted that if the current beat is the K / nth beat, and the number of the last beat payload symbols mentioned above is less than the parallelism n, then when calculating the second polynomial in the K / nth beat, (α i ) n The value of n in is the number of payload symbols at the last beat. For example, if the parallelism n is 10, and the number of payload symbols (i.e., the last beat payload symbols) input at the K / nth beat of the data to be encoded is 2, then when calculating the second polynomial corresponding to the K / nth beat, (α i ) n The value of n in is 2.

[0176] It can be seen that, although in timing, the calculation result of the current clock cycle of the feedback circuit 820 participates in the operation in the next clock cycle, the length of the feedback circuit 820 is independent of the parallelism of the feedforward circuit 810 receiving the data to be encoded. In this case, even in a large bandwidth scenario, the parallelism of the data to be encoded input to the encoder is very large, and the length of the feedback circuit in the encoder will not be affected. In other words, the encoder provided in the embodiment of the present application realizes the decoupling of the parallelism of the data to be encoded input to the encoder and the feedback circuit in the encoder, so that in a large bandwidth scenario, when the high parallelism inputs the data to be encoded to the encoder, there will be no technical problem that cannot converge in timing. This is because the addition and multiplication operations that need to be completed by the feedback circuit in the encoder provided in the embodiment of the present application can be completed completely within one clock cycle.

[0177] Furthermore, the feedforward circuit 810 receives the data to be encoded through K / n beats, thereby outputting K / n single-beat polynomials, and the feedback circuit can calculate the polynomial representing the data to be encoded through (K / n)-1 iterations according to each single-beat polynomial output by the feedforward circuit 810, and record it as the target polynomial. Further, the target polynomial is used to generate a check sequence of the data to be encoded, and the check sequence of the data to be encoded is used to check and correct errors in the data to be encoded, and the codeword obtained after the data to be encoded is encoded in the forward error correction encoding method includes the data to be encoded and the check sequence of the data to be encoded.

[0178] Combination Fig. 9 ,refer to Fig.10 , Fig.10 A schematic structural diagram of a feedforward circuit and a feedback circuit provided in an embodiment of the present application is shown.

[0179] like Fig.10 As shown, in the first beat, the feedback circuit 820 receives the single-beat polynomial B of n symbols output by the feedforward circuit 810 representing the first beat input 1a The feedback circuit 820 inputs 0 to the multiplier 1003 through the selector 1002. Then, the multiplier 1003 performs a multiplication of 0 and the coefficient (αi ) n The multiplication operation is performed and the multiplication result is output, and the result is 0. The adder 1001 adds the result 0 output by the multiplier 1003 and the single-shot polynomial B output by the feedforward circuit 810. 1a Perform addition operation to obtain the polynomial of the symbol of the data to be encoded input to the feedforward circuit 810 through the previous beat, recorded as B 1b .

[0180] In the second beat, the feedback circuit 820 receives the single-beat polynomial B of n symbols output by the feedforward circuit 810 representing the second beat input 2a The feedback circuit 820 inputs the polynomial B calculated by the feedback circuit 820 at the first beat to the multiplier 1003 through the selector 1002. 1b It should be understood that the polynomial B calculated by the feedback circuit 820 at the first beat is 1b , which is the result of the calculation obtained by the adder 1001 of the feedback circuit 820 at the first beat. Then, the multiplier 1003 calculates B 1b and coefficient (α i ) n Perform multiplication and output the multiplication result. The result is B. 1b ×(α i ) n The adder 1001 adds the result B output by the multiplier 1003. 1b ×(α i ) n The single-beat polynomial B calculated by the feedforward circuit 810 for the n symbols input in the second beat 2a Perform addition operation to obtain the polynomial B of the symbol of the data to be encoded input to the feedforward circuit 810 through the first 2 beats 1b ×(α i ) n +B 2a , denoted as B 2b .

[0181] Similarly, at the K / nth beat, the feedback circuit 820 receives the single-beat polynomial B representing the n symbols input at the K / nth beat output by the feedforward circuit 810. (K / n)a The feedback circuit 820 inputs the polynomial B calculated by the feedback circuit 820 at the [(K / n)-1]th beat into the multiplier 1003 through the selector 1002. ((K / n)-1)b It should be understood that the polynomial B calculated by the feedback circuit 820 at the [(K / n)-1]th beat is ((K / n)-1)b , which is the calculation result output by the adder 1001 of the feedback circuit 820 at the [(K / n)-1]th beat. The multiplier 1003 ((K / n)-1)b and coefficient (α i )n Perform multiplication and output the multiplication result. The result is B. ((K / n)-1)b ×(α i ) n The adder 1001 adds the result B output by the multiplier 1003. ((K / n)-1)b ×(α i ) n The single-beat polynomial B calculated by the feedforward circuit 810 for the n symbols input at the K / nth beat (K / n)a Perform addition operation to obtain the polynomial B of K symbols of the data to be encoded input to the feedforward circuit 810 through K / n beats ((K / n)-1)b ×(α i ) n +B (K / n)a , denoted as B (K / n)b At this time, B (K / n)b That is the target polynomial mentioned above, and the feedback circuit 820 outputs the target polynomial.

[0182] The feedforward circuit 810 and the feedback circuit 820 in the encoder 80 described above constitute a polynomial evaluation circuit in the encoder 80 .

[0183] It should be understood that a polynomial evaluation circuit includes a feedforward circuit 810 and a feedback circuit 820, and the feedforward circuit 810 and the feedback circuit 820 in the same polynomial evaluation circuit perform operations in the same finite field, and use the same root of the generator polynomial when performing finite field operations. In this way, a target polynomial of the data to be encoded that is input to the encoder 80 in parallel can be calculated in the finite field through a polynomial evaluation circuit.

[0184] To calculate the above Φ N,K In some embodiments, when the value of (NK) is 1, the encoder 80 includes a polynomial evaluation circuit. The root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit when performing finite field operations is α 0 .

[0185] In some other embodiments, when the value of (NK) is greater than 1, the encoder 80 includes (NK) polynomial evaluation circuits. Thus, the (NK) polynomial evaluation circuits are used to calculate (NK) target polynomials representing the data to be encoded in a finite field through the feedforward circuit and the feedback circuit in each of the (NK) polynomial evaluation circuits. Fig.11 , Fig.11 Another structural schematic diagram of the encoder provided in an embodiment of the present application is shown.

[0186] like Fig.11As shown, the encoder 80 includes (NK) polynomial evaluation circuits, namely polynomial evaluation circuit 0, polynomial evaluation circuit 1, ..., polynomial evaluation circuit (NK-2), and polynomial evaluation circuit (NK-1). The root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit 0 when performing finite field operations is α 0 The root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit 1 when performing finite field operations is α 1 ,…, the root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit (NK-2) when performing finite field operations is α N-K-2 , and the root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit (NK-1) when performing finite field operations is α N-K-1 In this way, the data to be encoded received by the encoder 80 through K / n beats can be respectively input into each polynomial generation circuit in the (NK) polynomial evaluation circuits, so as to calculate and output the corresponding target polynomial.

[0187] For example, the encoder 80 sequentially inputs the data to be encoded received by K / n beats into the polynomial evaluation circuit 0, so that the polynomial evaluation circuit 0 calculates the root of the generating polynomial as α according to the data to be encoded received by K / n beats. 0 The target polynomial M(α 0 ).

[0188] Similarly, the data to be encoded received by the encoder 80 through K / n beats are also sequentially input into the polynomial evaluation circuit 1, so that the polynomial evaluation circuit 1 calculates the root of the generating polynomial as α according to the data to be encoded received through K / n beats. 1 The target polynomial M(α 1 ).

[0189] Similarly, the data to be encoded received by the encoder 80 through K / n beats are also sequentially input into the polynomial evaluation circuit (NK-2), so that the polynomial evaluation circuit (NK-2) calculates the root of the generating polynomial as α according to the data to be encoded received through K / n beats. N-K-2 The target polynomial M(α N-K-2 ).

[0190] Similarly, the data to be encoded received by the encoder 80 through K / n beats are also sequentially input into the polynomial evaluation circuit (NK-1), so that the polynomial evaluation circuit (NK-1) calculates the root of the generating polynomial as α according to the data to be encoded received through K / n beats. N-K-1 The target polynomial M(α N-K-1 ).

[0191] The polynomial evaluation circuit calculates the root of the generating polynomial as α according to the K / n-beat received data to be encoded. i The target polynomial M(α i ) for detailed description, please refer to the above description and will not be repeated here.

[0192] Further, after (NK) target polynomials are calculated by (NK) polynomial evaluation circuits, in order to realize the calculation of the check sequence of the data to be encoded by the (NK) target polynomials, refer to Fig.12 , Fig.12 FIG. 2 shows another structural diagram of an encoder provided in an embodiment of the present application. Fig.12 As shown, the encoder 80 also includes a constant coefficient multiplication and addition module 1210 and a merging module 1220.

[0193] The constant coefficient multiplication and addition module 1210 is used to calculate the check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial representing the data to be encoded. Specifically, the constant coefficient multiplication and addition module 1210 is used to calculate the check sequence of the data to be encoded according to the constant coefficient matrix and (NK) target polynomials representing the data to be encoded.

[0194] Here, the constant coefficient matrix is ​​the matrix θ described in formula (13) above N,K , recorded as the first constant coefficient matrix, represents the (NK) target polynomials of the data to be encoded, which is the Φ mentioned above N,K Therefore, the constant coefficient multiplication and addition module 1210 is based on θ N,K and Φ N,K , and the mathematical constraints Ω described above N,K =Θ N,K ×Φ N,K , we can calculate Ω N,K ,Ω N,K It is the check sequence of the data to be encoded.

[0195] Specifically, Fig.12 As shown, when the data to be encoded is input to the encoder 80 with a parallel degree n, it is calculated by the (NK) polynomial evaluation circuits described above, and (NK) target polynomials [including M(α 0 )、M(α 1 ),…,M(α N-K-2 )、M(α N-K-1 )], the constant coefficient multiplication and addition module 1210 receives the (NK) target polynomials and calculates the check sequence of the data to be encoded according to the first constant coefficient matrix and the (NK) target polynomials.

[0196] For RS(N,K), the first coefficient matrix Θ N,Kis a matrix of size (NK)×(NK). Therefore, in the encoder for implementing RS(N,K) encoding, a first constant coefficient matrix is ​​preset. Each coefficient in the first constant coefficient matrix is ​​predetermined by formula (13). Since α is the root of the primitive polynomial in the finite field, when determining each coefficient in the first constant coefficient matrix, the root α can be first solved based on the primitive polynomial of the finite field, and each coefficient in the first constant coefficient matrix can be determined based on α, constant N, constant K and formula (13). Assuming that the finite field is GF(2 10 ) as an example, the primitive polynomial in this finite field is x 10 +x 3 +1, so that the root α of the primitive polynomial can be solved based on the primitive polynomial. Then, each coefficient in the first constant coefficient matrix is ​​determined according to the solved α, constant N, constant K and formula (13).

[0197] Furthermore, based on the matrix operation principle, the constant coefficient multiplication and addition module 1210 calculates the constant coefficient multiplication and addition module 1210 according to the above mathematical constraint relationship Ω N,K =Θ N,K ×Φ N,K Calculate Ω N,K That is, the constant coefficient multiplication and addition module 1210 includes (NK) submodules, each of which is used to calculate the constant coefficient multiplication and addition module 1210 according to the coefficient corresponding to each submodule and the (NK) target polynomials (i.e., Φ N,K ), calculate the corresponding check value. (NK) submodules obtain corresponding (NK) check values, and the (NK) check values ​​constitute the check sequence of the data to be encoded.

[0198] Combination Fig.11 and Fig.12 ,refer to Fig.13 , Fig.13 FIG. 2 shows another structural diagram of an encoder provided in an embodiment of the present application. Fig.13 As shown, the constant coefficient multiplication and addition module 1210 includes (NK) submodules, namely submodule 0, submodule 1, ..., submodule (NK-2), and submodule (NK-1). Among them, the coefficient corresponding to submodule 0 is the matrix θ shown in formula (13) N,K The first row of coefficients in , that is, θ 1,1 ~θ 1,N-K , the coefficient corresponding to submodule 1 is the matrix Θ shown in formula (13) N,K The coefficients of the second row in θ 2,1 ~θ 2,N-K , ..., the coefficients corresponding to the submodule (NK-2) are the matrix Θ shown in formula (13) N,K The coefficients of the (NK-1)th row in the N-K-1,1 ~θN-K-1,N-K , and the coefficients corresponding to the submodule (NK-1) are the matrix Θ shown in formula (13) N,K The coefficients of the (NK)th row in θ N-K,1 ~θ N-K,N-K .

[0199] Thus, when the data to be encoded is input to the encoder 80 with K / N beats and a parallel degree of n, it is calculated by the (NK) polynomial evaluation circuits described above and outputs (NK) target polynomials [including M(α 0 )、M(α 1 ),…,M(α N-K-2 )、M(α N-K-1 )], the encoder 80 sends the (NK) target polynomials to each submodule in the constant coefficient multiplication and addition module 1210, so that each submodule is based on the coefficient corresponding to each submodule and the (NK) target polynomials (i.e., Φ) representing the data to be encoded. N,K ), calculate the corresponding check value p. Then, the (NK) submodules obtain the corresponding (NK) check values ​​p, and the (NK) check values ​​p constitute the check sequence of the data to be encoded.

[0200] For example, the encoder 80 sends (NK) target polynomials to the submodule 0 in the constant coefficient multiplication and addition module 1210, and the submodule 0 performs the multiplication and addition of coefficients θ 1,1 ~θ 1,N-K Perform multiplication and addition operations with (NK) target polynomials to obtain the check value p N-K-1 Among them, based on Ω N,K =Θ N,K ×Φ N,K The mathematical constraints, formula (13) and formula (14), the multiplication and addition operation is specifically [θ 1,1 ×M(α 0 )+θ 1,2 ×M(α 1 )+…+θ 1,N-K-1 ×M(α N-K-2 )+θ 1,N-K ×M(α N-K-1 )].

[0201] Similarly, the encoder 80 sends the (NK) target polynomials to the submodule 1 in the constant coefficient multiplication and addition module 1210, and the submodule 1 performs the multiplication and addition of the coefficients θ 2,1 ~θ 2,N-K Perform multiplication and addition operations with (NK) target polynomials to obtain the check value p N-K-2 .

[0202] Similarly, the encoder 80 sends the (NK) target polynomials to the submodule (NK-2) in the constant coefficient multiplication and addition module 1210, and the submodule (NK-2) performs the multiplication and addition of the coefficients θ N-K-1,1 ~θ N-K-1,N-K Perform multiplication and addition operations with NK target polynomials to obtain the check value p1.

[0203] Similarly, the encoder 80 sends the (NK) target polynomials to the submodule (NK-1) in the constant coefficient multiplication and addition module 1210, and the submodule (NK-1) performs the multiplication of the coefficients θ N-K,1 ~θ N-K,N-K Perform multiplication and addition operations with NK target polynomials to obtain the check value p0.

[0204] The merging module 1220 is used to merge the data to be encoded and the check sequence of the data to be encoded, so as to obtain a codeword after the data to be encoded is encoded in a forward error correction coding manner.

[0205] Specifically, the merging module 1220 receives the check sequence of the data to be encoded calculated by the constant coefficient multiplication and addition module 1210, and receives the data to be encoded, and merges the data to be encoded and the check sequence of the data to be encoded, thereby obtaining a codeword after the data to be encoded is encoded by the forward error correction encoding method. Then, the merging module 1220 outputs a codeword including a payload and a check sequence. The payload of the codeword is the data to be encoded, and the check sequence of the codeword is the check sequence of the data to be encoded output by the constant coefficient multiplication and addition module 1210.

[0206] In this way, based on the encoder described above in the embodiment of the present application, when the encoder performs forward error correction coding on the data to be encoded input to the encoder in parallel, the feedback circuit in the encoder is decoupled from the parallelism of the data to be encoded when it is input to the encoder. Thus, in a large bandwidth scenario, when the encoder provided by the embodiment of the present application is input with high parallelism to the data to be encoded, there will be no technical problem of being unable to converge in timing. This is because the addition and multiplication operations that need to be completed by the feedback circuit in the encoder provided by the embodiment of the present application can be completed completely within one clock cycle.

[0207] However, the feedforward circuit in the encoder 80 is related to the parallelism of the data to be encoded when it is input to the encoder 80. Therefore, when the parallelism n of the data to be encoded when it is input to the encoder 80 is greater than the threshold, the feedforward circuit in the encoder 80 cannot complete the calculation of the single-beat polynomial within one clock cycle (or one beat, or one beat). The specific value of the threshold is not limited in the embodiment of the present application.

[0208] In this case, the feedforward circuit 810 of the encoder 80 described above further includes a register, which is used to control the feedforward circuit 810 to complete the calculation of the polynomial representing the n symbols of the single-beat input (i.e., the single-beat polynomial) through at least two clocks, that is, the register is used to control the feedforward circuit 810 to complete the calculation of a single-beat polynomial through at least two clocks. It should be understood that inserting a register in the feedforward circuit 810 can extend the duration of one clock cycle for the feedforward circuit 810 to complete the calculation of a single-beat polynomial. Inserting two registers in the feedforward circuit 810 can extend the duration of two clock cycles for the feedforward circuit 810 to complete the calculation of a single-beat polynomial.

[0209] In a first possible implementation, when the feedforward circuit 810 can complete the calculation of a single-beat polynomial through at least two clocks, the feedforward circuit 810 includes at least one register for delay and multiple subcircuits, the operation amount of each subcircuit in the multiple subcircuits can be executed and completed within one clock cycle, and the number of subcircuits in the feedforward circuit 810 is the number of registers for delay in the feedforward circuit 810 plus 1. For example, when the feedforward circuit 810 includes 1 register for delay, the feedforward circuit 810 includes 2 subcircuits. For another example, when the feedforward circuit 810 includes 2 registers for delay, the feedforward circuit 810 includes 3 subcircuits. Thus, through at least one register for delay in the feedforward circuit 810, the feedforward circuit 810 can complete the calculation of the single-beat polynomial within at least 2 clock cycles through the pipeline operation of at least 2 subcircuits. In addition, the last subcircuit in the pipeline operation line of the feedforward circuit 810 is connected to the feedback circuit 820 so as to output the single-beat polynomial to the feedback circuit. It should be understood that the working principle of the sub-circuit is the same as the working principle of the feedforward circuit 810 described above, and will not be described in detail.

[0210] The following describes the implementation process of the first possible implementation method by taking the case where the feedforward circuit 810 includes one register and the parallelism n of the data to be encoded input to the encoder 80 is 4 as an example. Fig.10 ,refer to Fig.14 , Fig.14 Another schematic diagram of a feedforward circuit provided in an embodiment of the present application is shown. The feedforward circuit 1400 is a feedforward circuit in which a register 1401 is inserted into the feedforward circuit 810, and the value of n is 4. The feedforward circuit 1400 includes a subcircuit 1410 and a subcircuit 1420, and the subcircuit 1420 is the last subcircuit on the pipeline of the feedforward circuit 1400, so the subcircuit 1420 is connected to the feedback circuit.

[0211] Assume that the data to be encoded includes 12 symbols, and the 12 symbols are: m 11 、m10 , m9, m8, m7, m6, m5, m4, m3, m2, m1 and m0, then Fig.14 As shown, the data to be encoded needs to be input to the feedforward circuit 1400 of the encoder through (K / n)+1 beats (ie (12 / 4)+1=4 beats).

[0212] In the first beat, the four symbols received by the feedforward circuit 1400 are m 11 、m 10 , 0, 0. Wherein, subcircuit 1410 receives m 11 、m 10 , thereby calculating the result 1a, and sending the result 1a to the sub-circuit 1420. The sub-circuit 1420 receives 0, 0, and the calculated result is actually 0 (or the sub-circuit 1420 does not receive any symbol in the first beat). It should be noted that the sub-circuit 1420 connected to the feedback circuit in the feedforward circuit 1400 does not output the result in the first beat.

[0213] In the second beat, the four symbols received by the feedforward circuit 1400 are m7, m6, m9, and m8. Among them, the subcircuit 1410 receives m7 and m6, thereby calculating the result 2a, and sends the result 2a to the subcircuit 1420. The subcircuit 1420 receives m9 and m8 and calculates the result 1b. Then the subcircuit 1420 sums the result 1b calculated in the second beat and the result 1a sent to the subcircuit 1420 by the subcircuit 1410 in the first beat, thereby obtaining the result 1 of the second beat, and outputs the result 1 to the feedback circuit. It can be seen that the result 1 is the result representing m 11 、m 10 , m9, and m8, and result 1 is the result calculated by the feedforward circuit 1400 through two clock cycles (beat 1 and beat 2). In other words, in beat 2, the sub-circuit 1420 in the feedforward circuit 1400 outputs a signal representing m to the feedback circuit. 11 、m 10 , m9, and m8 are single-shot polynomials (i.e., result 1).

[0214] Similarly, in the third beat, the four symbols received by the feedforward circuit 1400 are m3, m2, m5, and m4. Among them, the subcircuit 1410 receives m3 and m2, thereby calculating the result 3a, and sends the result 3a to the subcircuit 1420. The subcircuit 1420 receives m5 and m4, and calculates the result 2b. Then the subcircuit 1420 sums the result 2b calculated in the third beat and the result 2a sent to the subcircuit 1420 by the subcircuit 1410 in the second beat, thereby obtaining the result 2 of the third beat, and outputs the result 2 to the feedback circuit. It can be seen that the result 2 is a single-beat polynomial representing m7, m6, m5, and m4, and the result 2 is the result calculated by the feedforward circuit 1400 through two clock cycles (the second beat and the third beat). In other words, in the third beat, the sub-circuit 1420 in the feedforward circuit 1400 outputs a single-beat polynomial (ie, result 2) for representing m7, m6, m5, and m4 to the feedback circuit.

[0215] Similarly, in the fourth beat, the four symbols received by the feedforward circuit 1400 are 0, 0, m1, and m0, respectively. Among them, the subcircuit 1410 receives 0 and 0, so the calculated result is actually 0, and 0 is sent to the subcircuit 1420. The subcircuit 1420 receives m1 and m0, and calculates the result 3b. Then the subcircuit 1420 sums the result 3b calculated in the fourth beat and the result 3a sent to the subcircuit 1420 by the subcircuit 1410 in the third beat, so as to obtain the result 3 of the third beat, and outputs the result 3 to the feedback circuit. It can be seen that the result 3 is a single-beat polynomial representing m3, m2, m1, and m0, and the result 3 is the result calculated by the feedforward circuit 1400 through two clock cycles (the third beat and the fourth beat). In other words, in the fourth beat, the subcircuit 1420 in the feedforward circuit 1400 outputs the single-beat polynomial (i.e., result 3) representing m3, m2, m1, and m0 to the feedback circuit.

[0216] At this point, through 4 beats, all 12 characters in the data to be encoded are input into the feedforward circuit 1400, and the outputs representing m are output in the 2nd, 3rd and 4th beats respectively. 11 、m 10 , m9, m8, a single-shot polynomial representing m7, m6, m5, m4, and a single-shot polynomial representing m3, m2, m1, m0. Fig.14 The method of inputting the data to be encoded into the feedforward circuit 1400 shown is called a half-beat input method. Through this method, the calculation of a polynomial representing n symbols when the parallelism is n can be completed through two clock cycles (two beats).

[0217] Through the above implementation, it can be ensured that the feedforward circuit 810 of the encoder 80 completes the calculation of the single-shot polynomial through at least two clocks. That is to say, in a large bandwidth scenario, even if the parallelism input to the encoder 80 is large, the encoder 80 provided in the embodiment of the present application can complete the forward error correction coding. Figure 2 In the coding circuit shown in FIG. 1 , when the feedback loop cannot complete the data operation within one clock cycle, due to the constraint of the feedback loop in the time domain, Figure 2 The encoding circuit shown cannot insert a register in the feedback loop to extend the operating time of the feedback loop. Therefore, the current technology has a technical defect that the time domain cannot converge in the scenario of large bandwidth and high parallel input. The encoder provided in the embodiment of the present application does not have this technical defect.

[0218] In some other embodiments, the code type of RS(N+ΔN,K) is introduced. RS(N+ΔN,K) indicates that the length of the encoded codeword is N+ΔN, and the payload length is K. Accordingly, the length of the check sequence in the encoded codeword is N+ΔN-K. N, ΔN, and K are all integers, and N is greater than K.

[0219] Based on the above introduction to the RS(N,K) code type, when implementing RS(N+ΔN,K) encoding, Θ N+ΔN,K Satisfying formula (18), Φ N+ΔN,K Satisfy formula (19), and make Ω N+ΔN,K Satisfies formula (20). Where, Θ N+ΔN,K is to convert Θ shown in the above formula (13) N,K Replace N in (N+ΔN) to obtain Φ N+ΔN,K The Φ shown in the above formula (14) is N,K Substituting N in (N+ΔN) yields, and, Ω N+ΔN,K The Ω shown in the above formula (15) is NK Replace N in (N+ΔN) to obtain.

[0220] Formula (18)

[0221]

[0222] Formula (19)

[0223] Formula (20)

[0224] It can be seen that in the RS(N+ΔN,K) code type, Θ N+ΔN,K Means (N+ΔN-K) 2 The set of constant coefficients, Φ N+ΔN,KThe polynomial set representing the payload in the RS codeword, Ω N+ΔN,K represents the check sequence in the RS codeword. And, Θ N+ΔN,K , Φ N+ΔN,K and Ω N+ΔN,K Satisfy Ω N+ΔN,K =Θ N+ΔN,K ×Φ N+ΔN,K Mathematical constraints.

[0225] Thus, for the RS(N+ΔN,K) code type, that is, when the length of the codeword obtained after the data to be encoded is N+ΔN and the payload length is K after being encoded in the forward error correction coding mode, the encoder used to implement RS(N+ΔN,K) encoding includes (N+ΔN-K) polynomial evaluation circuits, and each of the (N+ΔN-K) polynomial evaluation circuits includes the feedforward circuit and feedback circuit described above. Thus, the (N+ΔN-K) polynomial evaluation circuits are used to calculate (N+ΔN-K) target polynomials representing the data to be encoded in a finite field through the feedforward circuit and feedback circuit in each polynomial evaluation circuit, that is, Φ N+ΔN,K Among them, the detailed description of the structure and working principle of the feedforward circuit, the feedback circuit, and the polynomial evaluation circuit can all be referred to the above description and will not be repeated here.

[0226] From formula (14) and formula (19), we can know that Φ N+ΔN,K Including Φ N,K , specific reference Fig.15 , Fig.15 FIG. 1 is a schematic diagram showing the relationship between a set of polynomials representing payloads under different codeword lengths provided in an embodiment of the present application. Fig.15 As shown, Φ N,K is Φ N+ΔN,K part of Φ N+ΔN,K Including Φ N,K .

[0227] Given that Φ N+ΔN,K Including Φ N,K , the (N+ΔN-K) polynomial evaluation circuits in the encoder for implementing RS(N+ΔN,K) encoding include the (NK) polynomial evaluation circuits in the encoder for implementing RS(N,K) encoding. That is, the (N+ΔN-K) polynomial evaluation circuits in the encoder for implementing RS(N+ΔN,K) encoding can reuse the (NK) polynomial evaluation circuits in the encoder for implementing RS(N,K) encoding.

[0228] refer to Fig.16 , Fig.161 shows a schematic diagram of the structure of an encoder 1600 provided in an embodiment of the present application. The encoder 1600 is an encoder that implements RS (N+ΔN, K) encoding. Fig.16 As shown, in addition to the (NK) polynomial evaluation circuits in the encoder 80 described above, the encoder 1600 also includes ΔN polynomial evaluation circuits, namely: polynomial evaluation circuit (NK), ..., and polynomial evaluation circuit (N+ΔN-K-1). The encoder 1600 also includes a constant coefficient multiplication and addition module 1610 and a merging module 1620. The detailed description of the constant coefficient multiplication and addition module 1610 and the merging module 1620 can be referred to above, and will not be repeated here.

[0229] The polynomial evaluation circuit (NK) is used to calculate the root of the generating polynomial according to the received data to be encoded with K / n beats as α N-K The target polynomial M(α N-K The polynomial evaluation circuit (N+ΔN-K-1) is used to calculate the root of the generating polynomial as α according to the K / n beats of the received data to be encoded. N+ΔN-K-1 The target polynomial M(α N+ΔN-K-1 ).

[0230] It can be seen that the polynomial evaluation circuit of (N+ΔN-K) in the encoder 1600 for implementing RS(N+ΔN,K) code type encoding includes the polynomial evaluation circuit of (NK) in the encoder 80 for implementing RS(N,K) code type encoding. Since (N+ΔN-K) / 2 is the error correction capability of the RS(N+ΔN,K) code type, and (NK) / 2 is the error correction capability of RS(N,K), the error correction capability of the RS(N+ΔN,K) code type is higher than the error correction capability of RS(N,K). Therefore, through the encoder provided by the embodiment of the present application, it is possible to implement the polynomial evaluation circuit in the encoder of the RS code type with higher error correction capability when encoding RS code types with different error correction capabilities, and the polynomial evaluation circuit in the encoder of the RS code type with lower error correction capability can be reused. That is, through the encoder design provided in the embodiment of the present application, it is possible to achieve an encoder for an RS code type with a higher error correction capability and an encoder for an RS code type with a lower error correction capability to share a common (i.e., multiplexed) polynomial evaluation circuit, thereby achieving significant savings in circuit area and circuit power consumption in actual circuit implementation.

[0231] In addition, for the RS (N + ΔN, K) code type, that is, when the codeword length obtained after the data to be encoded is encoded in the forward error correction coding mode is N + ΔN, and the payload length is K, the constant coefficient matrix preset in the constant coefficient multiplication and addition module of the encoder for implementing the RS (N + ΔN, K) encoding is the above-mentioned matrix Θ N+ΔN,K , recorded as the second constant coefficient matrix. From formula (18), we can see that the second constant coefficient matrix ΘN+ΔN,K It is a matrix of size (N+ΔN-K)×(N+ΔN-K).

[0232] From formula (13) and formula (18), we can know that Θ N+ΔN,K Including Θ N,K , specific reference Fig.17 , Fig.17 FIG. 1 is a schematic diagram showing the relationship between constant coefficient sets under different codeword lengths provided in an embodiment of the present application. Fig.17 As shown, Θ N,K is Θ N+ΔN,K part of θ N+ΔN,K Including Θ N,K .

[0233] Given Θ N+ΔN,K Including Θ N,K , a second constant coefficient matrix Θ preset in a constant coefficient multiplication and addition module in an encoder for implementing RS (N + ΔN, K) encoding N+ΔN,K , including a first constant coefficient matrix Θ preset in a constant coefficient multiplication and addition module in an encoder for implementing RS (N, K) encoding N,K That is, the second constant coefficient matrix Θ preset in the constant coefficient multiplication and addition module in the encoder for implementing RS (N + ΔN, K) encoding N+ΔN,K , the first constant coefficient matrix Θ preset in the constant coefficient multiplication and addition module in the encoder for implementing RS (N, K) coding can be reused N,K .

[0234] Combination Fig.16 ,refer to Fig.18 , Fig.18 1 shows another structural diagram of an encoder 1600 provided in an embodiment of the present application. The encoder 1600 is an encoder that implements RS (N+ΔN, K) encoding. Fig.18 As shown, the constant coefficient multiplication and addition module 1610 in the encoder 1600 includes (N+ΔN-K) submodules, namely submodule 0, submodule 1, ..., submodule (NK-2), submodule (NK-1), submodule (NK), ..., and submodule (N+ΔN-K-1). Among them, the coefficient corresponding to submodule 0 is the matrix Θ shown in formula (18) N+ΔN,K The first row of coefficients in , that is, θ 1,1 ~θ 1,N-K ~θ 1,N+ΔN-K , the coefficients corresponding to submodule 1 are the matrix Θ shown in formula (18) N+ΔN,K The coefficients of the second row in θ 2,1 ~θ 2,N-K ~θ 2,N+ΔN-K , ..., the coefficients corresponding to the submodule (NK-2) are the matrix Θ shown in formula (18)N+ΔN,K The coefficients of the (NK-1)th row in the N-K-1,1 ~θ N-K-1,N-K ~θ N-K-1,N+ΔN-K , the coefficients corresponding to the submodule (NK-1) are the matrix Θ shown in formula (18) N+ΔN,K The coefficients of the (NK)th row in θ N-K,1 ~θ N-K,N-K ~θ N-K,N+ΔN-K The coefficients corresponding to the submodule (NK) are the matrix Θ shown in formula (18) N+ΔN,K The coefficients of the (N+1-K)th row in the N+1-K,1 ~θ N+1-K,N-K ~θ N+1-K,N+ΔN-K , ..., and the coefficients corresponding to the submodule (N+ΔN-K-1) are the matrix Θ shown in formula (18) N+ΔN,K The coefficients of the (N+ΔN-K)th row in the N+ΔN-K,1 ~θ N+ΔN-K,N-K ~θ N+ΔN-K,N+ΔN-K .

[0235] Thus, when the data to be encoded, which is input to the encoder 1600 with K / N beats and a parallelism of n, is calculated by the (N+ΔN-K) polynomial evaluation circuits described above, and (N+ΔN-K) target polynomials [including M(α 0 )、M(α 1 ),…,M(α N-K-2 )、M(α N-K-1 )、M(α N-K ),…,M(α N+ΔN-K-1 )], the encoder 1600 sends the (N+ΔN-K) target polynomials to each submodule in the constant coefficient multiplication and addition module 1610, so that each submodule is encoded according to the coefficient corresponding to each submodule and the (N+ΔN-K) target polynomials (i.e., Θ N+ΔN,K ), calculate the corresponding check value p. Then, the (N+ΔN-K) submodules obtain the corresponding (N+ΔN-K) check values ​​p, and the (N+ΔN-K) check values ​​p constitute the check sequence of the data to be encoded.

[0236] For example, the encoder 1600 sends (N+ΔN-K) target polynomials to the submodule 0 in the constant coefficient multiplication and addition module 1610, and the submodule 0 performs the multiplication and addition of the coefficients (θ 1,1 ~θ 1,N-K ~θ 1,N+ΔN-K ) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p N+ΔN-K-1 Among them, based on Ω N+ΔN,K =Θ N+ΔN,K ×Φ N+ΔN,KThe mathematical constraints, formula (18) and formula (19), the multiplication and addition operation is specifically [θ 1,1 ×M(α 0 )+θ 1,2 ×M(α 1 )+…+θ 1,N-K-1 ×M(α N-K-2 )+θ 1,N-K ×M(α N-K-1 )+θ 1,N+1-K ×M(α N-K )+θ 1,N+ΔN-K ×M(α N+ΔN–K-1 )].

[0237] Similarly, the encoder 1600 sends (N+ΔN-K) target polynomials to the submodule 1 in the constant coefficient multiplication and addition module 1610, and the submodule 1 performs the multiplication and addition of the coefficients (θ 2,1 ~θ 2,N-K ~θ 2,N+ΔN-K ) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p N+ΔN-K-2 .

[0238] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials to the submodule (NK-2) in the constant coefficient multiplication and addition module 1610, and the submodule (NK-2) performs the multiplication and addition of the coefficients (θ N-K-1,1 ~θ N-K-1,N-K ~θ N-K-1,N+ΔN-K ) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p ΔN+1 .

[0239] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials to the submodule (NK-1) in the constant coefficient multiplication and addition module 1610, and the submodule (NK-1) performs the multiplication and addition of the coefficients (θ N-K,1 ~θ N-K,N-K ~θ N-K,N+ΔN-K ) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p ΔN .

[0240] Similarly, the encoder 1600 sends (N+ΔN-K) target polynomials to the submodule (NK) in the constant coefficient multiplication and addition module 1610, and the submodule (NK) performs the multiplication and addition of the coefficients (θ N+1-K,1 ~θ N+1-K,N-K ~θ N+1-K,N+ΔN-K ) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p ΔN-1 .

[0241] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials to the submodule (N+ΔN-K-1) in the constant coefficient multiplication and addition module 1610, and the submodule (N+ΔN-K-1) multiplies the coefficients (θ N+ΔN-K,1 ~θ N+ΔN-K,N-K ~θ N+ΔN-K,N+ΔN-K ) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p0.

[0242] Combination Fig.13 As can be seen from the description, the constant coefficient multiplication and addition module 1610 in the encoder implementing the RS(N+ΔN,K) code pattern includes a specific implementation circuit of the constant coefficient multiplication and addition module 1210 in the encoder implementing the RS(N,K) code pattern. For example, taking submodule 0 in the constant coefficient multiplication and addition module 1610 as an example, submodule 0 in the constant coefficient multiplication and addition module 1610 includes Fig.13 The specific implementation circuit of submodule 0 in the constant coefficient multiplication and addition module 1210 shown in FIG. 1 is used to implement the constant coefficient multiplication and addition module 1210. 1,1 ~θ 1,N-K ) for performing multiplication and addition. For another example, taking the submodule (NK-1) in the constant coefficient multiplication and addition module 1610 as an example, the submodule (NK-1) in the constant coefficient multiplication and addition module 1610 includes Fig.13 The specific implementation circuit of the submodule (NK-1) in the constant coefficient multiplication and addition module 1210 shown in FIG. 1 is used to implement the constant coefficient multiplication and addition module 1210. N-K,1 ~θ N-K,N-K ) is a circuit that performs multiplication and addition.

[0243] That is to say, the (N+ΔN-K) submodules in the constant coefficient multiplication and addition module in the encoder 1600 respectively include (NK) submodules in the constant coefficient multiplication and addition module in the encoder 80. Since the error correction capability [(N+ΔN-K) / 2] of the encoder 1600 for implementing the RS(N+ΔN,K) code type encoding is higher than the error correction capability [(NK) / 2] of the encoder 80 for implementing the RS(N,K) code type encoding, the constant coefficient multiplication and addition module 1610 in the encoder 1600 with higher error correction capability can reuse the specific implementation circuit of the constant coefficient multiplication and addition module 1210 in the encoder 80 with lower error correction capability. In other words, through the encoder provided by the embodiment of the present application, it can be realized that when encoding RS code types with different error correction capabilities, the constant coefficient multiplication and addition module in the encoder of the RS code type with higher error correction capability can reuse the constant coefficient multiplication and addition module in the encoder of the RS code type with lower error correction capability. That is, through the encoder design provided in the embodiment of the present application, it is possible to achieve an implementation circuit in which an encoder for an RS code type with a higher error correction capability and an encoder for an RS code type with a lower error correction capability share a common (i.e., multiplexed) constant coefficient multiplication and addition module, thereby achieving significant savings in circuit area and circuit power consumption in actual circuit implementation.

[0244] Furthermore, combined with Figure 15 to Figure 18 The encoder for realizing RS(N+ΔN,K) code type with higher error correction capability provided by the embodiment of the present application can reuse the circuit of the polynomial evaluation circuit and the constant coefficient multiplication and addition module in the encoder for realizing RS(N,K) code type with lower error correction capability. In this case, by realizing the encoder of RS(N+ΔN,K) code type with higher error correction capability, the encoding of RS(N,K) code type with lower error correction capability can be realized. That is, the encoder described in the embodiment of the present application can support the encoding of at least one forward error correction coding code type, and each code type in the at least one forward error correction coding code type has different error correction capabilities. Or it is understood that the encoder provided by the embodiment of the present application is a fusion encoder of forward error correction coding that can support multiple error correction capability code types.

[0245] As an example, when the encoder provided in an embodiment of the present application is an encoder for implementing the RS(N+ΔN,K) code type, the encoder supports encoding of at least one forward error correction coding code type. Wherein, each code type in the at least one forward error correction coding code type has a different error correction capability, and the error correction capability of the codeword encoded by the at least one forward error correction coding code type is less than or equal to (N+ΔN-K) / 2, that is, the error correction capability of the codeword encoded by the at least one forward error correction coding code type is less than or equal to the error correction capability of the RS(N+ΔN,K) code type.

[0246] It should be understood that when the encoding of the RS(N,K) code pattern is implemented by an encoder of the RS(N+ΔN,K) code pattern, it is only necessary to use Φ N+ΔN,K Φ ΔN,K = 0, and multiply the constant coefficients by Θ in the module N+ΔN,K Replace with Θ N,K (Or, reuse based on Θ N+ΔN,K The constant coefficient multiplication and addition module constructed is used to realize the coefficient Θ N,K The circuit module for multiplication and addition). The encoding of RS(N,K) code type can be realized in the encoder of RS(N+ΔN,K) code type. Among them, Φ ΔN,K Including [M(α N-K ),…,M(α N+ΔN-K-1 )].

[0247] As an example, when we need to let Φ ΔN,K = 0, the encoder can be switched to Fig.16 The multiplier of each polynomial evaluation circuit in the ΔN polynomial evaluation circuits shown is fed with a coefficient of 0, so that Φ can be realized. ΔN,K =0.

[0248] In order to deepen the understanding of the beneficial effects of the embodiments of the present application, the encoder provided in the embodiments of the present application is further introduced below by way of examples.

[0249] It can simultaneously support RS (N1, K1, T1, m) code type, RS (N2, K2, T2, m) code type, ..., and RS (N s , K s , T s , m) code type encoding encoder as an example, refer to Fig.19 , Fig.19 The schematic diagram of the structure of an encoder supporting multi-code fusion coding provided by an embodiment of the present application is shown. Wherein, N is the length of the codeword after forward error correction coding, K is the length of the payload in the codeword, m is used to indicate the finite field for RS coding calculation, T is the error correction capability, and T = (NK) / 2, and then NK = 2T. In addition, T1, T2, ..., T s Monotonically increasing, that is, T1 <T2<…<T s , s is an integer.

[0250] like Fig.19 As shown, the encoder 1900 includes s polynomial evaluation modules, namely a first polynomial evaluation module, a second polynomial evaluation module, ..., and an sth polynomial evaluation module.

[0251] The first polynomial evaluation module includes (N1-K1) polynomial evaluation circuits, and is used to calculate (N1-K1) (i.e., 2T1) target polynomials according to the received data. That is to say The second polynomial evaluation module includes (2T2-2T1) polynomial evaluation circuits and is used to calculate (2T2-2T1) target polynomials according to the received data. And, the sth polynomial evaluation module includes (2T s -2T s-1 ) polynomial evaluation circuits, and used to calculate (2T s -2T s-1 ) target polynomials It can be understood that the detailed description of how to calculate the target polynomial by the polynomial evaluation circuit can be referred to the above description and will not be repeated here.

[0252] The encoder 1900 further includes s constant coefficient multiplication-addition modules, namely a first constant coefficient multiplication-addition module, a second constant coefficient multiplication-addition module, ..., and an sth constant coefficient multiplication-addition module.

[0253] Among them, the constant coefficient preset in the first multiplication coefficient multiplication and addition module is: Where j1 = 1, 2, ..., (N1-K1). It should be understood that when j1 = [1, 2, ..., (N1-K1)], the constant coefficient is a coefficient matrix of (N1-K1)×(N1-K1). Furthermore, the first coefficient multiplication and addition module is used to calculate the corresponding check sequence according to the preset constant coefficients and the received (N1-K1) target polynomials. The constant coefficients preset in the second multiplication coefficient multiplication and addition module are: Where j2 = 1, 2, ..., (N2-K2). It should be understood that when j2 = [1, 2, ..., (N2-K2)], the constant coefficient is a coefficient matrix of (N2-K2)×(N2-K2). Furthermore, the second coefficient multiplication and addition module is used to calculate the corresponding check sequence according to the preset constant coefficients and the received (N2-K2) target polynomials. The constant coefficients preset in the sth multiplication and addition module are: Among them, j s =1,2,…,(N s -K s ). It should be understood that s =[1, 2, ..., (N s -K s )], constant coefficient is a (N s -K s)×(N s -K s ) coefficient matrix. Then, the sth coefficient multiplication and addition module is used to calculate the coefficient matrix according to the preset constant coefficient and the received (N s -K s ) target polynomials to obtain the corresponding check sequence

[0254] The encoder 1900 further includes a merging module 1910, which is used to merge the received check sequence and the corresponding data to be encoded to obtain an encoded codeword, and output the codeword.

[0255] Based on the above description, for the RS (N1, K1, T1, m) code type, assuming that data 1 includes K1 symbols, the encoder 1900 sends the data 1 that needs to be encoded with the RS (N1, K1, T1, m) code type to the first polynomial evaluation module in the encoder 1900 through K1 / n beats with a parallel degree n, thereby obtaining (N1-K1) (i.e., 2T1) target polynomials representing data 1 Next, encoder 1900 converts (N1-K1) target polynomials Send to the first constant coefficient multiplication and addition module to achieve (N1-K1) target polynomials and coefficient The multiplication and addition operation is performed to obtain the check sequence of data 1 with a length of (N1-K1) in, Where i = 0, 1, 2, ..., (N1-K1). Then, the encoder 1900 converts the check sequence The merge module 1910 will verify the sequence Merge with data 1 to obtain the code word of data 1 after RS ​​(N1, K1, T1, m) encoding, and output the code word.

[0256] For the RS (N2, K2, T2, m) code type, assuming that data 2 includes K2 symbols, the encoder 1900 sends the data 2 to be encoded with the RS (N2, K2, T2, m) code type to the first polynomial evaluation module and the second polynomial evaluation module through K2 / n beats with a parallel degree n. In this way, the first polynomial evaluation module can calculate and output 2 T1 target polynomials of data 2 And the second polynomial evaluation module can calculate and output the (2T2-2T1) target polynomials of data 2 Then, encoder 1900 converts 2 T2 target polynomials Send it to the second constant coefficient multiplication and addition module to achieve 2 T2 target polynomials and coefficient The multiplication and addition operation is performed to obtain the check sequence of data 2. The detailed process of the multiplication and addition operation can refer to the detailed explanation of the multiplication and addition operation in the first constant coefficient multiplication and addition module, which will not be repeated here. The merge module 1910 will verify the sequence Merge with data 2 to obtain the code word of data 2 after RS ​​(N2, K2, T2, m) encoding, and output the code word.

[0257] Similarly, for RS(N s , K s , T s , m) code type, assuming that data 3 includes K s symbols, the encoder 1900 with parallelism n will need to use RS (N s , K s , T s , m) code-coded data 3, through K s / n beats are sent to the first polynomial evaluation module, the second polynomial evaluation module, ..., and the third polynomial evaluation module, thereby obtaining the 2T of data 3 s Target polynomial Then, the encoder 1900 performs the multiplication and addition of the sth constant coefficient on the 2T s target polynomial and coefficients Perform multiplication and addition operations to obtain the check sequence of data 3 Then, the encoder 1900 verifies the sequence The merge module 1910 will verify the sequence and data 3, so as to obtain data 3 through RS(N s , K s , T s , m) the encoded codeword and output the codeword.

[0258] pass Fig.19 In the description of the example, when encoding RS code types with different error correction capabilities, the encoder for implementing RS code types with different error correction capabilities has a multiplexed circuit structure (such as Fig.19 The first polynomial evaluation module and the second polynomial evaluation module shown in the figure), therefore, the encoder provided in the embodiment of the present application can not only support RS code type encoding with different error correction capabilities, but also save the circuit area and circuit power consumption of the encoder.

[0259] The encoder provided in the present application is described above from a structural aspect. The encoding method performed by the encoder described above is described below from a method perspective.

[0260] refer to Fig. 20 , Fig. 20 A schematic diagram of a coding method provided by an embodiment of the present application is shown. The method comprises the encoder (eg Figure 8 , Fig.11 , Fig.13 , Fig.16 , Fig.18 or Fig.19 The encoder shown in Figure 1 is executed. Fig. 20 As shown, the method comprises the following steps:

[0261] S101 . Receive data to be encoded through a feedforward module with a parallelism of n symbols per beat.

[0262] Wherein, n is a positive integer.

[0263] Specifically, the detailed description of the encoder receiving the to-be-encoded data can be referred to the above description and will not be repeated here.

[0264] S102 , using a feedforward module, calculate in a finite field according to symbols in the data to be encoded received in the current beat to obtain a single-beat polynomial corresponding to the current beat.

[0265] The data to be encoded includes K symbols, K is a positive integer, and K is greater than or equal to n. Moreover, the polynomial “representing the symbols received in each beat” is the single-beat polynomial mentioned above.

[0266] Specifically, the encoder calculates the single-shot polynomial in the finite field through the feedforward module. For a detailed description, please refer to the description of calculating the single-shot polynomial above, which will not be repeated here.

[0267] S103, receiving the single-beat polynomial corresponding to the current beat output by the feedforward module through the feedback module, and calculating a second polynomial in a finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbols received in the historical beats.

[0268] Among them, the second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine the target polynomial representing the data to be encoded. Here, the first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat between the current beats in the process of the feedforward module receiving the data to be encoded. It should be noted that the feedback module of the encoder is decoupled from the input parallelism of the data to be encoded. For a detailed description, please refer to the above and will not be repeated.

[0269] Among them, the target polynomial is used to generate a check sequence of the data to be encoded, and the check sequence of the data to be encoded is used to check and correct errors in the data to be encoded. The codeword obtained after the data to be encoded is encoded in a forward error correction coding method includes the data to be encoded and the check sequence of the data to be encoded.

[0270] Specifically, the encoder receives the single-beat polynomial corresponding to the current beat output by the feedforward module through the feedback module, and calculates and outputs the second polynomial in a finite field based on the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbols received in the historical beat. For a detailed description, please refer to the detailed description of the feedback circuit above and will not be repeated here.

[0271] Furthermore, the encoder determines whether the current beat is the K / nth beat receiving the data to be encoded.

[0272] When the encoder determines that the current beat is the K / nth beat of receiving the data to be encoded, it means that the payload of a codeword has been input. In this case, the encoder determines the second polynomial calculated by the feedback module as the target polynomial representing the data to be encoded, and the encoder executes S104.

[0273] When the encoder determines that the current beat is not the K / nth beat of the data to be encoded, it means that the payload of a codeword has not been completely input. In this case, the encoder repeatedly executes S102 to S103 until the K / nth beat of the data to be encoded is received.

[0274] S104. Calculate and obtain a check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial.

[0275] Among them, the encoder calculates a detailed description of the check sequence of the data to be encoded based on the constant coefficient matrix and the target polynomial. Please refer to the detailed description of the constant coefficient multiplication and addition module above, which will not be repeated here.

[0276] S105 , combining the data to be encoded and the check sequence of the data to be encoded to obtain a codeword of the data to be encoded in a forward error correction encoding manner.

[0277] Among them, the encoder merges the data to be encoded and the check sequence of the data to be encoded to obtain a detailed description of the codeword after the data to be encoded is encoded in a forward error correction coding manner. Please refer to the detailed description of the merging module above and will not be repeated here.

[0278] In this way, the encoder provided in the embodiment of the present application can encode forward error correction code types with different error correction capabilities through the encoding method described in S101 to S105, and can also save the circuit area and circuit power consumption of the encoder.

[0279] In order to deepen the understanding of the encoder and encoding method described in the embodiments of the present application, further explanation is given below through specific examples.

[0280] Example 1 RS(528,514,7,10) pattern

[0281] The RS (528, 514, 7, 10) code type indicates that the RS codeword length is 528, the payload length in the codeword is 514, the check sequence length is (528-514) = 14 (i.e. (NK) mentioned above), the error correction capability is 7, and the finite field of RS coding calculation is GF (2 10 ).

[0282] When the encoder provided by the present application performs the encoding method described above, when the encoder performs encoding with the RS (528, 514, 7, 10) code type, the constant coefficient matrix preset in the constant coefficient multiplication and addition module in the encoder is recorded as the following matrix (3):

[0283] Matrix (3)

[0284] In this case, the 14 polynomial evaluation modules in the encoder first calculate the 14 target polynomials of the data to be encoded: [M(α 13 ), M(α 12 ),…,M(α 0 )]. Then, the constant coefficient multiplication and addition module in the encoder is [M(α 13 ), M(α 12 ),…,M(α 0 )] and the preset constant coefficient matrix (i.e., matrix (3)) to obtain the check sequence [p 13 , p 12 …, p0]. Among them, p 13 =∑θ (1，i+1) ×M(α i ), p 12 =∑θ (2，i+1) ×M(α i ),…,p0=∑θ (14，i+1) ×M(α i ), where i=1,2,…14.

[0285] Among them, [M(α 13 ), M(α 12 ),…,M(α 0 )] can be obtained according to the following formula (21) and the finite field GF(2 10 ) in the primitive polynomial x 10 +x 3 The root α of +1 is calculated as:

[0286] Formula (21)

[0287] Each coefficient in the above matrix (3) can be expressed according to the following formula (22) and the finite field GF(2 10 ) in the primitive polynomial x 10 +x 3 The root α of +1 is calculated. Wherein, formula (22) can be derived according to the above formula (13) and matrix (3), which will not be repeated here.

[0288] Formula 22

[0289] After pre-calculation, the coefficients in matrix (3) are specifically shown in the following matrix (4):

[0290] Matrix (4)

[0291] Then, the encoder calculates [M(α 13 ), M(α 12 ),…,M(α 0 )] and the coefficients shown in matrix (4), the check sequence [p 13 , p 12 …, p0]. After the encoder combines the data to be encoded and the check sequence, the codeword of the data to be encoded can be obtained after being encoded by the RS (528,514,7,10) code type.

[0292] Example 2 RS(544,514,15,10)

[0293] The RS (544, 514, 15, 10) code type indicates that the RS codeword length is 544, the payload length in the codeword is 514, the check sequence length is (544-514) = 30 (i.e. (NK) mentioned above), the error correction capability is 15, and the finite field of RS coding calculation is GF (2 10 ).

[0294] When the encoder provided by the present application performs the encoding method described above, when the encoder performs encoding with the RS (544, 514, 15, 10) code type, the constant coefficient matrix preset in the constant coefficient multiplication and addition module in the encoder is recorded as the following matrix (5):

[0295] Matrix(5)

[0296] In this case, the 30 polynomial evaluation modules in the encoder first calculate the 30 target polynomials of the data to be encoded: [M(α 29 ),…,M(α 0 )]. Then, the constant coefficient multiplication and addition module in the encoder is [M(α29 ),…,M(α 0 )] and the preset constant coefficient matrix (i.e., matrix (5)) to obtain the check sequence [p 29 , p 28 …, p0]. Among them, p 29 =∑θ (1 , i+1) ×M(α i ), p 28 =∑θ (2 , i+1) ×M(α i ),…,p0=∑θ (30 , i+1) ×M(α i ), where i=1,2,…30.

[0297] Among them, [M(α 29 ),…,M(α 0 )] can be obtained according to the following formula (23) and the finite field GF(2 10 ) in the primitive polynomial x 10 +x 3 The root α of +1 is calculated as:

[0298] Formula (23)

[0299] From formula (21) and formula (23), it can be seen that when the encoder encodes with the RS (544,514,15,10) code type, the encoder calculates [M (α 29 ),…,M(α 0 )], you can reuse [M(α 13 ),…,M(α 0 )] corresponding to 14 polynomial evaluation circuits, thereby saving circuit area and circuit power consumption.

[0300] Each coefficient in the above matrix (5) can be expressed according to the following formula (24) and the finite field GF(2 10 ) in the primitive polynomial x 10 +x 3 The root α of +1 is calculated. Wherein, formula (24) can be derived according to the above formula (13) and matrix (5), which will not be repeated here.

[0301] Formula 24

[0302] After calculation, reference Fig.21 , Fig.21The constant coefficient matrix of the RS(544,514,15,10) code type provided in the embodiment of the present application is shown. Compared with the coefficients of the RS(528,514) code type and the RS(544,514) code type in the current encoding method shown in Table 1, Fig.21 The sub-matrix ( Fig.21 ), which is the constant coefficient matrix of the RS(528,514,7,10) code type preset in the encoder provided in the embodiment of the present application. Based on this, according to the same coefficient matrix, the encoder of the RS(544,514,15,10) code type and the encoder of the RS(528,514,7,10) code type provided in the embodiment of the present application can share the circuit constructed based on the aforementioned same coefficient matrix, so that the encoder provided in the embodiment of the present application can not only realize the encoding of forward error correction code types with different error correction capabilities, but also save the circuit area and power consumption of the encoder.

[0303] Then, the encoder calculates [M(α 29 ),…,M(α 0 )], and Fig.21 The coefficients shown are used to calculate the check sequence [p 29 , p 28 …, p0]. After the encoder combines the data to be encoded and the check sequence, the codeword of the data to be encoded can be obtained after being encoded by the RS (544,514,15,10) code type.

[0304] In summary, the encoder provided in the embodiment of the present application will not have the technical defect of being unable to converge in timing under the scenario of large bandwidth and high parallelism input. Moreover, the encoder provided in the embodiment of the present application can not only encode forward error correction code types with different error correction capabilities, but also save the circuit area and power consumption of the encoder.

[0305] In order to achieve the functions described in the above method, Fig. 22 As shown, Fig. 22 2200 is a schematic diagram showing the structure of a coding device 2200 provided in an embodiment of the present application. The coding device 2200 is used to execute the above-mentioned coding method, for example, to execute Fig. 20 The encoding device 2200 may be the encoder including the feedforward module and the feedback module as described above, or the encoding device 2200 is applied to the encoder including the feedforward module and the feedback module as described above. The encoding device 2200 may include a receiving unit 2210 and a calculating unit 2220.

[0306] The receiving unit 2210 is used to receive the data to be encoded with a parallelism of n symbols per beat through the feedforward module, where n is a positive integer. The computing unit 2220 is used to calculate the single-beat polynomial corresponding to the current beat in the finite field through the feedforward module and according to the symbols in the data to be encoded received in the current beat. Here, the single-beat polynomial represents the symbol received by the feedforward module through one beat. The computing unit 2220 is also used to receive the single-beat polynomial corresponding to the current beat output by the feedforward module through the feedback module, and calculate the second polynomial in the finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbol received by the historical beat, the second polynomial represents the symbol received from the first beat to the current beat, and the second polynomial is used to determine the target polynomial representing the data to be encoded. Among them, the target polynomial is used to generate a check sequence of the data to be encoded, and the check sequence of the data to be encoded is used to check and correct the data to be encoded. The codeword obtained after the data to be encoded is encoded in a forward error correction coding method includes the data to be encoded and the check sequence of the data to be encoded. In addition, the aforementioned first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat between the current beats in the process of the feedforward module receiving the data to be encoded.

[0307] As an example, combining Fig. 20 , the receiving unit 2210 can be used to execute S101, and the computing unit 2220 can be used to execute S102 and S103.

[0308] Optionally, the data to be encoded includes K symbols, where K is a positive integer. When the length of the codeword obtained after the data to be encoded is N after being encoded in a forward error correction encoding manner, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each of which includes a feedforward module and a feedback module. The NK polynomial evaluation modules are used to calculate NK target polynomials representing the data to be encoded in a finite field through the feedforward module and the feedback module in each polynomial evaluation module.

[0309] Optionally, when the codeword length obtained after the above-mentioned data to be encoded is N+ΔN after being encoded in a forward error correction coding manner, the above-mentioned encoder includes N+ΔN-K polynomial evaluation modules, and each polynomial evaluation module includes a feedforward module and a feedback module. The N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in a finite field through the feedforward module and the feedback module in each polynomial evaluation module. In addition, the N+ΔN-K polynomial evaluation modules include the above-mentioned NK polynomial evaluation modules.

[0310] Optionally, the encoding device 2200 further includes: a determination unit 2230, which is used to determine the second polynomial as the target polynomial when determining that the current beat is the K / nth beat of receiving the data to be encoded. The calculation unit 2220 is also used to calculate the check sequence of the data to be encoded based on the constant coefficient matrix and the target polynomial. The merging unit 2240 is used to merge the data to be encoded and the check sequence of the data to be encoded to obtain the codeword of the data to be encoded in the forward error correction coding method.

[0311] As an example, combining Fig. 20 , the calculation unit 2220 can be used to execute S104, and the merging unit 2240 can be used to execute S105.

[0312] Optionally, when the codeword length obtained after the above-mentioned data to be encoded in the forward error correction coding mode is N, the above-mentioned constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK). When the codeword length after the above-mentioned data to be encoded in the forward error correction coding mode is N+ΔN, the above-mentioned constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K). The second constant coefficient matrix includes the constant first coefficient matrix.

[0313] Optionally, the encoder supports encoding of at least one forward error correction coding code type, and each code type in the at least one forward error correction coding code type has a different error correction capability.

[0314] Optionally, when the value of n is greater than a threshold, the encoding device 2200 further includes: a control unit 2250, configured to control the feedforward module to complete the calculation of a single-beat polynomial through at least two clock cycles via a register inserted in the feedforward module.

[0315] For the specific description of the above optional methods, please refer to the above method embodiments, which will not be repeated here. In addition, the explanation of any encoding device 2200 provided above and the description of the beneficial effects can refer to the above corresponding method and the embodiment introducing the encoder, which will not be repeated here.

[0316] As an example, combining Fig.12 The function implemented by the receiving unit 2210 in the encoding device 2200 can be Fig.12 The functions implemented by the computing unit 2220 can be performed by Fig.12 The polynomial evaluation circuit and constant coefficient multiplication and addition module 1210 shown in the figure are executed. The determination unit 2230 can be performed by Fig.12 The merging unit 2240 can be implemented by Fig.12 The merging module 1220 shown is executed. Fig.14 , the control unit 2250 can be Fig.14 The register of the feed-forward circuit 1400 is inserted into the execution.

[0317] Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0318] It should be noted that Fig. 22 The division of modules in the example is schematic and is only a logical function division. There may be other division methods in actual implementation. For example, two or more functions may be integrated into one processing module. The above integrated modules may be implemented in the form of hardware or software function modules.

[0319] An embodiment of the present application further provides a chip, which includes a coding circuit, and the coding circuit is used to execute the coding method as described above to achieve encoding of the data to be encoded in a forward error correction coding manner.

[0320] The present application also provides a computer program product and a computer-readable storage medium for storing the computer program product. The computer program product may include one or more program instructions, which, when executed by one or more processors, can provide the above Fig. 20 Thus, for example, reference to Fig. 20 One or more features of S101 to S105 may be undertaken by one or more instructions in the computer program product.

[0321] In some examples, such as for Fig. 20 The described encoding devices may be configured to provide various operations, functions, or actions in response to one or more program instructions stored in a computer-readable storage medium.

[0322] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When executing instructions on a computer and executing a computer, a process or function according to an embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. that contains one or more servers that can be integrated with a medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0323] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An encoder, characterized in that: include: A feedforward module, configured to receive data to be encoded with a parallelism of n symbols per beat, and, based on symbols in the data to be encoded received in a current beat, calculate a single-beat polynomial corresponding to the current beat in a finite field, wherein the single-beat polynomial represents the symbols received by the feedforward module through one beat, and n is a positive integer; A feedback module is used to receive the single-beat polynomial corresponding to the current beat output by the feedforward module, and calculate a second polynomial in the finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbols received by the historical beats, wherein the second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine a target polynomial representing the data to be encoded; wherein the target polynomial is used to generate a check sequence for the data to be encoded, and the check sequence for the data to be encoded is used to check and correct the data to be encoded, and the codeword obtained after the data to be encoded is encoded in a forward error correction coding manner includes the data to be encoded and the check sequence for the data to be encoded; the first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat located between the current beats during the process of the feedforward module receiving the data to be encoded.

2. The encoder according to claim 1, characterized in that The data to be encoded includes K symbols, K is a positive integer; when the length of the codeword obtained after the data to be encoded in the forward error correction encoding mode is N, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each polynomial evaluation module includes the feedforward module and the feedback module; The NK polynomial evaluation modules are used to calculate NK target polynomials representing the data to be encoded in the finite field through a feedforward module and a feedback module in each polynomial evaluation module.

3. The encoder according to claim 2, characterized in that When the length of the codeword obtained after the data to be encoded in the forward error correction encoding mode is N+ΔN, the encoder includes N+ΔN-K polynomial evaluation modules, each polynomial evaluation module includes the feedforward module and the feedback module; The N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in the finite field through the feedforward module and the feedback module in each polynomial evaluation module, and the N+ΔN-K polynomial evaluation modules include the NK polynomial evaluation modules.

4. The encoder according to any one of claims 1 to 3, characterized in that The encoder further comprises: A constant coefficient multiplication and addition module, used for calculating the check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial; The merging module is used to merge the data to be encoded and the check sequence of the data to be encoded to obtain a codeword after the data to be encoded is encoded in a forward error correction encoding manner.

5. The encoder according to claim 4, characterized in that When the length of the codeword obtained after the data to be encoded in the forward error correction encoding method is N, the constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK); When the codeword length of the data to be encoded after being encoded in a forward error correction coding manner is N+ΔN, the constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K), and the second constant coefficient matrix includes the first constant coefficient matrix.

6. The encoder according to any one of claims 1 to 5, characterized in that: The encoder supports encoding of at least one forward error correction encoding code type, each of the at least one forward error correction encoding code type having a different error correction capability.

7. The encoder according to any one of claims 1 to 6, characterized in that: When the value of n is greater than a threshold, the feedforward module includes a register; The register is used to control the feedforward module to complete the calculation of a single-beat polynomial through at least two clock cycles.

8. A coding method, characterized in that: The method is applied to an encoder, the encoder includes a feedforward module and a feedback module, and the method includes: Receiving the data to be encoded with a parallelism of n symbols per beat through the feedforward module, and calculating a single-beat polynomial corresponding to the current beat in a finite field according to the symbols in the data to be encoded received in the current beat, wherein the single-beat polynomial represents the symbols received by the feedforward module through one beat, and n is a positive integer; The single-beat polynomial corresponding to the current beat output by the feedforward module is received through the feedback module, and a second polynomial is calculated in the finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbols received by the historical beats, wherein the second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine a target polynomial representing the data to be encoded; wherein the target polynomial is used to generate a check sequence for the data to be encoded, and the check sequence for the data to be encoded is used to check and correct the data to be encoded, and the codeword obtained after the data to be encoded is encoded in a forward error correction coding manner includes the data to be encoded and the check sequence for the data to be encoded; the first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat located between the current beats in the process of the feedforward module receiving the data to be encoded.

9. The method according to claim 8, characterized in that The data to be encoded includes K symbols, K is a positive integer; when the codeword length obtained after the data to be encoded in a forward error correction encoding manner is N, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each polynomial evaluation module includes the feedforward module and the feedback module; the NK polynomial evaluation modules are used to calculate NK target polynomials representing the data to be encoded in the finite field through the feedforward module and the feedback module in each polynomial evaluation module.

10. The method according to claim 9, characterized in that When the codeword length obtained after the data to be encoded in a forward error correction coding manner is N+ΔN, the encoder includes N+ΔN-K polynomial evaluation modules, each of which includes the feedforward module and the feedback module; the N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in the finite field through the feedforward module and the feedback module in each polynomial evaluation module, and the N+ΔN-K polynomial evaluation modules include the NK polynomial evaluation modules.

11. The method according to any one of claims 8 to 10, characterized in that The method further comprises: When it is determined that the current beat is the K / nth beat of receiving the data to be encoded, determining the second polynomial as the target polynomial; Calculate and obtain a check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial; The data to be encoded and the check sequence of the data to be encoded are combined to obtain a codeword of the data to be encoded in a forward error correction encoding manner.

12. The method according to claim 11, characterized in that When the length of the codeword obtained after the data to be encoded in the forward error correction encoding method is N, the constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK); When the codeword length of the data to be encoded after being encoded in a forward error correction coding manner is N+ΔN, the constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K), and the second constant coefficient matrix includes the first constant coefficient matrix.

13. The encoding method according to any one of claims 8 to 12, characterized in that: The encoder supports encoding of at least one forward error correction encoding code type, each of the at least one forward error correction encoding code type having a different error correction capability.

14. The method according to any one of claims 8 to 13, characterized in that When the value of n is greater than a threshold, the method further includes: By means of the register inserted in the feedforward module, the feedforward module is controlled to complete the calculation of a single-beat polynomial through at least two clock cycles.

15. A chip, characterized in that: The chip comprises a coding circuit, and the coding circuit is used to execute the method according to any one of claims 8 to 14, so as to realize encoding of the data to be encoded in a forward error correction coding manner.

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