Field effect transistor based on combined regulation of components and gate voltage and preparation method thereof

Abstract

The field effect transistor based on the combined regulation of components and gate voltage of the present invention and the preparation method thereof, on the intrinsic low-resistance silicon substrate is a silicon dioxide layer, on the silicon dioxide layer are source and drain metal electrodes, the source and drain electrodes are metal composite electrodes, including chromium electrodes and gold electrodes, the bottom layer of the source and drain electrode channel filling is a bismuth selenium oxide nanosheet, on the bismuth selenium oxide nanosheet are black arsenic phosphorus nanosheets and top gate bismuth selenium oxide nanosheet dielectric layers, the source, drain electrodes and gate electrodes are connected to corresponding lead electrodes for connecting to external test circuits. The field effect transistor based on the combined regulation of components and gate voltage of the present invention and the preparation method thereof, through bismuth selenium oxide nanosheet encapsulation, has the function of adjusting the components of black arsenic phosphorus and the top gate voltage to optimize the photoelectric performance of the device in the visible light, near infrared and mid-wave infrared ranges.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a field effect transistor based on combined regulation of components and gate voltage and a preparation method thereof. Background Art

[0002] The wide application of field effect transistors in remote sensing, target recognition, gas sensing, imaging, free space optical communication and other important fields, the high performance demand for field effect transistors, especially the demand for broadband room temperature photodetection, has attracted great interest from researchers. Among them, two-dimensional semiconductor materials, including various transition metal dichalcogenides and materials such as black phosphorus, have been widely used in photonic and electronic applications. Most semiconductors, such as molybdenum disulfide and tungsten diselenide, have band gaps close to or greater than 1 eV, which limits their optical applications to the visible, near-infrared and mid-wave infrared spectral range. Black phosphorus has a band gap of 0.33 eV in thin film (>10 layers) or bulk form, which can cover the near-infrared and part of the mid-wave infrared (3-5μm). Various studies on ultraviolet, visible, near-infrared and mid-wave infrared (up to 3.4 μm) have been reported in the past few years, showing the potential of black phosphorus in broadband photoelectric applications. Extending the operating range of black phosphorus detectors to longer wavelengths will significantly improve their optical functions in various applications, such as thermal imaging and sensing. Currently, the most commonly used material for photodetector applications in the mid-wave infrared is mercury cadmium telluride. It is a popular choice due to its tunable bandgap by controlling its composition, as well as its high absorption in the mid-wave infrared. However, in addition to its toxicity, its bulk nature makes it challenging to integrate with other optical structures and components.

[0003] In addition, given that layered transition metal oxides such as molybdenum trioxide, vanadium pentoxide, and tungsten trioxide may suffer from current leakage caused by neutral oxygen vacancies in the oxides, it is also very important to find new high-k dielectrics with atomically smooth surfaces, no dangling bonds, and high breakdown field strength to achieve stronger gate control and lower operating voltage. Summary of the invention

[0004] The first object of the present invention is to provide a field effect transistor based on the joint regulation of components and gate voltage in order to solve the problems in the prior art.

[0005] To this end, the above-mentioned purpose of the present invention is achieved through the following technical solutions:

[0006] The field effect transistor based on the joint regulation of components and gate voltage has the following structure: a silicon dioxide layer is on the intrinsic low-resistance silicon substrate, source and drain metal electrodes are on the silicon dioxide layer, the source and drain electrodes are metal composite electrodes, including chromium electrodes and gold electrodes, the bottom layer of the source and drain electrode channels is filled with bismuth selenium oxide nanosheets, black arsenic phosphorus nanosheets and top gate bismuth selenium oxide nanosheet dielectric layers are on the bismuth selenium oxide nanosheets, the source, drain electrodes and gate electrodes are connected to corresponding lead electrodes for connecting to an external test circuit.

[0007] While adopting the above technical solutions, the present invention may also adopt or combine the following technical solutions:

[0008] As a preferred technical solution of the present invention: the resistivity of the intrinsic low-resistance silicon substrate is 0.001-0.005Ω·cm, and the thickness is 500 μm;

[0009] The thickness of the silicon dioxide layer is 300 nm;

[0010] The thickness of the bismuth selenium oxygen nanosheet is 15 nm;

[0011] The thickness of the black arsenic phosphorus nanosheet is 37 nm;

[0012] The thickness of the top gate bismuth selenium oxygen nanosheet is 20 nm.

[0013] As a preferred technical solution of the present invention: the source, drain electrodes and gate electrode are chromium and gold composite electrodes, the lower metal is chromium, which serves as an adhesion layer with a thickness of 5 nm, the upper metal is gold with a thickness of 50 nm, the overall size of the source and drain electrodes is 200μm×100μm, and the overall size of the gate electrode is 100μm×100μm; the lead electrode has a thickness of 200~400 nm.

[0014] As a preferred technical solution of the present invention: top gate voltage regulation is achieved at room temperature.

[0015] As the preferred technical solution of the present invention: to realize black arsenic phosphorus nanosheets b-As with different components at room temperature x P 1-x Infrared response, where x=0.2 / 0.3 / 0.4 / 0.5.

[0016] As a preferred technical solution of the present invention: the band gap of black arsenic phosphorus nanosheets is adjustable, the arsenic concentration is 83%, the band gap is ~0.12eV, and it has good responsiveness to mid-wave infrared light.

[0017] As a preferred technical solution of the present invention: the transistor has high performance detection of visible light, near infrared and medium-wave infrared, the laser is focused through the optical path, and the input control signal enables the mechanical shutter to realize data stream transmission. The transistor acts as a signal receiver to transmit the target data stream, converts the optical signal into an electrical signal, and the read signal is collected by a preamplifier, a phase-locked amplifier and an oscilloscope, and finally decoded on the computer side to realize photocurrent collection, and the response rate, external quantum efficiency, equivalent noise power and normalized detection rate are evaluated.

[0018] As a preferred technical solution of the present invention: the transistor has high performance detection of visible light, near infrared and medium-wave infrared, the laser is focused through the optical path, and the input control signal enables the mechanical shutter to realize data stream transmission. The transistor acts as a signal receiver to transmit the target data stream, converts the optical signal into an electrical signal, and the read signal is collected by a preamplifier, a phase-locked amplifier and an oscilloscope, and finally decoded on the computer side to realize photocurrent collection, and the response rate, external quantum efficiency, equivalent noise power and normalized detection rate are evaluated.

[0019] The second object of the present invention is to provide a method for preparing a field effect transistor based on the combined regulation of components and gate voltage in order to address the problems in the prior art.

[0020] To this end, the above-mentioned purpose of the present invention is achieved through the following technical solutions:

[0021] A method for preparing a field effect transistor based on the combined regulation of components and gate voltage comprises the following steps:

[0022] Step 1: First, the surface of the silicon substrate covered with silicon dioxide is ultrasonically cleaned using acetone, isopropanol, ethanol, and deionized water, and the substrate is cut into 0.8 cm × 0.8 cm samples using precision cutting technology;

[0023] Step 2: Use hot plate baking and glue coating machine to make the photoresist 5350 evenly adhere to the above substrate;

[0024] Step 3, preparing the pre-designed source and drain electrodes by combining UV lithography, electron beam evaporation and traditional lift-off process;

[0025] Step 4: Using the transfer platform micro-area positioning method and dry transfer technology, the bottom bismuth selenide nanocarbon is mechanically peeled off using blue adhesive tape, and then transferred to the source and drain electrode channels for numbering and positioning marking;

[0026] Step 5: Using the transfer platform micro-area positioning method and dry transfer technology, the black arsenic phosphorus is mechanically peeled off using blue adhesive tape, and then transferred to the source and drain electrodes for numbering and positioning marking;

[0027] Step 6: Through the transfer platform micro-area positioning method, using dry transfer technology, use blue adhesive tape to mechanically peel off the top layer of bismuth selenium oxygen sodium, and then use it as the encapsulation layer and top gate dielectric layer of black arsenic phosphide for numbering and positioning marking;

[0028] Step 7: Through the transfer platform micro-area positioning method, using dry transfer technology, use blue adhesive tape to mechanically peel off the top layer of bismuth selenium oxygen, and then use it as the encapsulation layer and top gate dielectric layer of the black arsenic phosphorus nanosheets for numbering and positioning marking;

[0029] Step 8: Prepare a gold electrode on the silicon substrate in advance, then use a probe to gently lift up one end of the engraved electrode with the help of a microscope platform, and then transfer the lifted gold electrode to the top-gate bismuth selenium oxygen nanosheet;

[0030] Step nine, attaching the black arsenic phosphorus field effect transistor with regulation capability to the PCB base, wiring, and packaging to prepare a detection device with a composite structure, which is used to achieve ultra-wideband detection in the visible light near infrared and mid-wave infrared regions at room temperature;

[0031] Among them, in step 4, step 5 and step 6, the microscopic morphology of bismuth selenium oxygen and black arsenic phosphorus samples is characterized by using atomic force microscopy, scanning electron microscopy and energy dispersive X-ray spectroscopy.

[0032] Compared with the prior art, the field effect transistor based on the joint regulation of component and gate voltage and the preparation method of the present invention have the following beneficial effects: through bismuth selenium oxide nanosheet encapsulation, the black arsenic phosphorus field effect transistor with the joint regulation of component and gate voltage and bismuth selenium oxide encapsulation is realized, the high dielectric constant of the top gate bismuth selenium oxide dielectric layer is utilized to enhance the gate control and reduce the operating voltage, and the optoelectronic performance of the device in the visible light, near infrared and mid-wave infrared ranges is optimized by adjusting the component of black arsenic phosphorus and the top gate voltage, thereby achieving low power consumption, strong control capability, high response rate and wide spectrum detection capability; at the same time, the mature device manufacturing process and simplified device structure are conducive to the realization of integration and complex applications, and expand the application potential of innovative semiconductor technology.

[0033] The field effect transistor and preparation method based on the combined regulation of components and gate voltage of the present invention adopts a black arsenic phosphorus material with high carrier mobility, high response rate and narrow band gap grown by chemical vapor deposition as a photosensitive conductive channel, and its band gap can be adjusted by different components (b-As x P 1-x, x=0.2 / 0.3 / 0.4 / 0.5) to adjust (0.22 eV~0.28 eV), and through the transfer platform micro-area positioning method, the black arsenic phosphorus nanosheet is obtained by mechanical stripping and dry transfer technology; the high dielectric constant material bismuth selenium oxide dielectric layer is used for top gate regulation, which can provide an atomic-level smooth surface without dangling bonds. It can be used in two-dimensional optoelectronics to promote high carrier mobility, enhance gate control and reduce operating voltage to solve such key problems in the development of field effect transistors. The gold electrode is prepared on the silicon substrate in advance, and then the probe is used to gently lift along one end of the engraved electrode with the help of a microscope platform, and then the lifted gold electrode is transferred to the top gate bismuth selenium oxide nanosheet; through this method, the contact surface between the gold electrode and the bismuth selenium oxide nanosheet is relatively good, which effectively avoids the contamination or surface defects that may be caused by the photolithography gate electrode and improves the gate control effect. The black arsenic phosphorus field effect transistor process is simple and cost-effective. Under the joint regulation of composition and gate voltage, the response rate is high, the external quantum efficiency is high, the equivalent noise power and the normalized detection rate are high, and visible light, near-infrared and medium-wave infrared detection can be achieved at room temperature, showing that mature device manufacturing technology and simplified device structure are conducive to the realization of integration and complex applications, and expand the application potential of innovative semiconductor technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a front view schematic diagram of the field effect transistor structure based on the joint regulation of components and gate voltage of the present invention;

[0035] Figure 2 It is a schematic top view of the field effect transistor structure based on the combined regulation of components and gate voltage of the present invention;

[0036] Figure 3 The transfer characteristic curve of the top gate regulation of the field effect transistor based on the combined regulation of the composition and the gate voltage of the present invention;

[0037] Figure 4 The black arsenic phosphorus nanosheets b-As of the present invention are different components. x P 1-x , infrared absorption spectra of x=0.2 / 0.3 / 0.4 / 0.5;

[0038] Figure 5 The photocurrent response magnitudes of the black arsenic phosphorus field effect transistors with different components under different bias voltages (-1 V and 1 V) and different gate voltages (-5 V, 0 V and 5 V) of the present invention;

[0039] Figure 6 The photocurrent response size of the black arsenic phosphorus field effect transistor with different components at different wavelengths of the present invention;

[0040] Figure 7In order to evaluate the field effect transistor of the present invention based on the combined regulation of components and gate voltage at different frequencies (10~10 4 Noise current spectrum at Hz;

[0041] Figure 8 To evaluate the noise current calculation size of the field effect transistor based on the combined regulation of components and gate voltage of the present invention;

[0042] Fig. 9 The photocurrent response waveform diagram of the field effect transistor based on the combined regulation of components and gate voltage at 520 nm, 638 nm, 940 nm, 1064 nm, 1310 nm, 1550 nm and 1650 nm of the present invention;

[0043] Fig.10 To evaluate the response rate, external quantum efficiency, equivalent noise power and normalized detection rate of the field effect transistor based on the combined regulation of composition and gate voltage of the present invention;

[0044] In the attached figure, 1 is a low-resistance silicon substrate, 2 is a silicon dioxide layer, 3 is a chromium electrode, 4 is a gold electrode, 5 is a bismuth selenium oxide nanosheet, 6 is a black arsenic phosphorus nanosheet, 7 is a top-gate bismuth selenium oxide nanosheet, 8 is a source electrode, 9 is a drain electrode, and 10 is a gate electrode. DETAILED DESCRIPTION

[0045] The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

[0046] The present invention discloses a field effect transistor based on the combined regulation of components and gate voltage and a preparation method thereof. The device preparation step first uses ultraviolet lithography technology and electron beam evaporation technology to manufacture the source and drain electrodes, and then transfers the mechanically peeled bismuth selenium oxide nanosheets to the channel to fill and reduce scattering, thereby improving the electrical performance of the device. Afterwards, the black arsenic phosphorus nanosheets are transferred to the source and drain electrodes, and the bismuth selenium oxide nanosheets are transferred as the encapsulation layer and the top gate dielectric layer for regulation. The top gate electrode is prepared by a probe-assisted gold electrode transfer method to avoid the pollution caused by the traditional photolithography method for making the gate electrode. Finally, the preparation of the black arsenic phosphorus field effect transistor is completed by ultrasonic lead and other processes. The black arsenic phosphorus field effect transistor of the present invention can optimize the photoelectric performance of the device in the visible light, near infrared and mid-wave infrared range by adjusting the components of black arsenic phosphorus and the top gate voltage. In addition, the contamination of the photosensitive material in the process is strictly avoided during the preparation process of the present invention. The high dielectric constant of the top gate bismuth selenium oxide dielectric layer enhances gate control and reduces the operating voltage. The advantages of the present invention include low power consumption, strong control capability, high response rate and wide spectrum detection capability. At the same time, mature device manufacturing processes and simplified device structures facilitate the realization of integrated and complex applications, expanding the application potential of innovative semiconductor technologies.

[0047] A field effect transistor based on the combined regulation of components and gate voltage, wherein the detector structure is a silicon dioxide layer 2 on an intrinsic low-resistance silicon substrate 1, source and drain metal electrodes on the silicon dioxide layer 2, the metal electrodes comprising a chromium electrode 3 and a gold electrode 4, the source and drain electrode channels are filled with a bottom layer of bismuth selenium oxygen nanosheet 5, on which are black arsenic phosphorus nanosheet 6 material and a top gate bismuth selenium oxygen nanosheet 7 dielectric layer, the source electrode 8, the drain electrode 9 and the gate electrode 10 are connected to corresponding lead electrodes for connecting to an external test circuit.

[0048] The present invention relates to a field effect transistor based on the joint regulation of components and gate voltage, and its preparation method and performance research. The field effect transistor optimizes the photoelectric performance of the device in the visible light, near infrared and mid-wave infrared range by adjusting the components of black arsenic phosphorus and the top gate voltage. Combined with micro-nano processing technology manufacturing and metal transfer methods, low power consumption, strong control capability, high response rate and wide spectrum detection capability are achieved. At the same time, mature device manufacturing technology and simplified device structure are conducive to the realization of integration and complex applications, expanding the application potential of innovative semiconductor technology.

[0049] In view of the problems in the prior art, a field effect transistor based on the joint regulation of components and gate voltage and a preparation method thereof are provided. To this end, the above-mentioned purpose of the present invention is achieved through the following technical scheme: The above-mentioned purpose of the present invention will be achieved through the following technical scheme: A field effect transistor based on the joint regulation of components and gate voltage, a silicon dioxide layer 2 is on an intrinsic low-resistance silicon substrate 1, a source and drain metal electrode is on the silicon dioxide layer 2, the metal electrode includes a chromium electrode 3 and a gold electrode 4, the source and drain electrode channel filling is a bottom layer of bismuth selenium oxygen nanosheet 5, on which is a black arsenic phosphorus nanosheet 6 material and a top gate bismuth selenium oxygen nanosheet 7 dielectric layer, a source electrode 8, a drain electrode 9 and a gate electrode 10 are connected to corresponding lead electrodes for connecting an external test circuit.

[0050] The intrinsic low-resistance silicon substrate has a resistivity of 0.001-0.005 Ω·cm and a thickness of 500 μm; a silicon dioxide layer 2 covering it has a thickness of 300 nm.

[0051] As a preferred technical solution of the present invention: the bottom bismuth selenium oxygen nanosheet 5 has a thickness of 15 nm; the black arsenic phosphorus nanosheet 6 has a thickness of 37 nm; and the top gate bismuth selenium oxygen nanosheet 7 has a thickness of 20 nm.

[0052] As a preferred technical solution of the present invention: the source, drain and gate electrodes are chromium and gold composite electrodes, the lower metal is chromium, which serves as an adhesion layer with a thickness of 5 nm, the upper metal is gold with a thickness of 50 nm, the overall size of the source and drain electrodes is 200 μm×100 μm, and the overall size of the gate electrode is 100 μm×100 μm; the lead electrode has a thickness of 200~400 nm.

[0053] In view of the problems in the prior art, a field effect transistor based on the joint regulation of components and gate voltage and a method for preparing the same are provided. To this end, the above-mentioned object of the present invention is achieved through the following technical solution: The above-mentioned object of the present invention is achieved through the following technical solution.

[0054] Step 1: First, the surface of the silicon substrate covered with silicon dioxide is ultrasonically cleaned using acetone, isopropanol, ethanol, and deionized water, and the substrate is cut into 0.8 cm × 0.8 cm samples using precision cutting technology;

[0055] Step 2: Use hot plate baking and glue coating machine to make the photoresist 5350 evenly adhere to the above substrate;

[0056] Step 3, preparing the pre-designed source and drain electrodes by combining UV lithography, electron beam evaporation and traditional lift-off process;

[0057] Step 4: Using the transfer platform micro-area positioning method and dry transfer technology, the bottom bismuth selenide nanocarbon is mechanically peeled off using blue adhesive tape, and then transferred to the source and drain electrode channels for numbering and positioning marking;

[0058] Step 5: Using the transfer platform micro-area positioning method and dry transfer technology, the black arsenic phosphorus is mechanically peeled off using blue adhesive tape, and then transferred to the source and drain electrodes for numbering and positioning marking;

[0059] Step 6: Through the transfer platform micro-area positioning method, using dry transfer technology, use blue adhesive tape to mechanically peel off the top layer of bismuth selenium oxygen sodium, and then use it as the encapsulation layer and top gate dielectric layer of black arsenic phosphide for numbering and positioning marking;

[0060] Step 7: Through the transfer platform micro-area positioning method, using dry transfer technology, use blue adhesive tape to mechanically peel off the top layer of bismuth selenium oxygen, and then use it as the encapsulation layer and top gate dielectric layer of the black arsenic phosphorus nanosheets for numbering and positioning marking;

[0061] Step 8: Prepare a gold electrode on the silicon substrate in advance, then use a probe to gently lift up one end of the engraved electrode with the help of a microscope platform, and then transfer the lifted gold electrode to the top-gate bismuth selenium oxygen nanosheet;

[0062] Step nine, attach the black arsenic phosphide field effect transistor with regulation capability to the PCB base, complete the lead and packaging to prepare a composite structure detection device for ultra-wideband detection in the visible light near-infrared and mid-wave infrared regions at room temperature.

[0063] Among them, in steps four, five and six, the microscopic morphology of bismuth selenium oxygen and black arsenic phosphorus samples is characterized by atomic force microscopy, scanning electron microscopy and energy dispersive X-ray spectroscopy.

[0064] A field effect transistor based on the joint regulation of components and gate voltage, which realizes top gate voltage regulation at room temperature.

[0065] Provided is a field effect transistor based on the joint regulation of components and gate voltage and a method for preparing the same. To this end, the above-mentioned object of the present invention is achieved by the following technical scheme: black arsenic phosphorus nanosheets (b-As) of different components are achieved at room temperature. x P 1-x , infrared response of x=0.2 / 0.3 / 0.4 / 0.5).

[0066] In the present invention, the band gap of black arsenic phosphorus alloys of different components synthesized from black arsenic phosphorus nanosheets is adjustable and can be reduced to ~0.12eV, the arsenic concentration is 83%, and it has good responsiveness to mid-wave infrared light.

[0067] In the present invention, the bismuth selenium oxide single crystal in the bismuth selenium oxide nanosheet has a typical centimeter-scale size. By utilizing its van der Waals layered structure and small cleavage energy, it can be effectively peeled into atomically flat nanosheets as thin as a single layer. The bismuth selenium oxide nanosheet serves as the encapsulation layer and gate dielectric of the two-dimensional semiconductor. Its high dielectric constant value allows strong gate control of carriers and reduces scattering in the packaged device.

[0068] A field effect transistor based on the joint regulation of components and gate voltage and a preparation method thereof in the present invention are used for high-performance detection of visible light, near-infrared and medium-wave infrared. The laser is focused through the optical path, and a control signal is input to enable a mechanical shutter to realize data stream transmission. The field effect transistor based on the joint regulation of components and gate voltage is used as a signal receiver to transmit the target data stream, convert the optical signal into an electrical signal, and the preamplifier, phase-locked amplifier and oscilloscope collect and read the signal, which is finally decoded on the computer side to realize photocurrent collection, and key performance parameters such as response rate, external quantum efficiency, equivalent noise power and normalized detection rate are evaluated.

[0069] The specific preparation and testing process is as follows:

[0070] Step 1: First, the surface of the silicon substrate covered with silicon dioxide is ultrasonically cleaned using acetone, isopropanol, ethanol, and deionized water, and the substrate is cut into 0.8 cm × 0.8 cm samples using precision cutting technology;

[0071] Step 2: Use hot plate baking and glue coating machine to make the photoresist 5350 evenly adhere to the above substrate;

[0072] Step 3, preparing the pre-designed source and drain electrodes by combining UV lithography, electron beam evaporation and traditional lift-off process;

[0073] Step 4: Using the transfer platform micro-area positioning method and dry transfer technology, the bottom bismuth selenide nanocarbon is mechanically peeled off using blue adhesive tape, and then transferred to the source and drain electrode channels for numbering and positioning marking;

[0074] Step 5: Using the transfer platform micro-area positioning method and dry transfer technology, the black arsenic phosphorus is mechanically peeled off using blue adhesive tape, and then transferred to the source and drain electrodes for numbering and positioning marking;

[0075] Step 6: Through the transfer platform micro-area positioning method, using dry transfer technology, use blue adhesive tape to mechanically peel off the top layer of bismuth selenium oxygen sodium, and then use it as the encapsulation layer and top gate dielectric layer of black arsenic phosphide for numbering and positioning marking;

[0076] Step 7: Through the transfer platform micro-area positioning method, using dry transfer technology, use blue adhesive tape to mechanically peel off the top layer of bismuth selenium oxygen, and then use it as the encapsulation layer and top gate dielectric layer of the black arsenic phosphorus nanosheets for numbering and positioning marking;

[0077] Step 8: Prepare a gold electrode on the silicon substrate in advance, then use a probe to gently lift up one end of the engraved electrode with the help of a microscope platform, and then transfer the lifted gold electrode to the top-gate bismuth selenium oxygen nanosheet;

[0078] Step nine, attach the black arsenic phosphide field effect transistor with regulation capability to the PCB base, complete the lead and packaging to prepare a composite structure detection device for ultra-wideband detection in the visible light near-infrared and mid-wave infrared regions at room temperature.

[0079] Among them, in step 4, step 5 and step 6, the microscopic morphology of bismuth selenium oxygen and black arsenic phosphorus samples is characterized by using atomic force microscopy, scanning electron microscopy and energy dispersive X-ray spectroscopy.

[0080] The technical solution of the present invention has the following innovative advantages:

[0081] 1. Black arsenic phosphorus material with high carrier mobility, high response rate and narrow band gap grown by chemical vapor deposition is used as the photosensitive conductive channel. The band gap can be changed by different components (b-As x P 1-x , x=0.2 / 0.3 / 0.4 / 0.5) were adjusted (0.22 eV~0.28 eV), and black arsenic phosphorus nanosheets were obtained by the transfer platform micro-area positioning method using mechanical exfoliation and dry transfer technology.

[0082] 2. The use of high dielectric constant material bismuth selenide oxide dielectric layer for top gate regulation can provide an atomically smooth surface without dangling bonds. Its use in two-dimensional optoelectronics can promote high carrier mobility, enhance gate control and reduce operating voltage to solve such key problems in the development of field effect transistors.

[0083] 3. Prepare a gold electrode on the silicon substrate in advance, then use a probe on the microscope platform to gently lift up one end of the engraved electrode, and then transfer the lifted gold electrode to the top gate bismuth selenium oxide nanosheet; through this method, the contact surface between the gold electrode and the bismuth selenium oxide nanosheet is relatively good, which effectively avoids the contamination or surface defects that may be caused by the photolithography gate electrode, and improves the gate voltage control effect.

[0084] 4. The process of the field effect transistor based on the joint regulation of components and gate voltage of the present invention is simple and cost-effective. Under the joint regulation of components and gate voltage, the response rate is high, the external quantum efficiency is high, the equivalent noise power and the normalized detection rate are high, and the visible light near infrared and mid-wave infrared detection at room temperature are realized, showing that the mature device manufacturing process and simplified device structure are conducive to the realization of integration and complex applications, and expand the application potential of innovative semiconductor technology.

[0085] Example 1

[0086] The thickness of the silicon substrate covered with silicon oxide is 500 μm; the thickness of the bottom bismuth selenium oxide nanosheet is 15 nm, the thickness of the black arsenic phosphorus nanosheet is 37 nm, and the thickness of the top gate bismuth selenium oxide nanosheet is 20 nm; the overall size of the source and drain electrodes is 200 μm×100 μm, and the overall size of the gate electrode is 100 μm×100 μm; the lead electrode has a thickness of 200~400 nm; the source, drain and gate electrodes are connected to the corresponding lead electrodes for external test circuits. The front view and top view of the black arsenic phosphorus field effect transistor are shown in the figure. Figure 1 and Figure 2 As shown, the gold electrode prepared in advance on the silicon substrate is gently lifted up along one end of the engraved electrode using a probe with the help of a microscope platform, and then the lifted gold electrode is transferred to the top gate bismuth selenium oxygen nanosheet to achieve better contact, avoiding contamination or surface defects that may be caused by the photolithographic gate electrode. Figure 3 The top gate voltage control effect diagram is shown when the source-drain voltage is -1 volt, which shows the typical P-type semiconductor behavior of black arsenic phosphide and the dynamic gate voltage regulation in a large range (-12 V~12 V), proving the feasibility and completeness of the black arsenic phosphide field effect transistor strategy we constructed.

[0087] Example 2

[0088] The thickness of the silicon substrate covered with silicon oxide is 500 μm; the thickness of the bottom bismuth selenium oxide nanosheet is 15 nm, the thickness of the black arsenic phosphorus nanosheet is 37 nm, and the thickness of the top gate bismuth selenium oxide nanosheet is 20 nm; the overall size of the source and drain electrodes is 200 μm×100 μm, and the overall size of the gate electrode is 100 μm×100 μm; the lead electrode, the thickness is 200~400 nm; the source, drain and gate electrodes are connected to the corresponding lead electrodes for external test circuits. First, we tested the infrared absorption spectra of black arsenic phosphorus nanosheets of different components by Fourier infrared spectrometer. With the increase of arsenic content, the absorption cutoff edge shows a gradual red shift phenomenon. At 4.65 μm in the mid-wave infrared, the absorption is the highest when the arsenic and phosphorus content is 1:1. The laser is focused through the optical path, and the input control signal enables the mechanical shutter to realize data stream transmission. The field effect transistor based on the joint regulation of components and gate voltage acts as a signal receiver to transmit the target data stream, converting the optical signal into an electrical signal. The preamplifier, phase-locked amplifier and oscilloscope collect and read the signal, and finally decoded on the computer side to realize photocurrent collection. Figure 5 and Figure 6 The photocurrent response of black arsenic phosphorus field effect transistors with different components at different bias voltages (-1 V and 1 V), different gate voltages (-5 V, 0 V and 5 V) and different wavelengths is shown; the results show that the black arsenic phosphorus field effect transistor provided by the present invention achieves high response detection in the visible near-infrared and mid-wave infrared range. In addition, the results show that the photocurrent response is the largest when the arsenic and phosphorus content is 1:1, which is consistent with the infrared absorption spectrum test results, revealing the feasibility of the black arsenic phosphorus field effect transistor strategy we constructed and its excellent photoelectric performance.

[0089] Example 3

[0090] The thickness of the silicon substrate covered with silicon oxide is 500 μm; the thickness of the bottom bismuth selenium oxide nanosheet is 15 nm, the thickness of the black arsenic phosphorus nanosheet is 37 nm, and the thickness of the top gate bismuth selenium oxide nanosheet is 20 nm; the overall size of the source and drain electrodes is 200 μm×100 μm, and the overall size of the gate electrode is 100 μm×100 μm; the lead electrode has a thickness of 200~400 nm; the source, drain and gate electrodes are connected to the corresponding lead electrodes for external test circuits. Figure 7 and Figure 8 This is the noise current spectrum obtained from the black arsenic phosphorus field effect transistor test. Comparing 1 / f, shot noise and thermal noise at low frequency, it is found that 1 / f is dominant. The noise current obtained by integral calculation is 1.8×10 -12 A / Hz 1 / 2 Response rate, external quantum efficiency, equivalent noise power and normalized detectivity are key indicators for measuring detector performance. Fig. 9The photocurrent response waveforms of the black arsenic phosphide field effect transistor at 520 nm, 638 nm, 940 nm, 1064 nm, 1310 nm, 1550 nm and 1650 nm are shown. By extracting the photocurrent value and calculating it, we get Fig.10 The responsivity, external quantum efficiency, equivalent noise power and normalized detectivity distribution at different wavelengths are shown. The peak responsivity is 6.77 A / W, the external quantum efficiency is as high as 8.15, and the equivalent noise power is as low as 0.27×10 -12 W Hz -1 / 2 and up to 5.3×10 10 cm Hz 1 / 2 W −1 The results show that the method provided by the present invention for optimizing and regulating the response current of the field effect transistor based on the combined regulation of the composition and the gate voltage to improve the detection capability of the device is reasonable and effective.

[0091] Various parameters in the structure of field effect transistors vary within a certain range. The present invention relates to a preparation method and performance research of a field effect transistor based on the joint regulation of components and gate voltage. The device preparation steps first use ultraviolet lithography technology and electron beam evaporation technology to manufacture the source and drain, and then transfer the mechanically stripped bismuth selenium oxide nanosheets to the channel to fill and reduce scattering, thereby improving the electrical performance of the device. Afterwards, the black arsenic phosphorus nanosheets are transferred to the source and drain, and the bismuth selenium oxide nanosheets are transferred as encapsulation layers and top gate dielectric layers for regulation. The top gate electrode is prepared using a probe-assisted gold electrode transfer method to avoid the pollution caused by the traditional photolithography method for making the gate electrode. Finally, the preparation of the black arsenic phosphorus field effect transistor is completed by ultrasonic lead and other processes. The black arsenic phosphorus field effect transistor of the present invention can optimize the photoelectric performance of the device in the visible light, near infrared and mid-wave infrared range by adjusting the components of black arsenic phosphorus and the top gate voltage. In addition, the contamination of the photosensitive material in the process is strictly avoided during the preparation process of the present invention. The high dielectric constant of the top gate bismuth selenium oxide dielectric layer enhances gate control and reduces the operating voltage. The advantages of the present invention include low power consumption, strong control capability, high response rate and wide spectrum detection capability. At the same time, the mature device manufacturing process and simplified device structure are conducive to the realization of integration and complex applications, expanding the application potential of innovative semiconductor technology.

[0092] Compared with the prior art, the field effect transistor based on the combined regulation of components and gate voltage and the preparation method thereof of the present invention have the following beneficial effects: a black arsenic phosphorus material with high carrier mobility, high response rate and narrow band gap grown by chemical vapor deposition is used as a photosensitive conductive channel, and its band gap can be adjusted by different components (b-As x P 1-x, x=0.2 / 0.3 / 0.4 / 0.5) to adjust (0.22 eV~0.28 eV), and through the transfer platform micro-area positioning method, the black arsenic phosphorus nanosheet is obtained by mechanical stripping and dry transfer technology. The high dielectric constant material bismuth selenium oxide dielectric layer is used for top gate regulation, which can provide an atomic-level smooth surface without dangling bonds. It can be used in two-dimensional optoelectronics to promote high carrier mobility, enhance gate control and reduce operating voltage to solve such key problems in the development of field effect transistors. A gold electrode is prepared on a silicon substrate in advance, and then a probe is used to gently lift up along one end of the engraved electrode with the help of a microscope platform, and then the lifted gold electrode is transferred to the top gate bismuth selenium oxide nanosheet; in this way, the contact surface between the gold electrode and the bismuth selenium oxide nanosheet is relatively good, which effectively avoids the contamination or surface defects that may be caused by the photolithography gate electrode and improves the gate control effect. The black arsenic phosphorus field effect transistor process is simple and cost-effective. Under the joint regulation of composition and gate voltage, the response rate is high, the external quantum efficiency is high, the equivalent noise power and the normalized detection rate are high, and visible light, near-infrared and medium-wave infrared detection can be achieved at room temperature, showing that mature device manufacturing technology and simplified device structure are conducive to the realization of integration and complex applications, and expand the application potential of innovative semiconductor technology.

[0093] The above-mentioned specific implementation methods are used to explain the present invention and are only preferred embodiments of the present invention, rather than limiting the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit of the present invention and the protection scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A field effect transistor based on the combined regulation of components and gate voltage, characterized in that: The structure is as follows: a silicon dioxide layer (2) is formed on an intrinsic low-resistance silicon substrate (1); source and drain metal electrodes are formed on the silicon dioxide layer (2); the source and drain electrodes are metal composite electrodes, including a chromium electrode (3) and a gold electrode (4); the bottom layer of the source and drain electrode channels is a bismuth selenium oxide nanosheet (5); a black arsenic phosphorus nanosheet (6) and a top gate bismuth selenium oxide nanosheet (7) dielectric layer are formed on the bismuth selenium oxide nanosheet (5); the source and drain electrodes and the gate (10) electrodes are connected to corresponding lead electrodes for connecting to an external test circuit.

2. The field effect transistor based on the combined regulation of components and gate voltage according to claim 1, characterized in that: The intrinsic low-resistance silicon substrate (1) has a resistivity of 0.001-0.005 Ω·cm and a thickness of 500 μm; The thickness of the silicon dioxide layer (2) is 300 nm; The thickness of the bismuth selenium oxide nanosheet (5) is 15 nm; The thickness of the black arsenic phosphorus nanosheet (6) is 37 nm; The thickness of the bismuth selenium oxygen nanosheet (5) is 20 nm.

3. The field effect transistor based on the combined regulation of components and gate voltage as claimed in claim 1, characterized in that: The source, drain and gate electrodes are chromium and gold composite electrodes. The lower metal layer is chromium, which serves as an adhesion layer with a thickness of 5nm. The upper metal layer is gold with a thickness of 50nm. The overall size of the source and drain electrodes is 200μm×100μm, and the overall size of the gate electrode is 100μm×100μm. The lead electrode has a thickness of 200-400nm.

4. The field effect transistor based on the combined regulation of components and gate voltage according to claim 1, characterized in that: Top gate voltage regulation is achieved at room temperature.

5. The field effect transistor based on the combined regulation of components and gate voltage according to claim 1, characterized in that: Realization of black arsenic phosphorus nanosheets (b-As) with different compositions at room temperature x P 1-x Infrared response, where x = 0.2 / 0.3 / 0.4 / 0.

5.

6. The field effect transistor based on the combined regulation of components and gate voltage according to claim 1, characterized in that: The band gap of black arsenic phosphorus nanosheets is adjustable. When the arsenic concentration is 83%, the band gap is 0.12eV, and it has good responsiveness to mid-wave infrared light.

7. The field effect transistor based on the combined regulation of components and gate voltage according to claim 1, characterized in that: The transistor has high performance in detecting visible light, near infrared and medium-wave infrared. The laser is focused through the optical path, and the input control signal enables the mechanical shutter to realize data stream transmission. The transistor acts as a signal receiver to transmit the target data stream and convert the optical signal into an electrical signal. The preamplifier, phase-locked amplifier and oscilloscope collect and read the signal, and finally decoded on the computer side to realize photocurrent collection, and the response rate, external quantum efficiency, equivalent noise power and normalized detection rate are evaluated.

8. A method for preparing a field effect transistor based on the combined regulation of components and gate voltage, characterized in that: The following steps are involved: Step 1: First, the surface of the silicon substrate covered with silicon dioxide is ultrasonically cleaned using acetone, isopropanol, ethanol and deionized water, and the substrate is cut into 0.8 cm × 0.8 cm samples using precision cutting technology; Step 2, using a hot plate to bake and a coating machine to coat the photoresist evenly on the substrate; Step 3, preparing the pre-designed source and drain electrodes by combining ultraviolet lithography, electron beam evaporation and lift-off process; Step 4: Using the transfer platform micro-area positioning method and dry transfer technology, the bottom bismuth selenium oxide nanosheets are mechanically peeled off using blue adhesive tape, and then transferred to the source and drain electrode channels for numbering and positioning marking; Step 5: Through the transfer platform micro-area positioning method, using dry transfer technology, using blue adhesive tape to mechanically peel off the black arsenic phosphorus nanosheets, and then transfer them to the source and drain electrodes for numbering and positioning marking; Step 6: Through the transfer platform micro-area positioning method, using dry transfer technology, use blue adhesive tape to mechanically peel off the top bismuth selenium oxygen nanosheet, and then use it as the encapsulation layer and top gate dielectric layer of the black arsenic phosphorus nanosheet for numbering and positioning marking; Step 7: Prepare a gold electrode on the silicon substrate in advance, then use a probe to gently lift up one end of the engraved electrode with the help of a microscope platform, and then transfer the lifted gold electrode to the top bismuth selenium oxide nanosheet; Step eight, attach the black arsenic phosphide field effect transistor with regulation capability to the PCB base, complete the lead and packaging to prepare a composite structure detection device for ultra-wideband detection in the visible light near-infrared and mid-wave infrared regions at room temperature.

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