Memory system, system and operating method thereof, computer readable storage medium

Abstract

The present disclosure provides a memory system and an operating method thereof, a system and an operating method thereof, and a computer readable storage medium, the memory system comprising an interface and an interface controller, the interface being connected with a host through a link; the interface controller being configured to: determine whether link equalization needs to be re-performed based on temperature change of the memory system and error count of the interface; the error count comprising a first error count and a second error count, the first error count being a number of recoverable errors in data packets received by the interface, and the second error count being a number of times that the interface switches between a normal working state and a recovery state; and in response to the link equalization needing to be re-performed, triggering the link equalization.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory system and its operation method, a system and its operation method, and a computer-readable storage medium. Background Technology

[0002] In a system comprising a host and a memory system, the host and memory systems communicate according to a communication protocol. They are connected via a link, with the host-side interface and the memory system-side interface at each end of the link. When the link becomes unstable, a recovery mechanism is needed to restore it to a stable operating state. However, the link recovery mechanisms in related technologies still require optimization. Summary of the Invention

[0003] In view of the above, this disclosure provides a memory system and its operation method, a system and its operation method, and a computer-readable storage medium to solve at least one problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a memory system, the memory system including an interface and an interface controller, the interface being connected to a host via a link; the interface controller is configured to:

[0006] The need for rebalancing of the link is determined based on the temperature change of the memory system and the error count of the interface; the error count includes a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the interface, and the second error count being the number of times the interface switches between normal operation state and recovery state;

[0007] In response to the need to re-perform the link balancing, the link balancing is triggered.

[0008] In one alternative implementation, the interface controller is specifically configured as follows:

[0009] Obtain the current temperature of the memory system and the temperature at the time of the last link equalization;

[0010] In response to the absolute value of the difference between the current temperature and the temperature at the time of the last link equalization being greater than a first preset value, the first error count and the second error count are obtained;

[0011] In response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, it is determined that the link equalization needs to be performed again.

[0012] In an alternative implementation, the interface controller is further configured to:

[0013] In response to a transmission rate of 8GT / s or greater on the link, the first error count and the second error count are cleared to zero, and a timer is started;

[0014] Whenever the timer reaches a timing period, the current temperature of the memory system is obtained.

[0015] In an alternative implementation, the interface controller is further configured to:

[0016] After the link balancing is successful, the first error count and the second error count are reset to zero.

[0017] In an alternative implementation, the interface controller is further configured to:

[0018] Before triggering the link balancing, request the interface to pause transmission and wait for the interface to enter an idle state;

[0019] After the interface enters the idle state, a flag for performing equalization is set in the control register of the interface.

[0020] In one alternative implementation, the interface is configured as follows:

[0021] In response to the flag indicating that link balancing is to be performed, link balancing is performed, including sending a training ordered set to the host to notify the host to perform link balancing.

[0022] In one alternative embodiment, the memory system includes a memory device and a memory controller coupled to the memory device and used to control the memory device; the memory controller includes the interface and the interface controller, or the memory controller includes the interface and the interface controller is external to the memory controller.

[0023] In one alternative implementation, the interface is a high-speed serial computer expansion bus standard interface.

[0024] Secondly, embodiments of this disclosure provide a method for operating a memory system, including:

[0025] The need for rebalancing of the link is determined based on the temperature changes of the memory system and the error count of the interface; the error count includes a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the interface, and the second error count being the number of times the interface switches between normal operation state and recovery state;

[0026] In response to the need to re-perform the link balancing, the link balancing is triggered.

[0027] In one alternative implementation, determining whether link equalization needs to be re-performed based on temperature changes in the memory system and error counts of the interface includes:

[0028] Obtain the current temperature of the memory system and the temperature at the time of the last link equalization;

[0029] In response to the absolute value of the difference between the current temperature and the temperature at the time of the last link equalization being greater than a first preset value, the first error count and the second error count are obtained;

[0030] In response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, it is determined that the link equalization needs to be performed again.

[0031] In one optional implementation, the operation method further includes:

[0032] In response to a link transmission rate greater than or equal to 8GT / s, the first error count and the second error count are cleared to zero, and a timer is started;

[0033] Whenever the timer reaches a timing period, the current temperature of the memory system is obtained.

[0034] In one optional implementation, the operation method further includes:

[0035] After the link balancing is successful, the first error count and the second error count are reset to zero.

[0036] In one optional implementation, the operation method further includes:

[0037] Before triggering the link balancing, request the interface to pause transmission and wait for the interface to enter an idle state;

[0038] Triggering the link equalization includes:

[0039] After the interface enters the idle state, a flag for performing equalization is set in the control register of the interface.

[0040] In one optional implementation, the operation method further includes:

[0041] The link balancing is performed in accordance with the flag indicating that balancing is to be performed, including sending a training ordered set to the host to notify the host to perform the link balancing.

[0042] Thirdly, embodiments of this disclosure provide a system, the system including a host and a memory system; the memory system includes an interface and an interface controller, the host includes a host interface, and the interface and the host interface are connected via a link;

[0043] The interface controller is configured to determine whether link equalization needs to be re-performed based on the temperature change of the memory system and the error count of the interface; the error count includes a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the interface, and the second error count being the number of times the interface switches between normal operation state and recovery state;

[0044] In response to the determination that the link balancing needs to be re-performed, the link balancing is triggered.

[0045] The interface is configured to perform the link balancing, including sending a training ordered set to the host interface to notify the host interface to perform the link balancing.

[0046] The host interface is configured to receive the ordered training set and perform the link balancing.

[0047] In one alternative implementation, the interface controller is specifically configured as follows:

[0048] Obtain the current temperature of the memory system and the temperature at the time of the last link equalization;

[0049] In response to the absolute value of the difference between the current temperature and the temperature at the time of the last link equalization being greater than a first preset value, the first error count and the second error count are obtained;

[0050] In response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, it is determined that the link equalization needs to be performed again.

[0051] In an alternative implementation, the interface controller is further configured to:

[0052] In response to a transmission rate of 8GT / s or greater on the link, the first error count and the second error count are cleared to zero, and a timer is started;

[0053] Whenever the timer reaches a timing period, the current temperature of the memory system is obtained.

[0054] In one alternative implementation, both the interface and the host interface are high-speed serial computer expansion bus standard interfaces.

[0055] Fourthly, embodiments of this disclosure provide a method for operating a system, including:

[0056] The interface controller determines whether link equalization needs to be re-performed based on the temperature changes of the memory system and the error count of the interface; in response to the need to re-perform the link equalization, the link equalization is triggered; the error count includes a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the interface, and the second error count being the number of times the interface switches between normal operation state and recovery state;

[0057] The link balancing process performed by the interface includes sending a training ordered set to the host interface to notify the host interface to perform the link balancing.

[0058] The host interface receives the ordered training set and performs the link balancing.

[0059] In one alternative implementation, determining whether link equalization needs to be re-performed based on temperature changes in the memory system and error counts of the interface includes:

[0060] Obtain the current temperature of the memory system and the temperature at the time of the last link equalization;

[0061] In response to the absolute value of the difference between the current temperature and the temperature at the time of the last link equalization being greater than a first preset value, the first error count and the second error count are obtained;

[0062] In response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, it is determined that the link equalization needs to be performed again.

[0063] In one optional implementation, the operation method further includes:

[0064] In response to a link transmission rate greater than or equal to 8GT / s, the interface controller clears the first error count and the second error count to zero and starts a timer;

[0065] Whenever the timer reaches a timing period, the interface controller obtains the current temperature of the memory system.

[0066] Fifthly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program, which, when executed, can implement the operation method of the memory system or the system operation method described in any of the foregoing embodiments.

[0067] In the technical solution provided in this disclosure, the interface controller in the memory system is configured to determine whether link balancing needs to be re-performed based on the temperature change of the memory system and the error count of the interface, and to trigger link balancing when it is determined that link balancing needs to be re-performed. That is, when the link is unstable because the balancing coefficient negotiated between the two ends of the link is no longer applicable due to temperature changes, resulting in an increase in the error count of the interface, the memory system can autonomously determine whether link balancing needs to be re-performed and trigger link balancing, without waiting for the host to determine whether link balancing needs to be re-performed and trigger link balancing. This can improve the efficiency of the link recovering to a stable operating state, release the host's computing resources, and improve the overall performance of the system. Attached Figure Description

[0068] Figure 1 A schematic diagram of an exemplary system with a memory system provided in the embodiments of this disclosure;

[0069] Figure 2 A schematic diagram of an exemplary memory card with a memory system provided for embodiments of this disclosure;

[0070] Figure 3 A schematic diagram of an exemplary solid-state drive with a memory system provided in an embodiment of this disclosure;

[0071] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuitry provided for embodiments of this disclosure;

[0072] Figure 5 A schematic cross-sectional view of a memory array including memory strings, provided for an embodiment of this disclosure;

[0073] Figure 6 A schematic diagram of an exemplary memory device including a memory array and peripheral circuitry, provided for embodiments of this disclosure;

[0074] Figure 7 A schematic diagram of a system including an interface and a host interface provided for embodiments of this disclosure;

[0075] Figure 8 A schematic diagram illustrating the implementation flow of the operation method of the memory system provided in this embodiment of the disclosure;

[0076] Figure 9 A schematic flowchart illustrating the operation method of a memory system provided as a specific example of this disclosure. Figure 1 ;

[0077] Figure 10 A schematic flowchart illustrating the operation method of a memory system provided as a specific example of this disclosure. Figure 2 ;

[0078] Figure 11 A partial schematic diagram of a memory system including an interface and an interface controller, provided as a specific example of this disclosure;

[0079] Figure 12 This is a schematic diagram illustrating the implementation flow of the system operation method provided in the embodiments of this disclosure. Detailed Implementation

[0080] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0081] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0082] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0083] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0084] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0085] In order to gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0086] The memory systems in the embodiments of this disclosure include, but are not limited to, memory systems including three-dimensional NAND type memory. For ease of understanding, the memory systems provided in this disclosure will be described using a memory system including three-dimensional NAND type memory as an example.

[0087] Figure 1 This is a schematic diagram of an exemplary system with a memory system provided for embodiments of this disclosure. In embodiments of this disclosure, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown, system 100 may include a host device 101 and a memory system 102. The memory system 102 may include one or more memory devices 103 and a memory controller 104. The host device 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 101 may be configured to send data to or receive data from the memory system 102.

[0088] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101 and is configured to control the memory device 103. The memory controller 104 can manage data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in low duty cycle environments, such as in Secure Digital Memory Cards (SD cards), Compact Flash Cards (CFC), Universal Serial Bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, the memory controller 104 is designed to operate in high duty cycle environments, such as in Solid State Drives (SSDs) or Embedded Multi-Media Cards (eMMCs).

[0089] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0090] In such Figure 2 In one example shown, the memory controller 104 and a single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a universal flash storage (UFS) card. The memory card 201 may also include a connection between the memory card 201 and a host device (e.g., Figure 1 The host device 101) is coupled to the memory card connector 202. In such a... Figure 3 In another example shown, the memory controller 104 and multiple memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include components for connecting the SSD 203 to host devices (e.g., Figure 1The host device 101 is coupled to an SSD connector 204. In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0091] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuitry, provided for embodiments of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 103 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, where memory cells 305 are NAND memory cells, provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0092] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0093] like Figure 4As shown, each memory string 304 may include a bottom-select transistor (BST) 307 at its source end and a top-select transistor (TST) 306 at its drain end. The bottom-select transistor 307 and the top-select transistor 306 may be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the sources of memory strings 304 within the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, the top-select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the upper select transistor 306) or a deselection voltage (e.g., 0V) to the corresponding upper select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the lower select transistor 307) or a deselection voltage (e.g., 0V) to the corresponding lower select transistor 307 via one or more bottom select lines (BSL) 309.

[0094] like Figure 4As shown, memory strings 304 can be organized into multiple memory blocks 303, each of which may have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and to unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation. In some embodiments, each word line 312 is coupled to a memory page 313. The size of a memory page 313, measured in bits, can be related to the number of memory strings 304 coupled by word lines 312 in a memory block 303. Each word line 312 may include multiple control gates at each memory cell 305 in the corresponding memory page 313, as well as gate lines coupling the control gates.

[0095] Figure 5 This is a schematic cross-sectional view of a memory array including memory strings, provided as an embodiment of this disclosure. Figure 5 As shown, the memory array may include a stacked structure 400, which includes a plurality of gate layers 401 and a plurality of insulating layers 402 stacked alternately in sequence, and a channel structure 403 perpendicularly penetrating the gate layers 401 and the insulating layers 402. The gate layers 401 and the insulating layers 402 may be stacked alternately, and two adjacent gate layers 401 are separated by an insulating layer 402. The number of memory cells included in the memory array is mainly related to the logarithm of the number of gate layers 401 and insulating layers 402 in the stacked structure 400.

[0096] The constituent materials of gate layer 401 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 401 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 401 includes a doped polysilicon layer. Multiple gate layers 401 surround a channel structure 403 to form a memory string. Gate layers 401 at the top of the stack 400 may extend laterally as upper select gate lines, gate layers 401 at the bottom of the stack 400 may extend laterally as lower select gate lines, and gate layers 401 extending laterally between the upper and lower select gate lines may serve as word line layers.

[0097] In some embodiments, the stacked structure 400 may be disposed on a substrate 404. The substrate 404 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0098] In some embodiments, the channel structure 403 includes a functional layer, a channel layer, and an insulating filler layer. In some embodiments, the channel layer includes silicon, for example, polysilicon. In some embodiments, the functional layer is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure 403 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the channel layer, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the functional layer may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0099] Return to reference Figure 4 The peripheral circuitry 302 can be coupled to the memory array 301 via bit lines 311, word lines 312, common-source lines 310, lower select lines 309, and upper select lines 308. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit lines 311, word lines 312, common-source lines 310, lower select lines 309, and upper select lines 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory array 301. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology. For example, Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 501, a column decoder / bit line driver 502, a row decoder / word line driver 503, a voltage generator 504, a control logic unit 505, a register 506, a flash memory interface 507, and a data bus 508. It should be understood that in some examples, additional components may be included. Figure 6 Additional peripheral circuitry not shown.

[0100] Page buffer / sensor amplifier 501 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic unit 505. In one example, page buffer / sensor amplifier 501 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 501 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 501 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 502 can be configured to be controlled by control logic unit 505 and select one or more memory strings by applying a bit line voltage generated from voltage generator 504.

[0101] The row decoder / word line driver 503 can be configured to be controlled by the control logic unit 505 and to select / deselect memory blocks of the memory array 301 and select / deselect word lines of the memory blocks. The row decoder / word line driver 503 can also be configured to drive word lines using word line voltages generated from the voltage generator 504. In some embodiments, the row decoder / word line driver 503 can also select / deselect and drive the lower select line and the upper select line. As described in detail below, the row decoder / word line driver 503 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 504 can be configured to be controlled by the control logic unit 505 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0102] Control logic unit 505 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 506 can be coupled to control logic unit 505 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 507 can be coupled to control logic unit 505 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic unit 505, as well as to buffer status information received from control logic unit 505 and relay it to memory controller. Flash interface 507 can also be coupled to column decoder / bit line driver 502 via data bus 508 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0103] Figure 7 A system diagram including a host and a memory system is provided for embodiments of this disclosure, such as... Figure 7 As shown, the system includes a memory system 601, which includes a memory controller 602 and a memory device 603. The memory device 603 may include at least one memory device 300 from any of the preceding embodiments. The memory controller 602 includes a control unit 608, a cache 609, an error checking and correcting (ECC) module 611, a front-end interface 604, a back-end interface 610, a wear leveling (WL) module 612, and a garbage collection (GC) module 613. The control unit 608 is coupled to other modules via a bus 614 and is configured to control the memory system 601 as a whole. The control unit 608 may be, for example, a central processing unit (CPU) or a microprocessor (MPU). The memory controller 602 is coupled to the host 606 via the front-end interface 604 and to the memory device 603 via the back-end interface 610. The memory controller 602 is configured to manage data stored or to be stored in the memory device 603 through wear leveling and garbage collection. The memory controller 602 is also configured to perform error correction on data read from the memory device 603 or data to be written to the memory device 603.

[0104] In some embodiments, the memory controller 602 may communicate with the host 606 according to a specific communication protocol. The memory controller 602 may communicate with the host 606 through at least one interface protocol, including USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Peripheral Component Interconnect Express (PCIe) protocol, Serial Advanced Technology Attachment (SATA) protocol, Parallel Advanced Technology Attachment (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced System Device Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, etc.

[0105] In some specific examples, the front-end interface 604 of the memory system 601 is connected to the host interface 607 of the host 606 via link 605. Here, the example is taken that both the front-end interface 604 and the host interface 607 are high-speed serial computer expansion bus standard interfaces, that is, both the front-end interface 604 and the host interface are PCIe interfaces. The front-end interface 604 and the host interface 607 communicate according to the PCIe protocol specification to realize the communication between the memory system 601 and the host 606.

[0106] According to the PCIe protocol specification, after the system powers on or resets, the Link Training and Status State Machine (LTSSM) in the front-end interface 604 and the host interface 607 controls link 605 to sequentially enter the Detect, Polling, and Configuration phases. Specifically, in the Detect phase, the front-end interface 604 and the host interface 607 detect whether the other party is present. After confirming that the other party is present, they enter the Polling phase, where bit and symbol locking and channel polarity determination are performed. Then, they enter the Configuration phase, where link bandwidth and link number are determined, and channel-to-channel phase compensation and other operations are performed. After configuration, Link 605 enters the Linkup state at a low speed (2.5GT / s), then enters the Recovery state. In this state, Link 605 performs a rate switch from the lowest to the highest speed. When the speed switches to 8GT / s or higher, the Link Training Machine enters the Equalization sub-state within the Recovery state. The front-end interface 604 and the host interface 607 perform link equalization, negotiating the equalization coefficients and adjusting their respective transmit parameters (Tx) and receive parameters (Rx) to reduce the Bit Error Rate (BER) of the received data at both ends of the link to below the maximum BER specified by the protocol (e.g., 10E-12). If the first rate switch is completed and Link 605 can operate stably, it switches to a higher speed, repeating this rate switch and link equalization process until equalization parameters that meet the link stability requirements are negotiated at each operating speed. Once link equalization is completed for all operating speeds supported by the interface, it enters the normal operating state (L0), where Link 605 operates at the highest speed supported by the interface or transmits data at the highest speed that meets the link stability requirements.

[0107] However, the link balancing mentioned above is performed at the temperature when the link enters the connected state. When the ambient temperature changes, the balancing parameters obtained through the link balancing negotiation may no longer be applicable, causing the link to enter an unstable state and resulting in a decrease in link performance.

[0108] In some embodiments, when a link becomes unstable, the memory system needs to report to the host, which then determines whether redo equivalence is needed and triggers redo equivalence accordingly. However, when the host is connected to multiple memory systems and other PCIe devices simultaneously, determining whether redo equivalence is needed and triggering redo equivalence consumes the host's computing resources, resulting in a decrease in overall system performance.

[0109] Therefore, optimizing the triggering mechanism for link load balancing has become an urgent problem to be solved. To address this, this disclosure proposes the following implementation method.

[0110] This disclosure provides an operation method for a memory system. Figure 8 This is a schematic diagram illustrating the implementation flow of the memory system operation method provided in the embodiments of this disclosure, such as... Figure 8 As shown, the operation of the memory system includes the following steps:

[0111] S10: Determine whether link equalization needs to be re-performed based on the temperature change of the memory system and the error count of the interface; the error count includes a first error count and a second error count, the first error count is the number of recoverable errors in the data packets received by the interface, and the second error count is the number of times the interface switches between normal operation state and recovery state;

[0112] S20: In response to the need to re-perform the link equalization, trigger the link equalization.

[0113] Figure 9 and Figure 10 The following is a framework flowchart illustrating the operation of a memory system for some specific examples. Figures 8 to 10 The operation method of the memory system provided in the embodiments of this disclosure will be described in detail.

[0114] It should be noted that in the operation method of the memory system provided in this disclosure, the interface can be... Figure 7 The front-end interface 604 of the memory controller 602 shown.

[0115] In some embodiments, before performing step S10, the operation method of the memory system further includes: in response to a link transmission rate greater than or equal to 8GT / s, clearing the first error count and the second error count to zero, and starting a timer.

[0116] In some specific examples, such as Figure 9 As shown, when the link is connected or the rate is switched, step S1001 is executed first to determine whether the transmission rate of the link is greater than or equal to 8GT / s; in response to the transmission rate of the link being greater than or equal to 8GT / s, steps S1002 to S1004 are executed to update the initial temperature t0, clear the first error count and the second error count to zero, and start the timer.

[0117] It should be noted that, as mentioned earlier, when the link transmission rate reaches 8GT / s or higher, the link state training machine in the interface will control the hardware in the interface to automatically perform one or more link equalizations. In this case, step S1002 can record the temperature of the memory system when the link automatically completes the last link equalization, and use this temperature as the initial temperature t0. Here, the link state training machine controlling the hardware in the interface to automatically complete link equalization means that after entering the recovery state, the link state training machine can automatically switch subsequent states. The hardware in the interface physical layer can respond to the state switching of the link state training machine and perform link equalization; this process does not require software or firmware intervention. However, when the link transmission rate is below 8GT / s, link equalization will not be performed. In this case, step S1005 needs to be executed to turn off the timer.

[0118] In this embodiment of the disclosure, the first error count is the number of recoverable errors in the data packets received by the interface. Here, the recoverable errors can be errors detected by the Transaction Layer Packet (TLP) received by the data link layer of the interface through Link Cyclic Redundancy Check (LCRC). The second error count is the number of times the interface switches between normal working state and recovery state.

[0119] It should be noted that the interface can be divided into a transaction layer, a data link layer, and a physical layer. During the data packet reception process, the physical layer assembles the received bit stream into a physical layer packet (PLP) and then transforms the physical layer packet into a data link layer packet (DLLP) for transmission to the data link layer. The data link layer packet includes the transaction layer packet and a link cyclic redundancy check (CRC) code. The data link layer uses the CRC code to perform CRC check on the transaction layer packet.

[0120] In some specific examples, the first error count and the second error count can be recorded in the first counter and the second counter of the interface, respectively. The first error count and the second error count can be obtained from the first counter and the second counter, respectively, or the first error count and the second error count can be cleared to zero.

[0121] In some specific examples, the temperature of the memory system can be obtained through a temperature sensing unit in the memory system, which may include a temperature sensor.

[0122] In some embodiments, when the timer is started and the timing reaches a timing period, step S10 is executed to determine whether link equalization needs to be re-performed based on the temperature change of the memory system and the error count of the interface.

[0123] In some embodiments, refer to Figure 10 The specific process of executing step S10 may include: executing step 2001, obtaining the current temperature t1 of the memory system, and executing step S2002, determining whether the absolute value of the difference between the current temperature t1 and the temperature at the time of the last link equalization is greater than a first preset value. Here, the temperature at the time of the last link equalization can be... Figure 9 The initial temperature t0 is recorded when step S1002 is executed. In response to the absolute value of the difference between the current temperature t1 and the temperature at the time of the last chain equilibration being greater than a first preset value, step S2003 is executed to obtain a first error count and a second error count, and step S2004 is executed to determine whether the first error count is greater than a second preset value and whether the second error count is greater than a third preset value.

[0124] In this embodiment, whenever the timer reaches a timing period, step 2001 is executed to obtain the current temperature of the memory system. This means the current temperature of the memory system can be periodically obtained and compared with the temperature at the time of the last link equalization. If the absolute value of the difference between the current temperature and the temperature at the time of the last link equalization is greater than a first preset value, it can be considered that the current temperature has changed significantly relative to the temperature at the time of the last link equalization. This temperature change may cause the equalization coefficient negotiated between the two ends of the link during the last link equalization to no longer be applicable. Therefore, it is necessary to further obtain the first error count and the second error count of the interface, and determine whether the first error count is greater than the second preset value and whether the second error count is greater than the third preset value. If the first error count is greater than the second preset value or the second error count is greater than the third preset value, it can be considered that the link is indeed in an unstable state due to a large temperature change. Therefore, it can be determined that link equalization needs to be performed again based on the current temperature to restore the link to a stable operating state.

[0125] It should be noted that this disclosure does not limit the specific size of the first preset value, the second preset value, and the third preset value, and different configurations can be made for different memory systems.

[0126] In some embodiments, in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, it is determined that link balancing needs to be re-performed, and step S20 is executed, triggering link balancing in response to the need to re-perform link balancing.

[0127] In some specific examples, refer to Figure 10In response to a first error count exceeding a second preset value or a second error count exceeding a third preset value, step S2005 is executed, requesting the interface to pause transmission and wait for the interface to enter an idle state. Specifically, after determining that link equalization needs to be re-performed, the interface can be requested to stop generating new data packets, stop receiving new data packets, and pause the transmission of already generated or received data packets. After the interface enters an idle state, steps S2006 and S2007 are executed, setting the performance equalization flag and triggering link retraining.

[0128] In some specific examples, the interface includes a control register containing a bit corresponding to the execution equalization. This bit can be toggled, for example, from 0 to 1, to set the execution equalization flag. Additionally, the control register includes a bit corresponding to link retraining, which can be toggled, for example, from 0 to 1, to trigger the link training state machine to enter the recovery state.

[0129] In some embodiments, in response to a flag indicating that link balancing is to be performed, the hardware in the interface begins link balancing under the control of the link training state machine, including sending a training ordered set to the host to notify the host to perform link balancing.

[0130] In some specific examples, the interface sends a training sequence TS2 to the host. TS2 includes a bit corresponding to the quiesce guarantee. Flipping this bit in TS2, for example, from 0 to 1, can notify the host to also pause transmission to ensure that the link is idle. TS2 also includes a bit corresponding to request equalization. Flipping this bit in TS2, for example, from 0 to 1, can notify the host to start link equalization.

[0131] In some embodiments, continue to refer to Figure 10 Once the link balancing is complete, step S2008 is executed to clear the first and second error counts to zero and update the initial temperature t0.

[0132] In some specific examples, when link equalization is successfully completed, that is, when the two ends of the link negotiate and obtain a new equalization coefficient that can make the link run stably based on the current temperature t1, the bit corresponding to equalization completion in the status register of the interface can be flipped, for example, from 0 to 1. In response to the bit being set to 1, the first error count and the second error count are cleared, and the initial temperature t0 is updated to the current temperature t1 obtained by executing step S2001. That is, when the timer reaches the next timing cycle and executes step S2002, the temperature of the memory system will be compared with the temperature when link equalization was performed to determine whether to execute step S2003.

[0133] In some embodiments, the temperature of the memory system during each link balancing operation can be recorded in a temperature recording table. The latest temperature in the temperature recording table can be used as the temperature during the previous link balancing operation in the above embodiments. When link balancing is successfully completed, the current temperature in the above embodiments will be recorded in the temperature recording table. In other embodiments, the temperature recording table may include only one temperature, which is the temperature during the previous link balancing operation in the above embodiments. When link balancing is successfully completed, the current temperature in the above embodiments will overwrite the temperature during the previous link balancing operation.

[0134] In some embodiments, if re-evaluating the link balance fails, i.e., the bit error rate of the data received at both ends of the link does not drop below the maximum bit error rate specified by the protocol within a specified time, the link training state machine will automatically reduce the transmission rate of the link to perform link balance at a lower rate until the balance parameters that meet the link stability requirements are obtained.

[0135] In this embodiment of the disclosure, the operation method of the memory system includes determining whether link balancing needs to be re-performed based on temperature changes and interface error counts, and triggering link balancing after determining that link balancing needs to be re-performed. That is, it can autonomously determine whether link balancing needs to be re-performed and trigger link balancing without waiting for the host to determine whether link balancing needs to be re-performed and trigger link balancing, thereby improving the efficiency of link recovery to a stable operating state.

[0136] Based on the above-described operation method of the memory system, this disclosure also provides a memory system including an interface and an interface controller. The interface is connected to a host via a link. The interface controller is configured to: determine whether link equalization needs to be re-performed based on the temperature change of the memory system and the error count of the interface; the error count includes a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the interface, and the second error count being the number of times the interface switches between a normal operating state and a recovery state; and trigger link equalization in response to the need for re-performation of link equalization.

[0137] In some specific examples, the memory system includes a memory device and a memory controller coupled to and controlling the memory device, the memory controller including an interface and an interface controller, or the memory controller including an interface with the interface controller external to the memory controller.

[0138] In a specific example, refer to Figure 7 The interface of the memory system provided in this disclosure can be Figure 7 The front-end interface 604 of the memory controller 602 shown, and the interface controller 615 can be part of the control unit 608 of the memory controller 602. The front-end interface 604 and the interface controller 615 can be coupled through the bus 614 in the memory controller 602.

[0139] In another specific example, the interface controller may also be a control unit in the memory controller 602 that is independent of the control unit 608.

[0140] In this embodiment, the interface controller includes firmware and the hardware required for firmware operation. The interface controller can control the interface by running the firmware. The firmware in the interface controller includes programs for determining whether link balancing needs to be re-performed and for triggering link balancing. In some specific examples, the interface is a high-speed serial computer expansion bus standard interface, i.e., a PCIe interface, and the memory system can communicate with the host or other PCIe devices according to the PCIe protocol specification.

[0141] Figure 11 A partial schematic diagram of a memory system provided as a specific example of this disclosure, such as Figure 11 As shown, the memory system includes an interface 701, an interface controller 702, a temperature sensor 707, and a timer 708. The interface 701 includes a first counter 703, a second counter 704, a link event recording unit 705, and a link equalization triggering unit 706.

[0142] In some embodiments, the interface controller is specifically configured to: obtain the current temperature of the memory system and the temperature at the time of the last link balancing; in response to the absolute value of the difference between the current temperature and the temperature at the time of the last link balancing being greater than a first preset value, obtain a first error count and a second error count; in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, determine that link balancing needs to be performed again.

[0143] In a specific example, refer to Figure 11 The interface controller 702 can obtain the current temperature of the memory system through the temperature sensor 707, and in response to the absolute value of the difference between the current temperature and the temperature when the last link equalization was performed being greater than a first preset value, it obtains the first error count and the second error count from the first counter 703 and the second counter 704 respectively.

[0144] In some embodiments, the interface controller is further configured to: in response to a link transmission rate greater than or equal to 8GT / s, clear the first error count and the second error count, and start a timer; and whenever the timer reaches a timing period, acquire the current temperature of the memory system.

[0145] In a specific example, refer to Figure 11 The link event recording unit 705 may include a status register. When the link connection status or transmission rate changes, the bits in the status register related to the link connection status or transmission rate can be toggled, for example, from 0 to 1. The interface controller 702 can respond to a link transmission rate greater than or equal to 8GT / s by clearing the counts in the first counter 703 and the second counter 704 and starting the timer 708. Whenever the timer 708 reaches a timing cycle, the interface controller 702 can obtain the current temperature of the memory system through the temperature sensor 707.

[0146] In some embodiments, the interface controller is further configured to: request the interface transmission to pause and wait for the interface to enter an idle state before triggering link equalization; and set a flag for performing equalization in the interface's control register after the interface enters an idle state.

[0147] In a specific example, refer to Figure 11 After determining that link balancing needs to be re-performed, the interface controller 702 can request the interface to stop generating new data packets, stop receiving new data packets, and suspend the transmission of already generated or received data packets. The link balancing trigger unit 706 includes a control register. After the interface enters an idle state, the interface controller 702 can toggle the bit in the control register corresponding to the execution of balancing, for example, from 0 to 1, to set the flag for performing balancing.

[0148] In some embodiments, the interface is configured to: perform link balancing in response to the flag indicating that link balancing is to be performed, including sending a training ordered set to the host to notify the host to perform link balancing.

[0149] In some specific examples, in response to a flag indicating that link balancing is to be performed, the hardware in the interface will begin link balancing under the control of the link training state machine, including sending a training ordered set to the host to notify the host to perform link balancing.

[0150] In some embodiments, the interface controller is further configured to clear the first error count and the second error count to zero after link balancing is successful.

[0151] In some specific examples, refer to Figure 11 When link equalization is successfully completed, the bit corresponding to the completion of equalization in the status register of interface 701 can be flipped, for example, from 0 to 1. In response to the bit being set to 1, interface controller 702 can clear the counts in the first counter 703 and the second counter 704.

[0152] Here, the specific structure and composition of the memory system can be referred to the aforementioned section. Figures 1 to 7 Introduction; the interface controller is configured to execute Figures 8 to 10 The operation method shown is described in detail in the operation method of the memory system in the foregoing embodiments, and will not be repeated here.

[0153] In this embodiment, the interface controller can determine whether link equalization needs to be re-performed based on temperature changes and the interface's error count. Furthermore, the interface provides a port for the interface controller to trigger link equalization. Specifically, the interface controller can set the bits related to triggering link equalization in the control register of the interface, thereby triggering link equalization after determining that link equalization needs to be re-performed. Thus, the memory system can autonomously determine whether link equalization needs to be re-performed and trigger link equalization without waiting for the host to determine whether link equalization needs to be re-performed and to trigger link equalization, thereby improving the efficiency of link recovery to a stable operating state.

[0154] Based on similarities to the memory systems and their operation methods described above, this disclosure also provides a system and its operation method. Figure 7 This is a schematic diagram of a system provided in an embodiment of the present disclosure. Figure 12 This is a schematic diagram illustrating the implementation flow of the system operation method provided in the embodiments of this disclosure.

[0155] In some embodiments, refer to Figure 7The system includes a host 606 and a memory system 601. The memory system 601 includes a front-end interface 604 and an interface controller 615. The host 606 includes a host interface 607. The front-end interface 604 and the host interface 607 are connected via a link 605. The interface controller 615 is configured to: determine whether link equalization needs to be re-performed based on temperature changes in the memory system and error counts of the front-end interface 604; the error counts include a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the front-end interface 604, and the second error count being the number of times the front-end interface 604 switches between normal operation and recovery states; in response to determining that link equalization needs to be re-performed, trigger link equalization; the front-end interface 604 is configured to: perform link equalization, including sending a training ordered set to the host interface 607 to notify the host interface 607 to perform link equalization; the host interface 607 is configured to: receive the training ordered set and perform link equalization.

[0156] In some specific examples, both the front-end interface 604 and the host interface 606 are high-speed serial computer expansion bus standard interfaces, namely PCIe interfaces. The memory system 601 and the host 606 can communicate through the front-end interface 604 and the host interface 607 in accordance with the PCIe protocol specification.

[0157] In some embodiments, such as Figure 12 As shown, the system operation method includes the following steps:

[0158] Step S30: The interface controller determines whether link equalization needs to be re-performed based on the temperature change of the memory system and the error count of the interface; in response to the need to re-perform the link equalization, the link equalization is triggered; the error count includes a first error count and a second error count, the first error count is the number of recoverable errors in the data packets received by the interface, and the second error count is the number of times the interface switches between normal operation state and recovery state;

[0159] Step S40: The interface performs the link balancing, including sending a training ordered set to the host interface to notify the host interface to perform the link balancing;

[0160] Step S50: The host interface receives the training ordered set and performs the link equalization.

[0161] Here, the interface in the system's operation method can be Figure 7 The front-end interface 604 of the memory controller 602 shown.

[0162] In some specific examples, the bits corresponding to the silent guarantee and requested equalization in the training ordered set sent by the interface to the host can be flipped, for example, from 0 to 1. When the host interface receives the training ordered set, in response to the bit corresponding to the silent guarantee being 1 in the training ordered set, it will pause transmission to ensure that the host interface is in an idle state. In response to the bit corresponding to the requested equalization being 1, the host interface will start performing link equalization.

[0163] In some embodiments, the link equalization process includes the interaction of the interface and the host interface with the training ordered set, and the adjustment of their respective transmission and reception parameters so that the bit error rate of the received data at both ends of the link is reduced to below the maximum bit error rate specified by the protocol (e.g., 10E-12).

[0164] In this embodiment of the disclosure, the interface and the host interface are connected via a link. The interface controller in the memory system can determine whether link balancing needs to be re-performed based on the temperature change of the memory system and the error count of the interface. When it is determined that link balancing needs to be re-performed, link balancing is triggered. That is, when the link is unstable because the balancing coefficient negotiated between the two ends of the link is no longer applicable due to temperature changes, resulting in an increase in the error count of the interface, the memory system can autonomously determine whether link balancing needs to be re-performed and trigger link balancing. This can free up the computing resources of the host and improve the performance of the system.

[0165] This disclosure also provides a computer-readable storage medium on which a computer program is stored.

[0166] In some embodiments, when a computer program is executed by a processor, it can perform the operation methods of the memory system in any of the above embodiments.

[0167] In other embodiments, when a computer program is executed by a processor, it can perform the operating methods of the system in any of the above embodiments.

[0168] Here, to implement all or part of the operation methods in the above embodiments, it can be accomplished by hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium, and the execution of the computer program can include the operation methods as described in any of the above embodiments. The computer-readable storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive, etc., and may also include a combination of the above storage media.

[0169] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0170] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0171] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory system, characterized in that, The memory system includes an interface and an interface controller, the interface being connected to a host via a link; the interface controller is configured to: In response to the absolute value of the difference between the current temperature of the memory system and the temperature at the time of the last link equalization being greater than a first preset value, the error count of the interface is obtained from the interface; The error count of the interface determines whether link balancing needs to be re-performed; the error count includes a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the interface, and the second error count being the number of times the interface switches between normal operation state and recovery state; In response to the need to re-perform the link balancing, the link balancing is triggered.

2. The memory system according to claim 1, characterized in that, The interface controller is specifically configured as follows: In response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, it is determined that the link equalization needs to be performed again.

3. The memory system according to claim 2, characterized in that, The interface controller is also configured to: In response to a transmission rate of 8GT / s or greater on the link, the first error count and the second error count are cleared to zero, and a timer is started; Whenever the timer reaches a timing period, the current temperature of the memory system is obtained.

4. The memory system according to claim 2, characterized in that, The interface controller is also configured to: After the link balancing is successful, the first error count and the second error count are reset to zero.

5. The memory system according to claim 1, characterized in that, The interface controller is also configured to: Before triggering the link balancing, request the interface to pause transmission and wait for the interface to enter an idle state; After the interface enters the idle state, a flag for performing equalization is set in the control register of the interface.

6. The memory system according to claim 5, characterized in that, The interface is configured as follows: In response to the flag indicating that link balancing is to be performed, link balancing is performed, including sending a training ordered set to the host to notify the host to perform link balancing.

7. The memory system according to claim 1, characterized in that, The memory system includes a memory device and a memory controller coupled to the memory device and used to control the memory device; the memory controller includes the interface and the interface controller, or the memory controller includes the interface and the interface controller is external to the memory controller.

8. The memory system according to claim 1, characterized in that, The interface is a high-speed serial computer expansion bus standard interface.

9. A method for operating a memory system, characterized in that, include: In response to the absolute value of the difference between the current temperature of the memory system and the temperature at the time of the last link equalization being greater than a first preset value, the error count of the interface is obtained from the interface. The error count of the interface determines whether link balancing needs to be re-performed; the error count includes a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the interface, and the second error count being the number of times the interface switches between normal operation state and recovery state; In response to the need to re-perform the link balancing, the link balancing is triggered.

10. The method of operating the memory system according to claim 9, characterized in that, The error count based on the interface to determine whether link equalization needs to be re-performed includes: In response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, it is determined that the link equalization needs to be performed again.

11. The method of operating the memory system according to claim 10, characterized in that, The operation method further includes: In response to a link transmission rate greater than or equal to 8GT / s, the first error count and the second error count are cleared to zero, and a timer is started; Whenever the timer reaches a timing period, the current temperature of the memory system is obtained.

12. The method of operating the memory system according to claim 10, characterized in that, The operation method further includes: After the link balancing is successful, the first error count and the second error count are reset to zero.

13. The method of operating the memory system according to claim 9, characterized in that, The operation method further includes: Before triggering the link balancing, request the interface to pause transmission and wait for the interface to enter an idle state; The triggering of the link equalization includes: After the interface enters the idle state, a flag for performing equalization is set in the control register of the interface.

14. The method of operating the memory system according to claim 13, characterized in that, The operation method further includes: In response to the flag indicating that link balancing is to be performed, link balancing is performed, including sending a training ordered set to the host to notify the host to perform link balancing.

15. A system, characterized in that, The system includes a host and a memory system; the memory system includes an interface and an interface controller, the host includes a host interface, and the interface and the host interface are connected by a link. The interface controller is configured to: in response to the absolute value of the difference between the current temperature of the memory system and the temperature at the time of the last link equalization being greater than a first preset value, obtain the error count of the interface from the interface; The error count of the interface determines whether link balancing needs to be re-performed; the error count includes a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the interface, and the second error count being the number of times the interface switches between normal operation state and recovery state; In response to the determination that the link balancing needs to be re-performed, the link balancing is triggered. The interface is configured to perform the link balancing, including sending a training ordered set to the host interface to notify the host interface to perform the link balancing. The host interface is configured to receive the ordered training set and perform the link balancing.

16. The system according to claim 15, characterized in that, The interface controller is specifically configured as follows: In response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, it is determined that the link equalization needs to be performed again.

17. The system according to claim 16, characterized in that, The interface controller is also configured to: In response to a transmission rate of 8GT / s or greater on the link, the first error count and the second error count are cleared to zero, and a timer is started; Whenever the timer reaches a timing period, the current temperature of the memory system is obtained.

18. The system according to claim 15, characterized in that, Both the interface and the host interface are standard interfaces for high-speed serial computer expansion buses.

19. A method for operating a system, characterized in that, include: The interface controller responds to the absolute value of the difference between the current temperature of the memory system and the temperature at the time of the last link equalization being greater than a first preset value by obtaining the error count of the interface from the interface. Based on the error count of the interface, determine whether link balancing needs to be re-performed; In response to the need to re-perform the link balancing, the link balancing is triggered; the error count includes a first error count and a second error count, the first error count being the number of recoverable errors in the data packets received by the interface, and the second error count being the number of times the interface switches between normal operation state and recovery state; The link balancing process performed by the interface includes sending a training ordered set to the host interface to notify the host interface to perform the link balancing. The host interface receives the ordered training set and performs the link balancing.

20. The method of operating the system according to claim 19, characterized in that, The error count based on the interface to determine whether link equalization needs to be re-performed includes: In response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, it is determined that the link equalization needs to be performed again.

21. The method of operating the system according to claim 20, characterized in that, The operation method further includes: In response to a link transmission rate greater than or equal to 8GT / s, the interface controller clears the first error count and the second error count to zero and starts a timer; Whenever the timer reaches a timing period, the interface controller obtains the current temperature of the memory system.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, can implement the operation method of the memory system as described in any one of claims 9 to 14 or the operation method of the system as described in any one of claims 19 to 21.

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