Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, the array substrate comprises a substrate, and a first conductive layer, a first insulating layer, a second conductive layer and an active layer which are arranged on the substrate, and the second conductive layer comprises a first auxiliary electrode and a second auxiliary electrode which are arranged at an interval; the first interval between the first auxiliary electrode and the second auxiliary electrode can limit the length of the channel part of the active layer to achieve a narrow channel, so that the size of a thin film transistor can be reduced, the pixel density can be improved, and the problems that the layout design space on the array substrate is limited, and high resolution is difficult to achieve are solved. Moreover, the first auxiliary electrode and the source electrode contact part of the active layer extend into the first via hole of the first insulating layer and are electrically connected with the source electrode of the first conductive layer, and the first auxiliary electrode located in the first via hole can reduce the risk that the source electrode contact part climbs and is broken in the first via hole.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In the field of display technology, the thin film transistor (TFT) array substrate is an important component of the display panel, and the manufacture of the thin film transistor array substrate involves the use of multiple photo masks. The more photo masks are used, the longer the overall process flow of the thin film transistor array substrate, the greater the difficulty and the higher the cost. In order to reduce the number of photo masks used, the source and drain layers of the thin film transistor and the light shielding layer under the thin film transistor can share a metal layer. However, since the source and drain layers and the light shielding layer share a metal layer, the layout design space on the array substrate is limited, making it difficult to achieve a high pixel density (Pixels Per Inch, PPI). Summary of the invention

[0003] The present application provides an array substrate and a display panel to improve the technical problem that the layout design space on the array substrate is limited and it is difficult to achieve high resolution.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] The present application provides an array substrate, which includes:

[0006] substrate;

[0007] A first conductive layer, disposed on one side of the substrate, the first conductive layer comprising a source electrode and a light shielding electrode disposed at intervals;

[0008] A first insulating layer is disposed on a side of the first conductive layer away from the substrate, and the first insulating layer is provided with a first via hole at a position corresponding to the source electrode;

[0009] A second conductive layer is disposed on a side of the first insulating layer away from the substrate, the second conductive layer comprises a first auxiliary electrode and a second auxiliary electrode which are spaced apart, and a first interval is formed between the first auxiliary electrode and the second auxiliary electrode;

[0010] an active layer, arranged on a side of the first insulating layer away from the substrate, the active layer comprising a source contact portion, a drain contact portion, and a channel portion connected between the source contact portion and the drain contact portion, the source contact portion being arranged corresponding to the first auxiliary electrode and being electrically connected to the first auxiliary electrode, the drain contact portion being arranged corresponding to the second auxiliary electrode and being electrically connected to the second auxiliary electrode, the channel portion being arranged corresponding to the first interval and being arranged opposite to at least part of the light shielding electrode;

[0011] A second insulating layer is disposed on a side of the active layer away from the substrate;

[0012] A third conductive layer is disposed on a side of the second insulating layer away from the substrate, the third conductive layer comprising a gate disposed corresponding to the channel portion;

[0013] Part of the first auxiliary electrode and part of the source contact portion are located in the first via hole and are electrically connected to the source; and a channel length of the channel portion is equal to a spacing distance of the first spacing.

[0014] In the array substrate provided in the embodiment of the present application, the orthographic projection of the first auxiliary electrode on the substrate covers the orthographic projection of the first via hole on the substrate, and the orthographic projection of the source contact portion on the substrate covers the orthographic projection of the first via hole on the substrate.

[0015] In the array substrate provided in the embodiment of the present application, the active layer is arranged on a side of the second conductive layer away from the substrate, and part of the first auxiliary electrode is located in the first via hole and electrically connected to the source electrode.

[0016] In the array substrate provided in the embodiment of the present application, the second conductive layer is arranged on a side of the active layer away from the substrate, and part of the source contact portion is located in the first via hole and is electrically connected to the source.

[0017] In the array substrate provided in the embodiment of the present application, the material of the second conductive layer includes at least one of 1TO, IZO, Cu, and Al.

[0018] In the array substrate provided in the embodiment of the present application, the orthographic projection of the gate on the substrate coincides with the orthographic projection of the channel portion on the substrate.

[0019] In the array substrate provided in an embodiment of the present application, the orthographic projection of the channel portion on the substrate is located within the orthographic projection of the gate on the substrate, and the orthographic projection of the gate on the substrate partially overlaps with the orthographic projections of the first auxiliary electrode and the second auxiliary electrode on the substrate.

[0020] In the array substrate provided in the embodiment of the present application, the length of the channel portion ranges from 0.5 micrometers to 3 micrometers.

[0021] In the array substrate provided in the embodiment of the present application, the first insulating layer is provided with a second via hole at a position corresponding to the light-shielding electrode, and part of the second auxiliary electrode and part of the drain contact portion are located in the second via hole and are electrically connected to the light-shielding electrode.

[0022] In the array substrate provided in the embodiment of the present application, the array substrate further includes:

[0023] A third insulating layer is disposed on a side of the third conductive layer away from the substrate;

[0024] A planarization layer, disposed on a side of the third insulating layer away from the substrate;

[0025] A common electrode is disposed on a side of the planarization layer away from the substrate;

[0026] a fourth insulating layer, disposed on a side of the common electrode away from the substrate, wherein the fourth insulating layer is provided with a third via hole at a position corresponding to the drain contact portion;

[0027] A pixel electrode is arranged on a side of the fourth insulating layer away from the substrate and is arranged opposite to the common electrode. A portion of the pixel electrode is located in the third via hole and is electrically connected to the drain contact portion.

[0028] In the array substrate provided in the embodiment of the present application, the third via hole is arranged corresponding to the second via hole, and the pixel electrode located in the third via hole is also located in the second via hole.

[0029] An embodiment of the present application further provides a display panel, which includes the array substrate of one of the aforementioned embodiments.

[0030] The beneficial effects of the present application are as follows: in the array substrate and display panel provided by the present application, the array substrate includes a substrate and a first conductive layer, a first insulating layer, a second conductive layer and an active layer arranged on the substrate, the second conductive layer includes a first auxiliary electrode and a second auxiliary electrode arranged at intervals, and the first interval between the first auxiliary electrode and the second auxiliary electrode can limit the length of the channel portion of the active layer to achieve a narrow channel, thereby reducing the size of the thin film transistor and increasing the pixel density to improve the problem of limited layout design space on the array substrate and difficulty in achieving high resolution; moreover, the first auxiliary electrode and the source contact portion of the active layer extend to the first via hole of the first insulating layer and are electrically connected to the source of the first conductive layer, and the first auxiliary electrode located in the first via hole can reduce the risk of the source contact portion climbing and breaking in the first via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 As a preface to an embodiment of the present application, an array substrate is provided.

[0033] Figure 2 A schematic diagram of a first cross-sectional structure of an array substrate provided in an embodiment of the present application.

[0034] Figure 3 A schematic diagram of a second cross-sectional structure of an array substrate provided in an embodiment of the present application.

[0035] Figure 4 This is a schematic diagram of a third cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0036] Figure 5 This is a schematic diagram of a fourth cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0037] Figure 6 A fifth cross-sectional structural schematic diagram of the array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and regions is exaggerated for clear understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0039] Reference Figure 1 , Figure 1As a preface to the embodiments of the present application, an array substrate is provided, the array substrate comprising a substrate 10' and a first conductive layer 20', a first insulating layer 11', and an active layer 30' arranged on the substrate 10', the first conductive layer 20' comprising a source electrode 21' and a light shielding electrode 22' arranged at intervals, and the active layer 30' is in contact with and electrically connected to the source electrode 21' through a first via hole in the first insulating layer 11'. By forming the source electrode 21' and the light shielding electrode 22' with the same metal layer, two masks can be reduced, the cost can be reduced, and the parasitic capacitance can be reduced. However, since the source and drain electrode layers share a metal layer with the light shielding electrode, the layout design space on the array substrate is limited, and it is difficult to achieve a high pixel density (Pixels Per Inch, PPI).

[0040] To this end, the present application provides an array substrate and a display panel.

[0041] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a first cross-sectional structure of an array substrate provided in an embodiment of the present application. Figure 2 The array substrate 100 includes a substrate 10 and a first conductive layer 20, a first insulating layer 11, a second conductive layer 40, an active layer 30, a second insulating layer 12 and a third conductive layer 50 arranged on the substrate 10. The first conductive layer 20 is arranged on one side of the substrate 10, and the first conductive layer 20 includes a source electrode 21 and a light shielding electrode 22 arranged at intervals. The first insulating layer 11 is arranged on a side of the first conductive layer 20 away from the substrate 10, and the first insulating layer 11 is provided with a first via 111 at a position corresponding to the source electrode 21. The second conductive layer 40 is arranged on a side of the first insulating layer 11 away from the substrate 10, and the second conductive layer 40 includes a first auxiliary electrode 41 and a second auxiliary electrode 42 arranged at intervals, and a first interval 401 is provided between the first auxiliary electrode 41 and the second auxiliary electrode 42.

[0042] The active layer 30 is arranged on the side of the first insulating layer 11 away from the substrate 10, and the active layer 30 includes a source contact portion 31, a drain contact portion 32, and a channel portion 33 connected between the source contact portion 31 and the drain contact portion 32. The source contact portion 31 is arranged corresponding to the first auxiliary electrode 41 and is electrically connected to the first auxiliary electrode 41. The drain contact portion 32 is arranged corresponding to the second auxiliary electrode 42 and is electrically connected to the second auxiliary electrode 42. The channel portion 33 is arranged corresponding to the first interval 401 and is arranged opposite to at least part of the light shielding electrode 22. It should be noted that the corresponding arrangement in this application refers to the corresponding relationship between two structures in the thickness direction of the array substrate 100. The second insulating layer 12 is arranged on the side of the active layer 30 away from the substrate 10. The third conductive layer 50 is arranged on the side of the second insulating layer 12 away from the substrate 10, and the third conductive layer 50 includes a gate 51 arranged corresponding to the channel portion 33.

[0043] Part of the first auxiliary electrode 41 and part of the source contact portion 31 are located in the first via hole 111 and are electrically connected to the source electrode 21; the channel length L1 of the channel portion 33 is equal to the spacing distance D1 of the first spacing 401. In this way, the first spacing 401 between the first auxiliary electrode 41 and the second auxiliary electrode 42 can limit the length L1 of the channel portion 33 of the active layer 30 to achieve a narrow channel, thereby reducing the size of the thin film transistor and increasing the pixel density, so as to improve the problem of limited layout design space on the array substrate 100 and difficulty in achieving high resolution; moreover, the first auxiliary electrode 41 and the source contact portion 31 of the active layer 30 extend to the first via hole 111 of the first insulating layer 11 and are electrically connected to the source electrode 21 of the first conductive layer 20, and the first auxiliary electrode 41 located in the first via hole 111 can reduce the risk of the source contact portion 31 climbing and breaking in the first via hole 111.

[0044] Specifically, continue to refer to Figure 2 , the array substrate 100 further includes a first transistor disposed on the substrate 10. The first transistor may be a thin film transistor. The first transistor includes a source 21, an active layer 30, and a gate 51. The active layer 30 is disposed on a side of the source 21 away from the substrate 10, and the gate 51 is disposed on a side of the active layer 30 away from the substrate 10. The active layer 30 includes a source contact portion 31, a drain contact portion 32, and a channel portion 33 connected between the source contact portion 31 and the drain contact portion 32, that is, the drain contact portion 32 and the source contact portion 31 are located on opposite sides of the channel portion 33. The gate 51 is disposed opposite to the channel portion 33.

[0045] Optionally, the substrate 10 may be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, it may include a rigid substrate such as a glass substrate, a quartz substrate or a silicon wafer; when the substrate 10 is a flexible substrate, it may include a flexible substrate such as a polyimide (PI) film or an ultra-thin glass film. When the substrate 10 is a polyimide, moisture or oxygen may more easily penetrate into the substrate 10 compared to a glass substrate. To prevent this, a buffer layer having a single-layer or multi-layer structure including silicon oxide or silicon nitride may be provided on the substrate 10.

[0046] The first conductive layer 20 is disposed on the substrate 10. The first conductive layer 20 includes a source electrode 21 and a light shielding electrode 22 that are spaced and insulated, and a first spacer 401 is provided between the source electrode 21 and the light shielding electrode 22. The light shielding electrode 22 is at least disposed corresponding to the channel portion 33 to shield the channel portion 33 and reduce the photogenerated leakage current of the first transistor. The material of the first conductive layer 20 includes Mo, Al, Cu, Ti, etc., and the thickness of the first conductive layer 20 ranges from 1000 angstroms to 8000 angstroms, such as 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, 5000 angstroms, 6000 angstroms, 7000 angstroms, 8000 angstroms, etc.

[0047] The first insulating layer 11 covers the first conductive layer 20 and the substrate 10. The first insulating layer 11 covering the source 21 is formed with a first via 111 at a position corresponding to the source 21, and the first via 111 exposes a portion of the source 21. The first via 111 penetrates the first insulating layer 11 to expose at least a portion of the source 21. The material of the first insulating layer 11 includes silicon oxide (SiOx), silicon nitride (SiNx) or a silicon oxide and silicon nitride stacked film, and the thickness of the first insulating layer 11 ranges from 6000 angstroms to 10000 angstroms, such as 6000 angstroms, 7000 angstroms, 8000 angstroms, 9000 angstroms, 10000 angstroms, etc.

[0048] The second conductive layer 40 is arranged on a side of the first insulating layer 11 away from the substrate 10. The second conductive layer 40 includes a first auxiliary electrode 41 and a second auxiliary electrode 42 arranged at intervals, and a first interval 401 is provided between the first auxiliary electrode 41 and the second auxiliary electrode 42. The first auxiliary electrode 41 covers a portion of the upper surface of the first insulating layer 11 and extends from the upper surface of the first insulating layer 11 to the first via hole 111. In the first via hole 111, the first auxiliary electrode 41 covers the hole wall of the first via hole 111 and the source electrode 21 exposed by the first via hole 111, so that the first auxiliary electrode 41 contacts and is electrically connected with the source electrode 21, that is, the first auxiliary electrode 41 completely covers the hole wall and the hole bottom of the first via hole 111, so that the orthographic projection of the first via hole 111 on the substrate 10 is located within the orthographic projection of the first auxiliary electrode 41 on the substrate 10. The second auxiliary electrode 42 covers another portion of the upper surface of the first insulating layer 11. The material of the second conductive layer 40 includes at least one of conductive materials such as ITO, IZO, Cu, and Al. The thickness of the second conductive layer 40 ranges from 1000 angstroms to 5000 angstroms, such as 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, and 5000 angstroms.

[0049] For ease of description, the present application defines the surface of each structure away from the substrate 10 as the upper surface, the surface opposite to the upper surface as the lower surface, and the sidewall connecting the upper surface and the lower surface. For example, the upper surface of the first insulating layer 11 refers to the surface of the first insulating layer 11 away from the substrate 10, and the surface opposite to the upper surface of the first insulating layer 11 is the lower surface of the first insulating layer 11. The lower surface of the first insulating layer 11 is in contact with the substrate 10 and the first conductive layer 20.

[0050] The active layer 30 is arranged on the side of the second conductive layer 40 away from the substrate 10. The source contact 31 and the drain contact 32 of the active layer 30 are formed by conducting the active layer 30, so that the source contact 31 and the drain contact 32 of the active layer 30 form a conductor area. The material of the active layer 30 includes indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium gallium oxide (IGO), indium zinc oxide (IZO), lanthanide IZO, etc. The thickness of the active layer 30 is less than the thickness of the second conductive layer 40, for example, the thickness of the active layer 30 ranges from 400 angstroms to 1000 angstroms, for example, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, etc.

[0051] The source contact portion 31 is arranged corresponding to the first auxiliary electrode 41, and the drain contact portion 32 is arranged corresponding to the second auxiliary electrode 42. The channel portion 33 is arranged corresponding to the first interval 401 between the first auxiliary electrode 41 and the second auxiliary electrode 42, and the length L1 of the channel portion 33 is equal to the interval distance D1 of the first interval 401, that is, the length L1 of the channel portion 33 depends on the interval distance D1 of the first interval 401. In other words, the length L1 of the channel portion 33 can be limited by limiting the interval distance D1 between the first auxiliary electrode 41 and the second auxiliary electrode 42, so as to achieve a narrow channel, thereby reducing the size of the thin film transistor and improving the pixel density, so as to improve the problem that the layout design space on the array substrate 100 is limited and it is difficult to achieve high resolution. The length L1 of the channel portion 33 ranges from 0.5 micrometers to 3 micrometers, such as 0.5 micrometers, 0.8 micrometers, 1 micrometer, 1.2 micrometers, 1.5 micrometers, 1.8 micrometers, 2 micrometers, 2.3 micrometers, 2.6 micrometers, 2.9 micrometers, 3 micrometers, etc.

[0052] The source contact portion 31 covers the upper surface of the first auxiliary electrode 41, contacts and is electrically connected to the first auxiliary electrode 41. The drain contact portion 32 covers the upper surface of the second auxiliary electrode 42, contacts and is electrically connected to the second auxiliary electrode 42. Of course, the source contact portion 31 also covers the upper surface of the first auxiliary electrode 41 located in the first via hole 111, and the orthographic projection of the source contact portion 31 on the substrate 10 covers the orthographic projection of the first via hole 111 on the substrate 10. In the first via hole 111, the first auxiliary electrode 41 contacts and is electrically connected to the source 21, and the source contact portion 31 contacts and is electrically connected to the first auxiliary electrode 41, so that the source contact portion 31 is electrically connected to the source 21 through the first auxiliary electrode 41, thereby reducing the risk of the source contact portion 31 climbing and breaking in the first via hole 111. Thus, by providing the first auxiliary electrode 41 and the second auxiliary electrode 42 , a narrow channel is achieved, the size of the thin film transistor is reduced, and the pixel density is improved, while the risk of the source contact portion 31 climbing up and breaking in the first via hole 111 can be reduced.

[0053] It should be noted that the film thickness of the first insulating layer 11 is relatively large, and the film thickness of the active layer 30 is relatively small, and the film thickness of the active layer 30 is much smaller than the film thickness of the first insulating layer 11. When the aperture size of the first via hole 111 is relatively small, due to the relatively large film thickness of the first insulating layer 11, the taper angle of the first via hole 111 is relatively large, and the active layer 30' with a relatively thin film thickness is prone to problems such as disconnection when climbing in the first via hole 111, thereby affecting the reliability of the electrical connection between the source contact portion 31 and the source 21. In order to improve the problems such as disconnection when the active layer 30 climbs in the first via hole 111, the first via hole 111 with a relatively large aperture can be provided, for example, the aperture of the first via hole 111 is greater than 2 microns, but this will increase the occupied area of ​​the first transistor device.

[0054] In the present embodiment, by extending the first auxiliary electrode 41 into the first via hole 111 and making the source contact portion 31 cover the first auxiliary electrode 41 in the first via hole 111, even if the source contact portion 31 is broken while climbing in the first via hole 111, the first auxiliary electrode 41 can fill the broken part of the source contact portion 31, thereby improving the reliability of the electrical connection between the source contact portion 31 and the source 21, so that the first via hole 111 with a smaller aperture can be set to achieve high-reliability electrical connection between the source contact portion 31 and the source 21, thereby further reducing the size of the thin film transistor, reducing the occupied area of ​​the first transistor device, and further improving the pixel density.

[0055] The second insulating layer 12 is disposed on a side of the active layer 30 away from the substrate 10, and is disposed corresponding to the channel portion 33. The material of the second insulating layer 12 includes an inorganic material, for example, the second insulating layer 12 may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide, etc. The thickness of the second insulating layer 12 ranges from 1000 angstroms to 3000 angstroms, for example, 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, etc.

[0056] The third conductive layer 50 is arranged on the side of the second insulating layer 12 away from the substrate 10, and the third conductive layer 50 includes a gate 51 of the first transistor, and the gate 51 is arranged corresponding to the second insulating layer 12. The third conductive layer 50 can be formed as a plurality of layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni or their alloys, or a material with high corrosion resistance. For example, the third conductive layer 50 can be a stack of Moti / Cu, Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti or Mo / Al / Mo and others. The thickness of the third conductive layer 50 ranges from 2000 angstroms to 8000 angstroms, such as 2000 angstroms, 3000 angstroms, 4000 angstroms, 5000 angstroms, 6000 angstroms, 7000 angstroms, 8000 angstroms, etc.

[0057] The orthographic projection of the gate 51 on the substrate 10 covers the orthographic projection of the channel portion 33 on the substrate 10, that is, the orthographic projection of the channel portion 33 on the substrate 10 is located within the orthographic projection of the gate 51 on the substrate 10, and the orthographic projection area of ​​the channel portion 33 is smaller than the orthographic projection area of ​​the gate 51. The channel portion 33 is located in the area defined by the first interval 401 of the first auxiliary electrode 41 and the second auxiliary electrode 42, so that the orthographic projection of the gate 51 on the substrate 10 also covers part of the orthographic projection of the first auxiliary electrode 41 and the second auxiliary electrode 42 on the substrate 10, that is, the orthographic projection of the first auxiliary electrode 41 and the second auxiliary electrode 42 on the substrate 10 partially overlaps with the orthographic projection of the gate 51 on the substrate 10, so that the size of the channel portion 33 does not need to be limited by the size of the gate 51, which can reduce the difficulty of manufacturing the gate 51 and facilitate the implementation of the process. The active layer 30 located in the overlapping area between the first auxiliary electrode 41 , the second auxiliary electrode 42 and the gate 51 does not serve as the channel portion 33 of the active layer 30 . The channel portion 33 is only located in the first gap 401 between the first auxiliary electrode 41 and the second auxiliary electrode 42 .

[0058] Continue to refer to Figure 2, the array substrate 100 further includes a third insulating layer 13, a planarization layer 14, a common electrode 60, a fourth insulating layer 15 and a pixel electrode 70. The third insulating layer 13 is disposed on a side of the third conductive layer 50 away from the substrate 10, for example, the third insulating layer 13 covers the upper surface and sidewall of the gate 51, the sidewall of the second insulating layer 12, the upper surface and sidewall of the source contact portion 31, the upper surface and sidewall of the drain contact portion 32 and part of the first insulating layer 11. The material of the third insulating layer 13 includes an inorganic material, for example, the third insulating layer 13 may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0059] The planarization layer 14 is disposed on a side of the third insulating layer 13 away from the substrate 10. The material of the planarization layer 14 includes an organic material, for example, the planarization layer 14 can be formed to include a resin, such as polyacrylate or polyimide, a silica-based organic material, and the like.

[0060] The common electrode 60 is disposed on a side of the planarization layer 14 away from the substrate 10. The common electrode 60 may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In2O3).

[0061] The fourth insulating layer 15 is disposed on a side of the common electrode 60 away from the substrate 10. The fourth insulating layer 15 includes a third via hole 151 disposed corresponding to the drain contact portion 32, and the third via hole 151 penetrates the fourth insulating layer 15, the planarization layer 14 and the third insulating layer 13 to expose a portion of the drain contact portion 32. The material of the fourth insulating layer 15 includes an inorganic material, for example, the fourth insulating layer 15 may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0062] The first pixel electrode 70 is disposed on a side of the fourth insulating layer 15 away from the substrate 10, and the pixel electrode 70 contacts and is electrically connected to the drain contact portion 32 through the third via hole 151, that is, part of the pixel electrode 70 is located in the third via hole 151, and contacts and is electrically connected to the drain contact portion 32 exposed by the third via hole 151. The pixel electrode 70 is disposed opposite to the common electrode 60, and the material of the pixel electrode 70 can be the same as that of the common electrode 60, for example, the pixel electrode 70 can also be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In2O3).

[0063] In one embodiment, please refer to Figure 3 , Figure 3 This is a schematic diagram of a second cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 3 ,and Figure 2 The difference of the exemplary embodiment is that the orthographic projection of the gate 51 on the substrate 10 coincides with the orthographic projection of the channel portion 33 on the substrate 10. For other explanations, please refer to the above embodiment, which will not be repeated here.

[0064] In one embodiment, please refer to Figure 4 , Figure 4 This is a schematic diagram of a third cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 4 ,and Figure 2 The difference between the exemplary embodiments is that a second via hole 112 is provided in the first insulating layer 11 at a position corresponding to the light-shielding electrode 22, and part of the second auxiliary electrode 42 and part of the drain contact portion 32 are located in the second via hole 112 and are electrically connected to the light-shielding electrode 22, so as to improve the stability of the first transistor and reduce the risk of the drain contact portion 32 climbing and breaking in the second via hole 112.

[0065] Specifically, the second auxiliary electrode 42 is covered on another portion of the upper surface of the first insulating layer 11, and extends from the upper surface of the first insulating layer 11 to the second via hole 112. In the second via hole 112, the second auxiliary electrode 42 covers the hole wall of the second via hole 112 and the light-shielding electrode 22 exposed by the second via hole 112, so that the second auxiliary electrode 42 is in contact with and electrically connected to the light-shielding electrode 22, that is, the second auxiliary electrode 42 completely covers the hole wall and the bottom of the second via hole 112, so that the orthographic projection of the second via hole 112 on the substrate 10 is located within the orthographic projection of the second auxiliary electrode 42 on the substrate 10.

[0066] The drain contact portion 32 covers the upper surface of the second auxiliary electrode 42, contacts and is electrically connected to the second auxiliary electrode 42. Of course, the drain contact portion 32 also covers the upper surface of the second auxiliary electrode 42 located in the second via hole 112. In the second via hole 112, the second auxiliary electrode 42 contacts and is electrically connected to the light shielding electrode 22, and the drain contact portion 32 contacts and is electrically connected to the second auxiliary electrode 42, so that the drain contact portion 32 is electrically connected to the light shielding electrode 22 through the second auxiliary electrode 42, thereby reducing the risk of the drain contact portion 32 climbing and breaking in the second via hole 112. For other descriptions, please refer to the above embodiment, which will not be repeated here.

[0067] In one embodiment, please refer to Figure 5 , Figure 5 This is a schematic diagram of a fourth cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 5 ,and Figure 4 The difference of the exemplary embodiment is that the second conductive layer 40 is disposed on a side of the active layer 30 away from the substrate 10 , and part of the source contact portion 31 is located in the first via hole 111 and electrically connected to the source 21 .

[0068] Specifically, the active layer 30 covers the upper surface of the first insulating layer 11, and extends from the upper surface of the first insulating layer 11 to the first via hole 111 and the second via hole 112. More specifically, the source contact portion 31 covers a portion of the upper surface of the first insulating layer 11, and extends from the upper surface of the first insulating layer 11 to the first via hole 111. In the first via hole 111, the source contact portion 31 covers the hole wall of the first via hole 111 and the source 21 exposed by the first via hole 111, so that the source contact portion 31 contacts and is electrically connected to the source 21, that is, the source contact portion 31 completely covers the hole wall and the hole bottom of the first via hole 111, so that the orthographic projection of the first via hole 111 on the substrate 10 is located within the orthographic projection of the source contact portion 31 on the substrate 10, and further, the source contact portion 31 contacts and is electrically connected to the source 21 through the first via hole 111.

[0069] Correspondingly, the drain contact portion 32 covers another portion of the upper surface of the first insulating layer 11, and extends from the upper surface of the first insulating layer 11 to the second via hole 112. In the second via hole 112, the drain contact portion 32 covers the hole wall of the second via hole 112 and the light-shielding electrode 22 exposed by the second via hole 112, so that the drain contact portion 32 is in contact with and electrically connected to the light-shielding electrode 22, so that the drain contact portion 32 is in contact with and electrically connected to the light-shielding electrode 22 through the second via hole 112.

[0070] The second conductive layer 40 is disposed on a side of the active layer 30 away from the substrate 10. The second conductive layer 40 includes a first auxiliary electrode 41 and a second auxiliary electrode 42 disposed at intervals. The channel portion 33 of the active layer 30 covers the upper surface of the first insulating layer 11 and is disposed corresponding to the first interval 401 between the first auxiliary electrode 41 and the second auxiliary electrode 42. The length L1 of the channel portion 33 is equal to the interval distance D1 of the first interval 401. That is, the length L1 of the channel portion 33 depends on the interval distance D1 of the first interval 401. In other words, the length L1 of the channel portion 33 can be limited by limiting the interval distance D1 between the first auxiliary electrode 41 and the second auxiliary electrode 42 to achieve a narrow channel, thereby reducing the size of the thin film transistor and increasing the pixel density, so as to improve the problem that the layout design space on the array substrate 100 is limited and it is difficult to achieve high resolution.

[0071] The first auxiliary electrode 41 covers the upper surface of the source contact 31, and the second auxiliary electrode 42 covers the upper surface of the drain contact 32. Of course, the first auxiliary electrode 41 also covers the upper surface of the source contact 31 located in the first via hole 111. In the first via hole 111, the source contact 31 contacts and is electrically connected to the source 21, and the first auxiliary electrode 41 contacts and is electrically connected to the source contact 31, thereby reducing the risk of the source contact 31 climbing up and breaking in the first via hole 111. Correspondingly, the second auxiliary electrode 42 also covers the upper surface of the drain contact 32 located in the second via hole 112. In the second via hole 112, the drain contact 32 contacts and is electrically connected to the light shielding electrode 22, and the second auxiliary electrode 42 contacts and is electrically connected to the drain contact 32, thereby reducing the risk of the drain contact 32 climbing up and breaking in the second via hole 112. In this way, by providing the second conductive layer 40 including the first auxiliary electrode 41 and the second auxiliary electrode 42 above the active layer 30, while realizing a narrow channel, reducing the size of the thin film transistor, and improving the pixel density, the risk of the source contact part 31 climbing up and breaking in the first via hole 111 and the risk of the drain contact part 32 climbing up and breaking in the second via hole 112 can be reduced.

[0072] In addition, Figure 4The difference of the exemplary embodiment also includes: the second insulating layer 12 covers part of the upper surface and sidewall of the first auxiliary electrode 41, and part of the upper surface and sidewall of the second auxiliary electrode 42. The pixel electrode 70 contacts and is electrically connected to the second auxiliary electrode 42 through the third via hole 151, that is, the third via hole 151 exposes part of the second auxiliary electrode 42, and part of the pixel electrode 70 is located in the third via hole 151, and contacts and is electrically connected to the second auxiliary electrode 42 exposed by the third via hole 151. In this way, the pixel electrode 70 is electrically connected to the drain contact portion 32 through the second auxiliary electrode 42, thereby reducing the contact impedance between the pixel electrode 70 and the drain contact portion 32 and improving the stability of the electrical connection between the pixel electrode 70 and the drain contact portion 32. For other descriptions, please refer to the above embodiment, which will not be repeated here.

[0073] In one embodiment, please refer to Figure 6 , Figure 6 This is a schematic diagram of a fifth cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 6 ,and Figure 5 The difference of the exemplary embodiment is that the third via hole 151 is arranged corresponding to the second via hole 112, and the pixel electrode 70 located in the third via hole 151 is also located in the second via hole 112, so as to increase the contact area between the pixel electrode 70 and the second auxiliary electrode 42, thereby further reducing the contact impedance between the pixel electrode 70 and the drain contact portion 32, and further improving the stability of the electrical connection between the pixel electrode 70 and the drain contact portion 32. For other descriptions, please refer to the above embodiment, which will not be repeated here.

[0074] Based on the same inventive concept, the present application also provides a display panel, which includes the array substrate 100 of one of the above embodiments. The display panel includes a liquid crystal display panel, an organic light emitting diode display panel or other types of display panels.

[0075] According to the above embodiments, it can be seen that:

[0076] The present application provides an array substrate and a display panel, wherein the array substrate includes a substrate and a first conductive layer, a first insulating layer, a second conductive layer and an active layer arranged on the substrate, the second conductive layer includes a first auxiliary electrode and a second auxiliary electrode arranged at intervals, and the first interval between the first auxiliary electrode and the second auxiliary electrode can limit the length of the channel portion of the active layer to achieve a narrow channel, thereby reducing the size of the thin film transistor and improving the pixel density to improve the problem of limited layout design space on the array substrate and difficulty in achieving high resolution; moreover, the first auxiliary electrode and the source contact portion of the active layer extend to the first via hole of the first insulating layer and are electrically connected to the source of the first conductive layer, and the first auxiliary electrode located in the first via hole can reduce the risk of the source contact portion climbing and breaking in the first via hole.

[0077] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0078] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first conductive layer, disposed on one side of the substrate, the first conductive layer comprising a source electrode and a light shielding electrode disposed at intervals; A first insulating layer is disposed on a side of the first conductive layer away from the substrate, and the first insulating layer is provided with a first via hole at a position corresponding to the source electrode; A second conductive layer is disposed on a side of the first insulating layer away from the substrate, the second conductive layer comprises a first auxiliary electrode and a second auxiliary electrode which are spaced apart, and a first interval is formed between the first auxiliary electrode and the second auxiliary electrode; an active layer, arranged on a side of the first insulating layer away from the substrate, the active layer comprising a source contact portion, a drain contact portion, and a channel portion connected between the source contact portion and the drain contact portion, the source contact portion being arranged corresponding to the first auxiliary electrode and being electrically connected to the first auxiliary electrode, the drain contact portion being arranged corresponding to the second auxiliary electrode and being electrically connected to the second auxiliary electrode, the channel portion being arranged corresponding to the first interval and being arranged opposite to at least part of the light shielding electrode; A second insulating layer is disposed on a side of the active layer away from the substrate; A third conductive layer is disposed on a side of the second insulating layer away from the substrate, the third conductive layer comprising a gate disposed corresponding to the channel portion; Part of the first auxiliary electrode and part of the source contact portion are located in the first via hole and are electrically connected to the source; and a channel length of the channel portion is equal to a spacing distance of the first spacing.

2. The array substrate according to claim 1, characterized in that: The orthographic projection of the first auxiliary electrode on the substrate covers the orthographic projection of the first via hole on the substrate, and the orthographic projection of the source contact portion on the substrate covers the orthographic projection of the first via hole on the substrate.

3. The array substrate according to claim 2, characterized in that: The active layer is disposed on a side of the second conductive layer away from the substrate, and a portion of the first auxiliary electrode is located in the first via hole and is electrically connected to the source electrode.

4. The array substrate according to claim 2, characterized in that: The second conductive layer is disposed on a side of the active layer away from the substrate, and a portion of the source contact portion is located in the first via hole and is electrically connected to the source.

5. The array substrate according to claim 2, characterized in that: The material of the second conductive layer includes at least one of 1TO, IZO, Cu, and Al.

6. The array substrate according to claim 1, characterized in that: An orthographic projection of the gate on the substrate coincides with an orthographic projection of the channel portion on the substrate.

7. The array substrate according to claim 1, characterized in that: The orthographic projection of the channel portion on the substrate is located within the orthographic projection of the gate on the substrate, and the orthographic projection of the gate on the substrate partially overlaps with the orthographic projections of the first auxiliary electrode and the second auxiliary electrode on the substrate.

8. The array substrate according to claim 7, characterized in that: The length of the channel portion ranges from 0.5 micrometers to 3 micrometers.

9. The array substrate according to any one of claims 1 to 8, characterized in that: The first insulating layer is provided with a second via hole at a position corresponding to the light-shielding electrode, and a portion of the second auxiliary electrode and a portion of the drain contact portion are located in the second via hole and are electrically connected to the light-shielding electrode.

10. The array substrate according to claim 9, characterized in that: The array substrate further includes: A third insulating layer is disposed on a side of the third conductive layer away from the substrate; A planarization layer, disposed on a side of the third insulating layer away from the substrate; A common electrode is disposed on a side of the planarization layer away from the substrate; a fourth insulating layer, disposed on a side of the common electrode away from the substrate, wherein the fourth insulating layer is provided with a third via hole at a position corresponding to the drain contact portion; A pixel electrode is arranged on a side of the fourth insulating layer away from the substrate and is arranged opposite to the common electrode. A portion of the pixel electrode is located in the third via hole and is electrically connected to the drain contact portion.

11. The array substrate according to claim 10, characterized in that: The third via hole is arranged corresponding to the second via hole, and the pixel electrode located in the third via hole is also located in the second via hole.

12. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 11.

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