Image sensor

Abstract

An image sensor includes: a substrate including a first surface and a second surface facing the first surface; a first photodiode in a first region of the substrate and generating photocharges from light incident on the first region; a second photodiode in a second region of the substrate and generating photocharges from light incident on the second region; and an isolation structure defining the first region where the first photodiode is located and the second region where the second photodiode is located, and extending between the first photodiode and the second photodiode. The area of the second region is smaller than that of the first region, a first end of the isolation structure is coplanar with the second surface, and the isolation structure extends from the second surface of the substrate to the first surface of the substrate in a vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a divisional application of a patent application with application date of January 6, 2022, application number 202210009703.5, and title “Image Sensor”. Technical Field

[0003] The inventive concept relates to an image sensor, and more particularly, to a complementary metal oxide semiconductor (CMOS) image sensor. Background Art

[0004] An LED flicker mitigation (LFM) image sensor may have a wide dynamic range (WDR). To achieve WDR, an LFM image sensor may include a plurality of photodiodes with different sensitivities. The photodiodes receive light and generate photocharges. Under high illumination, the photocharges generated by one photodiode may move toward an adjacent photodiode with a different sensitivity. The blooming phenomenon between photodiodes with different sensitivities may distort the image. Summary of the invention

[0005] The inventive concept provides an image sensor with reduced blooming for a wider wide dynamic range (WDR) and a higher signal-to-noise ratio (SNR).

[0006] According to one aspect of the present inventive concept, there is provided an image sensor, the image sensor comprising: a substrate, the substrate comprising a first surface and a second surface facing the first surface; a first photodiode, the first photodiode being located in a first region of the substrate and generating photocharges from light incident on the first region of the first surface; a second photodiode, the second photodiode being located in a second region of the substrate and generating photocharges from light incident on the second region of the first surface; and an isolation structure, the isolation structure defining the first region where the first photodiode is located and the second region where the second photodiode is located, and extending between the first photodiode and the second photodiode. The area of ​​the second region is smaller than the area of ​​the first region, the first end of the isolation structure is coplanar with the second surface, and the isolation structure extends in a vertical direction from the second surface of the substrate toward the first surface of the substrate.

[0007] According to one aspect of the inventive concept, there is provided an image sensor, the image sensor comprising: a substrate, the substrate comprising a first surface and a second surface facing the first surface; a first sensitivity photodiode, the first sensitivity photodiode being disposed in the substrate and having a first sensitivity; a second sensitivity photodiode, the second sensitivity photodiode being disposed in the substrate and having a second sensitivity lower than the first sensitivity of the first sensitivity photodiode; and an isolation structure, the isolation structure being configured to electrically isolate the first sensitivity photodiode and the second sensitivity photodiode from each other. The isolation structure completely penetrates the substrate from the second surface of the substrate to the first surface of the substrate in a vertical direction.

[0008] According to one aspect of the present inventive concept, there is provided an image sensor, the image sensor comprising: a substrate, the substrate comprising a first surface and a second surface facing each other; a first microlens, the first microlens being located on a first area of ​​the first surface; a second microlens, the second microlens being located on a second area of ​​the first surface; a first photodiode, the first photodiode being located in a portion of the substrate below the first microlens; a second photodiode, the second photodiode being located in a portion of the substrate below the second microlens; an isolation structure, the isolation structure extending in a vertical direction from the second surface toward the first surface and surrounding each of the first photodiode and the second photodiode; a first transfer gate, the first transfer gate extending from the second surface of the substrate into the substrate and electrically connected to the first photodiode; and a second transfer gate, the second transfer gate extending from the second surface of the substrate into the substrate and electrically connected to the second photodiode. The area of ​​the second microlens is smaller than the area of ​​the first microlens. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of an image sensor according to an embodiment of the inventive concept;

[0011] Figure 2 is a circuit diagram of a pixel included in an image sensor according to an embodiment of the inventive concept;

[0012] Figure 3 is a circuit diagram of a pixel included in an image sensor according to an embodiment of the inventive concept;

[0013] Figure 4is a top view of an image sensor according to an embodiment of the inventive concept;

[0014] Figure 5 It is along Figure 4 A cross-sectional view of an image sensor according to an embodiment of the inventive concept, taken along line AA′;

[0015] Figure 6 It is along Figure 4 A cross-sectional view of an image sensor according to an embodiment of the inventive concept, taken along line BB′;

[0016] Figure 7 is a top view of an image sensor according to an embodiment of the inventive concept;

[0017] Figure 8 is a top view of an image sensor according to an embodiment of the inventive concept;

[0018] Fig. 9 It is along Figure 4 A cross-sectional view of an image sensor according to an embodiment of the inventive concept, taken along line AA′;

[0019] Fig.10 It is along Figure 4 A cross-sectional view of an image sensor according to an embodiment of the inventive concept, taken along line BB′;

[0020] FIG. 11A to FIG. 11C is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment of the inventive concept; and

[0021] FIG. 12A to FIG. 12F is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0022] Figure 1 is a block diagram of an image sensor 100 according to an embodiment of the inventive concept.

[0023] The image sensor 100 may be mounted on an electronic device. For example, the image sensor 100 may be mounted on an electronic device such as a camera, a smart phone, a wearable device, an Internet of Things (IoT) device, a home appliance, a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation device, a drone, and an advanced driver assistance system (ADAS).

[0024] refer to Figure 1, the image sensor 100 may include a pixel array 1110, a row driver 1120, a readout circuit 1130, a ramp signal generator 1140, a timing controller 1150, and a signal processor 1190. The readout circuit 1130 may include an analog-to-digital conversion (ADC) circuit 1131 and a data bus 1132.

[0025] The pixel array 1110 may include a plurality of pixels PX arranged in rows and columns. Each pixel PX may convert light into an electrical signal. The pixel array 1110 may be connected to a plurality of row lines RoL and a plurality of column lines CL.

[0026] The row driver 1120 drives the pixel array 1110 row by row. The row driver 1120 may decode a row control signal (e.g., an address signal) received from the timing controller 1150 and select at least one of the row lines RoL in response to the decoded row control signal. For example, the row driver 1120 may generate a selection signal for selecting at least one of the row lines RoL. The pixel array 1110 outputs a pixel signal, such as a pixel voltage, from a row of pixels PX selected by the selection signal provided from the row driver 1120.

[0027] The ramp signal generator 1140 may generate a ramp signal RAMP that increases or decreases at a predetermined slope. In some embodiments, the voltage level of the ramp signal RAMP may increase or decrease at a predetermined slope. The ramp signal generator 1140 may provide the ramp signal RAMP to the ADC circuit 1131 of the readout circuit 1130.

[0028] The readout circuit 1130 may read out pixel signals from the pixels PX of the row selected by the row driver 1120 among the pixels PX. The pixel signal may include a reset signal or an image signal (or a sensing signal). The readout circuit 1130 may convert the reset signal and the image signal received from the pixel array 1110 through the column line CL into digital data based on the ramp signal RAMP from the ramp signal generator 1140, thereby generating and outputting pixel values ​​corresponding to the pixels PX row by row.

[0029] The ADC circuit 1131 may convert a pixel signal (e.g., a pixel voltage) received from the pixel array 1110 into a pixel value as a digital signal. The ADC circuit 1131 may include a plurality of ADCs corresponding to the column lines CL, respectively, and these ADCs may compare the reset signal and the image signal received from the respectively corresponding column lines CL with the ramp signal RAMP and generate a pixel value based on the result of such comparison. For example, the ADC may remove the reset signal from the image signal and generate a pixel value indicating the amount of light detected by the pixel PX.

[0030] The ADC circuit 1131 may include a plurality of correlated double sampling (CDS) circuits and a plurality of counter circuits. The CDS circuit may compare the pixel signal received through the column line CL with the ramp signal RAMP and output the result of the comparison. The CDS circuit may sample and hold the pixel signal provided by the pixel PX according to the CDS scheme, double sample the level of a specific noise (e.g., a reset signal) and the level according to the image signal, and generate a comparison signal based on a level corresponding to the difference between the level of the specific noise and the level of the image signal. In some embodiments, the CDS circuit may include one or more comparators. The comparator may be implemented as an operational transconductance amplifier (OTA) (or a differential amplifier). The ADC circuit 1131 may include a plurality of incremental reset sampling (DRS) circuits. The DRS circuit may sample the pixel signal by reading out the image signal according to the DRS scheme and then reading out the reset signal.

[0031] The multiple pixel values ​​generated by the ADC circuit 1131 can be output as image data IDT through the data bus 1132. The data bus 1132 can temporarily store the pixel values ​​output from the ADC circuit 1131 and then output them. The data bus 1132 may include multiple column memories (e.g., multiple buffer memories) and a column decoder. For example, each pixel in the column may be coupled to a corresponding column memory. The multiple pixel values ​​stored in the column memory may be output as image data IDT under the control of the column decoder. For example, the image data IDT may be provided to a signal processor 1190 inside or outside the image sensor 100.

[0032] In some embodiments, the image sensor 100 may further include a bias current controller (not shown) for increasing or decreasing the bias current when the operation mode of the pixel PX changes during the readout period. A plurality of bias current controllers may be connected to the column lines CL, respectively.

[0033] The signal processor 1190 may perform various operations on the image data IDT, such as noise reduction processing, gain adjustment, waveform formulation, interpolation processing, white balance processing, gamma processing, and edge emphasis processing. In some embodiments, the pixel array 1110 may operate in multiple modes during one frame period, and the signal processor 1190 may receive multiple pieces of image data IDT corresponding to these modes from the data bus 1132, and merge the multiple pieces of image data IDT to generate an image with a high dynamic range. In some embodiments, the signal processor 1190 may be provided in a processor outside the image sensor 100.

[0034] Figure 2 is a circuit diagram of a pixel PX included in an image sensor according to an embodiment of the inventive concept.

[0035] The pixel PX may include a plurality of photodiodes, such as a first photodiode LPD and a second photodiode SPD. The pixel PX may also include a first transfer gate LTG, a second transfer gate STG, a reset transistor RG, a drive transistor DX, a selection transistor SX, a gain control transistor DRG, and a switch transistor SW. The pixel PX may also include a plurality of floating diffusion regions, such as a first floating diffusion region FD1, a second floating diffusion region FD2, and a third floating diffusion region FD3. The pixel PX may also include a capacitor C1.

[0036] The first photodiode LPD and the second photodiode SPD may generate photocharges in response to incident light. For example, the photocharges may include electrons and holes. The first photodiode LPD and the second photodiode SPD may have different sensitivities. For example, the sensitivity of the first photodiode LPD may be higher than the sensitivity of the second photodiode SPD. As described above, a structure in which one pixel PX includes a first photodiode LPD and a second photodiode SPD with different sensitivities may be referred to as a split photodiode structure.

[0037] A first source / drain of the first transfer gate LTG may be connected to the first photodiode LPD, and a second source / drain of the first transfer gate LTG may be connected to the first floating diffusion region FD1. The first transfer gate LTG may transfer photocharges generated by the first photodiode LPD to the first floating diffusion region FD1 in response to a first transfer control signal LTS.

[0038] The first source / drain of the gain control transistor DRG may be connected to the first floating diffusion region FD1, and the second source / drain of the gain control transistor DRG may be connected to the second floating diffusion region FD2. The gain control transistor DRG may be turned on or off by a conversion gain signal CGS. When the gain control transistor DRG is turned on, the first floating diffusion region FD1 and the second floating diffusion region FD2 are connected to each other. The first floating diffusion region FD1 and the second floating diffusion region FD2 are connected to each other to form a connected floating diffusion region, and each of the first photodiode LPD and the second photodiode SPD may transfer photocharges to the connected floating diffusion region. The connected floating diffusion region may have an increased capacitance compared to if the first floating diffusion region FD1 and the second floating diffusion region FD2 are not connected to each other. When the capacitance increases, the conversion gain of each of the first photodiode LPD and the second photodiode SPD may decrease. In contrast, when the gain control transistor DRG is turned off, the first floating diffusion region FD1 and the second floating diffusion region FD2 are separated from each other, and the capacitance of each of the first floating diffusion region FD1 and the second floating diffusion region FD2 is reduced compared to if the first floating diffusion region FD1 and the second floating diffusion region FD2 are connected to each other, and thus, the conversion gain of each of the first photodiode LPD and the second photodiode SPD can be increased compared to if the first floating diffusion region FD1 and the second floating diffusion region FD2 are connected to each other. Here, the conversion gain refers to the rate at which the charge accumulated in the floating diffusion region is converted into a voltage. When the capacitance increases, the conversion gain decreases.

[0039] The first source / drain of the second transfer gate STG may be connected to the second photodiode SPD, and the second source / drain of the second transfer gate STG may be connected to the third floating diffusion area FD3. The second transfer gate STG may transfer the photocharges generated by the second photodiode SPD to the third floating diffusion area FD3 in response to the second transfer control signal STS.

[0040] The first electrode of the capacitor C1 may be connected to the third floating diffusion region FD3, and the second electrode of the capacitor C1 may be connected to the pixel voltage VPIX. In an embodiment, a voltage other than the pixel voltage VPIX may be applied to the second electrode of the capacitor C1. Photocharges generated by the second photodiode SPD and overflowing from the second photodiode SPD may be accumulated in the capacitor C1.

[0041] A first source / drain of the switch transistor SW may be connected to the second floating diffusion region FD2, and a second source / drain of the switch transistor SW may be connected to the third floating diffusion region FD3. The switch transistor SW may connect the second floating diffusion region FD2 and the third floating diffusion region FD3 to each other in response to a switch control signal SWS.

[0042] A reset voltage (e.g., pixel voltage VPIX) may be applied to a first source / drain of the reset transistor RG, and a second source / drain of the reset transistor RG may be connected to the second floating diffusion region FD2. The reset transistor RG may reset photocharges accumulated in at least one of the first floating diffusion region FD1, the second floating diffusion region FD2, and the third floating diffusion region FD3 in response to a reset control signal RS. In an embodiment, the reset voltage may be different from the pixel voltage VPIX.

[0043] A first source / drain of the drive transistor DX may be connected to the selection transistor SX, and a drive voltage (e.g., a pixel voltage VPIX) is applied to a second source / drain of the drive transistor DX. The drive transistor DX may operate as a source follower based on a bias current IL generated by a current source CS connected to a column line CL. The drive transistor DX may output a voltage corresponding to an amount of charge accumulated in at least one of the first floating diffusion region FD1, the second floating diffusion region FD2, and the third floating diffusion region FD3.

[0044] A first source / drain of the selection transistor SX may be connected to the drive transistor DX, and a second source / drain of the selection transistor SX may be connected to the column line CL. The selection transistor SX may output a pixel signal including a reset signal or an image signal to the column line CL in response to a selection signal SEL.

[0045] According to an embodiment of the present invention, the photocharge generated by the first photodiode LPD can be read out in a high conversion gain (HCG) mode or a low conversion gain (LCG) mode according to the conversion gain signal CGS. For example, in the HCG mode, the conversion gain signal CGS may have an invalid level, and the gain control transistor DRG may be turned off. Therefore, the first floating diffusion region FD1 and the second floating diffusion region FD2 may not be connected to each other. In the LCG mode, the conversion gain signal CGS may have an effective level, and the gain control transistor DRG may be turned on. Therefore, the first floating diffusion region FD1 and the second floating diffusion region FD2 may be connected to each other and the capacitance may increase, so the conversion gain may be reduced.

[0046] The photocharges generated by the second photodiode SPD may be read out in a first mode for reading out the photocharges accumulated in the second photodiode SPD or in a second mode for reading out the photocharges overflowing from the second photodiode SPD and stored in the capacitor C1.

[0047] The first photodiode LPD may generate a first pixel signal corresponding to a first illumination interval corresponding to the lowest illumination in the HCG mode and a second pixel signal corresponding to a second illumination interval corresponding to an illumination higher than the first illumination interval in the LCG mode. The second photodiode SPD may generate a third pixel signal corresponding to a third illumination interval corresponding to an illumination higher than the second illumination interval in the first mode and a fourth pixel signal corresponding to a fourth illumination interval corresponding to the highest illumination in the second mode. The first to fourth pixel signals may be merged into one image, and the merged image may have a high dynamic range. In addition, when the exposure time of the second photodiode SPD is increased, LED flicker suppression (LFM) may be achieved.

[0048] Figure 3 is a circuit diagram of a pixel PXa included in an image sensor according to an embodiment of the inventive concept. Figure 2 The pixel PX shown is Figure 3 The differences between pixels PXa are shown.

[0049] The pixel PXa may include a first switching transistor SW1 and a second switching transistor SW2 instead of Figure 2 The switching transistor SW is shown. The pixel PXa may further include a fourth floating diffusion region FD4.

[0050] The first source / drain of the second transfer gate STG may be connected to the second photodiode SPD, and the second source / drain of the second transfer gate STG may be connected to the fourth floating diffusion area FD4. The second transfer gate STG may transfer the photocharges generated by the second photodiode SPD to the fourth floating diffusion area FD4 in response to the second transfer control signal STS.

[0051] The first source / drain of the first switch transistor SW1 may be connected to the third floating diffusion region FD3, and the second source / drain of the first switch transistor SW1 may be connected to the fourth floating diffusion region FD4. The first switch transistor SW1 may connect the third floating diffusion region FD3 and the fourth floating diffusion region FD4 to each other in response to the first switch control signal SWS1. When the third floating diffusion region FD3 and the fourth floating diffusion region FD4 are connected to each other, capacitance may increase and conversion gain may decrease.

[0052] The first source / drain of the second switch transistor SW2 may be connected to the fourth floating diffusion region FD4, and the second source / drain of the second switch transistor SW2 may be connected to the second floating diffusion region FD2. The second switch transistor SW2 may connect the second floating diffusion region FD2 and the fourth floating diffusion region FD4 to each other in response to the second switch control signal SWS2.

[0053] According to an embodiment of the present invention, when the photocharge generated by the second photodiode SPD is read out in the first mode, the first switch control signal SWS1 may have an invalid level, and the first switch transistor SW1 may be turned off. Therefore, the third floating diffusion region FD3 and the fourth floating diffusion region FD4 may not be connected to each other, and the conversion gain may be relatively high in the first mode. When the photocharge generated by the second photodiode SPD is read out in the second mode, the first switch control signal SWS1 may have an effective level, and the first switch transistor SW1 may be turned on. Therefore, since the third floating diffusion region FD3 and the fourth floating diffusion region FD4 may be connected to each other, the capacitance may increase, and the conversion gain may be relatively low in the second mode.

[0054] The dynamic range can be further widened by using capacitor C1 with high capacitance in the second mode. Figure 2 In the embodiment shown, capacitor C1 having a high capacitance will reduce the conversion gain and thus reduce the signal-to-noise ratio (SNR). Figure 3 In the illustrated embodiment, by separating the capacitor C1 having high capacitance from the fourth floating diffusion region FD4 using the first switching transistor SW1, a reduction in conversion gain due to the capacitor C1 having high capacitance can be prevented. Therefore, due to the high conversion gain in the first mode, the SNR can be increased.

[0055] Figure 4 is a top view of an image sensor 100 according to an embodiment of the inventive concept. Figure 5 It is along Figure 4 1 is a cross-sectional view of the image sensor 100 according to an embodiment of the inventive concept, taken along line AA′. Figure 6 It is along Figure 4 1 is a cross-sectional view of the image sensor 100 according to an embodiment of the inventive concept, taken along line BB′.

[0056] refer to Figures 4 to 6, the image sensor 100 may include: a substrate 110 having a first surface F1 and a second surface F2; a first photodiode LPD and a second photodiode SPD located inside the substrate 110; and an isolation structure 150 extending between the first photodiode LPD and the second photodiode SPD. In some embodiments, the image sensor 100 may also include a first transfer gate LTG and a second transfer gate STG. In some embodiments, the image sensor 100 may also include a reset transistor RG, a select transistor SX, a drive transistor DX, a switch transistor SW, and a gain control transistor DRG located at the second surface F2 of the substrate 110. In some embodiments, the image sensor 100 may also include a first floating diffusion region FD1, a second floating diffusion region FD2, and a third floating diffusion region FD3 located inside the substrate 110 (refer to Figure 2 ). In some embodiments, the image sensor 100 may further include a front surface structure 130 located on the second surface F2 of the substrate 110. In some embodiments, the image sensor 100 may further include an anti-reflection layer 161 located on the first surface F1 of the substrate 110, a fence 163 and a color filter 170 located on the anti-reflection layer 161, and a first microlens 180L and a second microlens 180S located on the fence 163 and the color filter 170.

[0057] The substrate 110 may include a first surface F1 and a second surface F2 facing each other. The first surface F1 may be a surface through which light transmitted by the first microlens 180L or the second microlens 180S enters the substrate 110. The substrate 110 may include semiconductor materials such as IV semiconductor materials, III-V semiconductor materials, and II-VI semiconductor materials, or may be formed of semiconductor materials such as IV semiconductor materials, III-V semiconductor materials, and II-VI semiconductor materials. IV semiconductor materials may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). III-V semiconductor materials may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or indium gallium arsenide (InGaAs). II-VI semiconductor materials may include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS).

[0058] The first photodiode LPD is located inside the substrate 110 and may be configured to generate photocharges from light incident on the first region RL of the first surface F1 of the substrate 110. The first photodiode LPD may be located inside a portion of the substrate 110d below the first region RL. The second photodiode SPD is located inside the substrate 110 and may be configured to generate photocharges from light incident on the second region RS of the first surface F1 of the substrate 110. The second photodiode SPD may be located inside a portion of the substrate 110 below the second region RS.

[0059] The area of ​​the second region RS may be smaller than the area of ​​the first region RL. Therefore, for incident light of the same intensity, the second photodiode SPD generates less photocharge than the first photodiode LPD. In other words, the sensitivity of the second photodiode SPD may be lower than the sensitivity of the first photodiode LPD. Therefore, the first photodiode LPD may have a relatively high sensitivity and generate a pixel signal corresponding to a relatively low illumination, while the second photodiode SPD may have a relatively low sensitivity and generate a pixel signal corresponding to a relatively high illumination.

[0060] In some embodiments, Figure 4 As shown, when viewed from above (i.e., when the image sensor 100 is viewed in a top view), the first region RL may have an octagonal shape, and the second region RS may have a quadrilateral shape. However, the shapes of the first region RL and the second region RS are not limited thereto. For example, the shapes of the first region RL and the second region RS may each be a circle or a quadrilateral.

[0061] The isolation structure 150 may extend from the second surface F2 of the substrate 110 to the first surface F1 of the substrate 110 in the vertical direction (Z direction) by completely penetrating the substrate 110 and extending between the first photodiode LPD and the second photodiode SPD. When viewed from above, the isolation structure 150 may surround the first photodiode LPD and the second photodiode SPD. For example, when viewed from above, the isolation structure 150 may surround or may define each of the first photodiode LPD and the second photodiode SPD. Therefore, the isolation structure 150 may isolate the first photodiode LPD and the second photodiode SPD from each other. Therefore, a blooming phenomenon in which photocharges generated by one of the first photodiode LPD and the second photodiode SPD move to the other of the first photodiode LPD and the second photodiode SPD may be prevented.

[0062] like Figure 4 and Figure 6As shown, the isolation structure 150 may also extend between two first photodiodes LPD adjacent to each other. The isolation structure 150 may surround two first photodiodes LPD adjacent to each other. For example, the isolation structure 150 may surround or may define each of two first photodiodes LPD adjacent to each other. Two first photodiodes LPD adjacent to each other may be located in corresponding portions of the substrate 110 below two first regions RL adjacent to each other on the first surface F1 of the substrate 110. Two first photodiodes LPD adjacent to each other may be configured to generate photocharges from light beams incident on the two first regions RL adjacent to each other, respectively. The two first regions RL adjacent to each other may have the same area as each other.

[0063] The portion of the isolation structure 150 between the two adjacent first photodiodes LPD may completely penetrate the substrate 110 from the second surface F2 of the substrate 110 to the first surface F1 of the substrate 110. Therefore, the isolation structure 150 may separate the two adjacent first photodiodes LPD from each other. Therefore, a blooming phenomenon in which photocharges generated by any first photodiode LPD move to an adjacent first photodiode LPD may be prevented.

[0064] The first end of the isolation structure 150 may be coplanar with the second surface F2 of the substrate 110, and the second end of the isolation structure 150 may be coplanar with the first surface F1 of the substrate 110. The width W2 of the first end of the isolation structure 150 in the first horizontal direction (X direction) may be greater than the width W1 of the second end of the isolation structure 150 in the first horizontal direction (X direction). The width W of the isolation structure 150 in the first horizontal direction (X direction) may decrease in the vertical direction (i.e., Z direction) from the second surface F2 of the substrate 110 toward the first surface F1 of the substrate 110. In some embodiments, the width W of the isolation structure 150 in the first horizontal direction (X direction) may gradually decrease in the vertical direction.

[0065] The isolation structure 150 may include a conductive layer 151 and an isolation insulating layer 152. The conductive layer 151 may completely penetrate the substrate 110 by extending from the second surface F2 of the substrate 110 to the first surface F1 of the substrate 110. The isolation insulating layer 152 may extend between the conductive layer 151 and the substrate 110 to electrically isolate the conductive layer 151 from the substrate 110. The conductive layer 151 may include or may be formed of a conductive material such as polysilicon and a metal. The isolation insulating layer 152 may include or may be formed of silicon oxide, silicon nitride, a metal oxide, or a combination thereof.

[0066] The first transfer gate LTG may extend from the second surface F2 of the substrate 110 into the substrate 110 and may be electrically connected to the first photodiode LPD. Figure 4As shown, the first transfer gate LTG may overlap with the center of the first region RL of the first surface F1 of the substrate 110 when viewed from above.

[0067] The second transfer gate STG may extend from the second surface F2 of the substrate 110 into the substrate 110 and may be electrically connected to the second photodiode SPD. Figure 4 As shown, the second transfer gate STG may overlap with the center of the second region RS of the first surface F1 of the substrate 110 when viewed from above.

[0068] The reset transistor RG, the selection transistor SX, the drive transistor DX, the switch transistor SW, and the gain control transistor DRG may be arranged at the second surface F2 of the substrate 110. In addition, the first floating diffusion region FD1, the second floating diffusion region FD2, and the third floating diffusion region FD3 (see Figure 2 ) may be arranged inside the substrate 110.

[0069] The front surface structure 130 may be disposed on the second surface F2 of the substrate 110. The front surface structure 130 may include a wire 134, a capacitor C1, and an insulating layer 136 surrounding the wire 134 and the capacitor C1. The wire 134 may include tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, or doped polysilicon or may be formed of tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, or doped polysilicon. The capacitor C1 may store photocharges generated and overflowed by the second photodiode SPD. The insulating layer 136 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material or may be formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.

[0070] The low-k material may include, for example, at least one of the following or may be formed from, for example, at least one of the following: flowable oxide (FOX), ton-burning silazane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer materials, and combinations thereof, but are not limited thereto.

[0071] The anti-reflection layer 161 may be disposed on the first surface F1 of the substrate 110. The anti-reflection layer 161 may include or may be formed of: hafnium oxide (HfO 2 ), silicon oxide (SiO 2 ), silicon nitride (SiN), aluminum oxide (Al 2 O3 ), zirconium oxide (ZrO 2 ), Tantalum Oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), praseodymium oxide (Pr 2 O 3 ), cerium oxide (CeO 2 ), neodymium oxide (Nd 2 O 3 ), Promethium oxide (Pm 2 O 3 ), samarium oxide (Sm 2 O 3 ), europium oxide (Eu 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), terbium oxide (Tb 2 O 3 ), Dysprosium oxide (Dy 2 O 3 ), holmium oxide (Ho 2 O 3 ), thulium oxide (Tm 2 O 3 ), Ytterbium oxide (Yb 2 O 3 ), Lutetium oxide (Lu 2 O 3 ), yttrium oxide (Y 2 O 3 ) or a combination thereof.

[0072] The fence 163 may be disposed on the anti-reflection layer 161. When viewed from above, the fence 163 may overlap the isolation structure 150. The fence 163 may include or may be formed of a metal or a low refractive index material. For example, the low refractive index material may include polymethyl methacrylate (PMMA), acrylate silicone, cellulose acetate butyrate (CAB), silica, fluorosilicone acrylate (FSA), or a polymer material in which silica particles are dispersed. The fence 163 may surround a plurality of color filters 170. For example, the fence 163 may surround each of the plurality of color filters 170.

[0073] The color filters 170 may be arranged on the anti-reflection layer 161 and may be isolated from each other by the fence 163. For example, the color filters 170 may include a green filter, a blue filter, and a red filter. In some embodiments, for example, the color filters 170 may include a cyan filter, a magenta filter, and a yellow filter.

[0074] The first microlens 180L and the second microlens 180S may be disposed on the color filter 170 and the fence 163. Figure 4 As shown, when viewed from above, the first microlens 180L may overlap the first region RL of the first surface F1 of the substrate 110, and the second microlens 180S may overlap the second region RS of the first surface F1 of the substrate 110. The first microlens 180L may converge incident light, and the light converged by the first microlens 180L may be incident on the first photodiode LPD via the color filter 170 and the first region RL. The second microlens 180S may converge incident light, and the light converged by the second microlens 180S may be incident on the second photodiode SPD via the color filter 170 and the second region RS. The first microlens 180L and the second microlens 180S may include, for example, a resin material such as a styrene resin, an acrylic resin, a styrene-acrylic copolymer resin, and a siloxane resin, or may be formed of a resin material such as a styrene resin, an acrylic resin, a styrene-acrylic copolymer resin, and a siloxane resin.

[0075] Figure 7 is a top view of an image sensor 100 a according to an embodiment of the inventive concept. Figure 8 FIG. 1 is a top view of an image sensor 100 b according to an embodiment of the inventive concept. Figure 4 The image sensor 100 shown, Figure 7 The image sensor 100a and Figure 8 The differences between the image sensor 100b are shown.

[0076] refer to Figure 4 , Figure 7 and Figure 8 , when viewed from above, the arrangement of the reset transistor RG, the selection transistor SX, the drive transistor DX, the switch transistor SW, and the gain control transistor DRG may vary. Figure 4 , Figure 7 and Figure 8 The illustrated arrangement of the reset transistor RG, the selection transistor SX, the drive transistor DX, the switch transistor SW, and the gain control transistor DRG is merely an example and is not limited thereto.

[0077] For example, in Figure 4In the embodiment, the reset transistor RG may be located at a region adjacent to the first transfer gate LTG in the third horizontal direction (D1 direction), the selection transistor SX may be located at a region adjacent to the first transfer gate LTG in a direction opposite to the fourth horizontal direction (D2 direction), the drive transistor DX may be located at a region adjacent to the first transfer gate LTG in a direction opposite to the third horizontal direction (D1 direction), and the switching transistor SW and the gain control transistor DRG may be located at a region adjacent to the first transfer gate LTG in the fourth horizontal direction (D2 direction).

[0078] For example, in Figure 7 In the embodiment, the reset transistor RG may be located at a region adjacent to the first transfer gate LTG in a direction opposite to the fourth horizontal direction (D2 direction), the selection transistor SX and the drive transistor DX may be located at relative regions adjacent to the first transfer gate LTG in the third horizontal direction (D1 direction) and in a direction opposite to the third horizontal direction (D1 direction), respectively, and the switching transistor SW and the gain control transistor DRG may be located at a region adjacent to the first transfer gate LTG in the fourth horizontal direction (D2 direction).

[0079] For example, in Figure 8 In the embodiment, the reset transistor RG and the gain control transistor DRG may be located at a region adjacent to the first transfer gate LTG in a fourth horizontal direction (D2 direction), the switch transistor SW may be located at a region adjacent to the first transfer gate LTG in a direction opposite to the fourth horizontal direction (D2 direction), and the drive transistor DX and the selection transistor SX may be located at relative regions adjacent to the first transfer gate LTG in a third horizontal direction (D1 direction) and a direction opposite to the third horizontal direction (D1 direction), respectively.

[0080] Fig. 9 It is along Figure 4 FIG. 1 is a cross-sectional view of an image sensor 100 c according to an embodiment of the inventive concept, taken along line AA′. Fig.10 It is along Figure 4 A cross-sectional view of an image sensor 100c according to an embodiment of the present invention is taken along line BB'. Figures 4 to 6 The image sensor 100 is shown with Fig. 9 and Fig.10 The differences between the image sensor 100c are shown.

[0081] refer to Fig. 9 and Fig.10 , the image sensor 100c may include an isolation structure 150c instead of Figures 4 to 6The isolation structure 150c shown may include a portion extending between the first photodiode LPD and the second photodiode LPD and a portion extending between two first photodiodes LPD adjacent to each other.

[0082] like Fig. 9 As shown, the portion of the isolation structure 150c extending between the first photodiode LPD and the second photodiode SPD may extend from the second surface F2 of the substrate 110 toward the first surface F1 of the substrate 110 in the vertical direction (Z direction). However, the portion of the isolation structure 150c extending between the first photodiode LPD and the second photodiode SPD may only partially penetrate the substrate 110 in the vertical direction (Z direction) instead of completely penetrating the substrate 110. On the contrary, as Fig.10 As shown, a portion of the isolation structure 150 c between two adjacent first photodiodes LPD may completely penetrate the substrate 110 from the second surface F2 of the substrate 110 toward the first surface F1 of the substrate 110 in a vertical direction (Z direction).

[0083] FIG. 11A to FIG. 11C is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment of the inventive concept. FIG. 11A to FIG. 11C is with Figure 4 A cross-sectional view corresponding to the line AA'.

[0084] refer to Fig.11A , a substrate 110 having a second surface F2 and a third surface F3 is prepared. A mask pattern (not shown) may be formed on the second surface F2 of the substrate 110, and a groove 150T may be formed in the substrate 110 by removing a portion of the substrate 110 from the second surface F2 of the substrate 110 using the mask pattern as an etching mask. Thereafter, the mask pattern may be removed. Because a portion of the substrate 110 is etched from the second surface F2 of the substrate 110 to form the groove 150T, the width W3 of the bottom of the groove 150T may be less than the width of the top of the groove 150T. The width W of the groove 150T may be reduced in a direction from the second surface F2 of the substrate 110 toward the third surface F3 of the substrate 110. In some embodiments, the width W of the groove 150T may be gradually reduced in a direction from the second surface F2 of the substrate 110 toward the third surface F3 of the substrate 110.

[0085] Thereafter, an isolation insulating layer 152 is formed on the second surface F2 and the trench 150T. A conductive layer 151 is formed on the isolation insulating layer 152 to fill the remaining portion of the trench 150T. A portion of the isolation insulating layer 152 and the conductive layer 151 may be removed by a planarization process, for example, to expose the second surface F2 of the substrate 110. Thus, an isolation structure 150 may be formed. The top of the isolation structure 150 may be coplanar with the second surface F2 of the substrate 110. The isolation structure 150 may be formed to extend from the second surface F2 of the substrate 110 toward the third surface F3 of the substrate 110. However, the isolation structure 150 may not reach the third surface F3. For example, the isolation structure 150 may only partially penetrate the substrate 110 instead of completely penetrating the substrate 110.

[0086] Next, the first photodiode LPD and the second photodiode SPD may be formed through an ion implantation process performed on the second surface F2 of the substrate 110 .

[0087] refer to Fig. 11B A first transfer gate LTG extending from the second surface F2 of the substrate 110 into the substrate 110 and electrically connected to the first photodiode LPD and a second transfer gate STG extending from the second surface F2 of the substrate 110 into the substrate 110 and electrically connected to the second photodiode SPD may be formed.

[0088] A selection transistor SX, a drive transistor DX, a reset transistor RG, a switch transistor SW, and a gain control transistor DRG may be formed on the second surface F2 of the substrate 110. Next, a front surface structure 130 may be formed on the second surface F2 of the substrate 110. For example, an insulating layer 136, a wire 314, and a capacitor C1 may be formed to constitute the front surface structure 130.

[0089] refer to Fig. 11C , can be turned upside down Fig. 11B Next, the third surface F3 (reference Fig. 11B ) removes a portion of the substrate 110, for example, to expose the conductive layer 151. Thus, the first surface F1 of the substrate 110 may be formed. The isolation structure 150 may completely penetrate the substrate 110 by extending from the second surface F2 of the substrate 110 to the first surface F1 of the substrate 110. The first end of the isolation structure 150 may be coplanar with the second surface F2 of the substrate, and the second end of the isolation structure 150 may be coplanar with the first surface F1 of the substrate 110.

[0090] refer to Figure 5, an anti-reflection layer 161 may be formed on the first surface F1 of the substrate 110. Next, a fence 163 may be formed on the anti-reflection layer 161. Next, a color filter 170 may be formed on the anti-reflection layer 161. Next, a first microlens 180L may be formed on the color filter 170 and the fence 163 so that the first microlens 180L overlaps with the first photodiode LPD when viewed from above. In addition, a second microlens 180S may be formed on the color filter 170 and the fence 163 so that the second microlens 180S overlaps with the second photodiode SPD when viewed from above. Thus, the image sensor 100 may be manufactured.

[0091] FIG. 12A to FIG. 12F is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment of the inventive concept. Fig. 12A , Fig. 12C and Fig.12E It is along Figure 4 The cross-sectional view taken along the line A-A' is Fig. 12B , Fig.12D and Fig.12F It is along Figure 4 A cross-sectional view taken along line BB'.

[0092] refer to Fig. 12A and Fig. 12B , a substrate 110 having a second surface F2 and a third surface F3 is prepared. The first trench 150T1 may be formed by removing a portion of the substrate 110 from the second surface F2 of the substrate 110. In addition, the second trench 150T2 may be formed by removing a portion of the substrate 110 from the second surface F2 of the substrate 110. The depth D1 of the first trench 150T1 may be less than the depth D2 of the second trench 150T2.

[0093] Next, an isolation insulating layer 152 is formed on the second surface F2 of the substrate 110, the first trench 150T1, and the second surface F2. Next, a conductive layer 151 is formed on the isolation insulating layer 152 to fill the remaining portion of the first trench 150T1 and the second trench 150T2. Next, a portion of the isolation insulating layer 152 and the conductive layer 151 may be removed by a planarization process, for example, to expose the second surface F2 of the substrate 110. Thus, an isolation structure 150c may be formed. The isolation structure 150c may be formed to extend from the second surface F2 of the substrate 110 toward the third surface F3 of the substrate 110. However, the isolation structure 150c may not reach the third surface F3. For example, the isolation structure 150c may only partially penetrate the substrate 110 instead of completely penetrating the substrate 110.

[0094] The first photodiode LPD and the second photodiode SPD may be formed by an ion implantation process performed on the second surface F2 of the substrate 110. The first trench 150T1 may extend between the first photodiode LPD and the second photodiode SPD, and the second trench 150T2 may extend between two first photodiodes LPD adjacent to each other.

[0095] refer to Fig. 12C and Fig.12D A first transfer gate LTG extending from the second surface F2 of the substrate 110 into the substrate 110 and electrically connected to the first photodiode LPD may be formed, and a second transfer gate STG extending from the second surface F2 of the substrate 110 into the substrate 110 and electrically connected to the second photodiode SPD may be formed.

[0096] In addition, a selection transistor SX, a drive transistor DX, a reset transistor RG, a switch transistor SW, and a gain control transistor DRG may be formed on the second surface F2 of the substrate 110. Next, a front surface structure 130 may be formed on the second surface F2 of the substrate 110. For example, an insulating layer 136, a wire 314, and a capacitor C1 may be formed to constitute the front surface structure 130.

[0097] refer to Fig.12E and Fig.12F , can be turned upside down Fig. 12C and Fig.12D Next, the third surface F3 (reference Fig. 12C and Fig.12D ) removes a portion of the substrate 110, for example, to expose a portion of the conductive layer 151 in the second trench 150T2. Thus, the first surface F1 of the substrate 110 may be formed. Fig.12E As shown, a portion of the isolation structure 150c in the first trench 150T1 may not reach the first surface F1 of the substrate 110. For example, a portion of the isolation structure 150c in the first trench 150T1 may only partially penetrate the substrate 110 instead of completely penetrating the substrate 110. In contrast, a portion of the isolation structure 150c in the second trench 150T2 may completely penetrate the substrate 110 by extending from the second surface F2 of the substrate 110 to the first surface F1 of the substrate 110. A first end of the portion of the isolation structure 150c in the second trench 150T2 may be coplanar with the second surface F2 of the substrate 110, and a second end of the portion of the isolation structure 150c in the second trench 150T2 may be coplanar with the first surface F1 of the substrate 110.

[0098] refer to Fig. 9 and Fig.10, an anti-reflection layer 161 may be formed on the first surface F1 of the substrate 110. Next, a fence 163 may be formed on the anti-reflection layer 161. Next, a color filter 170 may be formed on the anti-reflection layer 161. Next, a first microlens 180L may be formed on the color filter 170 and the fence 163 so that the first microlens 180L overlaps with the first photodiode LPD when viewed from above. In addition, a second microlens 180S may be formed on the color filter 170 and the fence 163 so that the second microlens 180S overlaps with the second photodiode SPD when viewed from above. Thus, the image sensor 100c may be manufactured.

[0099] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: a substrate comprising a first surface and a second surface facing the first surface of the substrate; a first photodiode located in a first region of the substrate; a second photodiode located in a second region of the substrate; a third photodiode, the third photodiode being located in a third region of the substrate; a first isolation trench, wherein the first isolation trench is located between the first photodiode and the second photodiode; as well as a second isolation trench, the second isolation trench being located between the first photodiode and the third photodiode, wherein the area of ​​the second region in the top view is smaller than each of the area of ​​the first region in the top view and the area of ​​the third region in the top view, wherein the second isolation trench contacts the first surface of the substrate and the second surface of the substrate, wherein the second area is adjacent to the first area, wherein the third area is adjacent to the first area and the second area, and Wherein, the image sensor is configured to receive light through the second surface.

2. The image sensor according to claim 1, wherein: An area of ​​the third region in the plan view is the same as an area of ​​the first region in the plan view.

3. The image sensor according to claim 2, further comprising: a first floating diffusion region; a transfer gate configured to transfer photocharges generated by the first photodiode to the first floating diffusion region; a second floating diffusion region; a switching transistor configured to transfer photocharges generated by the second photodiode to the second floating diffusion region; a gain control transistor, the gain control transistor being located between the first floating diffusion region and the second floating diffusion region; a driving transistor configured to be connected to the first floating diffusion region; as well as A select transistor is configured to be connected to the drive transistor.

4. The image sensor according to claim 3, further comprising: Reset transistor, The reset transistor, the second floating diffusion region, the gain control transistor and the first floating diffusion region are connected in series.

5. The image sensor according to claim 4, further comprising: a third floating diffusion region, wherein the third floating diffusion region is located between the second photodiode and the switch transistor; as well as A capacitor is connected in series to the third floating diffusion region.

6. The image sensor according to claim 4, wherein: The second isolation trench contacts the second surface of the substrate.

7. The image sensor according to claim 4, wherein: A second isolation trench contacts the first surface of the substrate and the second surface of the substrate.

8. The image sensor according to claim 6, wherein: The sensitivity of the first photodiode is higher than the sensitivity of the second photodiode.

9. The image sensor according to claim 8, wherein: In the top view, the first region is an octagonal shape, and the second region is a quadrilateral shape.

10. The image sensor according to claim 9, wherein: The transfer gate extends from the first surface of the substrate into the substrate.

11. The image sensor according to claim 4, wherein: The reset transistor, the transfer gate, and the gain control transistor are arranged along a first direction in the plan view.

12. An image sensor, comprising: a substrate comprising a first surface and a second surface facing the first surface of the substrate; a first photodiode located in a first region of the substrate; a second photodiode located in a second region of the substrate; as well as a first isolation layer, the first isolation layer being located between the first photodiode and the second photodiode, The area of ​​the second region in the top view is smaller than the area of ​​the first region in the top view. wherein the first isolation layer is in contact with the first surface of the substrate and the second surface of the substrate, wherein the second region is arranged adjacent to the first region in the top view, and Wherein, the image sensor is configured to receive light through the second surface.

13. The image sensor according to claim 12, further comprising: a first floating diffusion region; as well as a transfer gate configured to transfer photocharges generated by the first photodiode to the first floating diffusion region, Wherein, the transfer gate extends into the substrate.

14. The image sensor according to claim 13, wherein: The second region is arranged directly diagonally to the first region in the plan view.

15. The image sensor according to claim 12, further comprising: a third photodiode, the third photodiode being located in a third region of the substrate; as well as a second isolation layer, the second isolation layer being located between the first photodiode and the third photodiode, The area of ​​the third region in the top view is the same as the area of ​​the first region in the top view, and The second isolation layer is in contact with the first surface of the substrate and the second surface of the substrate.

16. The image sensor according to claim 15, further comprising: a first floating diffusion region; a transfer gate configured to transfer photocharges generated by the first photodiode to the first floating diffusion region; a second floating diffusion region; a switching transistor configured to transfer photocharges generated by the second photodiode to the second floating diffusion region; a gain control transistor, the gain control transistor being located between the first floating diffusion region and the second floating diffusion region; a driving transistor configured to be connected to the second floating diffusion region; as well as A select transistor is configured to be connected to the drive transistor.

17. The image sensor according to claim 15, wherein: The first isolation layer has a first width on the first surface and a second width on the second surface, and Wherein, in a first direction parallel to the first surface of the substrate, the first width is greater than the second width.

18. The image sensor according to claim 16, further comprising: Reset transistor, wherein the reset transistor, the second floating diffusion region, the gain control transistor and the first floating diffusion region are connected in series, wherein the reset transistor is configured to receive a pixel voltage, and Wherein, the driving transistor is configured to receive the pixel voltage.

19. An image sensor, comprising: a substrate comprising a first surface and a second surface facing the first surface of the substrate; a first photodiode located in a first region of the substrate; a second photodiode located in a second region of the substrate; a first floating diffusion region; a second floating diffusion region; a first transfer gate configured to transfer photocharges generated by the first photodiode to the first floating diffusion region; a second transfer gate configured to transfer photocharges generated by the second photodiode to the second floating diffusion region; an isolation layer, the isolation layer being located between the first photodiode and the second photodiode, The area of ​​the second region in the top view is smaller than the area of ​​the first region in the top view. wherein the isolation layer is in contact with the first surface of the substrate and the second surface of the substrate, wherein each of the first transfer gate and the second transfer gate extends into the substrate, wherein the second region is arranged adjacent to the first region in the top view, and Wherein, the image sensor is configured to receive light through the second surface.

Images